1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/mlx5/driver.h> 34 #include <linux/mlx5/cmd.h> 35 #include <linux/mlx5/eswitch.h> 36 #include <linux/module.h> 37 #include "mlx5_core.h" 38 #include "../../mlxfw/mlxfw.h" 39 40 enum { 41 MCQS_IDENTIFIER_BOOT_IMG = 0x1, 42 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4, 43 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5, 44 MCQS_IDENTIFIER_CS_TOKEN = 0x6, 45 MCQS_IDENTIFIER_DBG_TOKEN = 0x7, 46 MCQS_IDENTIFIER_GEARBOX = 0xA, 47 }; 48 49 enum { 50 MCQS_UPDATE_STATE_IDLE, 51 MCQS_UPDATE_STATE_IN_PROGRESS, 52 MCQS_UPDATE_STATE_APPLIED, 53 MCQS_UPDATE_STATE_ACTIVE, 54 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET, 55 MCQS_UPDATE_STATE_FAILED, 56 MCQS_UPDATE_STATE_CANCELED, 57 MCQS_UPDATE_STATE_BUSY, 58 }; 59 60 enum { 61 MCQI_INFO_TYPE_CAPABILITIES = 0x0, 62 MCQI_INFO_TYPE_VERSION = 0x1, 63 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5, 64 }; 65 66 enum { 67 MCQI_FW_RUNNING_VERSION = 0, 68 MCQI_FW_STORED_VERSION = 1, 69 }; 70 71 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out, 72 int outlen) 73 { 74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0}; 75 76 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 77 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 78 } 79 80 int mlx5_query_board_id(struct mlx5_core_dev *dev) 81 { 82 u32 *out; 83 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 84 int err; 85 86 out = kzalloc(outlen, GFP_KERNEL); 87 if (!out) 88 return -ENOMEM; 89 90 err = mlx5_cmd_query_adapter(dev, out, outlen); 91 if (err) 92 goto out; 93 94 memcpy(dev->board_id, 95 MLX5_ADDR_OF(query_adapter_out, out, 96 query_adapter_struct.vsd_contd_psid), 97 MLX5_FLD_SZ_BYTES(query_adapter_out, 98 query_adapter_struct.vsd_contd_psid)); 99 100 out: 101 kfree(out); 102 return err; 103 } 104 105 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id) 106 { 107 u32 *out; 108 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 109 int err; 110 111 out = kzalloc(outlen, GFP_KERNEL); 112 if (!out) 113 return -ENOMEM; 114 115 err = mlx5_cmd_query_adapter(mdev, out, outlen); 116 if (err) 117 goto out; 118 119 *vendor_id = MLX5_GET(query_adapter_out, out, 120 query_adapter_struct.ieee_vendor_id); 121 out: 122 kfree(out); 123 return err; 124 } 125 EXPORT_SYMBOL(mlx5_core_query_vendor_id); 126 127 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev) 128 { 129 return mlx5_query_pcam_reg(dev, dev->caps.pcam, 130 MLX5_PCAM_FEATURE_ENHANCED_FEATURES, 131 MLX5_PCAM_REGS_5000_TO_507F); 132 } 133 134 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev, 135 enum mlx5_mcam_reg_groups group) 136 { 137 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group], 138 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group); 139 } 140 141 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev) 142 { 143 return mlx5_query_qcam_reg(dev, dev->caps.qcam, 144 MLX5_QCAM_FEATURE_ENHANCED_FEATURES, 145 MLX5_QCAM_REGS_FIRST_128); 146 } 147 148 int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 149 { 150 int err; 151 152 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 153 if (err) 154 return err; 155 156 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 157 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS); 158 if (err) 159 return err; 160 } 161 162 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 163 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS); 164 if (err) 165 return err; 166 } 167 168 if (MLX5_CAP_GEN(dev, pg)) { 169 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 170 if (err) 171 return err; 172 } 173 174 if (MLX5_CAP_GEN(dev, atomic)) { 175 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 176 if (err) 177 return err; 178 } 179 180 if (MLX5_CAP_GEN(dev, roce)) { 181 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 182 if (err) 183 return err; 184 } 185 186 if (MLX5_CAP_GEN(dev, nic_flow_table) || 187 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 188 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE); 189 if (err) 190 return err; 191 } 192 193 if (MLX5_CAP_GEN(dev, vport_group_manager) && 194 MLX5_ESWITCH_MANAGER(dev)) { 195 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE); 196 if (err) 197 return err; 198 } 199 200 if (MLX5_ESWITCH_MANAGER(dev)) { 201 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH); 202 if (err) 203 return err; 204 } 205 206 if (MLX5_CAP_GEN(dev, vector_calc)) { 207 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC); 208 if (err) 209 return err; 210 } 211 212 if (MLX5_CAP_GEN(dev, qos)) { 213 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS); 214 if (err) 215 return err; 216 } 217 218 if (MLX5_CAP_GEN(dev, debug)) 219 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG); 220 221 if (MLX5_CAP_GEN(dev, pcam_reg)) 222 mlx5_get_pcam_reg(dev); 223 224 if (MLX5_CAP_GEN(dev, mcam_reg)) { 225 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); 226 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF); 227 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); 228 } 229 230 if (MLX5_CAP_GEN(dev, qcam_reg)) 231 mlx5_get_qcam_reg(dev); 232 233 if (MLX5_CAP_GEN(dev, device_memory)) { 234 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM); 235 if (err) 236 return err; 237 } 238 239 if (MLX5_CAP_GEN(dev, event_cap)) { 240 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT); 241 if (err) 242 return err; 243 } 244 245 if (MLX5_CAP_GEN(dev, tls_tx)) { 246 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS); 247 if (err) 248 return err; 249 } 250 251 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 252 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 253 err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION); 254 if (err) 255 return err; 256 } 257 258 return 0; 259 } 260 261 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id) 262 { 263 u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0}; 264 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0}; 265 int i; 266 267 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); 268 269 if (MLX5_CAP_GEN(dev, sw_owner_id)) { 270 for (i = 0; i < 4; i++) 271 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i, 272 sw_owner_id[i]); 273 } 274 275 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 276 } 277 278 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev) 279 { 280 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 281 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 282 283 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 284 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 285 } 286 287 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev) 288 { 289 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 290 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 291 int force_state; 292 int ret; 293 294 if (!MLX5_CAP_GEN(dev, force_teardown)) { 295 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 296 return -EOPNOTSUPP; 297 } 298 299 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 300 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE); 301 302 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out)); 303 if (ret) 304 return ret; 305 306 force_state = MLX5_GET(teardown_hca_out, out, state); 307 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 308 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n"); 309 return -EIO; 310 } 311 312 return 0; 313 } 314 315 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000 316 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev) 317 { 318 unsigned long end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS; 319 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 320 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 321 int state; 322 int ret; 323 324 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 325 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n"); 326 return -EOPNOTSUPP; 327 } 328 329 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 330 MLX5_SET(teardown_hca_in, in, profile, 331 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN); 332 333 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 334 if (ret) 335 return ret; 336 337 state = MLX5_GET(teardown_hca_out, out, state); 338 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 339 mlx5_core_warn(dev, "teardown with fast mode failed\n"); 340 return -EIO; 341 } 342 343 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED); 344 345 /* Loop until device state turns to disable */ 346 end = jiffies + msecs_to_jiffies(delay_ms); 347 do { 348 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED) 349 break; 350 351 cond_resched(); 352 } while (!time_after(jiffies, end)); 353 354 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) { 355 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n", 356 mlx5_get_nic_state(dev), delay_ms); 357 return -EIO; 358 } 359 360 return 0; 361 } 362 363 enum mlxsw_reg_mcc_instruction { 364 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 365 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 366 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 367 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 368 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 369 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08, 370 }; 371 372 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev, 373 enum mlxsw_reg_mcc_instruction instr, 374 u16 component_index, u32 update_handle, 375 u32 component_size) 376 { 377 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 378 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 379 380 memset(in, 0, sizeof(in)); 381 382 MLX5_SET(mcc_reg, in, instruction, instr); 383 MLX5_SET(mcc_reg, in, component_index, component_index); 384 MLX5_SET(mcc_reg, in, update_handle, update_handle); 385 MLX5_SET(mcc_reg, in, component_size, component_size); 386 387 return mlx5_core_access_reg(dev, in, sizeof(in), out, 388 sizeof(out), MLX5_REG_MCC, 0, 1); 389 } 390 391 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev, 392 u32 *update_handle, u8 *error_code, 393 u8 *control_state) 394 { 395 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 396 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 397 int err; 398 399 memset(in, 0, sizeof(in)); 400 memset(out, 0, sizeof(out)); 401 MLX5_SET(mcc_reg, in, update_handle, *update_handle); 402 403 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 404 sizeof(out), MLX5_REG_MCC, 0, 0); 405 if (err) 406 goto out; 407 408 *update_handle = MLX5_GET(mcc_reg, out, update_handle); 409 *error_code = MLX5_GET(mcc_reg, out, error_code); 410 *control_state = MLX5_GET(mcc_reg, out, control_state); 411 412 out: 413 return err; 414 } 415 416 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev, 417 u32 update_handle, 418 u32 offset, u16 size, 419 u8 *data) 420 { 421 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size; 422 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; 423 int i, j, dw_size = size >> 2; 424 __be32 data_element; 425 u32 *in; 426 427 in = kzalloc(in_size, GFP_KERNEL); 428 if (!in) 429 return -ENOMEM; 430 431 MLX5_SET(mcda_reg, in, update_handle, update_handle); 432 MLX5_SET(mcda_reg, in, offset, offset); 433 MLX5_SET(mcda_reg, in, size, size); 434 435 for (i = 0; i < dw_size; i++) { 436 j = i * 4; 437 data_element = htonl(*(u32 *)&data[j]); 438 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4); 439 } 440 441 err = mlx5_core_access_reg(dev, in, in_size, out, 442 sizeof(out), MLX5_REG_MCDA, 0, 1); 443 kfree(in); 444 return err; 445 } 446 447 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev, 448 u16 component_index, bool read_pending, 449 u8 info_type, u16 data_size, void *mcqi_data) 450 { 451 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {}; 452 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {}; 453 void *data; 454 int err; 455 456 MLX5_SET(mcqi_reg, in, component_index, component_index); 457 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending); 458 MLX5_SET(mcqi_reg, in, info_type, info_type); 459 MLX5_SET(mcqi_reg, in, data_size, data_size); 460 461 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 462 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size, 463 MLX5_REG_MCQI, 0, 0); 464 if (err) 465 return err; 466 467 data = MLX5_ADDR_OF(mcqi_reg, out, data); 468 memcpy(mcqi_data, data, data_size); 469 470 return 0; 471 } 472 473 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index, 474 u32 *max_component_size, u8 *log_mcda_word_size, 475 u16 *mcda_max_write_size) 476 { 477 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {}; 478 int err; 479 480 err = mlx5_reg_mcqi_query(dev, component_index, 0, 481 MCQI_INFO_TYPE_CAPABILITIES, 482 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg); 483 if (err) 484 return err; 485 486 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size); 487 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size); 488 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size); 489 490 return 0; 491 } 492 493 struct mlx5_mlxfw_dev { 494 struct mlxfw_dev mlxfw_dev; 495 struct mlx5_core_dev *mlx5_core_dev; 496 }; 497 498 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev, 499 u16 component_index, u32 *p_max_size, 500 u8 *p_align_bits, u16 *p_max_write_size) 501 { 502 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 503 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 504 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 505 506 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) { 507 mlx5_core_warn(dev, "caps query isn't supported by running FW\n"); 508 return -EOPNOTSUPP; 509 } 510 511 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size, 512 p_align_bits, p_max_write_size); 513 } 514 515 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 516 { 517 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 518 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 519 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 520 u8 control_state, error_code; 521 int err; 522 523 *fwhandle = 0; 524 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state); 525 if (err) 526 return err; 527 528 if (control_state != MLXFW_FSM_STATE_IDLE) 529 return -EBUSY; 530 531 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 532 0, *fwhandle, 0); 533 } 534 535 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 536 u16 component_index, u32 component_size) 537 { 538 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 539 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 540 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 541 542 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 543 component_index, fwhandle, component_size); 544 } 545 546 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 547 u8 *data, u16 size, u32 offset) 548 { 549 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 550 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 551 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 552 553 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data); 554 } 555 556 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 557 u16 component_index) 558 { 559 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 560 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 561 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 562 563 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 564 component_index, fwhandle, 0); 565 } 566 567 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 568 { 569 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 570 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 571 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 572 573 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0, 574 fwhandle, 0); 575 } 576 577 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 578 enum mlxfw_fsm_state *fsm_state, 579 enum mlxfw_fsm_state_err *fsm_state_err) 580 { 581 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 582 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 583 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 584 u8 control_state, error_code; 585 int err; 586 587 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state); 588 if (err) 589 return err; 590 591 *fsm_state = control_state; 592 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 593 MLXFW_FSM_STATE_ERR_MAX); 594 return 0; 595 } 596 597 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 598 { 599 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 600 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 601 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 602 603 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 604 } 605 606 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 607 { 608 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 609 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 610 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 611 612 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 613 fwhandle, 0); 614 } 615 616 #define MLX5_FSM_REACTIVATE_TOUT 5000 /* msecs */ 617 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status) 618 { 619 unsigned long exp_time = jiffies + msecs_to_jiffies(MLX5_FSM_REACTIVATE_TOUT); 620 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 621 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 622 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 623 u32 out[MLX5_ST_SZ_DW(mirc_reg)]; 624 u32 in[MLX5_ST_SZ_DW(mirc_reg)]; 625 int err; 626 627 if (!MLX5_CAP_MCAM_REG2(dev, mirc)) 628 return -EOPNOTSUPP; 629 630 memset(in, 0, sizeof(in)); 631 632 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 633 sizeof(out), MLX5_REG_MIRC, 0, 1); 634 if (err) 635 return err; 636 637 do { 638 memset(out, 0, sizeof(out)); 639 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 640 sizeof(out), MLX5_REG_MIRC, 0, 0); 641 if (err) 642 return err; 643 644 *status = MLX5_GET(mirc_reg, out, status_code); 645 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY) 646 return 0; 647 648 msleep(20); 649 } while (time_before(jiffies, exp_time)); 650 651 return 0; 652 } 653 654 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = { 655 .component_query = mlx5_component_query, 656 .fsm_lock = mlx5_fsm_lock, 657 .fsm_component_update = mlx5_fsm_component_update, 658 .fsm_block_download = mlx5_fsm_block_download, 659 .fsm_component_verify = mlx5_fsm_component_verify, 660 .fsm_activate = mlx5_fsm_activate, 661 .fsm_reactivate = mlx5_fsm_reactivate, 662 .fsm_query_state = mlx5_fsm_query_state, 663 .fsm_cancel = mlx5_fsm_cancel, 664 .fsm_release = mlx5_fsm_release 665 }; 666 667 int mlx5_firmware_flash(struct mlx5_core_dev *dev, 668 const struct firmware *firmware, 669 struct netlink_ext_ack *extack) 670 { 671 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = { 672 .mlxfw_dev = { 673 .ops = &mlx5_mlxfw_dev_ops, 674 .psid = dev->board_id, 675 .psid_size = strlen(dev->board_id), 676 .devlink = priv_to_devlink(dev), 677 }, 678 .mlx5_core_dev = dev 679 }; 680 681 if (!MLX5_CAP_GEN(dev, mcam_reg) || 682 !MLX5_CAP_MCAM_REG(dev, mcqi) || 683 !MLX5_CAP_MCAM_REG(dev, mcc) || 684 !MLX5_CAP_MCAM_REG(dev, mcda)) { 685 pr_info("%s flashing isn't supported by the running FW\n", __func__); 686 return -EOPNOTSUPP; 687 } 688 689 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, 690 firmware, extack); 691 } 692 693 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev, 694 u16 component_index, bool read_pending, 695 u32 *mcqi_version_out) 696 { 697 return mlx5_reg_mcqi_query(dev, component_index, read_pending, 698 MCQI_INFO_TYPE_VERSION, 699 MLX5_ST_SZ_BYTES(mcqi_version), 700 mcqi_version_out); 701 } 702 703 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out, 704 u16 component_index) 705 { 706 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg); 707 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {}; 708 int err; 709 710 memset(out, 0, out_sz); 711 712 MLX5_SET(mcqs_reg, in, component_index, component_index); 713 714 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 715 out_sz, MLX5_REG_MCQS, 0, 0); 716 return err; 717 } 718 719 /* scans component index sequentially, to find the boot img index */ 720 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev) 721 { 722 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {}; 723 u16 identifier, component_idx = 0; 724 bool quit; 725 int err; 726 727 do { 728 err = mlx5_reg_mcqs_query(dev, out, component_idx); 729 if (err) 730 return err; 731 732 identifier = MLX5_GET(mcqs_reg, out, identifier); 733 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag); 734 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG; 735 } while (!quit && ++component_idx); 736 737 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) { 738 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n", 739 component_idx); 740 return -EOPNOTSUPP; 741 } 742 743 return component_idx; 744 } 745 746 static int 747 mlx5_fw_image_pending(struct mlx5_core_dev *dev, 748 int component_index, 749 bool *pending_version_exists) 750 { 751 u32 out[MLX5_ST_SZ_DW(mcqs_reg)]; 752 u8 component_update_state; 753 int err; 754 755 err = mlx5_reg_mcqs_query(dev, out, component_index); 756 if (err) 757 return err; 758 759 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state); 760 761 if (component_update_state == MCQS_UPDATE_STATE_IDLE) { 762 *pending_version_exists = false; 763 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) { 764 *pending_version_exists = true; 765 } else { 766 mlx5_core_warn(dev, 767 "mcqs: can't read pending fw version while fw state is %d\n", 768 component_update_state); 769 return -ENODATA; 770 } 771 return 0; 772 } 773 774 int mlx5_fw_version_query(struct mlx5_core_dev *dev, 775 u32 *running_ver, u32 *pending_ver) 776 { 777 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {}; 778 bool pending_version_exists; 779 int component_index; 780 int err; 781 782 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) || 783 !MLX5_CAP_MCAM_REG(dev, mcqs)) { 784 mlx5_core_warn(dev, "fw query isn't supported by the FW\n"); 785 return -EOPNOTSUPP; 786 } 787 788 component_index = mlx5_get_boot_img_component_index(dev); 789 if (component_index < 0) 790 return component_index; 791 792 err = mlx5_reg_mcqi_version_query(dev, component_index, 793 MCQI_FW_RUNNING_VERSION, 794 reg_mcqi_version); 795 if (err) 796 return err; 797 798 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version); 799 800 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists); 801 if (err) 802 return err; 803 804 if (!pending_version_exists) { 805 *pending_ver = 0; 806 return 0; 807 } 808 809 err = mlx5_reg_mcqi_version_query(dev, component_index, 810 MCQI_FW_STORED_VERSION, 811 reg_mcqi_version); 812 if (err) 813 return err; 814 815 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version); 816 817 return 0; 818 } 819