xref: /linux/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c (revision a13d7201d7deedcbb6ac6efa94a1a7d34d3d79ec)
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include "en.h"
34 
35 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq)
36 {
37 	struct mlx5_cqwq *wq = &cq->wq;
38 	u32 ci = mlx5_cqwq_get_ci(wq);
39 	struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
40 	int cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
41 	int sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
42 
43 	if (cqe_ownership_bit != sw_ownership_val)
44 		return NULL;
45 
46 	/* ensure cqe content is read after cqe ownership bit */
47 	rmb();
48 
49 	return cqe;
50 }
51 
52 int mlx5e_napi_poll(struct napi_struct *napi, int budget)
53 {
54 	struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
55 					       napi);
56 	bool busy = false;
57 	int i;
58 
59 	clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
60 
61 	for (i = 0; i < c->num_tc; i++)
62 		busy |= mlx5e_poll_tx_cq(&c->sq[i].cq);
63 
64 	busy |= mlx5e_poll_rx_cq(&c->rq.cq, budget);
65 
66 	busy |= mlx5e_post_rx_wqes(&c->rq);
67 
68 	if (busy)
69 		return budget;
70 
71 	napi_complete(napi);
72 
73 	/* avoid losing completion event during/after polling cqs */
74 	if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) {
75 		napi_schedule(napi);
76 		return 0;
77 	}
78 
79 	for (i = 0; i < c->num_tc; i++)
80 		mlx5e_cq_arm(&c->sq[i].cq);
81 	mlx5e_cq_arm(&c->rq.cq);
82 
83 	return 0;
84 }
85 
86 void mlx5e_completion_event(struct mlx5_core_cq *mcq)
87 {
88 	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
89 
90 	set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);
91 	set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags);
92 	barrier();
93 	napi_schedule(cq->napi);
94 }
95 
96 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
97 {
98 	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
99 	struct mlx5e_channel *c = cq->channel;
100 	struct mlx5e_priv *priv = c->priv;
101 	struct net_device *netdev = priv->netdev;
102 
103 	netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
104 		   __func__, mcq->cqn, event);
105 }
106