1 /* 2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <net/flow_dissector.h> 34 #include <net/sch_generic.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_skbedit.h> 38 #include <linux/mlx5/fs.h> 39 #include <linux/mlx5/device.h> 40 #include <linux/rhashtable.h> 41 #include <net/tc_act/tc_mirred.h> 42 #include <net/tc_act/tc_vlan.h> 43 #include <net/tc_act/tc_tunnel_key.h> 44 #include <net/tc_act/tc_pedit.h> 45 #include <net/tc_act/tc_csum.h> 46 #include <net/arp.h> 47 #include <net/ipv6_stubs.h> 48 #include "en.h" 49 #include "en_rep.h" 50 #include "en_tc.h" 51 #include "eswitch.h" 52 #include "fs_core.h" 53 #include "en/port.h" 54 #include "en/tc_tun.h" 55 #include "lib/devcom.h" 56 57 struct mlx5_nic_flow_attr { 58 u32 action; 59 u32 flow_tag; 60 u32 mod_hdr_id; 61 u32 hairpin_tirn; 62 u8 match_level; 63 struct mlx5_flow_table *hairpin_ft; 64 struct mlx5_fc *counter; 65 }; 66 67 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1) 68 69 enum { 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS, 71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS, 72 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD, 73 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD, 74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE), 75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1), 76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2), 77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3), 78 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4), 79 MLX5E_TC_FLOW_NOT_READY = BIT(MLX5E_TC_FLOW_BASE + 5), 80 }; 81 82 #define MLX5E_TC_MAX_SPLITS 1 83 84 /* Helper struct for accessing a struct containing list_head array. 85 * Containing struct 86 * |- Helper array 87 * [0] Helper item 0 88 * |- list_head item 0 89 * |- index (0) 90 * [1] Helper item 1 91 * |- list_head item 1 92 * |- index (1) 93 * To access the containing struct from one of the list_head items: 94 * 1. Get the helper item from the list_head item using 95 * helper item = 96 * container_of(list_head item, helper struct type, list_head field) 97 * 2. Get the contining struct from the helper item and its index in the array: 98 * containing struct = 99 * container_of(helper item, containing struct type, helper field[index]) 100 */ 101 struct encap_flow_item { 102 struct list_head list; 103 int index; 104 }; 105 106 struct mlx5e_tc_flow { 107 struct rhash_head node; 108 struct mlx5e_priv *priv; 109 u64 cookie; 110 u16 flags; 111 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1]; 112 /* Flow can be associated with multiple encap IDs. 113 * The number of encaps is bounded by the number of supported 114 * destinations. 115 */ 116 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS]; 117 struct mlx5e_tc_flow *peer_flow; 118 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */ 119 struct list_head hairpin; /* flows sharing the same hairpin */ 120 struct list_head peer; /* flows with peer flow */ 121 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */ 122 union { 123 struct mlx5_esw_flow_attr esw_attr[0]; 124 struct mlx5_nic_flow_attr nic_attr[0]; 125 }; 126 }; 127 128 struct mlx5e_tc_flow_parse_attr { 129 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS]; 130 struct net_device *filter_dev; 131 struct mlx5_flow_spec spec; 132 int num_mod_hdr_actions; 133 int max_mod_hdr_actions; 134 void *mod_hdr_actions; 135 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS]; 136 }; 137 138 #define MLX5E_TC_TABLE_NUM_GROUPS 4 139 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16) 140 141 struct mlx5e_hairpin { 142 struct mlx5_hairpin *pair; 143 144 struct mlx5_core_dev *func_mdev; 145 struct mlx5e_priv *func_priv; 146 u32 tdn; 147 u32 tirn; 148 149 int num_channels; 150 struct mlx5e_rqt indir_rqt; 151 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; 152 struct mlx5e_ttc_table ttc; 153 }; 154 155 struct mlx5e_hairpin_entry { 156 /* a node of a hash table which keeps all the hairpin entries */ 157 struct hlist_node hairpin_hlist; 158 159 /* flows sharing the same hairpin */ 160 struct list_head flows; 161 162 u16 peer_vhca_id; 163 u8 prio; 164 struct mlx5e_hairpin *hp; 165 }; 166 167 struct mod_hdr_key { 168 int num_actions; 169 void *actions; 170 }; 171 172 struct mlx5e_mod_hdr_entry { 173 /* a node of a hash table which keeps all the mod_hdr entries */ 174 struct hlist_node mod_hdr_hlist; 175 176 /* flows sharing the same mod_hdr entry */ 177 struct list_head flows; 178 179 struct mod_hdr_key key; 180 181 u32 mod_hdr_id; 182 }; 183 184 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto) 185 186 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key) 187 { 188 return jhash(key->actions, 189 key->num_actions * MLX5_MH_ACT_SZ, 0); 190 } 191 192 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a, 193 struct mod_hdr_key *b) 194 { 195 if (a->num_actions != b->num_actions) 196 return 1; 197 198 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ); 199 } 200 201 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv, 202 struct mlx5e_tc_flow *flow, 203 struct mlx5e_tc_flow_parse_attr *parse_attr) 204 { 205 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 206 int num_actions, actions_size, namespace, err; 207 struct mlx5e_mod_hdr_entry *mh; 208 struct mod_hdr_key key; 209 bool found = false; 210 u32 hash_key; 211 212 num_actions = parse_attr->num_mod_hdr_actions; 213 actions_size = MLX5_MH_ACT_SZ * num_actions; 214 215 key.actions = parse_attr->mod_hdr_actions; 216 key.num_actions = num_actions; 217 218 hash_key = hash_mod_hdr_info(&key); 219 220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { 221 namespace = MLX5_FLOW_NAMESPACE_FDB; 222 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh, 223 mod_hdr_hlist, hash_key) { 224 if (!cmp_mod_hdr_info(&mh->key, &key)) { 225 found = true; 226 break; 227 } 228 } 229 } else { 230 namespace = MLX5_FLOW_NAMESPACE_KERNEL; 231 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh, 232 mod_hdr_hlist, hash_key) { 233 if (!cmp_mod_hdr_info(&mh->key, &key)) { 234 found = true; 235 break; 236 } 237 } 238 } 239 240 if (found) 241 goto attach_flow; 242 243 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL); 244 if (!mh) 245 return -ENOMEM; 246 247 mh->key.actions = (void *)mh + sizeof(*mh); 248 memcpy(mh->key.actions, key.actions, actions_size); 249 mh->key.num_actions = num_actions; 250 INIT_LIST_HEAD(&mh->flows); 251 252 err = mlx5_modify_header_alloc(priv->mdev, namespace, 253 mh->key.num_actions, 254 mh->key.actions, 255 &mh->mod_hdr_id); 256 if (err) 257 goto out_err; 258 259 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) 260 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key); 261 else 262 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key); 263 264 attach_flow: 265 list_add(&flow->mod_hdr, &mh->flows); 266 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) 267 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id; 268 else 269 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id; 270 271 return 0; 272 273 out_err: 274 kfree(mh); 275 return err; 276 } 277 278 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv, 279 struct mlx5e_tc_flow *flow) 280 { 281 struct list_head *next = flow->mod_hdr.next; 282 283 list_del(&flow->mod_hdr); 284 285 if (list_empty(next)) { 286 struct mlx5e_mod_hdr_entry *mh; 287 288 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows); 289 290 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id); 291 hash_del(&mh->mod_hdr_hlist); 292 kfree(mh); 293 } 294 } 295 296 static 297 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex) 298 { 299 struct net_device *netdev; 300 struct mlx5e_priv *priv; 301 302 netdev = __dev_get_by_index(net, ifindex); 303 priv = netdev_priv(netdev); 304 return priv->mdev; 305 } 306 307 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp) 308 { 309 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 310 void *tirc; 311 int err; 312 313 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn); 314 if (err) 315 goto alloc_tdn_err; 316 317 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 318 319 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 320 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]); 321 MLX5_SET(tirc, tirc, transport_domain, hp->tdn); 322 323 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn); 324 if (err) 325 goto create_tir_err; 326 327 return 0; 328 329 create_tir_err: 330 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); 331 alloc_tdn_err: 332 return err; 333 } 334 335 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp) 336 { 337 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn); 338 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); 339 } 340 341 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc) 342 { 343 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn; 344 struct mlx5e_priv *priv = hp->func_priv; 345 int i, ix, sz = MLX5E_INDIR_RQT_SIZE; 346 347 mlx5e_build_default_indir_rqt(indirection_rqt, sz, 348 hp->num_channels); 349 350 for (i = 0; i < sz; i++) { 351 ix = i; 352 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR) 353 ix = mlx5e_bits_invert(i, ilog2(sz)); 354 ix = indirection_rqt[ix]; 355 rqn = hp->pair->rqn[ix]; 356 MLX5_SET(rqtc, rqtc, rq_num[i], rqn); 357 } 358 } 359 360 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp) 361 { 362 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE; 363 struct mlx5e_priv *priv = hp->func_priv; 364 struct mlx5_core_dev *mdev = priv->mdev; 365 void *rqtc; 366 u32 *in; 367 368 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 369 in = kvzalloc(inlen, GFP_KERNEL); 370 if (!in) 371 return -ENOMEM; 372 373 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 374 375 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 376 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 377 378 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc); 379 380 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn); 381 if (!err) 382 hp->indir_rqt.enabled = true; 383 384 kvfree(in); 385 return err; 386 } 387 388 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp) 389 { 390 struct mlx5e_priv *priv = hp->func_priv; 391 u32 in[MLX5_ST_SZ_DW(create_tir_in)]; 392 int tt, i, err; 393 void *tirc; 394 395 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 396 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt); 397 398 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in)); 399 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 400 401 MLX5_SET(tirc, tirc, transport_domain, hp->tdn); 402 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); 403 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn); 404 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false); 405 406 err = mlx5_core_create_tir(hp->func_mdev, in, 407 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]); 408 if (err) { 409 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err); 410 goto err_destroy_tirs; 411 } 412 } 413 return 0; 414 415 err_destroy_tirs: 416 for (i = 0; i < tt; i++) 417 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]); 418 return err; 419 } 420 421 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp) 422 { 423 int tt; 424 425 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 426 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]); 427 } 428 429 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp, 430 struct ttc_params *ttc_params) 431 { 432 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr; 433 int tt; 434 435 memset(ttc_params, 0, sizeof(*ttc_params)); 436 437 ttc_params->any_tt_tirn = hp->tirn; 438 439 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 440 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt]; 441 442 ft_attr->max_fte = MLX5E_NUM_TT; 443 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL; 444 ft_attr->prio = MLX5E_TC_PRIO; 445 } 446 447 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp) 448 { 449 struct mlx5e_priv *priv = hp->func_priv; 450 struct ttc_params ttc_params; 451 int err; 452 453 err = mlx5e_hairpin_create_indirect_rqt(hp); 454 if (err) 455 return err; 456 457 err = mlx5e_hairpin_create_indirect_tirs(hp); 458 if (err) 459 goto err_create_indirect_tirs; 460 461 mlx5e_hairpin_set_ttc_params(hp, &ttc_params); 462 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc); 463 if (err) 464 goto err_create_ttc_table; 465 466 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n", 467 hp->num_channels, hp->ttc.ft.t->id); 468 469 return 0; 470 471 err_create_ttc_table: 472 mlx5e_hairpin_destroy_indirect_tirs(hp); 473 err_create_indirect_tirs: 474 mlx5e_destroy_rqt(priv, &hp->indir_rqt); 475 476 return err; 477 } 478 479 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp) 480 { 481 struct mlx5e_priv *priv = hp->func_priv; 482 483 mlx5e_destroy_ttc_table(priv, &hp->ttc); 484 mlx5e_hairpin_destroy_indirect_tirs(hp); 485 mlx5e_destroy_rqt(priv, &hp->indir_rqt); 486 } 487 488 static struct mlx5e_hairpin * 489 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params, 490 int peer_ifindex) 491 { 492 struct mlx5_core_dev *func_mdev, *peer_mdev; 493 struct mlx5e_hairpin *hp; 494 struct mlx5_hairpin *pair; 495 int err; 496 497 hp = kzalloc(sizeof(*hp), GFP_KERNEL); 498 if (!hp) 499 return ERR_PTR(-ENOMEM); 500 501 func_mdev = priv->mdev; 502 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); 503 504 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params); 505 if (IS_ERR(pair)) { 506 err = PTR_ERR(pair); 507 goto create_pair_err; 508 } 509 hp->pair = pair; 510 hp->func_mdev = func_mdev; 511 hp->func_priv = priv; 512 hp->num_channels = params->num_channels; 513 514 err = mlx5e_hairpin_create_transport(hp); 515 if (err) 516 goto create_transport_err; 517 518 if (hp->num_channels > 1) { 519 err = mlx5e_hairpin_rss_init(hp); 520 if (err) 521 goto rss_init_err; 522 } 523 524 return hp; 525 526 rss_init_err: 527 mlx5e_hairpin_destroy_transport(hp); 528 create_transport_err: 529 mlx5_core_hairpin_destroy(hp->pair); 530 create_pair_err: 531 kfree(hp); 532 return ERR_PTR(err); 533 } 534 535 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp) 536 { 537 if (hp->num_channels > 1) 538 mlx5e_hairpin_rss_cleanup(hp); 539 mlx5e_hairpin_destroy_transport(hp); 540 mlx5_core_hairpin_destroy(hp->pair); 541 kvfree(hp); 542 } 543 544 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio) 545 { 546 return (peer_vhca_id << 16 | prio); 547 } 548 549 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv, 550 u16 peer_vhca_id, u8 prio) 551 { 552 struct mlx5e_hairpin_entry *hpe; 553 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio); 554 555 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe, 556 hairpin_hlist, hash_key) { 557 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) 558 return hpe; 559 } 560 561 return NULL; 562 } 563 564 #define UNKNOWN_MATCH_PRIO 8 565 566 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv, 567 struct mlx5_flow_spec *spec, u8 *match_prio, 568 struct netlink_ext_ack *extack) 569 { 570 void *headers_c, *headers_v; 571 u8 prio_val, prio_mask = 0; 572 bool vlan_present; 573 574 #ifdef CONFIG_MLX5_CORE_EN_DCB 575 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) { 576 NL_SET_ERR_MSG_MOD(extack, 577 "only PCP trust state supported for hairpin"); 578 return -EOPNOTSUPP; 579 } 580 #endif 581 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers); 582 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); 583 584 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag); 585 if (vlan_present) { 586 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); 587 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); 588 } 589 590 if (!vlan_present || !prio_mask) { 591 prio_val = UNKNOWN_MATCH_PRIO; 592 } else if (prio_mask != 0x7) { 593 NL_SET_ERR_MSG_MOD(extack, 594 "masked priority match not supported for hairpin"); 595 return -EOPNOTSUPP; 596 } 597 598 *match_prio = prio_val; 599 return 0; 600 } 601 602 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv, 603 struct mlx5e_tc_flow *flow, 604 struct mlx5e_tc_flow_parse_attr *parse_attr, 605 struct netlink_ext_ack *extack) 606 { 607 int peer_ifindex = parse_attr->mirred_ifindex[0]; 608 struct mlx5_hairpin_params params; 609 struct mlx5_core_dev *peer_mdev; 610 struct mlx5e_hairpin_entry *hpe; 611 struct mlx5e_hairpin *hp; 612 u64 link_speed64; 613 u32 link_speed; 614 u8 match_prio; 615 u16 peer_id; 616 int err; 617 618 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); 619 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) { 620 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported"); 621 return -EOPNOTSUPP; 622 } 623 624 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id); 625 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio, 626 extack); 627 if (err) 628 return err; 629 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio); 630 if (hpe) 631 goto attach_flow; 632 633 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL); 634 if (!hpe) 635 return -ENOMEM; 636 637 INIT_LIST_HEAD(&hpe->flows); 638 hpe->peer_vhca_id = peer_id; 639 hpe->prio = match_prio; 640 641 params.log_data_size = 15; 642 params.log_data_size = min_t(u8, params.log_data_size, 643 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz)); 644 params.log_data_size = max_t(u8, params.log_data_size, 645 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz)); 646 647 params.log_num_packets = params.log_data_size - 648 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev); 649 params.log_num_packets = min_t(u8, params.log_num_packets, 650 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets)); 651 652 params.q_counter = priv->q_counter; 653 /* set hairpin pair per each 50Gbs share of the link */ 654 mlx5e_port_max_linkspeed(priv->mdev, &link_speed); 655 link_speed = max_t(u32, link_speed, 50000); 656 link_speed64 = link_speed; 657 do_div(link_speed64, 50000); 658 params.num_channels = link_speed64; 659 660 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex); 661 if (IS_ERR(hp)) { 662 err = PTR_ERR(hp); 663 goto create_hairpin_err; 664 } 665 666 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n", 667 hp->tirn, hp->pair->rqn[0], 668 dev_name(hp->pair->peer_mdev->device), 669 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets); 670 671 hpe->hp = hp; 672 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist, 673 hash_hairpin_info(peer_id, match_prio)); 674 675 attach_flow: 676 if (hpe->hp->num_channels > 1) { 677 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS; 678 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t; 679 } else { 680 flow->nic_attr->hairpin_tirn = hpe->hp->tirn; 681 } 682 list_add(&flow->hairpin, &hpe->flows); 683 684 return 0; 685 686 create_hairpin_err: 687 kfree(hpe); 688 return err; 689 } 690 691 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv, 692 struct mlx5e_tc_flow *flow) 693 { 694 struct list_head *next = flow->hairpin.next; 695 696 list_del(&flow->hairpin); 697 698 /* no more hairpin flows for us, release the hairpin pair */ 699 if (list_empty(next)) { 700 struct mlx5e_hairpin_entry *hpe; 701 702 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows); 703 704 netdev_dbg(priv->netdev, "del hairpin: peer %s\n", 705 dev_name(hpe->hp->pair->peer_mdev->device)); 706 707 mlx5e_hairpin_destroy(hpe->hp); 708 hash_del(&hpe->hairpin_hlist); 709 kfree(hpe); 710 } 711 } 712 713 static int 714 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv, 715 struct mlx5e_tc_flow_parse_attr *parse_attr, 716 struct mlx5e_tc_flow *flow, 717 struct netlink_ext_ack *extack) 718 { 719 struct mlx5_nic_flow_attr *attr = flow->nic_attr; 720 struct mlx5_core_dev *dev = priv->mdev; 721 struct mlx5_flow_destination dest[2] = {}; 722 struct mlx5_flow_act flow_act = { 723 .action = attr->action, 724 .flow_tag = attr->flow_tag, 725 .reformat_id = 0, 726 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND, 727 }; 728 struct mlx5_fc *counter = NULL; 729 bool table_created = false; 730 int err, dest_ix = 0; 731 732 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) { 733 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack); 734 if (err) { 735 goto err_add_hairpin_flow; 736 } 737 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) { 738 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 739 dest[dest_ix].ft = attr->hairpin_ft; 740 } else { 741 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR; 742 dest[dest_ix].tir_num = attr->hairpin_tirn; 743 } 744 dest_ix++; 745 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { 746 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 747 dest[dest_ix].ft = priv->fs.vlan.ft.t; 748 dest_ix++; 749 } 750 751 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 752 counter = mlx5_fc_create(dev, true); 753 if (IS_ERR(counter)) { 754 err = PTR_ERR(counter); 755 goto err_fc_create; 756 } 757 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; 758 dest[dest_ix].counter_id = mlx5_fc_id(counter); 759 dest_ix++; 760 attr->counter = counter; 761 } 762 763 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { 764 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); 765 flow_act.modify_id = attr->mod_hdr_id; 766 kfree(parse_attr->mod_hdr_actions); 767 if (err) 768 goto err_create_mod_hdr_id; 769 } 770 771 if (IS_ERR_OR_NULL(priv->fs.tc.t)) { 772 int tc_grp_size, tc_tbl_size; 773 u32 max_flow_counter; 774 775 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) | 776 MLX5_CAP_GEN(dev, max_flow_counter_15_0); 777 778 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE); 779 780 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS, 781 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size))); 782 783 priv->fs.tc.t = 784 mlx5_create_auto_grouped_flow_table(priv->fs.ns, 785 MLX5E_TC_PRIO, 786 tc_tbl_size, 787 MLX5E_TC_TABLE_NUM_GROUPS, 788 MLX5E_TC_FT_LEVEL, 0); 789 if (IS_ERR(priv->fs.tc.t)) { 790 NL_SET_ERR_MSG_MOD(extack, 791 "Failed to create tc offload table\n"); 792 netdev_err(priv->netdev, 793 "Failed to create tc offload table\n"); 794 err = PTR_ERR(priv->fs.tc.t); 795 goto err_create_ft; 796 } 797 798 table_created = true; 799 } 800 801 if (attr->match_level != MLX5_MATCH_NONE) 802 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; 803 804 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec, 805 &flow_act, dest, dest_ix); 806 807 if (IS_ERR(flow->rule[0])) { 808 err = PTR_ERR(flow->rule[0]); 809 goto err_add_rule; 810 } 811 812 return 0; 813 814 err_add_rule: 815 if (table_created) { 816 mlx5_destroy_flow_table(priv->fs.tc.t); 817 priv->fs.tc.t = NULL; 818 } 819 err_create_ft: 820 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 821 mlx5e_detach_mod_hdr(priv, flow); 822 err_create_mod_hdr_id: 823 mlx5_fc_destroy(dev, counter); 824 err_fc_create: 825 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) 826 mlx5e_hairpin_flow_del(priv, flow); 827 err_add_hairpin_flow: 828 return err; 829 } 830 831 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv, 832 struct mlx5e_tc_flow *flow) 833 { 834 struct mlx5_nic_flow_attr *attr = flow->nic_attr; 835 struct mlx5_fc *counter = NULL; 836 837 counter = attr->counter; 838 mlx5_del_flow_rules(flow->rule[0]); 839 mlx5_fc_destroy(priv->mdev, counter); 840 841 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) { 842 mlx5_destroy_flow_table(priv->fs.tc.t); 843 priv->fs.tc.t = NULL; 844 } 845 846 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 847 mlx5e_detach_mod_hdr(priv, flow); 848 849 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) 850 mlx5e_hairpin_flow_del(priv, flow); 851 } 852 853 static void mlx5e_detach_encap(struct mlx5e_priv *priv, 854 struct mlx5e_tc_flow *flow, int out_index); 855 856 static int mlx5e_attach_encap(struct mlx5e_priv *priv, 857 struct mlx5e_tc_flow *flow, 858 struct net_device *mirred_dev, 859 int out_index, 860 struct netlink_ext_ack *extack, 861 struct net_device **encap_dev, 862 bool *encap_valid); 863 864 static struct mlx5_flow_handle * 865 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw, 866 struct mlx5e_tc_flow *flow, 867 struct mlx5_flow_spec *spec, 868 struct mlx5_esw_flow_attr *attr) 869 { 870 struct mlx5_flow_handle *rule; 871 872 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr); 873 if (IS_ERR(rule)) 874 return rule; 875 876 if (attr->split_count) { 877 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr); 878 if (IS_ERR(flow->rule[1])) { 879 mlx5_eswitch_del_offloaded_rule(esw, rule, attr); 880 return flow->rule[1]; 881 } 882 } 883 884 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; 885 return rule; 886 } 887 888 static void 889 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw, 890 struct mlx5e_tc_flow *flow, 891 struct mlx5_esw_flow_attr *attr) 892 { 893 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED; 894 895 if (attr->split_count) 896 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr); 897 898 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr); 899 } 900 901 static struct mlx5_flow_handle * 902 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw, 903 struct mlx5e_tc_flow *flow, 904 struct mlx5_flow_spec *spec, 905 struct mlx5_esw_flow_attr *slow_attr) 906 { 907 struct mlx5_flow_handle *rule; 908 909 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr)); 910 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 911 slow_attr->split_count = 0; 912 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN; 913 914 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr); 915 if (!IS_ERR(rule)) 916 flow->flags |= MLX5E_TC_FLOW_SLOW; 917 918 return rule; 919 } 920 921 static void 922 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw, 923 struct mlx5e_tc_flow *flow, 924 struct mlx5_esw_flow_attr *slow_attr) 925 { 926 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr)); 927 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 928 slow_attr->split_count = 0; 929 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN; 930 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr); 931 flow->flags &= ~MLX5E_TC_FLOW_SLOW; 932 } 933 934 static void add_unready_flow(struct mlx5e_tc_flow *flow) 935 { 936 struct mlx5_rep_uplink_priv *uplink_priv; 937 struct mlx5e_rep_priv *rpriv; 938 struct mlx5_eswitch *esw; 939 940 esw = flow->priv->mdev->priv.eswitch; 941 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); 942 uplink_priv = &rpriv->uplink_priv; 943 944 flow->flags |= MLX5E_TC_FLOW_NOT_READY; 945 list_add_tail(&flow->unready, &uplink_priv->unready_flows); 946 } 947 948 static void remove_unready_flow(struct mlx5e_tc_flow *flow) 949 { 950 list_del(&flow->unready); 951 flow->flags &= ~MLX5E_TC_FLOW_NOT_READY; 952 } 953 954 static int 955 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv, 956 struct mlx5e_tc_flow *flow, 957 struct netlink_ext_ack *extack) 958 { 959 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 960 u32 max_chain = mlx5_eswitch_get_chain_range(esw); 961 struct mlx5_esw_flow_attr *attr = flow->esw_attr; 962 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; 963 u16 max_prio = mlx5_eswitch_get_prio_range(esw); 964 struct net_device *out_dev, *encap_dev = NULL; 965 struct mlx5_fc *counter = NULL; 966 struct mlx5e_rep_priv *rpriv; 967 struct mlx5e_priv *out_priv; 968 bool encap_valid = true; 969 int err = 0; 970 int out_index; 971 972 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) { 973 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW"); 974 return -EOPNOTSUPP; 975 } 976 977 if (attr->chain > max_chain) { 978 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range"); 979 err = -EOPNOTSUPP; 980 goto err_max_prio_chain; 981 } 982 983 if (attr->prio > max_prio) { 984 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range"); 985 err = -EOPNOTSUPP; 986 goto err_max_prio_chain; 987 } 988 989 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) { 990 int mirred_ifindex; 991 992 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)) 993 continue; 994 995 mirred_ifindex = parse_attr->mirred_ifindex[out_index]; 996 out_dev = __dev_get_by_index(dev_net(priv->netdev), 997 mirred_ifindex); 998 err = mlx5e_attach_encap(priv, flow, out_dev, out_index, 999 extack, &encap_dev, &encap_valid); 1000 if (err) 1001 goto err_attach_encap; 1002 1003 out_priv = netdev_priv(encap_dev); 1004 rpriv = out_priv->ppriv; 1005 attr->dests[out_index].rep = rpriv->rep; 1006 attr->dests[out_index].mdev = out_priv->mdev; 1007 } 1008 1009 err = mlx5_eswitch_add_vlan_action(esw, attr); 1010 if (err) 1011 goto err_add_vlan; 1012 1013 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { 1014 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); 1015 kfree(parse_attr->mod_hdr_actions); 1016 if (err) 1017 goto err_mod_hdr; 1018 } 1019 1020 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 1021 counter = mlx5_fc_create(attr->counter_dev, true); 1022 if (IS_ERR(counter)) { 1023 err = PTR_ERR(counter); 1024 goto err_create_counter; 1025 } 1026 1027 attr->counter = counter; 1028 } 1029 1030 /* we get here if one of the following takes place: 1031 * (1) there's no error 1032 * (2) there's an encap action and we don't have valid neigh 1033 */ 1034 if (!encap_valid) { 1035 /* continue with goto slow path rule instead */ 1036 struct mlx5_esw_flow_attr slow_attr; 1037 1038 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr); 1039 } else { 1040 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr); 1041 } 1042 1043 if (IS_ERR(flow->rule[0])) { 1044 err = PTR_ERR(flow->rule[0]); 1045 goto err_add_rule; 1046 } 1047 1048 return 0; 1049 1050 err_add_rule: 1051 mlx5_fc_destroy(attr->counter_dev, counter); 1052 err_create_counter: 1053 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 1054 mlx5e_detach_mod_hdr(priv, flow); 1055 err_mod_hdr: 1056 mlx5_eswitch_del_vlan_action(esw, attr); 1057 err_add_vlan: 1058 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) 1059 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) 1060 mlx5e_detach_encap(priv, flow, out_index); 1061 err_attach_encap: 1062 err_max_prio_chain: 1063 return err; 1064 } 1065 1066 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv, 1067 struct mlx5e_tc_flow *flow) 1068 { 1069 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 1070 struct mlx5_esw_flow_attr *attr = flow->esw_attr; 1071 struct mlx5_esw_flow_attr slow_attr; 1072 int out_index; 1073 1074 if (flow->flags & MLX5E_TC_FLOW_NOT_READY) { 1075 remove_unready_flow(flow); 1076 kvfree(attr->parse_attr); 1077 return; 1078 } 1079 1080 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { 1081 if (flow->flags & MLX5E_TC_FLOW_SLOW) 1082 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr); 1083 else 1084 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr); 1085 } 1086 1087 mlx5_eswitch_del_vlan_action(esw, attr); 1088 1089 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) 1090 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) 1091 mlx5e_detach_encap(priv, flow, out_index); 1092 kvfree(attr->parse_attr); 1093 1094 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 1095 mlx5e_detach_mod_hdr(priv, flow); 1096 1097 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 1098 mlx5_fc_destroy(attr->counter_dev, attr->counter); 1099 } 1100 1101 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv, 1102 struct mlx5e_encap_entry *e) 1103 { 1104 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 1105 struct mlx5_esw_flow_attr slow_attr, *esw_attr; 1106 struct mlx5_flow_handle *rule; 1107 struct mlx5_flow_spec *spec; 1108 struct encap_flow_item *efi; 1109 struct mlx5e_tc_flow *flow; 1110 int err; 1111 1112 err = mlx5_packet_reformat_alloc(priv->mdev, 1113 e->reformat_type, 1114 e->encap_size, e->encap_header, 1115 MLX5_FLOW_NAMESPACE_FDB, 1116 &e->encap_id); 1117 if (err) { 1118 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n", 1119 err); 1120 return; 1121 } 1122 e->flags |= MLX5_ENCAP_ENTRY_VALID; 1123 mlx5e_rep_queue_neigh_stats_work(priv); 1124 1125 list_for_each_entry(efi, &e->flows, list) { 1126 bool all_flow_encaps_valid = true; 1127 int i; 1128 1129 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]); 1130 esw_attr = flow->esw_attr; 1131 spec = &esw_attr->parse_attr->spec; 1132 1133 esw_attr->dests[efi->index].encap_id = e->encap_id; 1134 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID; 1135 /* Flow can be associated with multiple encap entries. 1136 * Before offloading the flow verify that all of them have 1137 * a valid neighbour. 1138 */ 1139 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) { 1140 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)) 1141 continue; 1142 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) { 1143 all_flow_encaps_valid = false; 1144 break; 1145 } 1146 } 1147 /* Do not offload flows with unresolved neighbors */ 1148 if (!all_flow_encaps_valid) 1149 continue; 1150 /* update from slow path rule to encap rule */ 1151 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr); 1152 if (IS_ERR(rule)) { 1153 err = PTR_ERR(rule); 1154 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n", 1155 err); 1156 continue; 1157 } 1158 1159 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr); 1160 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */ 1161 flow->rule[0] = rule; 1162 } 1163 } 1164 1165 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv, 1166 struct mlx5e_encap_entry *e) 1167 { 1168 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 1169 struct mlx5_esw_flow_attr slow_attr; 1170 struct mlx5_flow_handle *rule; 1171 struct mlx5_flow_spec *spec; 1172 struct encap_flow_item *efi; 1173 struct mlx5e_tc_flow *flow; 1174 int err; 1175 1176 list_for_each_entry(efi, &e->flows, list) { 1177 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]); 1178 spec = &flow->esw_attr->parse_attr->spec; 1179 1180 /* update from encap rule to slow path rule */ 1181 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr); 1182 /* mark the flow's encap dest as non-valid */ 1183 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID; 1184 1185 if (IS_ERR(rule)) { 1186 err = PTR_ERR(rule); 1187 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n", 1188 err); 1189 continue; 1190 } 1191 1192 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr); 1193 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */ 1194 flow->rule[0] = rule; 1195 } 1196 1197 /* we know that the encap is valid */ 1198 e->flags &= ~MLX5_ENCAP_ENTRY_VALID; 1199 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id); 1200 } 1201 1202 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow) 1203 { 1204 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) 1205 return flow->esw_attr->counter; 1206 else 1207 return flow->nic_attr->counter; 1208 } 1209 1210 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe) 1211 { 1212 struct mlx5e_neigh *m_neigh = &nhe->m_neigh; 1213 u64 bytes, packets, lastuse = 0; 1214 struct mlx5e_tc_flow *flow; 1215 struct mlx5e_encap_entry *e; 1216 struct mlx5_fc *counter; 1217 struct neigh_table *tbl; 1218 bool neigh_used = false; 1219 struct neighbour *n; 1220 1221 if (m_neigh->family == AF_INET) 1222 tbl = &arp_tbl; 1223 #if IS_ENABLED(CONFIG_IPV6) 1224 else if (m_neigh->family == AF_INET6) 1225 tbl = &nd_tbl; 1226 #endif 1227 else 1228 return; 1229 1230 list_for_each_entry(e, &nhe->encap_list, encap_list) { 1231 struct encap_flow_item *efi; 1232 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID)) 1233 continue; 1234 list_for_each_entry(efi, &e->flows, list) { 1235 flow = container_of(efi, struct mlx5e_tc_flow, 1236 encaps[efi->index]); 1237 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { 1238 counter = mlx5e_tc_get_counter(flow); 1239 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse); 1240 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) { 1241 neigh_used = true; 1242 break; 1243 } 1244 } 1245 } 1246 if (neigh_used) 1247 break; 1248 } 1249 1250 if (neigh_used) { 1251 nhe->reported_lastuse = jiffies; 1252 1253 /* find the relevant neigh according to the cached device and 1254 * dst ip pair 1255 */ 1256 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev); 1257 if (!n) 1258 return; 1259 1260 neigh_event_send(n, NULL); 1261 neigh_release(n); 1262 } 1263 } 1264 1265 static void mlx5e_detach_encap(struct mlx5e_priv *priv, 1266 struct mlx5e_tc_flow *flow, int out_index) 1267 { 1268 struct list_head *next = flow->encaps[out_index].list.next; 1269 1270 list_del(&flow->encaps[out_index].list); 1271 if (list_empty(next)) { 1272 struct mlx5e_encap_entry *e; 1273 1274 e = list_entry(next, struct mlx5e_encap_entry, flows); 1275 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e); 1276 1277 if (e->flags & MLX5_ENCAP_ENTRY_VALID) 1278 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id); 1279 1280 hash_del_rcu(&e->encap_hlist); 1281 kfree(e->encap_header); 1282 kfree(e); 1283 } 1284 } 1285 1286 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) 1287 { 1288 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch; 1289 1290 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) || 1291 !(flow->flags & MLX5E_TC_FLOW_DUP)) 1292 return; 1293 1294 mutex_lock(&esw->offloads.peer_mutex); 1295 list_del(&flow->peer); 1296 mutex_unlock(&esw->offloads.peer_mutex); 1297 1298 flow->flags &= ~MLX5E_TC_FLOW_DUP; 1299 1300 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow); 1301 kvfree(flow->peer_flow); 1302 flow->peer_flow = NULL; 1303 } 1304 1305 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) 1306 { 1307 struct mlx5_core_dev *dev = flow->priv->mdev; 1308 struct mlx5_devcom *devcom = dev->priv.devcom; 1309 struct mlx5_eswitch *peer_esw; 1310 1311 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 1312 if (!peer_esw) 1313 return; 1314 1315 __mlx5e_tc_del_fdb_peer_flow(flow); 1316 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 1317 } 1318 1319 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv, 1320 struct mlx5e_tc_flow *flow) 1321 { 1322 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { 1323 mlx5e_tc_del_fdb_peer_flow(flow); 1324 mlx5e_tc_del_fdb_flow(priv, flow); 1325 } else { 1326 mlx5e_tc_del_nic_flow(priv, flow); 1327 } 1328 } 1329 1330 1331 static int parse_tunnel_attr(struct mlx5e_priv *priv, 1332 struct mlx5_flow_spec *spec, 1333 struct tc_cls_flower_offload *f, 1334 struct net_device *filter_dev, u8 *match_level) 1335 { 1336 struct netlink_ext_ack *extack = f->common.extack; 1337 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 1338 outer_headers); 1339 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 1340 outer_headers); 1341 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); 1342 struct flow_match_control enc_control; 1343 int err; 1344 1345 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f, 1346 headers_c, headers_v, match_level); 1347 if (err) { 1348 NL_SET_ERR_MSG_MOD(extack, 1349 "failed to parse tunnel attributes"); 1350 return err; 1351 } 1352 1353 flow_rule_match_enc_control(rule, &enc_control); 1354 1355 if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 1356 struct flow_match_ipv4_addrs match; 1357 1358 flow_rule_match_enc_ipv4_addrs(rule, &match); 1359 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1360 src_ipv4_src_ipv6.ipv4_layout.ipv4, 1361 ntohl(match.mask->src)); 1362 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1363 src_ipv4_src_ipv6.ipv4_layout.ipv4, 1364 ntohl(match.key->src)); 1365 1366 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1367 dst_ipv4_dst_ipv6.ipv4_layout.ipv4, 1368 ntohl(match.mask->dst)); 1369 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1370 dst_ipv4_dst_ipv6.ipv4_layout.ipv4, 1371 ntohl(match.key->dst)); 1372 1373 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype); 1374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP); 1375 } else if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 1376 struct flow_match_ipv6_addrs match; 1377 1378 flow_rule_match_enc_ipv6_addrs(rule, &match); 1379 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1380 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1381 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); 1382 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1383 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1384 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); 1385 1386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1387 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1388 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); 1389 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1390 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1391 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); 1392 1393 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype); 1394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6); 1395 } 1396 1397 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) { 1398 struct flow_match_ip match; 1399 1400 flow_rule_match_enc_ip(rule, &match); 1401 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, 1402 match.mask->tos & 0x3); 1403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, 1404 match.key->tos & 0x3); 1405 1406 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, 1407 match.mask->tos >> 2); 1408 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, 1409 match.key->tos >> 2); 1410 1411 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, 1412 match.mask->ttl); 1413 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, 1414 match.key->ttl); 1415 1416 if (match.mask->ttl && 1417 !MLX5_CAP_ESW_FLOWTABLE_FDB 1418 (priv->mdev, 1419 ft_field_support.outer_ipv4_ttl)) { 1420 NL_SET_ERR_MSG_MOD(extack, 1421 "Matching on TTL is not supported"); 1422 return -EOPNOTSUPP; 1423 } 1424 1425 } 1426 1427 /* Enforce DMAC when offloading incoming tunneled flows. 1428 * Flow counters require a match on the DMAC. 1429 */ 1430 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16); 1431 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0); 1432 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1433 dmac_47_16), priv->netdev->dev_addr); 1434 1435 /* let software handle IP fragments */ 1436 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1); 1437 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0); 1438 1439 return 0; 1440 } 1441 1442 static void *get_match_headers_criteria(u32 flags, 1443 struct mlx5_flow_spec *spec) 1444 { 1445 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? 1446 MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 1447 inner_headers) : 1448 MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 1449 outer_headers); 1450 } 1451 1452 static void *get_match_headers_value(u32 flags, 1453 struct mlx5_flow_spec *spec) 1454 { 1455 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? 1456 MLX5_ADDR_OF(fte_match_param, spec->match_value, 1457 inner_headers) : 1458 MLX5_ADDR_OF(fte_match_param, spec->match_value, 1459 outer_headers); 1460 } 1461 1462 static int __parse_cls_flower(struct mlx5e_priv *priv, 1463 struct mlx5_flow_spec *spec, 1464 struct tc_cls_flower_offload *f, 1465 struct net_device *filter_dev, 1466 u8 *match_level, u8 *tunnel_match_level) 1467 { 1468 struct netlink_ext_ack *extack = f->common.extack; 1469 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 1470 outer_headers); 1471 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 1472 outer_headers); 1473 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 1474 misc_parameters); 1475 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 1476 misc_parameters); 1477 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); 1478 struct flow_dissector *dissector = rule->match.dissector; 1479 u16 addr_type = 0; 1480 u8 ip_proto = 0; 1481 1482 *match_level = MLX5_MATCH_NONE; 1483 1484 if (dissector->used_keys & 1485 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1486 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1487 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 1488 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1489 BIT(FLOW_DISSECTOR_KEY_CVLAN) | 1490 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 1491 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 1492 BIT(FLOW_DISSECTOR_KEY_PORTS) | 1493 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | 1494 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | 1495 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | 1496 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | 1497 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | 1498 BIT(FLOW_DISSECTOR_KEY_TCP) | 1499 BIT(FLOW_DISSECTOR_KEY_IP) | 1500 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) { 1501 NL_SET_ERR_MSG_MOD(extack, "Unsupported key"); 1502 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n", 1503 dissector->used_keys); 1504 return -EOPNOTSUPP; 1505 } 1506 1507 if ((flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) || 1508 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) || 1509 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) && 1510 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) { 1511 struct flow_match_control match; 1512 1513 flow_rule_match_enc_control(rule, &match); 1514 switch (match.key->addr_type) { 1515 case FLOW_DISSECTOR_KEY_IPV4_ADDRS: 1516 case FLOW_DISSECTOR_KEY_IPV6_ADDRS: 1517 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level)) 1518 return -EOPNOTSUPP; 1519 break; 1520 default: 1521 return -EOPNOTSUPP; 1522 } 1523 1524 /* In decap flow, header pointers should point to the inner 1525 * headers, outer header were already set by parse_tunnel_attr 1526 */ 1527 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP, 1528 spec); 1529 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP, 1530 spec); 1531 } 1532 1533 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 1534 struct flow_match_basic match; 1535 1536 flow_rule_match_basic(rule, &match); 1537 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype, 1538 ntohs(match.mask->n_proto)); 1539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 1540 ntohs(match.key->n_proto)); 1541 1542 if (match.mask->n_proto) 1543 *match_level = MLX5_MATCH_L2; 1544 } 1545 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) || 1546 is_vlan_dev(filter_dev)) { 1547 struct flow_dissector_key_vlan filter_dev_mask; 1548 struct flow_dissector_key_vlan filter_dev_key; 1549 struct flow_match_vlan match; 1550 1551 if (is_vlan_dev(filter_dev)) { 1552 match.key = &filter_dev_key; 1553 match.key->vlan_id = vlan_dev_vlan_id(filter_dev); 1554 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev); 1555 match.key->vlan_priority = 0; 1556 match.mask = &filter_dev_mask; 1557 memset(match.mask, 0xff, sizeof(*match.mask)); 1558 match.mask->vlan_priority = 0; 1559 } else { 1560 flow_rule_match_vlan(rule, &match); 1561 } 1562 if (match.mask->vlan_id || 1563 match.mask->vlan_priority || 1564 match.mask->vlan_tpid) { 1565 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { 1566 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1567 svlan_tag, 1); 1568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1569 svlan_tag, 1); 1570 } else { 1571 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1572 cvlan_tag, 1); 1573 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1574 cvlan_tag, 1); 1575 } 1576 1577 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, 1578 match.mask->vlan_id); 1579 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, 1580 match.key->vlan_id); 1581 1582 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, 1583 match.mask->vlan_priority); 1584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, 1585 match.key->vlan_priority); 1586 1587 *match_level = MLX5_MATCH_L2; 1588 } 1589 } else if (*match_level != MLX5_MATCH_NONE) { 1590 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1); 1591 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1); 1592 *match_level = MLX5_MATCH_L2; 1593 } 1594 1595 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) { 1596 struct flow_match_vlan match; 1597 1598 flow_rule_match_cvlan(rule, &match); 1599 if (match.mask->vlan_id || 1600 match.mask->vlan_priority || 1601 match.mask->vlan_tpid) { 1602 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { 1603 MLX5_SET(fte_match_set_misc, misc_c, 1604 outer_second_svlan_tag, 1); 1605 MLX5_SET(fte_match_set_misc, misc_v, 1606 outer_second_svlan_tag, 1); 1607 } else { 1608 MLX5_SET(fte_match_set_misc, misc_c, 1609 outer_second_cvlan_tag, 1); 1610 MLX5_SET(fte_match_set_misc, misc_v, 1611 outer_second_cvlan_tag, 1); 1612 } 1613 1614 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid, 1615 match.mask->vlan_id); 1616 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid, 1617 match.key->vlan_id); 1618 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio, 1619 match.mask->vlan_priority); 1620 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio, 1621 match.key->vlan_priority); 1622 1623 *match_level = MLX5_MATCH_L2; 1624 } 1625 } 1626 1627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1628 struct flow_match_eth_addrs match; 1629 1630 flow_rule_match_eth_addrs(rule, &match); 1631 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1632 dmac_47_16), 1633 match.mask->dst); 1634 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1635 dmac_47_16), 1636 match.key->dst); 1637 1638 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1639 smac_47_16), 1640 match.mask->src); 1641 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1642 smac_47_16), 1643 match.key->src); 1644 1645 if (!is_zero_ether_addr(match.mask->src) || 1646 !is_zero_ether_addr(match.mask->dst)) 1647 *match_level = MLX5_MATCH_L2; 1648 } 1649 1650 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { 1651 struct flow_match_control match; 1652 1653 flow_rule_match_control(rule, &match); 1654 addr_type = match.key->addr_type; 1655 1656 /* the HW doesn't support frag first/later */ 1657 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) 1658 return -EOPNOTSUPP; 1659 1660 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) { 1661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1); 1662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1663 match.key->flags & FLOW_DIS_IS_FRAGMENT); 1664 1665 /* the HW doesn't need L3 inline to match on frag=no */ 1666 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT)) 1667 *match_level = MLX5_MATCH_L2; 1668 /* *** L2 attributes parsing up to here *** */ 1669 else 1670 *match_level = MLX5_MATCH_L3; 1671 } 1672 } 1673 1674 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 1675 struct flow_match_basic match; 1676 1677 flow_rule_match_basic(rule, &match); 1678 ip_proto = match.key->ip_proto; 1679 1680 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1681 match.mask->ip_proto); 1682 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1683 match.key->ip_proto); 1684 1685 if (match.mask->ip_proto) 1686 *match_level = MLX5_MATCH_L3; 1687 } 1688 1689 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 1690 struct flow_match_ipv4_addrs match; 1691 1692 flow_rule_match_ipv4_addrs(rule, &match); 1693 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1694 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1695 &match.mask->src, sizeof(match.mask->src)); 1696 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1697 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1698 &match.key->src, sizeof(match.key->src)); 1699 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1700 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1701 &match.mask->dst, sizeof(match.mask->dst)); 1702 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1703 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1704 &match.key->dst, sizeof(match.key->dst)); 1705 1706 if (match.mask->src || match.mask->dst) 1707 *match_level = MLX5_MATCH_L3; 1708 } 1709 1710 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 1711 struct flow_match_ipv6_addrs match; 1712 1713 flow_rule_match_ipv6_addrs(rule, &match); 1714 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1715 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1716 &match.mask->src, sizeof(match.mask->src)); 1717 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1718 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1719 &match.key->src, sizeof(match.key->src)); 1720 1721 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1722 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1723 &match.mask->dst, sizeof(match.mask->dst)); 1724 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1725 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1726 &match.key->dst, sizeof(match.key->dst)); 1727 1728 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY || 1729 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY) 1730 *match_level = MLX5_MATCH_L3; 1731 } 1732 1733 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) { 1734 struct flow_match_ip match; 1735 1736 flow_rule_match_ip(rule, &match); 1737 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, 1738 match.mask->tos & 0x3); 1739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, 1740 match.key->tos & 0x3); 1741 1742 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, 1743 match.mask->tos >> 2); 1744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, 1745 match.key->tos >> 2); 1746 1747 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, 1748 match.mask->ttl); 1749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, 1750 match.key->ttl); 1751 1752 if (match.mask->ttl && 1753 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, 1754 ft_field_support.outer_ipv4_ttl)) { 1755 NL_SET_ERR_MSG_MOD(extack, 1756 "Matching on TTL is not supported"); 1757 return -EOPNOTSUPP; 1758 } 1759 1760 if (match.mask->tos || match.mask->ttl) 1761 *match_level = MLX5_MATCH_L3; 1762 } 1763 1764 /* *** L3 attributes parsing up to here *** */ 1765 1766 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { 1767 struct flow_match_ports match; 1768 1769 flow_rule_match_ports(rule, &match); 1770 switch (ip_proto) { 1771 case IPPROTO_TCP: 1772 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1773 tcp_sport, ntohs(match.mask->src)); 1774 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1775 tcp_sport, ntohs(match.key->src)); 1776 1777 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1778 tcp_dport, ntohs(match.mask->dst)); 1779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1780 tcp_dport, ntohs(match.key->dst)); 1781 break; 1782 1783 case IPPROTO_UDP: 1784 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1785 udp_sport, ntohs(match.mask->src)); 1786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1787 udp_sport, ntohs(match.key->src)); 1788 1789 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1790 udp_dport, ntohs(match.mask->dst)); 1791 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1792 udp_dport, ntohs(match.key->dst)); 1793 break; 1794 default: 1795 NL_SET_ERR_MSG_MOD(extack, 1796 "Only UDP and TCP transports are supported for L4 matching"); 1797 netdev_err(priv->netdev, 1798 "Only UDP and TCP transport are supported\n"); 1799 return -EINVAL; 1800 } 1801 1802 if (match.mask->src || match.mask->dst) 1803 *match_level = MLX5_MATCH_L4; 1804 } 1805 1806 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) { 1807 struct flow_match_tcp match; 1808 1809 flow_rule_match_tcp(rule, &match); 1810 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags, 1811 ntohs(match.mask->flags)); 1812 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags, 1813 ntohs(match.key->flags)); 1814 1815 if (match.mask->flags) 1816 *match_level = MLX5_MATCH_L4; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int parse_cls_flower(struct mlx5e_priv *priv, 1823 struct mlx5e_tc_flow *flow, 1824 struct mlx5_flow_spec *spec, 1825 struct tc_cls_flower_offload *f, 1826 struct net_device *filter_dev) 1827 { 1828 struct netlink_ext_ack *extack = f->common.extack; 1829 struct mlx5_core_dev *dev = priv->mdev; 1830 struct mlx5_eswitch *esw = dev->priv.eswitch; 1831 struct mlx5e_rep_priv *rpriv = priv->ppriv; 1832 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE; 1833 struct mlx5_eswitch_rep *rep; 1834 int err; 1835 1836 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level); 1837 1838 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) { 1839 rep = rpriv->rep; 1840 if (rep->vport != MLX5_VPORT_UPLINK && 1841 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE && 1842 esw->offloads.inline_mode < match_level)) { 1843 NL_SET_ERR_MSG_MOD(extack, 1844 "Flow is not offloaded due to min inline setting"); 1845 netdev_warn(priv->netdev, 1846 "Flow is not offloaded due to min inline setting, required %d actual %d\n", 1847 match_level, esw->offloads.inline_mode); 1848 return -EOPNOTSUPP; 1849 } 1850 } 1851 1852 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { 1853 flow->esw_attr->match_level = match_level; 1854 flow->esw_attr->tunnel_match_level = tunnel_match_level; 1855 } else { 1856 flow->nic_attr->match_level = match_level; 1857 } 1858 1859 return err; 1860 } 1861 1862 struct pedit_headers { 1863 struct ethhdr eth; 1864 struct vlan_hdr vlan; 1865 struct iphdr ip4; 1866 struct ipv6hdr ip6; 1867 struct tcphdr tcp; 1868 struct udphdr udp; 1869 }; 1870 1871 struct pedit_headers_action { 1872 struct pedit_headers vals; 1873 struct pedit_headers masks; 1874 u32 pedits; 1875 }; 1876 1877 static int pedit_header_offsets[] = { 1878 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth), 1879 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4), 1880 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6), 1881 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp), 1882 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp), 1883 }; 1884 1885 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype]) 1886 1887 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset, 1888 struct pedit_headers_action *hdrs) 1889 { 1890 u32 *curr_pmask, *curr_pval; 1891 1892 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset); 1893 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset); 1894 1895 if (*curr_pmask & mask) /* disallow acting twice on the same location */ 1896 goto out_err; 1897 1898 *curr_pmask |= mask; 1899 *curr_pval |= (val & mask); 1900 1901 return 0; 1902 1903 out_err: 1904 return -EOPNOTSUPP; 1905 } 1906 1907 struct mlx5_fields { 1908 u8 field; 1909 u8 size; 1910 u32 offset; 1911 u32 match_offset; 1912 }; 1913 1914 #define OFFLOAD(fw_field, size, field, off, match_field) \ 1915 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \ 1916 offsetof(struct pedit_headers, field) + (off), \ 1917 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)} 1918 1919 /* masked values are the same and there are no rewrites that do not have a 1920 * match. 1921 */ 1922 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \ 1923 type matchmaskx = *(type *)(matchmaskp); \ 1924 type matchvalx = *(type *)(matchvalp); \ 1925 type maskx = *(type *)(maskp); \ 1926 type valx = *(type *)(valp); \ 1927 \ 1928 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \ 1929 matchmaskx)); \ 1930 }) 1931 1932 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp, 1933 void *matchmaskp, int size) 1934 { 1935 bool same = false; 1936 1937 switch (size) { 1938 case sizeof(u8): 1939 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp); 1940 break; 1941 case sizeof(u16): 1942 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp); 1943 break; 1944 case sizeof(u32): 1945 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp); 1946 break; 1947 } 1948 1949 return same; 1950 } 1951 1952 static struct mlx5_fields fields[] = { 1953 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16), 1954 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0), 1955 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16), 1956 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0), 1957 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype), 1958 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid), 1959 1960 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit), 1961 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4), 1962 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1963 1964 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0, 1965 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]), 1966 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0, 1967 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]), 1968 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0, 1969 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]), 1970 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0, 1971 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]), 1972 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0, 1973 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]), 1974 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0, 1975 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]), 1976 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0, 1977 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]), 1978 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0, 1979 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]), 1980 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit), 1981 1982 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport), 1983 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport), 1984 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags), 1985 1986 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport), 1987 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport), 1988 }; 1989 1990 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at 1991 * max from the SW pedit action. On success, attr->num_mod_hdr_actions 1992 * says how many HW actions were actually parsed. 1993 */ 1994 static int offload_pedit_fields(struct pedit_headers_action *hdrs, 1995 struct mlx5e_tc_flow_parse_attr *parse_attr, 1996 u32 *action_flags, 1997 struct netlink_ext_ack *extack) 1998 { 1999 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals; 2000 void *headers_c = get_match_headers_criteria(*action_flags, 2001 &parse_attr->spec); 2002 void *headers_v = get_match_headers_value(*action_flags, 2003 &parse_attr->spec); 2004 int i, action_size, nactions, max_actions, first, last, next_z; 2005 void *s_masks_p, *a_masks_p, *vals_p; 2006 struct mlx5_fields *f; 2007 u8 cmd, field_bsize; 2008 u32 s_mask, a_mask; 2009 unsigned long mask; 2010 __be32 mask_be32; 2011 __be16 mask_be16; 2012 void *action; 2013 2014 set_masks = &hdrs[0].masks; 2015 add_masks = &hdrs[1].masks; 2016 set_vals = &hdrs[0].vals; 2017 add_vals = &hdrs[1].vals; 2018 2019 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto); 2020 action = parse_attr->mod_hdr_actions + 2021 parse_attr->num_mod_hdr_actions * action_size; 2022 2023 max_actions = parse_attr->max_mod_hdr_actions; 2024 nactions = parse_attr->num_mod_hdr_actions; 2025 2026 for (i = 0; i < ARRAY_SIZE(fields); i++) { 2027 bool skip; 2028 2029 f = &fields[i]; 2030 /* avoid seeing bits set from previous iterations */ 2031 s_mask = 0; 2032 a_mask = 0; 2033 2034 s_masks_p = (void *)set_masks + f->offset; 2035 a_masks_p = (void *)add_masks + f->offset; 2036 2037 memcpy(&s_mask, s_masks_p, f->size); 2038 memcpy(&a_mask, a_masks_p, f->size); 2039 2040 if (!s_mask && !a_mask) /* nothing to offload here */ 2041 continue; 2042 2043 if (s_mask && a_mask) { 2044 NL_SET_ERR_MSG_MOD(extack, 2045 "can't set and add to the same HW field"); 2046 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field); 2047 return -EOPNOTSUPP; 2048 } 2049 2050 if (nactions == max_actions) { 2051 NL_SET_ERR_MSG_MOD(extack, 2052 "too many pedit actions, can't offload"); 2053 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions); 2054 return -EOPNOTSUPP; 2055 } 2056 2057 skip = false; 2058 if (s_mask) { 2059 void *match_mask = headers_c + f->match_offset; 2060 void *match_val = headers_v + f->match_offset; 2061 2062 cmd = MLX5_ACTION_TYPE_SET; 2063 mask = s_mask; 2064 vals_p = (void *)set_vals + f->offset; 2065 /* don't rewrite if we have a match on the same value */ 2066 if (cmp_val_mask(vals_p, s_masks_p, match_val, 2067 match_mask, f->size)) 2068 skip = true; 2069 /* clear to denote we consumed this field */ 2070 memset(s_masks_p, 0, f->size); 2071 } else { 2072 u32 zero = 0; 2073 2074 cmd = MLX5_ACTION_TYPE_ADD; 2075 mask = a_mask; 2076 vals_p = (void *)add_vals + f->offset; 2077 /* add 0 is no change */ 2078 if (!memcmp(vals_p, &zero, f->size)) 2079 skip = true; 2080 /* clear to denote we consumed this field */ 2081 memset(a_masks_p, 0, f->size); 2082 } 2083 if (skip) 2084 continue; 2085 2086 field_bsize = f->size * BITS_PER_BYTE; 2087 2088 if (field_bsize == 32) { 2089 mask_be32 = *(__be32 *)&mask; 2090 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32)); 2091 } else if (field_bsize == 16) { 2092 mask_be16 = *(__be16 *)&mask; 2093 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16)); 2094 } 2095 2096 first = find_first_bit(&mask, field_bsize); 2097 next_z = find_next_zero_bit(&mask, field_bsize, first); 2098 last = find_last_bit(&mask, field_bsize); 2099 if (first < next_z && next_z < last) { 2100 NL_SET_ERR_MSG_MOD(extack, 2101 "rewrite of few sub-fields isn't supported"); 2102 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n", 2103 mask); 2104 return -EOPNOTSUPP; 2105 } 2106 2107 MLX5_SET(set_action_in, action, action_type, cmd); 2108 MLX5_SET(set_action_in, action, field, f->field); 2109 2110 if (cmd == MLX5_ACTION_TYPE_SET) { 2111 MLX5_SET(set_action_in, action, offset, first); 2112 /* length is num of bits to be written, zero means length of 32 */ 2113 MLX5_SET(set_action_in, action, length, (last - first + 1)); 2114 } 2115 2116 if (field_bsize == 32) 2117 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first); 2118 else if (field_bsize == 16) 2119 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first); 2120 else if (field_bsize == 8) 2121 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first); 2122 2123 action += action_size; 2124 nactions++; 2125 } 2126 2127 parse_attr->num_mod_hdr_actions = nactions; 2128 return 0; 2129 } 2130 2131 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev, 2132 int namespace) 2133 { 2134 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */ 2135 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions); 2136 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */ 2137 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions); 2138 } 2139 2140 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv, 2141 struct pedit_headers_action *hdrs, 2142 int namespace, 2143 struct mlx5e_tc_flow_parse_attr *parse_attr) 2144 { 2145 int nkeys, action_size, max_actions; 2146 2147 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits + 2148 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits; 2149 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto); 2150 2151 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace); 2152 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */ 2153 max_actions = min(max_actions, nkeys * 16); 2154 2155 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL); 2156 if (!parse_attr->mod_hdr_actions) 2157 return -ENOMEM; 2158 2159 parse_attr->max_mod_hdr_actions = max_actions; 2160 return 0; 2161 } 2162 2163 static const struct pedit_headers zero_masks = {}; 2164 2165 static int parse_tc_pedit_action(struct mlx5e_priv *priv, 2166 const struct flow_action_entry *act, int namespace, 2167 struct mlx5e_tc_flow_parse_attr *parse_attr, 2168 struct pedit_headers_action *hdrs, 2169 struct netlink_ext_ack *extack) 2170 { 2171 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1; 2172 int err = -EOPNOTSUPP; 2173 u32 mask, val, offset; 2174 u8 htype; 2175 2176 htype = act->mangle.htype; 2177 err = -EOPNOTSUPP; /* can't be all optimistic */ 2178 2179 if (htype == FLOW_ACT_MANGLE_UNSPEC) { 2180 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded"); 2181 goto out_err; 2182 } 2183 2184 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) { 2185 NL_SET_ERR_MSG_MOD(extack, 2186 "The pedit offload action is not supported"); 2187 goto out_err; 2188 } 2189 2190 mask = act->mangle.mask; 2191 val = act->mangle.val; 2192 offset = act->mangle.offset; 2193 2194 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]); 2195 if (err) 2196 goto out_err; 2197 2198 hdrs[cmd].pedits++; 2199 2200 return 0; 2201 out_err: 2202 return err; 2203 } 2204 2205 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace, 2206 struct mlx5e_tc_flow_parse_attr *parse_attr, 2207 struct pedit_headers_action *hdrs, 2208 u32 *action_flags, 2209 struct netlink_ext_ack *extack) 2210 { 2211 struct pedit_headers *cmd_masks; 2212 int err; 2213 u8 cmd; 2214 2215 if (!parse_attr->mod_hdr_actions) { 2216 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr); 2217 if (err) 2218 goto out_err; 2219 } 2220 2221 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack); 2222 if (err < 0) 2223 goto out_dealloc_parsed_actions; 2224 2225 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) { 2226 cmd_masks = &hdrs[cmd].masks; 2227 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) { 2228 NL_SET_ERR_MSG_MOD(extack, 2229 "attempt to offload an unsupported field"); 2230 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd); 2231 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS, 2232 16, 1, cmd_masks, sizeof(zero_masks), true); 2233 err = -EOPNOTSUPP; 2234 goto out_dealloc_parsed_actions; 2235 } 2236 } 2237 2238 return 0; 2239 2240 out_dealloc_parsed_actions: 2241 kfree(parse_attr->mod_hdr_actions); 2242 out_err: 2243 return err; 2244 } 2245 2246 static bool csum_offload_supported(struct mlx5e_priv *priv, 2247 u32 action, 2248 u32 update_flags, 2249 struct netlink_ext_ack *extack) 2250 { 2251 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP | 2252 TCA_CSUM_UPDATE_FLAG_UDP; 2253 2254 /* The HW recalcs checksums only if re-writing headers */ 2255 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) { 2256 NL_SET_ERR_MSG_MOD(extack, 2257 "TC csum action is only offloaded with pedit"); 2258 netdev_warn(priv->netdev, 2259 "TC csum action is only offloaded with pedit\n"); 2260 return false; 2261 } 2262 2263 if (update_flags & ~prot_flags) { 2264 NL_SET_ERR_MSG_MOD(extack, 2265 "can't offload TC csum action for some header/s"); 2266 netdev_warn(priv->netdev, 2267 "can't offload TC csum action for some header/s - flags %#x\n", 2268 update_flags); 2269 return false; 2270 } 2271 2272 return true; 2273 } 2274 2275 struct ip_ttl_word { 2276 __u8 ttl; 2277 __u8 protocol; 2278 __sum16 check; 2279 }; 2280 2281 struct ipv6_hoplimit_word { 2282 __be16 payload_len; 2283 __u8 nexthdr; 2284 __u8 hop_limit; 2285 }; 2286 2287 static bool is_action_keys_supported(const struct flow_action_entry *act) 2288 { 2289 u32 mask, offset; 2290 u8 htype; 2291 2292 htype = act->mangle.htype; 2293 offset = act->mangle.offset; 2294 mask = ~act->mangle.mask; 2295 /* For IPv4 & IPv6 header check 4 byte word, 2296 * to determine that modified fields 2297 * are NOT ttl & hop_limit only. 2298 */ 2299 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) { 2300 struct ip_ttl_word *ttl_word = 2301 (struct ip_ttl_word *)&mask; 2302 2303 if (offset != offsetof(struct iphdr, ttl) || 2304 ttl_word->protocol || 2305 ttl_word->check) { 2306 return true; 2307 } 2308 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) { 2309 struct ipv6_hoplimit_word *hoplimit_word = 2310 (struct ipv6_hoplimit_word *)&mask; 2311 2312 if (offset != offsetof(struct ipv6hdr, payload_len) || 2313 hoplimit_word->payload_len || 2314 hoplimit_word->nexthdr) { 2315 return true; 2316 } 2317 } 2318 return false; 2319 } 2320 2321 static bool modify_header_match_supported(struct mlx5_flow_spec *spec, 2322 struct flow_action *flow_action, 2323 u32 actions, 2324 struct netlink_ext_ack *extack) 2325 { 2326 const struct flow_action_entry *act; 2327 bool modify_ip_header; 2328 void *headers_v; 2329 u16 ethertype; 2330 u8 ip_proto; 2331 int i; 2332 2333 headers_v = get_match_headers_value(actions, spec); 2334 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype); 2335 2336 /* for non-IP we only re-write MACs, so we're okay */ 2337 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6) 2338 goto out_ok; 2339 2340 modify_ip_header = false; 2341 flow_action_for_each(i, act, flow_action) { 2342 if (act->id != FLOW_ACTION_MANGLE && 2343 act->id != FLOW_ACTION_ADD) 2344 continue; 2345 2346 if (is_action_keys_supported(act)) { 2347 modify_ip_header = true; 2348 break; 2349 } 2350 } 2351 2352 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol); 2353 if (modify_ip_header && ip_proto != IPPROTO_TCP && 2354 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) { 2355 NL_SET_ERR_MSG_MOD(extack, 2356 "can't offload re-write of non TCP/UDP"); 2357 pr_info("can't offload re-write of ip proto %d\n", ip_proto); 2358 return false; 2359 } 2360 2361 out_ok: 2362 return true; 2363 } 2364 2365 static bool actions_match_supported(struct mlx5e_priv *priv, 2366 struct flow_action *flow_action, 2367 struct mlx5e_tc_flow_parse_attr *parse_attr, 2368 struct mlx5e_tc_flow *flow, 2369 struct netlink_ext_ack *extack) 2370 { 2371 u32 actions; 2372 2373 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) 2374 actions = flow->esw_attr->action; 2375 else 2376 actions = flow->nic_attr->action; 2377 2378 if (flow->flags & MLX5E_TC_FLOW_EGRESS && 2379 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) || 2380 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP))) 2381 return false; 2382 2383 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2384 return modify_header_match_supported(&parse_attr->spec, 2385 flow_action, actions, 2386 extack); 2387 2388 return true; 2389 } 2390 2391 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv) 2392 { 2393 struct mlx5_core_dev *fmdev, *pmdev; 2394 u64 fsystem_guid, psystem_guid; 2395 2396 fmdev = priv->mdev; 2397 pmdev = peer_priv->mdev; 2398 2399 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev); 2400 psystem_guid = mlx5_query_nic_system_image_guid(pmdev); 2401 2402 return (fsystem_guid == psystem_guid); 2403 } 2404 2405 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace, 2406 const struct flow_action_entry *act, 2407 struct mlx5e_tc_flow_parse_attr *parse_attr, 2408 struct pedit_headers_action *hdrs, 2409 u32 *action, struct netlink_ext_ack *extack) 2410 { 2411 u16 mask16 = VLAN_VID_MASK; 2412 u16 val16 = act->vlan.vid & VLAN_VID_MASK; 2413 const struct flow_action_entry pedit_act = { 2414 .id = FLOW_ACTION_MANGLE, 2415 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH, 2416 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI), 2417 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16), 2418 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16), 2419 }; 2420 u8 match_prio_mask, match_prio_val; 2421 void *headers_c, *headers_v; 2422 int err; 2423 2424 headers_c = get_match_headers_criteria(*action, &parse_attr->spec); 2425 headers_v = get_match_headers_value(*action, &parse_attr->spec); 2426 2427 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) && 2428 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) { 2429 NL_SET_ERR_MSG_MOD(extack, 2430 "VLAN rewrite action must have VLAN protocol match"); 2431 return -EOPNOTSUPP; 2432 } 2433 2434 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); 2435 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); 2436 if (act->vlan.prio != (match_prio_val & match_prio_mask)) { 2437 NL_SET_ERR_MSG_MOD(extack, 2438 "Changing VLAN prio is not supported"); 2439 return -EOPNOTSUPP; 2440 } 2441 2442 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, 2443 hdrs, NULL); 2444 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2445 2446 return err; 2447 } 2448 2449 static int 2450 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv, 2451 struct mlx5e_tc_flow_parse_attr *parse_attr, 2452 struct pedit_headers_action *hdrs, 2453 u32 *action, struct netlink_ext_ack *extack) 2454 { 2455 const struct flow_action_entry prio_tag_act = { 2456 .vlan.vid = 0, 2457 .vlan.prio = 2458 MLX5_GET(fte_match_set_lyr_2_4, 2459 get_match_headers_value(*action, 2460 &parse_attr->spec), 2461 first_prio) & 2462 MLX5_GET(fte_match_set_lyr_2_4, 2463 get_match_headers_criteria(*action, 2464 &parse_attr->spec), 2465 first_prio), 2466 }; 2467 2468 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB, 2469 &prio_tag_act, parse_attr, hdrs, action, 2470 extack); 2471 } 2472 2473 static int parse_tc_nic_actions(struct mlx5e_priv *priv, 2474 struct flow_action *flow_action, 2475 struct mlx5e_tc_flow_parse_attr *parse_attr, 2476 struct mlx5e_tc_flow *flow, 2477 struct netlink_ext_ack *extack) 2478 { 2479 struct mlx5_nic_flow_attr *attr = flow->nic_attr; 2480 struct pedit_headers_action hdrs[2] = {}; 2481 const struct flow_action_entry *act; 2482 u32 action = 0; 2483 int err, i; 2484 2485 if (!flow_action_has_entries(flow_action)) 2486 return -EINVAL; 2487 2488 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2489 2490 flow_action_for_each(i, act, flow_action) { 2491 switch (act->id) { 2492 case FLOW_ACTION_DROP: 2493 action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2494 if (MLX5_CAP_FLOWTABLE(priv->mdev, 2495 flow_table_properties_nic_receive.flow_counter)) 2496 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2497 break; 2498 case FLOW_ACTION_MANGLE: 2499 case FLOW_ACTION_ADD: 2500 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL, 2501 parse_attr, hdrs, extack); 2502 if (err) 2503 return err; 2504 2505 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | 2506 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 2507 break; 2508 case FLOW_ACTION_VLAN_MANGLE: 2509 err = add_vlan_rewrite_action(priv, 2510 MLX5_FLOW_NAMESPACE_KERNEL, 2511 act, parse_attr, hdrs, 2512 &action, extack); 2513 if (err) 2514 return err; 2515 2516 break; 2517 case FLOW_ACTION_CSUM: 2518 if (csum_offload_supported(priv, action, 2519 act->csum_flags, 2520 extack)) 2521 break; 2522 2523 return -EOPNOTSUPP; 2524 case FLOW_ACTION_REDIRECT: { 2525 struct net_device *peer_dev = act->dev; 2526 2527 if (priv->netdev->netdev_ops == peer_dev->netdev_ops && 2528 same_hw_devs(priv, netdev_priv(peer_dev))) { 2529 parse_attr->mirred_ifindex[0] = peer_dev->ifindex; 2530 flow->flags |= MLX5E_TC_FLOW_HAIRPIN; 2531 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | 2532 MLX5_FLOW_CONTEXT_ACTION_COUNT; 2533 } else { 2534 NL_SET_ERR_MSG_MOD(extack, 2535 "device is not on same HW, can't offload"); 2536 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n", 2537 peer_dev->name); 2538 return -EINVAL; 2539 } 2540 } 2541 break; 2542 case FLOW_ACTION_MARK: { 2543 u32 mark = act->mark; 2544 2545 if (mark & ~MLX5E_TC_FLOW_ID_MASK) { 2546 NL_SET_ERR_MSG_MOD(extack, 2547 "Bad flow mark - only 16 bit is supported"); 2548 return -EINVAL; 2549 } 2550 2551 attr->flow_tag = mark; 2552 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 2553 } 2554 break; 2555 default: 2556 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); 2557 return -EOPNOTSUPP; 2558 } 2559 } 2560 2561 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || 2562 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { 2563 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL, 2564 parse_attr, hdrs, &action, extack); 2565 if (err) 2566 return err; 2567 /* in case all pedit actions are skipped, remove the MOD_HDR 2568 * flag. 2569 */ 2570 if (parse_attr->num_mod_hdr_actions == 0) { 2571 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2572 kfree(parse_attr->mod_hdr_actions); 2573 } 2574 } 2575 2576 attr->action = action; 2577 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) 2578 return -EOPNOTSUPP; 2579 2580 return 0; 2581 } 2582 2583 struct encap_key { 2584 struct ip_tunnel_key *ip_tun_key; 2585 int tunnel_type; 2586 }; 2587 2588 static inline int cmp_encap_info(struct encap_key *a, 2589 struct encap_key *b) 2590 { 2591 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) || 2592 a->tunnel_type != b->tunnel_type; 2593 } 2594 2595 static inline int hash_encap_info(struct encap_key *key) 2596 { 2597 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key), 2598 key->tunnel_type); 2599 } 2600 2601 2602 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv, 2603 struct net_device *peer_netdev) 2604 { 2605 struct mlx5e_priv *peer_priv; 2606 2607 peer_priv = netdev_priv(peer_netdev); 2608 2609 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) && 2610 mlx5e_eswitch_rep(priv->netdev) && 2611 mlx5e_eswitch_rep(peer_netdev) && 2612 same_hw_devs(priv, peer_priv)); 2613 } 2614 2615 2616 2617 static int mlx5e_attach_encap(struct mlx5e_priv *priv, 2618 struct mlx5e_tc_flow *flow, 2619 struct net_device *mirred_dev, 2620 int out_index, 2621 struct netlink_ext_ack *extack, 2622 struct net_device **encap_dev, 2623 bool *encap_valid) 2624 { 2625 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 2626 struct mlx5_esw_flow_attr *attr = flow->esw_attr; 2627 struct mlx5e_tc_flow_parse_attr *parse_attr; 2628 struct ip_tunnel_info *tun_info; 2629 struct encap_key key, e_key; 2630 struct mlx5e_encap_entry *e; 2631 unsigned short family; 2632 uintptr_t hash_key; 2633 bool found = false; 2634 int err = 0; 2635 2636 parse_attr = attr->parse_attr; 2637 tun_info = &parse_attr->tun_info[out_index]; 2638 family = ip_tunnel_info_af(tun_info); 2639 key.ip_tun_key = &tun_info->key; 2640 key.tunnel_type = mlx5e_tc_tun_get_type(mirred_dev); 2641 2642 hash_key = hash_encap_info(&key); 2643 2644 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e, 2645 encap_hlist, hash_key) { 2646 e_key.ip_tun_key = &e->tun_info.key; 2647 e_key.tunnel_type = e->tunnel_type; 2648 if (!cmp_encap_info(&e_key, &key)) { 2649 found = true; 2650 break; 2651 } 2652 } 2653 2654 /* must verify if encap is valid or not */ 2655 if (found) 2656 goto attach_flow; 2657 2658 e = kzalloc(sizeof(*e), GFP_KERNEL); 2659 if (!e) 2660 return -ENOMEM; 2661 2662 e->tun_info = *tun_info; 2663 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack); 2664 if (err) 2665 goto out_err; 2666 2667 INIT_LIST_HEAD(&e->flows); 2668 2669 if (family == AF_INET) 2670 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e); 2671 else if (family == AF_INET6) 2672 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e); 2673 2674 if (err) 2675 goto out_err; 2676 2677 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key); 2678 2679 attach_flow: 2680 list_add(&flow->encaps[out_index].list, &e->flows); 2681 flow->encaps[out_index].index = out_index; 2682 *encap_dev = e->out_dev; 2683 if (e->flags & MLX5_ENCAP_ENTRY_VALID) { 2684 attr->dests[out_index].encap_id = e->encap_id; 2685 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID; 2686 *encap_valid = true; 2687 } else { 2688 *encap_valid = false; 2689 } 2690 2691 return err; 2692 2693 out_err: 2694 kfree(e); 2695 return err; 2696 } 2697 2698 static int parse_tc_vlan_action(struct mlx5e_priv *priv, 2699 const struct flow_action_entry *act, 2700 struct mlx5_esw_flow_attr *attr, 2701 u32 *action) 2702 { 2703 u8 vlan_idx = attr->total_vlan; 2704 2705 if (vlan_idx >= MLX5_FS_VLAN_DEPTH) 2706 return -EOPNOTSUPP; 2707 2708 switch (act->id) { 2709 case FLOW_ACTION_VLAN_POP: 2710 if (vlan_idx) { 2711 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 2712 MLX5_FS_VLAN_DEPTH)) 2713 return -EOPNOTSUPP; 2714 2715 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2; 2716 } else { 2717 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; 2718 } 2719 break; 2720 case FLOW_ACTION_VLAN_PUSH: 2721 attr->vlan_vid[vlan_idx] = act->vlan.vid; 2722 attr->vlan_prio[vlan_idx] = act->vlan.prio; 2723 attr->vlan_proto[vlan_idx] = act->vlan.proto; 2724 if (!attr->vlan_proto[vlan_idx]) 2725 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q); 2726 2727 if (vlan_idx) { 2728 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 2729 MLX5_FS_VLAN_DEPTH)) 2730 return -EOPNOTSUPP; 2731 2732 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2; 2733 } else { 2734 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) && 2735 (act->vlan.proto != htons(ETH_P_8021Q) || 2736 act->vlan.prio)) 2737 return -EOPNOTSUPP; 2738 2739 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH; 2740 } 2741 break; 2742 default: 2743 return -EINVAL; 2744 } 2745 2746 attr->total_vlan = vlan_idx + 1; 2747 2748 return 0; 2749 } 2750 2751 static int add_vlan_push_action(struct mlx5e_priv *priv, 2752 struct mlx5_esw_flow_attr *attr, 2753 struct net_device **out_dev, 2754 u32 *action) 2755 { 2756 struct net_device *vlan_dev = *out_dev; 2757 struct flow_action_entry vlan_act = { 2758 .id = FLOW_ACTION_VLAN_PUSH, 2759 .vlan.vid = vlan_dev_vlan_id(vlan_dev), 2760 .vlan.proto = vlan_dev_vlan_proto(vlan_dev), 2761 .vlan.prio = 0, 2762 }; 2763 int err; 2764 2765 err = parse_tc_vlan_action(priv, &vlan_act, attr, action); 2766 if (err) 2767 return err; 2768 2769 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), 2770 dev_get_iflink(vlan_dev)); 2771 if (is_vlan_dev(*out_dev)) 2772 err = add_vlan_push_action(priv, attr, out_dev, action); 2773 2774 return err; 2775 } 2776 2777 static int add_vlan_pop_action(struct mlx5e_priv *priv, 2778 struct mlx5_esw_flow_attr *attr, 2779 u32 *action) 2780 { 2781 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev); 2782 struct flow_action_entry vlan_act = { 2783 .id = FLOW_ACTION_VLAN_POP, 2784 }; 2785 int err = 0; 2786 2787 while (nest_level--) { 2788 err = parse_tc_vlan_action(priv, &vlan_act, attr, action); 2789 if (err) 2790 return err; 2791 } 2792 2793 return err; 2794 } 2795 2796 static int parse_tc_fdb_actions(struct mlx5e_priv *priv, 2797 struct flow_action *flow_action, 2798 struct mlx5e_tc_flow *flow, 2799 struct netlink_ext_ack *extack) 2800 { 2801 struct pedit_headers_action hdrs[2] = {}; 2802 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 2803 struct mlx5_esw_flow_attr *attr = flow->esw_attr; 2804 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; 2805 struct mlx5e_rep_priv *rpriv = priv->ppriv; 2806 const struct ip_tunnel_info *info = NULL; 2807 const struct flow_action_entry *act; 2808 bool encap = false; 2809 u32 action = 0; 2810 int err, i; 2811 2812 if (!flow_action_has_entries(flow_action)) 2813 return -EINVAL; 2814 2815 attr->in_rep = rpriv->rep; 2816 attr->in_mdev = priv->mdev; 2817 2818 flow_action_for_each(i, act, flow_action) { 2819 switch (act->id) { 2820 case FLOW_ACTION_DROP: 2821 action |= MLX5_FLOW_CONTEXT_ACTION_DROP | 2822 MLX5_FLOW_CONTEXT_ACTION_COUNT; 2823 break; 2824 case FLOW_ACTION_MANGLE: 2825 case FLOW_ACTION_ADD: 2826 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB, 2827 parse_attr, hdrs, extack); 2828 if (err) 2829 return err; 2830 2831 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2832 attr->split_count = attr->out_count; 2833 break; 2834 case FLOW_ACTION_CSUM: 2835 if (csum_offload_supported(priv, action, 2836 act->csum_flags, extack)) 2837 break; 2838 2839 return -EOPNOTSUPP; 2840 case FLOW_ACTION_REDIRECT: 2841 case FLOW_ACTION_MIRRED: { 2842 struct mlx5e_priv *out_priv; 2843 struct net_device *out_dev; 2844 2845 out_dev = act->dev; 2846 if (!out_dev) { 2847 /* out_dev is NULL when filters with 2848 * non-existing mirred device are replayed to 2849 * the driver. 2850 */ 2851 return -EINVAL; 2852 } 2853 2854 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) { 2855 NL_SET_ERR_MSG_MOD(extack, 2856 "can't support more output ports, can't offload forwarding"); 2857 pr_err("can't support more than %d output ports, can't offload forwarding\n", 2858 attr->out_count); 2859 return -EOPNOTSUPP; 2860 } 2861 2862 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | 2863 MLX5_FLOW_CONTEXT_ACTION_COUNT; 2864 if (netdev_port_same_parent_id(priv->netdev, 2865 out_dev) || 2866 is_merged_eswitch_dev(priv, out_dev)) { 2867 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 2868 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH); 2869 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev); 2870 2871 if (uplink_upper && 2872 netif_is_lag_master(uplink_upper) && 2873 uplink_upper == out_dev) 2874 out_dev = uplink_dev; 2875 2876 if (is_vlan_dev(out_dev)) { 2877 err = add_vlan_push_action(priv, attr, 2878 &out_dev, 2879 &action); 2880 if (err) 2881 return err; 2882 } 2883 if (is_vlan_dev(parse_attr->filter_dev)) { 2884 err = add_vlan_pop_action(priv, attr, 2885 &action); 2886 if (err) 2887 return err; 2888 } 2889 2890 if (!mlx5e_eswitch_rep(out_dev)) 2891 return -EOPNOTSUPP; 2892 2893 out_priv = netdev_priv(out_dev); 2894 rpriv = out_priv->ppriv; 2895 attr->dests[attr->out_count].rep = rpriv->rep; 2896 attr->dests[attr->out_count].mdev = out_priv->mdev; 2897 attr->out_count++; 2898 } else if (encap) { 2899 parse_attr->mirred_ifindex[attr->out_count] = 2900 out_dev->ifindex; 2901 parse_attr->tun_info[attr->out_count] = *info; 2902 encap = false; 2903 attr->dests[attr->out_count].flags |= 2904 MLX5_ESW_DEST_ENCAP; 2905 attr->out_count++; 2906 /* attr->dests[].rep is resolved when we 2907 * handle encap 2908 */ 2909 } else if (parse_attr->filter_dev != priv->netdev) { 2910 /* All mlx5 devices are called to configure 2911 * high level device filters. Therefore, the 2912 * *attempt* to install a filter on invalid 2913 * eswitch should not trigger an explicit error 2914 */ 2915 return -EINVAL; 2916 } else { 2917 NL_SET_ERR_MSG_MOD(extack, 2918 "devices are not on same switch HW, can't offload forwarding"); 2919 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n", 2920 priv->netdev->name, out_dev->name); 2921 return -EINVAL; 2922 } 2923 } 2924 break; 2925 case FLOW_ACTION_TUNNEL_ENCAP: 2926 info = act->tunnel; 2927 if (info) 2928 encap = true; 2929 else 2930 return -EOPNOTSUPP; 2931 2932 break; 2933 case FLOW_ACTION_VLAN_PUSH: 2934 case FLOW_ACTION_VLAN_POP: 2935 if (act->id == FLOW_ACTION_VLAN_PUSH && 2936 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) { 2937 /* Replace vlan pop+push with vlan modify */ 2938 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; 2939 err = add_vlan_rewrite_action(priv, 2940 MLX5_FLOW_NAMESPACE_FDB, 2941 act, parse_attr, hdrs, 2942 &action, extack); 2943 } else { 2944 err = parse_tc_vlan_action(priv, act, attr, &action); 2945 } 2946 if (err) 2947 return err; 2948 2949 attr->split_count = attr->out_count; 2950 break; 2951 case FLOW_ACTION_VLAN_MANGLE: 2952 err = add_vlan_rewrite_action(priv, 2953 MLX5_FLOW_NAMESPACE_FDB, 2954 act, parse_attr, hdrs, 2955 &action, extack); 2956 if (err) 2957 return err; 2958 2959 attr->split_count = attr->out_count; 2960 break; 2961 case FLOW_ACTION_TUNNEL_DECAP: 2962 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2963 break; 2964 case FLOW_ACTION_GOTO: { 2965 u32 dest_chain = act->chain_index; 2966 u32 max_chain = mlx5_eswitch_get_chain_range(esw); 2967 2968 if (dest_chain <= attr->chain) { 2969 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported"); 2970 return -EOPNOTSUPP; 2971 } 2972 if (dest_chain > max_chain) { 2973 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range"); 2974 return -EOPNOTSUPP; 2975 } 2976 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2977 attr->dest_chain = dest_chain; 2978 break; 2979 } 2980 default: 2981 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); 2982 return -EOPNOTSUPP; 2983 } 2984 } 2985 2986 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) && 2987 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) { 2988 /* For prio tag mode, replace vlan pop with rewrite vlan prio 2989 * tag rewrite. 2990 */ 2991 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; 2992 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs, 2993 &action, extack); 2994 if (err) 2995 return err; 2996 } 2997 2998 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || 2999 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { 3000 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB, 3001 parse_attr, hdrs, &action, extack); 3002 if (err) 3003 return err; 3004 /* in case all pedit actions are skipped, remove the MOD_HDR 3005 * flag. we might have set split_count either by pedit or 3006 * pop/push. if there is no pop/push either, reset it too. 3007 */ 3008 if (parse_attr->num_mod_hdr_actions == 0) { 3009 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 3010 kfree(parse_attr->mod_hdr_actions); 3011 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) || 3012 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))) 3013 attr->split_count = 0; 3014 } 3015 } 3016 3017 attr->action = action; 3018 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) 3019 return -EOPNOTSUPP; 3020 3021 if (attr->dest_chain) { 3022 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { 3023 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported"); 3024 return -EOPNOTSUPP; 3025 } 3026 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3027 } 3028 3029 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) { 3030 NL_SET_ERR_MSG_MOD(extack, 3031 "current firmware doesn't support split rule for port mirroring"); 3032 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n"); 3033 return -EOPNOTSUPP; 3034 } 3035 3036 return 0; 3037 } 3038 3039 static void get_flags(int flags, u16 *flow_flags) 3040 { 3041 u16 __flow_flags = 0; 3042 3043 if (flags & MLX5E_TC_INGRESS) 3044 __flow_flags |= MLX5E_TC_FLOW_INGRESS; 3045 if (flags & MLX5E_TC_EGRESS) 3046 __flow_flags |= MLX5E_TC_FLOW_EGRESS; 3047 3048 if (flags & MLX5E_TC_ESW_OFFLOAD) 3049 __flow_flags |= MLX5E_TC_FLOW_ESWITCH; 3050 if (flags & MLX5E_TC_NIC_OFFLOAD) 3051 __flow_flags |= MLX5E_TC_FLOW_NIC; 3052 3053 *flow_flags = __flow_flags; 3054 } 3055 3056 static const struct rhashtable_params tc_ht_params = { 3057 .head_offset = offsetof(struct mlx5e_tc_flow, node), 3058 .key_offset = offsetof(struct mlx5e_tc_flow, cookie), 3059 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie), 3060 .automatic_shrinking = true, 3061 }; 3062 3063 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags) 3064 { 3065 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 3066 struct mlx5e_rep_priv *uplink_rpriv; 3067 3068 if (flags & MLX5E_TC_ESW_OFFLOAD) { 3069 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); 3070 return &uplink_rpriv->uplink_priv.tc_ht; 3071 } else /* NIC offload */ 3072 return &priv->fs.tc.ht; 3073 } 3074 3075 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow) 3076 { 3077 struct mlx5_esw_flow_attr *attr = flow->esw_attr; 3078 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK && 3079 flow->flags & MLX5E_TC_FLOW_INGRESS; 3080 bool act_is_encap = !!(attr->action & 3081 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT); 3082 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom, 3083 MLX5_DEVCOM_ESW_OFFLOADS); 3084 3085 if (!esw_paired) 3086 return false; 3087 3088 if ((mlx5_lag_is_sriov(attr->in_mdev) || 3089 mlx5_lag_is_multipath(attr->in_mdev)) && 3090 (is_rep_ingress || act_is_encap)) 3091 return true; 3092 3093 return false; 3094 } 3095 3096 static int 3097 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size, 3098 struct tc_cls_flower_offload *f, u16 flow_flags, 3099 struct mlx5e_tc_flow_parse_attr **__parse_attr, 3100 struct mlx5e_tc_flow **__flow) 3101 { 3102 struct mlx5e_tc_flow_parse_attr *parse_attr; 3103 struct mlx5e_tc_flow *flow; 3104 int err; 3105 3106 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL); 3107 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL); 3108 if (!parse_attr || !flow) { 3109 err = -ENOMEM; 3110 goto err_free; 3111 } 3112 3113 flow->cookie = f->cookie; 3114 flow->flags = flow_flags; 3115 flow->priv = priv; 3116 3117 *__flow = flow; 3118 *__parse_attr = parse_attr; 3119 3120 return 0; 3121 3122 err_free: 3123 kfree(flow); 3124 kvfree(parse_attr); 3125 return err; 3126 } 3127 3128 static void 3129 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr, 3130 struct mlx5e_priv *priv, 3131 struct mlx5e_tc_flow_parse_attr *parse_attr, 3132 struct tc_cls_flower_offload *f, 3133 struct mlx5_eswitch_rep *in_rep, 3134 struct mlx5_core_dev *in_mdev) 3135 { 3136 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 3137 3138 esw_attr->parse_attr = parse_attr; 3139 esw_attr->chain = f->common.chain_index; 3140 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16; 3141 3142 esw_attr->in_rep = in_rep; 3143 esw_attr->in_mdev = in_mdev; 3144 3145 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) == 3146 MLX5_COUNTER_SOURCE_ESWITCH) 3147 esw_attr->counter_dev = in_mdev; 3148 else 3149 esw_attr->counter_dev = priv->mdev; 3150 } 3151 3152 static struct mlx5e_tc_flow * 3153 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv, 3154 struct tc_cls_flower_offload *f, 3155 u16 flow_flags, 3156 struct net_device *filter_dev, 3157 struct mlx5_eswitch_rep *in_rep, 3158 struct mlx5_core_dev *in_mdev) 3159 { 3160 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); 3161 struct netlink_ext_ack *extack = f->common.extack; 3162 struct mlx5e_tc_flow_parse_attr *parse_attr; 3163 struct mlx5e_tc_flow *flow; 3164 int attr_size, err; 3165 3166 flow_flags |= MLX5E_TC_FLOW_ESWITCH; 3167 attr_size = sizeof(struct mlx5_esw_flow_attr); 3168 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, 3169 &parse_attr, &flow); 3170 if (err) 3171 goto out; 3172 3173 parse_attr->filter_dev = filter_dev; 3174 mlx5e_flow_esw_attr_init(flow->esw_attr, 3175 priv, parse_attr, 3176 f, in_rep, in_mdev); 3177 3178 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, 3179 f, filter_dev); 3180 if (err) 3181 goto err_free; 3182 3183 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack); 3184 if (err) 3185 goto err_free; 3186 3187 err = mlx5e_tc_add_fdb_flow(priv, flow, extack); 3188 if (err) { 3189 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev))) 3190 goto err_free; 3191 3192 add_unready_flow(flow); 3193 } 3194 3195 return flow; 3196 3197 err_free: 3198 kfree(flow); 3199 kvfree(parse_attr); 3200 out: 3201 return ERR_PTR(err); 3202 } 3203 3204 static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f, 3205 struct mlx5e_tc_flow *flow, 3206 u16 flow_flags) 3207 { 3208 struct mlx5e_priv *priv = flow->priv, *peer_priv; 3209 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw; 3210 struct mlx5_devcom *devcom = priv->mdev->priv.devcom; 3211 struct mlx5e_tc_flow_parse_attr *parse_attr; 3212 struct mlx5e_rep_priv *peer_urpriv; 3213 struct mlx5e_tc_flow *peer_flow; 3214 struct mlx5_core_dev *in_mdev; 3215 int err = 0; 3216 3217 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 3218 if (!peer_esw) 3219 return -ENODEV; 3220 3221 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH); 3222 peer_priv = netdev_priv(peer_urpriv->netdev); 3223 3224 /* in_mdev is assigned of which the packet originated from. 3225 * So packets redirected to uplink use the same mdev of the 3226 * original flow and packets redirected from uplink use the 3227 * peer mdev. 3228 */ 3229 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK) 3230 in_mdev = peer_priv->mdev; 3231 else 3232 in_mdev = priv->mdev; 3233 3234 parse_attr = flow->esw_attr->parse_attr; 3235 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags, 3236 parse_attr->filter_dev, 3237 flow->esw_attr->in_rep, in_mdev); 3238 if (IS_ERR(peer_flow)) { 3239 err = PTR_ERR(peer_flow); 3240 goto out; 3241 } 3242 3243 flow->peer_flow = peer_flow; 3244 flow->flags |= MLX5E_TC_FLOW_DUP; 3245 mutex_lock(&esw->offloads.peer_mutex); 3246 list_add_tail(&flow->peer, &esw->offloads.peer_flows); 3247 mutex_unlock(&esw->offloads.peer_mutex); 3248 3249 out: 3250 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 3251 return err; 3252 } 3253 3254 static int 3255 mlx5e_add_fdb_flow(struct mlx5e_priv *priv, 3256 struct tc_cls_flower_offload *f, 3257 u16 flow_flags, 3258 struct net_device *filter_dev, 3259 struct mlx5e_tc_flow **__flow) 3260 { 3261 struct mlx5e_rep_priv *rpriv = priv->ppriv; 3262 struct mlx5_eswitch_rep *in_rep = rpriv->rep; 3263 struct mlx5_core_dev *in_mdev = priv->mdev; 3264 struct mlx5e_tc_flow *flow; 3265 int err; 3266 3267 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep, 3268 in_mdev); 3269 if (IS_ERR(flow)) 3270 return PTR_ERR(flow); 3271 3272 if (is_peer_flow_needed(flow)) { 3273 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags); 3274 if (err) { 3275 mlx5e_tc_del_fdb_flow(priv, flow); 3276 goto out; 3277 } 3278 } 3279 3280 *__flow = flow; 3281 3282 return 0; 3283 3284 out: 3285 return err; 3286 } 3287 3288 static int 3289 mlx5e_add_nic_flow(struct mlx5e_priv *priv, 3290 struct tc_cls_flower_offload *f, 3291 u16 flow_flags, 3292 struct net_device *filter_dev, 3293 struct mlx5e_tc_flow **__flow) 3294 { 3295 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); 3296 struct netlink_ext_ack *extack = f->common.extack; 3297 struct mlx5e_tc_flow_parse_attr *parse_attr; 3298 struct mlx5e_tc_flow *flow; 3299 int attr_size, err; 3300 3301 /* multi-chain not supported for NIC rules */ 3302 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common)) 3303 return -EOPNOTSUPP; 3304 3305 flow_flags |= MLX5E_TC_FLOW_NIC; 3306 attr_size = sizeof(struct mlx5_nic_flow_attr); 3307 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, 3308 &parse_attr, &flow); 3309 if (err) 3310 goto out; 3311 3312 parse_attr->filter_dev = filter_dev; 3313 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, 3314 f, filter_dev); 3315 if (err) 3316 goto err_free; 3317 3318 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack); 3319 if (err) 3320 goto err_free; 3321 3322 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack); 3323 if (err) 3324 goto err_free; 3325 3326 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; 3327 kvfree(parse_attr); 3328 *__flow = flow; 3329 3330 return 0; 3331 3332 err_free: 3333 kfree(flow); 3334 kvfree(parse_attr); 3335 out: 3336 return err; 3337 } 3338 3339 static int 3340 mlx5e_tc_add_flow(struct mlx5e_priv *priv, 3341 struct tc_cls_flower_offload *f, 3342 int flags, 3343 struct net_device *filter_dev, 3344 struct mlx5e_tc_flow **flow) 3345 { 3346 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; 3347 u16 flow_flags; 3348 int err; 3349 3350 get_flags(flags, &flow_flags); 3351 3352 if (!tc_can_offload_extack(priv->netdev, f->common.extack)) 3353 return -EOPNOTSUPP; 3354 3355 if (esw && esw->mode == SRIOV_OFFLOADS) 3356 err = mlx5e_add_fdb_flow(priv, f, flow_flags, 3357 filter_dev, flow); 3358 else 3359 err = mlx5e_add_nic_flow(priv, f, flow_flags, 3360 filter_dev, flow); 3361 3362 return err; 3363 } 3364 3365 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv, 3366 struct tc_cls_flower_offload *f, int flags) 3367 { 3368 struct netlink_ext_ack *extack = f->common.extack; 3369 struct rhashtable *tc_ht = get_tc_ht(priv, flags); 3370 struct mlx5e_tc_flow *flow; 3371 int err = 0; 3372 3373 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); 3374 if (flow) { 3375 NL_SET_ERR_MSG_MOD(extack, 3376 "flow cookie already exists, ignoring"); 3377 netdev_warn_once(priv->netdev, 3378 "flow cookie %lx already exists, ignoring\n", 3379 f->cookie); 3380 err = -EEXIST; 3381 goto out; 3382 } 3383 3384 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow); 3385 if (err) 3386 goto out; 3387 3388 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params); 3389 if (err) 3390 goto err_free; 3391 3392 return 0; 3393 3394 err_free: 3395 mlx5e_tc_del_flow(priv, flow); 3396 kfree(flow); 3397 out: 3398 return err; 3399 } 3400 3401 #define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS) 3402 #define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS) 3403 3404 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags) 3405 { 3406 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK)) 3407 return true; 3408 3409 return false; 3410 } 3411 3412 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv, 3413 struct tc_cls_flower_offload *f, int flags) 3414 { 3415 struct rhashtable *tc_ht = get_tc_ht(priv, flags); 3416 struct mlx5e_tc_flow *flow; 3417 3418 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); 3419 if (!flow || !same_flow_direction(flow, flags)) 3420 return -EINVAL; 3421 3422 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params); 3423 3424 mlx5e_tc_del_flow(priv, flow); 3425 3426 kfree(flow); 3427 3428 return 0; 3429 } 3430 3431 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv, 3432 struct tc_cls_flower_offload *f, int flags) 3433 { 3434 struct mlx5_devcom *devcom = priv->mdev->priv.devcom; 3435 struct rhashtable *tc_ht = get_tc_ht(priv, flags); 3436 struct mlx5_eswitch *peer_esw; 3437 struct mlx5e_tc_flow *flow; 3438 struct mlx5_fc *counter; 3439 u64 lastuse = 0; 3440 u64 packets = 0; 3441 u64 bytes = 0; 3442 3443 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); 3444 if (!flow || !same_flow_direction(flow, flags)) 3445 return -EINVAL; 3446 3447 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { 3448 counter = mlx5e_tc_get_counter(flow); 3449 if (!counter) 3450 return 0; 3451 3452 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse); 3453 } 3454 3455 /* Under multipath it's possible for one rule to be currently 3456 * un-offloaded while the other rule is offloaded. 3457 */ 3458 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 3459 if (!peer_esw) 3460 goto out; 3461 3462 if ((flow->flags & MLX5E_TC_FLOW_DUP) && 3463 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) { 3464 u64 bytes2; 3465 u64 packets2; 3466 u64 lastuse2; 3467 3468 counter = mlx5e_tc_get_counter(flow->peer_flow); 3469 if (!counter) 3470 goto no_peer_counter; 3471 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2); 3472 3473 bytes += bytes2; 3474 packets += packets2; 3475 lastuse = max_t(u64, lastuse, lastuse2); 3476 } 3477 3478 no_peer_counter: 3479 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); 3480 out: 3481 flow_stats_update(&f->stats, bytes, packets, lastuse); 3482 3483 return 0; 3484 } 3485 3486 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv, 3487 struct mlx5e_priv *peer_priv) 3488 { 3489 struct mlx5_core_dev *peer_mdev = peer_priv->mdev; 3490 struct mlx5e_hairpin_entry *hpe; 3491 u16 peer_vhca_id; 3492 int bkt; 3493 3494 if (!same_hw_devs(priv, peer_priv)) 3495 return; 3496 3497 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id); 3498 3499 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) { 3500 if (hpe->peer_vhca_id == peer_vhca_id) 3501 hpe->hp->pair->peer_gone = true; 3502 } 3503 } 3504 3505 static int mlx5e_tc_netdev_event(struct notifier_block *this, 3506 unsigned long event, void *ptr) 3507 { 3508 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 3509 struct mlx5e_flow_steering *fs; 3510 struct mlx5e_priv *peer_priv; 3511 struct mlx5e_tc_table *tc; 3512 struct mlx5e_priv *priv; 3513 3514 if (ndev->netdev_ops != &mlx5e_netdev_ops || 3515 event != NETDEV_UNREGISTER || 3516 ndev->reg_state == NETREG_REGISTERED) 3517 return NOTIFY_DONE; 3518 3519 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb); 3520 fs = container_of(tc, struct mlx5e_flow_steering, tc); 3521 priv = container_of(fs, struct mlx5e_priv, fs); 3522 peer_priv = netdev_priv(ndev); 3523 if (priv == peer_priv || 3524 !(priv->netdev->features & NETIF_F_HW_TC)) 3525 return NOTIFY_DONE; 3526 3527 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv); 3528 3529 return NOTIFY_DONE; 3530 } 3531 3532 int mlx5e_tc_nic_init(struct mlx5e_priv *priv) 3533 { 3534 struct mlx5e_tc_table *tc = &priv->fs.tc; 3535 int err; 3536 3537 hash_init(tc->mod_hdr_tbl); 3538 hash_init(tc->hairpin_tbl); 3539 3540 err = rhashtable_init(&tc->ht, &tc_ht_params); 3541 if (err) 3542 return err; 3543 3544 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event; 3545 if (register_netdevice_notifier(&tc->netdevice_nb)) { 3546 tc->netdevice_nb.notifier_call = NULL; 3547 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n"); 3548 } 3549 3550 return err; 3551 } 3552 3553 static void _mlx5e_tc_del_flow(void *ptr, void *arg) 3554 { 3555 struct mlx5e_tc_flow *flow = ptr; 3556 struct mlx5e_priv *priv = flow->priv; 3557 3558 mlx5e_tc_del_flow(priv, flow); 3559 kfree(flow); 3560 } 3561 3562 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) 3563 { 3564 struct mlx5e_tc_table *tc = &priv->fs.tc; 3565 3566 if (tc->netdevice_nb.notifier_call) 3567 unregister_netdevice_notifier(&tc->netdevice_nb); 3568 3569 rhashtable_destroy(&tc->ht); 3570 3571 if (!IS_ERR_OR_NULL(tc->t)) { 3572 mlx5_destroy_flow_table(tc->t); 3573 tc->t = NULL; 3574 } 3575 } 3576 3577 int mlx5e_tc_esw_init(struct rhashtable *tc_ht) 3578 { 3579 return rhashtable_init(tc_ht, &tc_ht_params); 3580 } 3581 3582 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht) 3583 { 3584 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL); 3585 } 3586 3587 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags) 3588 { 3589 struct rhashtable *tc_ht = get_tc_ht(priv, flags); 3590 3591 return atomic_read(&tc_ht->nelems); 3592 } 3593 3594 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw) 3595 { 3596 struct mlx5e_tc_flow *flow, *tmp; 3597 3598 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer) 3599 __mlx5e_tc_del_fdb_peer_flow(flow); 3600 } 3601 3602 void mlx5e_tc_reoffload_flows_work(struct work_struct *work) 3603 { 3604 struct mlx5_rep_uplink_priv *rpriv = 3605 container_of(work, struct mlx5_rep_uplink_priv, 3606 reoffload_flows_work); 3607 struct mlx5e_tc_flow *flow, *tmp; 3608 3609 rtnl_lock(); 3610 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) { 3611 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL)) 3612 remove_unready_flow(flow); 3613 } 3614 rtnl_unlock(); 3615 } 3616