1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <net/ip6_checksum.h> 38 #include <net/page_pool.h> 39 #include <net/inet_ecn.h> 40 #include "en.h" 41 #include "en_tc.h" 42 #include "eswitch.h" 43 #include "en_rep.h" 44 #include "ipoib/ipoib.h" 45 #include "en_accel/ipsec_rxtx.h" 46 #include "en_accel/tls_rxtx.h" 47 #include "lib/clock.h" 48 #include "en/xdp.h" 49 50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 51 { 52 return config->rx_filter == HWTSTAMP_FILTER_ALL; 53 } 54 55 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq, 56 u32 cqcc, void *data) 57 { 58 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 59 60 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64)); 61 } 62 63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 64 struct mlx5_cqwq *wq, 65 u32 cqcc) 66 { 67 struct mlx5e_cq_decomp *cqd = &rq->cqd; 68 struct mlx5_cqe64 *title = &cqd->title; 69 70 mlx5e_read_cqe_slot(wq, cqcc, title); 71 cqd->left = be32_to_cpu(title->byte_cnt); 72 cqd->wqe_counter = be16_to_cpu(title->wqe_counter); 73 rq->stats->cqe_compress_blks++; 74 } 75 76 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq, 77 struct mlx5e_cq_decomp *cqd, 78 u32 cqcc) 79 { 80 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr); 81 cqd->mini_arr_idx = 0; 82 } 83 84 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n) 85 { 86 u32 cqcc = wq->cc; 87 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1; 88 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 89 u32 wq_sz = mlx5_cqwq_get_size(wq); 90 u32 ci_top = min_t(u32, wq_sz, ci + n); 91 92 for (; ci < ci_top; ci++, n--) { 93 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 94 95 cqe->op_own = op_own; 96 } 97 98 if (unlikely(ci == wq_sz)) { 99 op_own = !op_own; 100 for (ci = 0; ci < n; ci++) { 101 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 102 103 cqe->op_own = op_own; 104 } 105 } 106 } 107 108 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 109 struct mlx5_cqwq *wq, 110 u32 cqcc) 111 { 112 struct mlx5e_cq_decomp *cqd = &rq->cqd; 113 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx]; 114 struct mlx5_cqe64 *title = &cqd->title; 115 116 title->byte_cnt = mini_cqe->byte_cnt; 117 title->check_sum = mini_cqe->checksum; 118 title->op_own &= 0xf0; 119 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz); 120 title->wqe_counter = cpu_to_be16(cqd->wqe_counter); 121 122 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 123 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title); 124 else 125 cqd->wqe_counter = 126 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1); 127 } 128 129 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 130 struct mlx5_cqwq *wq, 131 u32 cqcc) 132 { 133 struct mlx5e_cq_decomp *cqd = &rq->cqd; 134 135 mlx5e_decompress_cqe(rq, wq, cqcc); 136 cqd->title.rss_hash_type = 0; 137 cqd->title.rss_hash_result = 0; 138 } 139 140 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 141 struct mlx5_cqwq *wq, 142 int update_owner_only, 143 int budget_rem) 144 { 145 struct mlx5e_cq_decomp *cqd = &rq->cqd; 146 u32 cqcc = wq->cc + update_owner_only; 147 u32 cqe_count; 148 u32 i; 149 150 cqe_count = min_t(u32, cqd->left, budget_rem); 151 152 for (i = update_owner_only; i < cqe_count; 153 i++, cqd->mini_arr_idx++, cqcc++) { 154 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 155 mlx5e_read_mini_arr_slot(wq, cqd, cqcc); 156 157 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc); 158 rq->handle_rx_cqe(rq, &cqd->title); 159 } 160 mlx5e_cqes_update_owner(wq, cqcc - wq->cc); 161 wq->cc = cqcc; 162 cqd->left -= cqe_count; 163 rq->stats->cqe_compress_pkts += cqe_count; 164 165 return cqe_count; 166 } 167 168 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 169 struct mlx5_cqwq *wq, 170 int budget_rem) 171 { 172 struct mlx5e_cq_decomp *cqd = &rq->cqd; 173 u32 cc = wq->cc; 174 175 mlx5e_read_title_slot(rq, wq, cc); 176 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1); 177 mlx5e_decompress_cqe(rq, wq, cc); 178 rq->handle_rx_cqe(rq, &cqd->title); 179 cqd->mini_arr_idx++; 180 181 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1; 182 } 183 184 static inline bool mlx5e_page_is_reserved(struct page *page) 185 { 186 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 187 } 188 189 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 190 struct mlx5e_dma_info *dma_info) 191 { 192 struct mlx5e_page_cache *cache = &rq->page_cache; 193 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 194 struct mlx5e_rq_stats *stats = rq->stats; 195 196 if (tail_next == cache->head) { 197 stats->cache_full++; 198 return false; 199 } 200 201 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 202 stats->cache_waive++; 203 return false; 204 } 205 206 cache->page_cache[cache->tail] = *dma_info; 207 cache->tail = tail_next; 208 return true; 209 } 210 211 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 212 struct mlx5e_dma_info *dma_info) 213 { 214 struct mlx5e_page_cache *cache = &rq->page_cache; 215 struct mlx5e_rq_stats *stats = rq->stats; 216 217 if (unlikely(cache->head == cache->tail)) { 218 stats->cache_empty++; 219 return false; 220 } 221 222 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 223 stats->cache_busy++; 224 return false; 225 } 226 227 *dma_info = cache->page_cache[cache->head]; 228 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 229 stats->cache_reuse++; 230 231 dma_sync_single_for_device(rq->pdev, dma_info->addr, 232 PAGE_SIZE, 233 DMA_FROM_DEVICE); 234 return true; 235 } 236 237 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 238 struct mlx5e_dma_info *dma_info) 239 { 240 if (mlx5e_rx_cache_get(rq, dma_info)) 241 return 0; 242 243 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool); 244 if (unlikely(!dma_info->page)) 245 return -ENOMEM; 246 247 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, 248 PAGE_SIZE, rq->buff.map_dir); 249 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 250 put_page(dma_info->page); 251 dma_info->page = NULL; 252 return -ENOMEM; 253 } 254 255 return 0; 256 } 257 258 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info) 259 { 260 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir); 261 } 262 263 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 264 bool recycle) 265 { 266 if (likely(recycle)) { 267 if (mlx5e_rx_cache_put(rq, dma_info)) 268 return; 269 270 mlx5e_page_dma_unmap(rq, dma_info); 271 page_pool_recycle_direct(rq->page_pool, dma_info->page); 272 } else { 273 mlx5e_page_dma_unmap(rq, dma_info); 274 put_page(dma_info->page); 275 } 276 } 277 278 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, 279 struct mlx5e_wqe_frag_info *frag) 280 { 281 int err = 0; 282 283 if (!frag->offset) 284 /* On first frag (offset == 0), replenish page (dma_info actually). 285 * Other frags that point to the same dma_info (with a different 286 * offset) should just use the new one without replenishing again 287 * by themselves. 288 */ 289 err = mlx5e_page_alloc_mapped(rq, frag->di); 290 291 return err; 292 } 293 294 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq, 295 struct mlx5e_wqe_frag_info *frag, 296 bool recycle) 297 { 298 if (frag->last_in_page) 299 mlx5e_page_release(rq, frag->di, recycle); 300 } 301 302 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix) 303 { 304 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags]; 305 } 306 307 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe, 308 u16 ix) 309 { 310 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix); 311 int err; 312 int i; 313 314 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) { 315 err = mlx5e_get_rx_frag(rq, frag); 316 if (unlikely(err)) 317 goto free_frags; 318 319 wqe->data[i].addr = cpu_to_be64(frag->di->addr + 320 frag->offset + rq->buff.headroom); 321 } 322 323 return 0; 324 325 free_frags: 326 while (--i >= 0) 327 mlx5e_put_rx_frag(rq, --frag, true); 328 329 return err; 330 } 331 332 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 333 struct mlx5e_wqe_frag_info *wi, 334 bool recycle) 335 { 336 int i; 337 338 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++) 339 mlx5e_put_rx_frag(rq, wi, recycle); 340 } 341 342 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 343 { 344 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix); 345 346 mlx5e_free_rx_wqe(rq, wi, false); 347 } 348 349 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk) 350 { 351 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 352 int err; 353 int i; 354 355 for (i = 0; i < wqe_bulk; i++) { 356 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i); 357 358 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i); 359 if (unlikely(err)) 360 goto free_wqes; 361 } 362 363 return 0; 364 365 free_wqes: 366 while (--i >= 0) 367 mlx5e_dealloc_rx_wqe(rq, ix + i); 368 369 return err; 370 } 371 372 static inline void 373 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb, 374 struct mlx5e_dma_info *di, u32 frag_offset, u32 len, 375 unsigned int truesize) 376 { 377 dma_sync_single_for_cpu(rq->pdev, 378 di->addr + frag_offset, 379 len, DMA_FROM_DEVICE); 380 page_ref_inc(di->page); 381 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 382 di->page, frag_offset, len, truesize); 383 } 384 385 static inline void 386 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb, 387 struct mlx5e_dma_info *dma_info, 388 int offset_from, u32 headlen) 389 { 390 const void *from = page_address(dma_info->page) + offset_from; 391 /* Aligning len to sizeof(long) optimizes memcpy performance */ 392 unsigned int len = ALIGN(headlen, sizeof(long)); 393 394 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len, 395 DMA_FROM_DEVICE); 396 skb_copy_to_linear_data(skb, from, len); 397 } 398 399 static void 400 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle) 401 { 402 const bool no_xdp_xmit = 403 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 404 struct mlx5e_dma_info *dma_info = wi->umr.dma_info; 405 int i; 406 407 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) 408 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) 409 mlx5e_page_release(rq, &dma_info[i], recycle); 410 } 411 412 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n) 413 { 414 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 415 416 do { 417 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head); 418 419 mlx5_wq_ll_push(wq, next_wqe_index); 420 } while (--n); 421 422 /* ensure wqes are visible to device before updating doorbell record */ 423 dma_wmb(); 424 425 mlx5_wq_ll_update_db_record(wq); 426 } 427 428 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq) 429 { 430 return mlx5_wq_cyc_get_ctr_wrap_cnt(&sq->wq, sq->pc); 431 } 432 433 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq, 434 struct mlx5_wq_cyc *wq, 435 u16 pi, u16 nnops) 436 { 437 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi]; 438 439 edge_wi = wi + nnops; 440 441 /* fill sq frag edge with nops to avoid wqe wrapping two pages */ 442 for (; wi < edge_wi; wi++) { 443 wi->opcode = MLX5_OPCODE_NOP; 444 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 445 } 446 } 447 448 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 449 { 450 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 451 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 452 struct mlx5e_icosq *sq = &rq->channel->icosq; 453 struct mlx5_wq_cyc *wq = &sq->wq; 454 struct mlx5e_umr_wqe *umr_wqe; 455 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1); 456 u16 pi, contig_wqebbs_room; 457 int err; 458 int i; 459 460 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 461 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); 462 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) { 463 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room); 464 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 465 } 466 467 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi); 468 if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2)) 469 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, 470 offsetof(struct mlx5e_umr_wqe, inline_mtts)); 471 472 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 473 err = mlx5e_page_alloc_mapped(rq, dma_info); 474 if (unlikely(err)) 475 goto err_unmap; 476 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 477 } 478 479 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 480 wi->consumed_strides = 0; 481 482 umr_wqe->ctrl.opmod_idx_opcode = 483 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 484 MLX5_OPCODE_UMR); 485 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset); 486 487 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 488 sq->pc += MLX5E_UMR_WQEBBS; 489 490 sq->doorbell_cseg = &umr_wqe->ctrl; 491 492 return 0; 493 494 err_unmap: 495 while (--i >= 0) { 496 dma_info--; 497 mlx5e_page_release(rq, dma_info, true); 498 } 499 rq->stats->buff_alloc_err++; 500 501 return err; 502 } 503 504 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 505 { 506 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 507 /* Don't recycle, this function is called on rq/netdev close */ 508 mlx5e_free_rx_mpwqe(rq, wi, false); 509 } 510 511 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 512 { 513 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 514 u8 wqe_bulk; 515 int err; 516 517 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 518 return false; 519 520 wqe_bulk = rq->wqe.info.wqe_bulk; 521 522 if (mlx5_wq_cyc_missing(wq) < wqe_bulk) 523 return false; 524 525 do { 526 u16 head = mlx5_wq_cyc_get_head(wq); 527 528 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk); 529 if (unlikely(err)) { 530 rq->stats->buff_alloc_err++; 531 break; 532 } 533 534 mlx5_wq_cyc_push_n(wq, wqe_bulk); 535 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk); 536 537 /* ensure wqes are visible to device before updating doorbell record */ 538 dma_wmb(); 539 540 mlx5_wq_cyc_update_db_record(wq); 541 542 return !!err; 543 } 544 545 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 546 { 547 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 548 struct mlx5_cqe64 *cqe; 549 u8 completed_umr = 0; 550 u16 sqcc; 551 int i; 552 553 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) 554 return; 555 556 cqe = mlx5_cqwq_get_cqe(&cq->wq); 557 if (likely(!cqe)) 558 return; 559 560 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 561 * otherwise a cq overrun may occur 562 */ 563 sqcc = sq->cc; 564 565 i = 0; 566 do { 567 u16 wqe_counter; 568 bool last_wqe; 569 570 mlx5_cqwq_pop(&cq->wq); 571 572 wqe_counter = be16_to_cpu(cqe->wqe_counter); 573 574 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) { 575 netdev_WARN_ONCE(cq->channel->netdev, 576 "Bad OP in ICOSQ CQE: 0x%x\n", get_cqe_opcode(cqe)); 577 break; 578 } 579 do { 580 struct mlx5e_sq_wqe_info *wi; 581 u16 ci; 582 583 last_wqe = (sqcc == wqe_counter); 584 585 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); 586 wi = &sq->db.ico_wqe[ci]; 587 588 if (likely(wi->opcode == MLX5_OPCODE_UMR)) { 589 sqcc += MLX5E_UMR_WQEBBS; 590 completed_umr++; 591 } else if (likely(wi->opcode == MLX5_OPCODE_NOP)) { 592 sqcc++; 593 } else { 594 netdev_WARN_ONCE(cq->channel->netdev, 595 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", 596 wi->opcode); 597 } 598 599 } while (!last_wqe); 600 601 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 602 603 sq->cc = sqcc; 604 605 mlx5_cqwq_update_db_record(&cq->wq); 606 607 if (likely(completed_umr)) { 608 mlx5e_post_rx_mpwqe(rq, completed_umr); 609 rq->mpwqe.umr_in_progress -= completed_umr; 610 } 611 } 612 613 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 614 { 615 struct mlx5e_icosq *sq = &rq->channel->icosq; 616 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 617 u8 missing, i; 618 u16 head; 619 620 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 621 return false; 622 623 mlx5e_poll_ico_cq(&sq->cq, rq); 624 625 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress; 626 627 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk)) 628 rq->stats->congst_umr++; 629 630 #define UMR_WQE_BULK (2) 631 if (likely(missing < UMR_WQE_BULK)) 632 return false; 633 634 head = rq->mpwqe.actual_wq_head; 635 i = missing; 636 do { 637 if (unlikely(mlx5e_alloc_rx_mpwqe(rq, head))) 638 break; 639 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 640 } while (--i); 641 642 rq->mpwqe.umr_last_bulk = missing - i; 643 if (sq->doorbell_cseg) { 644 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg); 645 sq->doorbell_cseg = NULL; 646 } 647 648 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk; 649 rq->mpwqe.actual_wq_head = head; 650 651 return false; 652 } 653 654 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) 655 { 656 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 657 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 658 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 659 660 tcp->check = 0; 661 tcp->psh = get_cqe_lro_tcppsh(cqe); 662 663 if (tcp_ack) { 664 tcp->ack = 1; 665 tcp->ack_seq = cqe->lro_ack_seq_num; 666 tcp->window = cqe->lro_tcp_win; 667 } 668 } 669 670 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 671 u32 cqe_bcnt) 672 { 673 struct ethhdr *eth = (struct ethhdr *)(skb->data); 674 struct tcphdr *tcp; 675 int network_depth = 0; 676 __wsum check; 677 __be16 proto; 678 u16 tot_len; 679 void *ip_p; 680 681 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 682 683 tot_len = cqe_bcnt - network_depth; 684 ip_p = skb->data + network_depth; 685 686 if (proto == htons(ETH_P_IP)) { 687 struct iphdr *ipv4 = ip_p; 688 689 tcp = ip_p + sizeof(struct iphdr); 690 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 691 692 ipv4->ttl = cqe->lro_min_ttl; 693 ipv4->tot_len = cpu_to_be16(tot_len); 694 ipv4->check = 0; 695 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 696 ipv4->ihl); 697 698 mlx5e_lro_update_tcp_hdr(cqe, tcp); 699 check = csum_partial(tcp, tcp->doff * 4, 700 csum_unfold((__force __sum16)cqe->check_sum)); 701 /* Almost done, don't forget the pseudo header */ 702 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, 703 tot_len - sizeof(struct iphdr), 704 IPPROTO_TCP, check); 705 } else { 706 u16 payload_len = tot_len - sizeof(struct ipv6hdr); 707 struct ipv6hdr *ipv6 = ip_p; 708 709 tcp = ip_p + sizeof(struct ipv6hdr); 710 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 711 712 ipv6->hop_limit = cqe->lro_min_ttl; 713 ipv6->payload_len = cpu_to_be16(payload_len); 714 715 mlx5e_lro_update_tcp_hdr(cqe, tcp); 716 check = csum_partial(tcp, tcp->doff * 4, 717 csum_unfold((__force __sum16)cqe->check_sum)); 718 /* Almost done, don't forget the pseudo header */ 719 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, 720 IPPROTO_TCP, check); 721 } 722 } 723 724 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 725 struct sk_buff *skb) 726 { 727 u8 cht = cqe->rss_hash_type; 728 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 729 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 730 PKT_HASH_TYPE_NONE; 731 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 732 } 733 734 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth, 735 __be16 *proto) 736 { 737 *proto = ((struct ethhdr *)skb->data)->h_proto; 738 *proto = __vlan_get_protocol(skb, *proto, network_depth); 739 740 if (*proto == htons(ETH_P_IP)) 741 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr)); 742 743 if (*proto == htons(ETH_P_IPV6)) 744 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr)); 745 746 return false; 747 } 748 749 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb) 750 { 751 int network_depth = 0; 752 __be16 proto; 753 void *ip; 754 int rc; 755 756 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto))) 757 return; 758 759 ip = skb->data + network_depth; 760 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) : 761 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip)); 762 763 rq->stats->ecn_mark += !!rc; 764 } 765 766 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto) 767 { 768 void *ip_p = skb->data + network_depth; 769 770 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol : 771 ((struct ipv6hdr *)ip_p)->nexthdr; 772 } 773 774 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN) 775 776 #define MAX_PADDING 8 777 778 static void 779 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len, 780 struct mlx5e_rq_stats *stats) 781 { 782 stats->csum_complete_tail_slow++; 783 skb->csum = csum_block_add(skb->csum, 784 skb_checksum(skb, offset, len, 0), 785 offset); 786 } 787 788 static void 789 tail_padding_csum(struct sk_buff *skb, int offset, 790 struct mlx5e_rq_stats *stats) 791 { 792 u8 tail_padding[MAX_PADDING]; 793 int len = skb->len - offset; 794 void *tail; 795 796 if (unlikely(len > MAX_PADDING)) { 797 tail_padding_csum_slow(skb, offset, len, stats); 798 return; 799 } 800 801 tail = skb_header_pointer(skb, offset, len, tail_padding); 802 if (unlikely(!tail)) { 803 tail_padding_csum_slow(skb, offset, len, stats); 804 return; 805 } 806 807 stats->csum_complete_tail++; 808 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset); 809 } 810 811 static void 812 mlx5e_skb_padding_csum(struct sk_buff *skb, int network_depth, __be16 proto, 813 struct mlx5e_rq_stats *stats) 814 { 815 struct ipv6hdr *ip6; 816 struct iphdr *ip4; 817 int pkt_len; 818 819 switch (proto) { 820 case htons(ETH_P_IP): 821 ip4 = (struct iphdr *)(skb->data + network_depth); 822 pkt_len = network_depth + ntohs(ip4->tot_len); 823 break; 824 case htons(ETH_P_IPV6): 825 ip6 = (struct ipv6hdr *)(skb->data + network_depth); 826 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len); 827 break; 828 default: 829 return; 830 } 831 832 if (likely(pkt_len >= skb->len)) 833 return; 834 835 tail_padding_csum(skb, pkt_len, stats); 836 } 837 838 static inline void mlx5e_handle_csum(struct net_device *netdev, 839 struct mlx5_cqe64 *cqe, 840 struct mlx5e_rq *rq, 841 struct sk_buff *skb, 842 bool lro) 843 { 844 struct mlx5e_rq_stats *stats = rq->stats; 845 int network_depth = 0; 846 __be16 proto; 847 848 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 849 goto csum_none; 850 851 if (lro) { 852 skb->ip_summed = CHECKSUM_UNNECESSARY; 853 stats->csum_unnecessary++; 854 return; 855 } 856 857 /* True when explicitly set via priv flag, or XDP prog is loaded */ 858 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state)) 859 goto csum_unnecessary; 860 861 /* CQE csum doesn't cover padding octets in short ethernet 862 * frames. And the pad field is appended prior to calculating 863 * and appending the FCS field. 864 * 865 * Detecting these padded frames requires to verify and parse 866 * IP headers, so we simply force all those small frames to be 867 * CHECKSUM_UNNECESSARY even if they are not padded. 868 */ 869 if (short_frame(skb->len)) 870 goto csum_unnecessary; 871 872 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) { 873 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP)) 874 goto csum_unnecessary; 875 876 skb->ip_summed = CHECKSUM_COMPLETE; 877 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 878 if (network_depth > ETH_HLEN) 879 /* CQE csum is calculated from the IP header and does 880 * not cover VLAN headers (if present). This will add 881 * the checksum manually. 882 */ 883 skb->csum = csum_partial(skb->data + ETH_HLEN, 884 network_depth - ETH_HLEN, 885 skb->csum); 886 887 mlx5e_skb_padding_csum(skb, network_depth, proto, stats); 888 stats->csum_complete++; 889 return; 890 } 891 892 csum_unnecessary: 893 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 894 (cqe->hds_ip_ext & CQE_L4_OK))) { 895 skb->ip_summed = CHECKSUM_UNNECESSARY; 896 if (cqe_is_tunneled(cqe)) { 897 skb->csum_level = 1; 898 skb->encapsulation = 1; 899 stats->csum_unnecessary_inner++; 900 return; 901 } 902 stats->csum_unnecessary++; 903 return; 904 } 905 csum_none: 906 skb->ip_summed = CHECKSUM_NONE; 907 stats->csum_none++; 908 } 909 910 #define MLX5E_CE_BIT_MASK 0x80 911 912 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 913 u32 cqe_bcnt, 914 struct mlx5e_rq *rq, 915 struct sk_buff *skb) 916 { 917 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 918 struct mlx5e_rq_stats *stats = rq->stats; 919 struct net_device *netdev = rq->netdev; 920 921 skb->mac_len = ETH_HLEN; 922 923 #ifdef CONFIG_MLX5_EN_TLS 924 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt); 925 #endif 926 927 if (lro_num_seg > 1) { 928 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 929 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 930 /* Subtract one since we already counted this as one 931 * "regular" packet in mlx5e_complete_rx_cqe() 932 */ 933 stats->packets += lro_num_seg - 1; 934 stats->lro_packets++; 935 stats->lro_bytes += cqe_bcnt; 936 } 937 938 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 939 skb_hwtstamps(skb)->hwtstamp = 940 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 941 942 skb_record_rx_queue(skb, rq->ix); 943 944 if (likely(netdev->features & NETIF_F_RXHASH)) 945 mlx5e_skb_set_hash(cqe, skb); 946 947 if (cqe_has_vlan(cqe)) { 948 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 949 be16_to_cpu(cqe->vlan_info)); 950 stats->removed_vlan_packets++; 951 } 952 953 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 954 955 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 956 /* checking CE bit in cqe - MSB in ml_path field */ 957 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK)) 958 mlx5e_enable_ecn(rq, skb); 959 960 skb->protocol = eth_type_trans(skb, netdev); 961 } 962 963 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 964 struct mlx5_cqe64 *cqe, 965 u32 cqe_bcnt, 966 struct sk_buff *skb) 967 { 968 struct mlx5e_rq_stats *stats = rq->stats; 969 970 stats->packets++; 971 stats->bytes += cqe_bcnt; 972 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 973 } 974 975 static inline 976 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, 977 u32 frag_size, u16 headroom, 978 u32 cqe_bcnt) 979 { 980 struct sk_buff *skb = build_skb(va, frag_size); 981 982 if (unlikely(!skb)) { 983 rq->stats->buff_alloc_err++; 984 return NULL; 985 } 986 987 skb_reserve(skb, headroom); 988 skb_put(skb, cqe_bcnt); 989 990 return skb; 991 } 992 993 struct sk_buff * 994 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 995 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 996 { 997 struct mlx5e_dma_info *di = wi->di; 998 u16 rx_headroom = rq->buff.headroom; 999 struct sk_buff *skb; 1000 void *va, *data; 1001 bool consumed; 1002 u32 frag_size; 1003 1004 va = page_address(di->page) + wi->offset; 1005 data = va + rx_headroom; 1006 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1007 1008 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, 1009 frag_size, DMA_FROM_DEVICE); 1010 prefetchw(va); /* xdp_frame data area */ 1011 prefetch(data); 1012 1013 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) { 1014 rq->stats->wqe_err++; 1015 return NULL; 1016 } 1017 1018 rcu_read_lock(); 1019 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 1020 rcu_read_unlock(); 1021 if (consumed) 1022 return NULL; /* page/packet was consumed by XDP */ 1023 1024 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); 1025 if (unlikely(!skb)) 1026 return NULL; 1027 1028 /* queue up for recycling/reuse */ 1029 page_ref_inc(di->page); 1030 1031 return skb; 1032 } 1033 1034 struct sk_buff * 1035 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 1036 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 1037 { 1038 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 1039 struct mlx5e_wqe_frag_info *head_wi = wi; 1040 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt); 1041 u16 frag_headlen = headlen; 1042 u16 byte_cnt = cqe_bcnt - headlen; 1043 struct sk_buff *skb; 1044 1045 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) { 1046 rq->stats->wqe_err++; 1047 return NULL; 1048 } 1049 1050 /* XDP is not supported in this configuration, as incoming packets 1051 * might spread among multiple pages. 1052 */ 1053 skb = napi_alloc_skb(rq->cq.napi, 1054 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); 1055 if (unlikely(!skb)) { 1056 rq->stats->buff_alloc_err++; 1057 return NULL; 1058 } 1059 1060 prefetchw(skb->data); 1061 1062 while (byte_cnt) { 1063 u16 frag_consumed_bytes = 1064 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt); 1065 1066 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen, 1067 frag_consumed_bytes, frag_info->frag_stride); 1068 byte_cnt -= frag_consumed_bytes; 1069 frag_headlen = 0; 1070 frag_info++; 1071 wi++; 1072 } 1073 1074 /* copy header */ 1075 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen); 1076 /* skb linear part was allocated with headlen and aligned to long */ 1077 skb->tail += headlen; 1078 skb->len += headlen; 1079 1080 return skb; 1081 } 1082 1083 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1084 { 1085 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1086 struct mlx5e_wqe_frag_info *wi; 1087 struct sk_buff *skb; 1088 u32 cqe_bcnt; 1089 u16 ci; 1090 1091 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1092 wi = get_frag(rq, ci); 1093 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1094 1095 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1096 if (!skb) { 1097 /* probably for XDP */ 1098 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1099 /* do not return page to cache, 1100 * it will be returned on XDP_TX completion. 1101 */ 1102 goto wq_cyc_pop; 1103 } 1104 goto free_wqe; 1105 } 1106 1107 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1108 napi_gro_receive(rq->cq.napi, skb); 1109 1110 free_wqe: 1111 mlx5e_free_rx_wqe(rq, wi, true); 1112 wq_cyc_pop: 1113 mlx5_wq_cyc_pop(wq); 1114 } 1115 1116 #ifdef CONFIG_MLX5_ESWITCH 1117 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1118 { 1119 struct net_device *netdev = rq->netdev; 1120 struct mlx5e_priv *priv = netdev_priv(netdev); 1121 struct mlx5e_rep_priv *rpriv = priv->ppriv; 1122 struct mlx5_eswitch_rep *rep = rpriv->rep; 1123 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1124 struct mlx5e_wqe_frag_info *wi; 1125 struct sk_buff *skb; 1126 u32 cqe_bcnt; 1127 u16 ci; 1128 1129 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1130 wi = get_frag(rq, ci); 1131 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1132 1133 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1134 if (!skb) { 1135 /* probably for XDP */ 1136 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1137 /* do not return page to cache, 1138 * it will be returned on XDP_TX completion. 1139 */ 1140 goto wq_cyc_pop; 1141 } 1142 goto free_wqe; 1143 } 1144 1145 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1146 1147 if (rep->vlan && skb_vlan_tag_present(skb)) 1148 skb_vlan_pop(skb); 1149 1150 napi_gro_receive(rq->cq.napi, skb); 1151 1152 free_wqe: 1153 mlx5e_free_rx_wqe(rq, wi, true); 1154 wq_cyc_pop: 1155 mlx5_wq_cyc_pop(wq); 1156 } 1157 #endif 1158 1159 struct sk_buff * 1160 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1161 u16 cqe_bcnt, u32 head_offset, u32 page_idx) 1162 { 1163 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); 1164 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; 1165 u32 frag_offset = head_offset + headlen; 1166 u32 byte_cnt = cqe_bcnt - headlen; 1167 struct mlx5e_dma_info *head_di = di; 1168 struct sk_buff *skb; 1169 1170 skb = napi_alloc_skb(rq->cq.napi, 1171 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); 1172 if (unlikely(!skb)) { 1173 rq->stats->buff_alloc_err++; 1174 return NULL; 1175 } 1176 1177 prefetchw(skb->data); 1178 1179 if (unlikely(frag_offset >= PAGE_SIZE)) { 1180 di++; 1181 frag_offset -= PAGE_SIZE; 1182 } 1183 1184 while (byte_cnt) { 1185 u32 pg_consumed_bytes = 1186 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 1187 unsigned int truesize = 1188 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); 1189 1190 mlx5e_add_skb_frag(rq, skb, di, frag_offset, 1191 pg_consumed_bytes, truesize); 1192 byte_cnt -= pg_consumed_bytes; 1193 frag_offset = 0; 1194 di++; 1195 } 1196 /* copy header */ 1197 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen); 1198 /* skb linear part was allocated with headlen and aligned to long */ 1199 skb->tail += headlen; 1200 skb->len += headlen; 1201 1202 return skb; 1203 } 1204 1205 struct sk_buff * 1206 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1207 u16 cqe_bcnt, u32 head_offset, u32 page_idx) 1208 { 1209 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; 1210 u16 rx_headroom = rq->buff.headroom; 1211 u32 cqe_bcnt32 = cqe_bcnt; 1212 struct sk_buff *skb; 1213 void *va, *data; 1214 u32 frag_size; 1215 bool consumed; 1216 1217 /* Check packet size. Note LRO doesn't use linear SKB */ 1218 if (unlikely(cqe_bcnt > rq->hw_mtu)) { 1219 rq->stats->oversize_pkts_sw_drop++; 1220 return NULL; 1221 } 1222 1223 va = page_address(di->page) + head_offset; 1224 data = va + rx_headroom; 1225 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32); 1226 1227 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset, 1228 frag_size, DMA_FROM_DEVICE); 1229 prefetchw(va); /* xdp_frame data area */ 1230 prefetch(data); 1231 1232 rcu_read_lock(); 1233 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32); 1234 rcu_read_unlock(); 1235 if (consumed) { 1236 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) 1237 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */ 1238 return NULL; /* page/packet was consumed by XDP */ 1239 } 1240 1241 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32); 1242 if (unlikely(!skb)) 1243 return NULL; 1244 1245 /* queue up for recycling/reuse */ 1246 page_ref_inc(di->page); 1247 1248 return skb; 1249 } 1250 1251 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1252 { 1253 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1254 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1255 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1256 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 1257 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 1258 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 1259 u32 page_idx = wqe_offset >> PAGE_SHIFT; 1260 struct mlx5e_rx_wqe_ll *wqe; 1261 struct mlx5_wq_ll *wq; 1262 struct sk_buff *skb; 1263 u16 cqe_bcnt; 1264 1265 wi->consumed_strides += cstrides; 1266 1267 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) { 1268 rq->stats->wqe_err++; 1269 goto mpwrq_cqe_out; 1270 } 1271 1272 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1273 struct mlx5e_rq_stats *stats = rq->stats; 1274 1275 stats->mpwqe_filler_cqes++; 1276 stats->mpwqe_filler_strides += cstrides; 1277 goto mpwrq_cqe_out; 1278 } 1279 1280 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1281 1282 skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset, 1283 page_idx); 1284 if (!skb) 1285 goto mpwrq_cqe_out; 1286 1287 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1288 napi_gro_receive(rq->cq.napi, skb); 1289 1290 mpwrq_cqe_out: 1291 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1292 return; 1293 1294 wq = &rq->mpwqe.wq; 1295 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id); 1296 mlx5e_free_rx_mpwqe(rq, wi, true); 1297 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1298 } 1299 1300 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1301 { 1302 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1303 struct mlx5_cqwq *cqwq = &cq->wq; 1304 struct mlx5_cqe64 *cqe; 1305 int work_done = 0; 1306 1307 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 1308 return 0; 1309 1310 if (rq->cqd.left) 1311 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget); 1312 1313 cqe = mlx5_cqwq_get_cqe(cqwq); 1314 if (!cqe) { 1315 if (unlikely(work_done)) 1316 goto out; 1317 return 0; 1318 } 1319 1320 do { 1321 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1322 work_done += 1323 mlx5e_decompress_cqes_start(rq, cqwq, 1324 budget - work_done); 1325 continue; 1326 } 1327 1328 mlx5_cqwq_pop(cqwq); 1329 1330 rq->handle_rx_cqe(rq, cqe); 1331 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq))); 1332 1333 out: 1334 if (rq->xdp_prog) 1335 mlx5e_xdp_rx_poll_complete(rq); 1336 1337 mlx5_cqwq_update_db_record(cqwq); 1338 1339 /* ensure cq space is freed before enabling more cqes */ 1340 wmb(); 1341 1342 return work_done; 1343 } 1344 1345 #ifdef CONFIG_MLX5_CORE_IPOIB 1346 1347 #define MLX5_IB_GRH_DGID_OFFSET 24 1348 #define MLX5_GID_SIZE 16 1349 1350 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1351 struct mlx5_cqe64 *cqe, 1352 u32 cqe_bcnt, 1353 struct sk_buff *skb) 1354 { 1355 struct hwtstamp_config *tstamp; 1356 struct mlx5e_rq_stats *stats; 1357 struct net_device *netdev; 1358 struct mlx5e_priv *priv; 1359 char *pseudo_header; 1360 u32 qpn; 1361 u8 *dgid; 1362 u8 g; 1363 1364 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1365 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1366 1367 /* No mapping present, cannot process SKB. This might happen if a child 1368 * interface is going down while having unprocessed CQEs on parent RQ 1369 */ 1370 if (unlikely(!netdev)) { 1371 /* TODO: add drop counters support */ 1372 skb->dev = NULL; 1373 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1374 return; 1375 } 1376 1377 priv = mlx5i_epriv(netdev); 1378 tstamp = &priv->tstamp; 1379 stats = &priv->channel_stats[rq->ix].rq; 1380 1381 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1382 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1383 if ((!g) || dgid[0] != 0xff) 1384 skb->pkt_type = PACKET_HOST; 1385 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1386 skb->pkt_type = PACKET_BROADCAST; 1387 else 1388 skb->pkt_type = PACKET_MULTICAST; 1389 1390 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1391 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1392 */ 1393 1394 skb_pull(skb, MLX5_IB_GRH_BYTES); 1395 1396 skb->protocol = *((__be16 *)(skb->data)); 1397 1398 if (netdev->features & NETIF_F_RXCSUM) { 1399 skb->ip_summed = CHECKSUM_COMPLETE; 1400 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1401 stats->csum_complete++; 1402 } else { 1403 skb->ip_summed = CHECKSUM_NONE; 1404 stats->csum_none++; 1405 } 1406 1407 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1408 skb_hwtstamps(skb)->hwtstamp = 1409 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1410 1411 skb_record_rx_queue(skb, rq->ix); 1412 1413 if (likely(netdev->features & NETIF_F_RXHASH)) 1414 mlx5e_skb_set_hash(cqe, skb); 1415 1416 /* 20 bytes of ipoib header and 4 for encap existing */ 1417 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1418 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1419 skb_reset_mac_header(skb); 1420 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1421 1422 skb->dev = netdev; 1423 1424 stats->packets++; 1425 stats->bytes += cqe_bcnt; 1426 } 1427 1428 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1429 { 1430 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1431 struct mlx5e_wqe_frag_info *wi; 1432 struct sk_buff *skb; 1433 u32 cqe_bcnt; 1434 u16 ci; 1435 1436 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1437 wi = get_frag(rq, ci); 1438 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1439 1440 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1441 if (!skb) 1442 goto wq_free_wqe; 1443 1444 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1445 if (unlikely(!skb->dev)) { 1446 dev_kfree_skb_any(skb); 1447 goto wq_free_wqe; 1448 } 1449 napi_gro_receive(rq->cq.napi, skb); 1450 1451 wq_free_wqe: 1452 mlx5e_free_rx_wqe(rq, wi, true); 1453 mlx5_wq_cyc_pop(wq); 1454 } 1455 1456 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1457 1458 #ifdef CONFIG_MLX5_EN_IPSEC 1459 1460 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1461 { 1462 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1463 struct mlx5e_wqe_frag_info *wi; 1464 struct sk_buff *skb; 1465 u32 cqe_bcnt; 1466 u16 ci; 1467 1468 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1469 wi = get_frag(rq, ci); 1470 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1471 1472 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1473 if (unlikely(!skb)) { 1474 /* a DROP, save the page-reuse checks */ 1475 mlx5e_free_rx_wqe(rq, wi, true); 1476 goto wq_cyc_pop; 1477 } 1478 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt); 1479 if (unlikely(!skb)) { 1480 mlx5e_free_rx_wqe(rq, wi, true); 1481 goto wq_cyc_pop; 1482 } 1483 1484 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1485 napi_gro_receive(rq->cq.napi, skb); 1486 1487 mlx5e_free_rx_wqe(rq, wi, true); 1488 wq_cyc_pop: 1489 mlx5_wq_cyc_pop(wq); 1490 } 1491 1492 #endif /* CONFIG_MLX5_EN_IPSEC */ 1493