1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 10 #include "ice_status.h" 11 #include "ice_hw_autogen.h" 12 #include "ice_osdep.h" 13 #include "ice_controlq.h" 14 #include "ice_lan_tx_rx.h" 15 #include "ice_flex_type.h" 16 #include "ice_protocol_type.h" 17 18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 19 { 20 return test_bit(tc, &bitmap); 21 } 22 23 static inline u64 round_up_64bit(u64 a, u32 b) 24 { 25 return div64_long(((a) + (b) / 2), (b)); 26 } 27 28 static inline u32 ice_round_to_num(u32 N, u32 R) 29 { 30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 31 ((((N) + (R) - 1) / (R)) * (R))); 32 } 33 34 /* Driver always calls main vsi_handle first */ 35 #define ICE_MAIN_VSI_HANDLE 0 36 37 /* debug masks - set these bits in hw->debug_mask to control output */ 38 #define ICE_DBG_INIT BIT_ULL(1) 39 #define ICE_DBG_FW_LOG BIT_ULL(3) 40 #define ICE_DBG_LINK BIT_ULL(4) 41 #define ICE_DBG_PHY BIT_ULL(5) 42 #define ICE_DBG_QCTX BIT_ULL(6) 43 #define ICE_DBG_NVM BIT_ULL(7) 44 #define ICE_DBG_LAN BIT_ULL(8) 45 #define ICE_DBG_FLOW BIT_ULL(9) 46 #define ICE_DBG_SW BIT_ULL(13) 47 #define ICE_DBG_SCHED BIT_ULL(14) 48 #define ICE_DBG_PKG BIT_ULL(16) 49 #define ICE_DBG_RES BIT_ULL(17) 50 #define ICE_DBG_AQ_MSG BIT_ULL(24) 51 #define ICE_DBG_AQ_DESC BIT_ULL(25) 52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 53 #define ICE_DBG_AQ_CMD BIT_ULL(27) 54 #define ICE_DBG_USER BIT_ULL(31) 55 56 enum ice_aq_res_ids { 57 ICE_NVM_RES_ID = 1, 58 ICE_SPD_RES_ID, 59 ICE_CHANGE_LOCK_RES_ID, 60 ICE_GLOBAL_CFG_LOCK_RES_ID 61 }; 62 63 /* FW update timeout definitions are in milliseconds */ 64 #define ICE_NVM_TIMEOUT 180000 65 #define ICE_CHANGE_LOCK_TIMEOUT 1000 66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 67 68 enum ice_aq_res_access_type { 69 ICE_RES_READ = 1, 70 ICE_RES_WRITE 71 }; 72 73 struct ice_driver_ver { 74 u8 major_ver; 75 u8 minor_ver; 76 u8 build_ver; 77 u8 subbuild_ver; 78 u8 driver_string[32]; 79 }; 80 81 enum ice_fc_mode { 82 ICE_FC_NONE = 0, 83 ICE_FC_RX_PAUSE, 84 ICE_FC_TX_PAUSE, 85 ICE_FC_FULL, 86 ICE_FC_PFC, 87 ICE_FC_DFLT 88 }; 89 90 enum ice_fec_mode { 91 ICE_FEC_NONE = 0, 92 ICE_FEC_RS, 93 ICE_FEC_BASER, 94 ICE_FEC_AUTO 95 }; 96 97 enum ice_set_fc_aq_failures { 98 ICE_SET_FC_AQ_FAIL_NONE = 0, 99 ICE_SET_FC_AQ_FAIL_GET, 100 ICE_SET_FC_AQ_FAIL_SET, 101 ICE_SET_FC_AQ_FAIL_UPDATE 102 }; 103 104 /* Various MAC types */ 105 enum ice_mac_type { 106 ICE_MAC_UNKNOWN = 0, 107 ICE_MAC_GENERIC, 108 }; 109 110 /* Media Types */ 111 enum ice_media_type { 112 ICE_MEDIA_UNKNOWN = 0, 113 ICE_MEDIA_FIBER, 114 ICE_MEDIA_BASET, 115 ICE_MEDIA_BACKPLANE, 116 ICE_MEDIA_DA, 117 }; 118 119 enum ice_vsi_type { 120 ICE_VSI_PF = 0, 121 ICE_VSI_VF = 1, 122 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 123 ICE_VSI_LB = 6, 124 }; 125 126 struct ice_link_status { 127 /* Refer to ice_aq_phy_type for bits definition */ 128 u64 phy_type_low; 129 u64 phy_type_high; 130 u8 topo_media_conflict; 131 u16 max_frame_size; 132 u16 link_speed; 133 u16 req_speeds; 134 u8 lse_ena; /* Link Status Event notification */ 135 u8 link_info; 136 u8 an_info; 137 u8 ext_info; 138 u8 fec_info; 139 u8 pacing; 140 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 141 * ice_aqc_get_phy_caps structure 142 */ 143 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 144 }; 145 146 /* Different reset sources for which a disable queue AQ call has to be made in 147 * order to clean the Tx scheduler as a part of the reset 148 */ 149 enum ice_disq_rst_src { 150 ICE_NO_RESET = 0, 151 ICE_VM_RESET, 152 ICE_VF_RESET, 153 }; 154 155 /* PHY info such as phy_type, etc... */ 156 struct ice_phy_info { 157 struct ice_link_status link_info; 158 struct ice_link_status link_info_old; 159 u64 phy_type_low; 160 u64 phy_type_high; 161 enum ice_media_type media_type; 162 u8 get_link_info; 163 }; 164 165 /* protocol enumeration for filters */ 166 enum ice_fltr_ptype { 167 /* NONE - used for undef/error */ 168 ICE_FLTR_PTYPE_NONF_NONE = 0, 169 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 170 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 171 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 172 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 173 ICE_FLTR_PTYPE_FRAG_IPV4, 174 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 175 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 176 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 177 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 178 ICE_FLTR_PTYPE_MAX, 179 }; 180 181 enum ice_fd_hw_seg { 182 ICE_FD_HW_SEG_NON_TUN = 0, 183 ICE_FD_HW_SEG_TUN, 184 ICE_FD_HW_SEG_MAX, 185 }; 186 187 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 188 #define ICE_MAX_FDIR_VSI_PER_FILTER 2 189 190 struct ice_fd_hw_prof { 191 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 192 int cnt; 193 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 194 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 195 }; 196 197 /* Common HW capabilities for SW use */ 198 struct ice_hw_common_caps { 199 u32 valid_functions; 200 /* DCB capabilities */ 201 u32 active_tc_bitmap; 202 u32 maxtc; 203 204 /* Tx/Rx queues */ 205 u16 num_rxq; /* Number/Total Rx queues */ 206 u16 rxq_first_id; /* First queue ID for Rx queues */ 207 u16 num_txq; /* Number/Total Tx queues */ 208 u16 txq_first_id; /* First queue ID for Tx queues */ 209 210 /* MSI-X vectors */ 211 u16 num_msix_vectors; 212 u16 msix_vector_first_id; 213 214 /* Max MTU for function or device */ 215 u16 max_mtu; 216 217 /* Virtualization support */ 218 u8 sr_iov_1_1; /* SR-IOV enabled */ 219 220 /* RSS related capabilities */ 221 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 222 u8 rss_table_entry_width; /* RSS Entry width in bits */ 223 224 u8 dcb; 225 }; 226 227 /* Function specific capabilities */ 228 struct ice_hw_func_caps { 229 struct ice_hw_common_caps common_cap; 230 u32 num_allocd_vfs; /* Number of allocated VFs */ 231 u32 vf_base_id; /* Logical ID of the first VF */ 232 u32 guar_num_vsi; 233 u32 fd_fltr_guar; /* Number of filters guaranteed */ 234 u32 fd_fltr_best_effort; /* Number of best effort filters */ 235 }; 236 237 /* Device wide capabilities */ 238 struct ice_hw_dev_caps { 239 struct ice_hw_common_caps common_cap; 240 u32 num_vfs_exposed; /* Total number of VFs exposed */ 241 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 242 u32 num_flow_director_fltr; /* Number of FD filters available */ 243 u32 num_funcs; 244 }; 245 246 /* MAC info */ 247 struct ice_mac_info { 248 u8 lan_addr[ETH_ALEN]; 249 u8 perm_addr[ETH_ALEN]; 250 }; 251 252 /* Reset types used to determine which kind of reset was requested. These 253 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 254 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 255 * because its reset source is different than the other types listed. 256 */ 257 enum ice_reset_req { 258 ICE_RESET_POR = 0, 259 ICE_RESET_INVAL = 0, 260 ICE_RESET_CORER = 1, 261 ICE_RESET_GLOBR = 2, 262 ICE_RESET_EMPR = 3, 263 ICE_RESET_PFR = 4, 264 }; 265 266 /* Bus parameters */ 267 struct ice_bus_info { 268 u16 device; 269 u8 func; 270 }; 271 272 /* Flow control (FC) parameters */ 273 struct ice_fc_info { 274 enum ice_fc_mode current_mode; /* FC mode in effect */ 275 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 276 }; 277 278 /* Option ROM version information */ 279 struct ice_orom_info { 280 u8 major; /* Major version of OROM */ 281 u8 patch; /* Patch version of OROM */ 282 u16 build; /* Build version of OROM */ 283 }; 284 285 /* NVM Information */ 286 struct ice_nvm_info { 287 struct ice_orom_info orom; /* Option ROM version info */ 288 u32 eetrack; /* NVM data version */ 289 u16 sr_words; /* Shadow RAM size in words */ 290 u32 flash_size; /* Size of available flash in bytes */ 291 u8 major_ver; /* major version of NVM package */ 292 u8 minor_ver; /* minor version of dev starter */ 293 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 294 }; 295 296 #define ICE_NVM_VER_LEN 32 297 298 /* netlist version information */ 299 struct ice_netlist_ver_info { 300 u32 major; /* major high/low */ 301 u32 minor; /* minor high/low */ 302 u32 type; /* type high/low */ 303 u32 rev; /* revision high/low */ 304 u32 hash; /* SHA-1 hash word */ 305 u16 cust_ver; /* customer version */ 306 }; 307 308 /* Max number of port to queue branches w.r.t topology */ 309 #define ICE_MAX_TRAFFIC_CLASS 8 310 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 311 312 #define ice_for_each_traffic_class(_i) \ 313 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 314 315 #define ICE_INVAL_TEID 0xFFFFFFFF 316 317 struct ice_sched_node { 318 struct ice_sched_node *parent; 319 struct ice_sched_node *sibling; /* next sibling in the same layer */ 320 struct ice_sched_node **children; 321 struct ice_aqc_txsched_elem_data info; 322 u32 agg_id; /* aggregator group ID */ 323 u16 vsi_handle; 324 u8 in_use; /* suspended or in use */ 325 u8 tx_sched_layer; /* Logical Layer (1-9) */ 326 u8 num_children; 327 u8 tc_num; 328 u8 owner; 329 #define ICE_SCHED_NODE_OWNER_LAN 0 330 }; 331 332 /* Access Macros for Tx Sched Elements data */ 333 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 334 335 /* The aggregator type determines if identifier is for a VSI group, 336 * aggregator group, aggregator of queues, or queue group. 337 */ 338 enum ice_agg_type { 339 ICE_AGG_TYPE_UNKNOWN = 0, 340 ICE_AGG_TYPE_VSI, 341 ICE_AGG_TYPE_AGG, /* aggregator */ 342 ICE_AGG_TYPE_Q, 343 ICE_AGG_TYPE_QG 344 }; 345 346 /* Rate limit types */ 347 enum ice_rl_type { 348 ICE_UNKNOWN_BW = 0, 349 ICE_MIN_BW, /* for CIR profile */ 350 ICE_MAX_BW, /* for EIR profile */ 351 ICE_SHARED_BW /* for shared profile */ 352 }; 353 354 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 355 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 356 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 357 #define ICE_SCHED_DFLT_RL_PROF_ID 0 358 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 359 #define ICE_SCHED_DFLT_BW_WT 1 360 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 361 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 362 363 /* Data structure for saving BW information */ 364 enum ice_bw_type { 365 ICE_BW_TYPE_PRIO, 366 ICE_BW_TYPE_CIR, 367 ICE_BW_TYPE_CIR_WT, 368 ICE_BW_TYPE_EIR, 369 ICE_BW_TYPE_EIR_WT, 370 ICE_BW_TYPE_SHARED, 371 ICE_BW_TYPE_CNT /* This must be last */ 372 }; 373 374 struct ice_bw { 375 u32 bw; 376 u16 bw_alloc; 377 }; 378 379 struct ice_bw_type_info { 380 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 381 u8 generic; 382 struct ice_bw cir_bw; 383 struct ice_bw eir_bw; 384 u32 shared_bw; 385 }; 386 387 /* VSI queue context structure for given TC */ 388 struct ice_q_ctx { 389 u16 q_handle; 390 u32 q_teid; 391 /* bw_t_info saves queue BW information */ 392 struct ice_bw_type_info bw_t_info; 393 }; 394 395 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 396 struct ice_sched_vsi_info { 397 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 398 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 399 struct list_head list_entry; 400 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 401 }; 402 403 /* driver defines the policy */ 404 struct ice_sched_tx_policy { 405 u16 max_num_vsis; 406 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 407 u8 rdma_ena; 408 }; 409 410 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 411 struct ice_dcb_ets_cfg { 412 u8 willing; 413 u8 cbs; 414 u8 maxtcs; 415 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 416 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 417 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 418 }; 419 420 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 421 struct ice_dcb_pfc_cfg { 422 u8 willing; 423 u8 mbc; 424 u8 pfccap; 425 u8 pfcena; 426 }; 427 428 /* CEE or IEEE 802.1Qaz Application Priority data */ 429 struct ice_dcb_app_priority_table { 430 u16 prot_id; 431 u8 priority; 432 u8 selector; 433 }; 434 435 #define ICE_MAX_USER_PRIORITY 8 436 #define ICE_DCBX_MAX_APPS 32 437 #define ICE_LLDPDU_SIZE 1500 438 #define ICE_TLV_STATUS_OPER 0x1 439 #define ICE_TLV_STATUS_SYNC 0x2 440 #define ICE_TLV_STATUS_ERR 0x4 441 #define ICE_APP_PROT_ID_FCOE 0x8906 442 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 443 #define ICE_APP_PROT_ID_FIP 0x8914 444 #define ICE_APP_SEL_ETHTYPE 0x1 445 #define ICE_APP_SEL_TCPIP 0x2 446 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 447 #define ICE_CEE_APP_SEL_TCPIP 0x1 448 449 struct ice_dcbx_cfg { 450 u32 numapps; 451 u32 tlv_status; /* CEE mode TLV status */ 452 struct ice_dcb_ets_cfg etscfg; 453 struct ice_dcb_ets_cfg etsrec; 454 struct ice_dcb_pfc_cfg pfc; 455 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 456 u8 dcbx_mode; 457 #define ICE_DCBX_MODE_CEE 0x1 458 #define ICE_DCBX_MODE_IEEE 0x2 459 u8 app_mode; 460 #define ICE_DCBX_APPS_NON_WILLING 0x1 461 }; 462 463 struct ice_port_info { 464 struct ice_sched_node *root; /* Root Node per Port */ 465 struct ice_hw *hw; /* back pointer to HW instance */ 466 u32 last_node_teid; /* scheduler last node info */ 467 u16 sw_id; /* Initial switch ID belongs to port */ 468 u16 pf_vf_num; 469 u8 port_state; 470 #define ICE_SCHED_PORT_STATE_INIT 0x0 471 #define ICE_SCHED_PORT_STATE_READY 0x1 472 u8 lport; 473 #define ICE_LPORT_MASK 0xff 474 u16 dflt_tx_vsi_rule_id; 475 u16 dflt_tx_vsi_num; 476 u16 dflt_rx_vsi_rule_id; 477 u16 dflt_rx_vsi_num; 478 struct ice_fc_info fc; 479 struct ice_mac_info mac; 480 struct ice_phy_info phy; 481 struct mutex sched_lock; /* protect access to TXSched tree */ 482 struct ice_sched_node * 483 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 484 /* List contain profile ID(s) and other params per layer */ 485 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 486 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 487 /* DCBX info */ 488 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 489 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 490 /* LLDP/DCBX Status */ 491 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ 492 u8 is_sw_lldp:1; 493 u8 is_vf:1; 494 }; 495 496 struct ice_switch_info { 497 struct list_head vsi_list_map_head; 498 struct ice_sw_recipe *recp_list; 499 }; 500 501 /* FW logging configuration */ 502 struct ice_fw_log_evnt { 503 u8 cfg : 4; /* New event enables to configure */ 504 u8 cur : 4; /* Current/active event enables */ 505 }; 506 507 struct ice_fw_log_cfg { 508 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 509 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 510 u8 actv_evnts; /* Cumulation of currently enabled log events */ 511 512 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 513 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 514 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 515 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 516 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 517 }; 518 519 /* Port hardware description */ 520 struct ice_hw { 521 u8 __iomem *hw_addr; 522 void *back; 523 struct ice_aqc_layer_props *layer_info; 524 struct ice_port_info *port_info; 525 u64 debug_mask; /* bitmap for debug mask */ 526 enum ice_mac_type mac_type; 527 528 u16 fd_ctr_base; /* FD counter base index */ 529 530 /* pci info */ 531 u16 device_id; 532 u16 vendor_id; 533 u16 subsystem_device_id; 534 u16 subsystem_vendor_id; 535 u8 revision_id; 536 537 u8 pf_id; /* device profile info */ 538 539 u16 max_burst_size; /* driver sets this value */ 540 541 /* Tx Scheduler values */ 542 u8 num_tx_sched_layers; 543 u8 num_tx_sched_phys_layers; 544 u8 flattened_layers; 545 u8 max_cgds; 546 u8 sw_entry_point_layer; 547 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 548 struct list_head agg_list; /* lists all aggregator */ 549 550 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 551 u8 evb_veb; /* true for VEB, false for VEPA */ 552 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 553 struct ice_bus_info bus; 554 struct ice_nvm_info nvm; 555 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 556 struct ice_hw_func_caps func_caps; /* function capabilities */ 557 struct ice_netlist_ver_info netlist_ver; /* netlist version info */ 558 559 struct ice_switch_info *switch_info; /* switch filter lists */ 560 561 /* Control Queue info */ 562 struct ice_ctl_q_info adminq; 563 struct ice_ctl_q_info mailboxq; 564 565 u8 api_branch; /* API branch version */ 566 u8 api_maj_ver; /* API major version */ 567 u8 api_min_ver; /* API minor version */ 568 u8 api_patch; /* API patch version */ 569 u8 fw_branch; /* firmware branch version */ 570 u8 fw_maj_ver; /* firmware major version */ 571 u8 fw_min_ver; /* firmware minor version */ 572 u8 fw_patch; /* firmware patch version */ 573 u32 fw_build; /* firmware build number */ 574 575 struct ice_fw_log_cfg fw_log; 576 577 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 578 * register. Used for determining the ITR/INTRL granularity during 579 * initialization. 580 */ 581 #define ICE_MAX_AGG_BW_200G 0x0 582 #define ICE_MAX_AGG_BW_100G 0X1 583 #define ICE_MAX_AGG_BW_50G 0x2 584 #define ICE_MAX_AGG_BW_25G 0x3 585 /* ITR granularity for different speeds */ 586 #define ICE_ITR_GRAN_ABOVE_25 2 587 #define ICE_ITR_GRAN_MAX_25 4 588 /* ITR granularity in 1 us */ 589 u8 itr_gran; 590 /* INTRL granularity for different speeds */ 591 #define ICE_INTRL_GRAN_ABOVE_25 4 592 #define ICE_INTRL_GRAN_MAX_25 8 593 /* INTRL granularity in 1 us */ 594 u8 intrl_gran; 595 596 u8 ucast_shared; /* true if VSIs can share unicast addr */ 597 598 /* Active package version (currently active) */ 599 struct ice_pkg_ver active_pkg_ver; 600 u32 active_track_id; 601 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 602 u8 active_pkg_in_nvm; 603 604 enum ice_aq_err pkg_dwnld_status; 605 606 /* Driver's package ver - (from the Metadata seg) */ 607 struct ice_pkg_ver pkg_ver; 608 u8 pkg_name[ICE_PKG_NAME_SIZE]; 609 610 /* Driver's Ice package version (from the Ice seg) */ 611 struct ice_pkg_ver ice_pkg_ver; 612 u8 ice_pkg_name[ICE_PKG_NAME_SIZE]; 613 614 /* Pointer to the ice segment */ 615 struct ice_seg *seg; 616 617 /* Pointer to allocated copy of pkg memory */ 618 u8 *pkg_copy; 619 u32 pkg_size; 620 621 /* tunneling info */ 622 struct mutex tnl_lock; 623 struct ice_tunnel_table tnl; 624 625 /* HW block tables */ 626 struct ice_blk_info blk[ICE_BLK_COUNT]; 627 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 628 struct list_head fl_profs[ICE_BLK_COUNT]; 629 630 /* Flow Director filter info */ 631 int fdir_active_fltr; 632 633 struct mutex fdir_fltr_lock; /* protect Flow Director */ 634 struct list_head fdir_list_head; 635 636 /* Book-keeping of side-band filter count per flow-type. 637 * This is used to detect and handle input set changes for 638 * respective flow-type. 639 */ 640 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 641 642 struct ice_fd_hw_prof **fdir_prof; 643 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 644 struct mutex rss_locks; /* protect RSS configuration */ 645 struct list_head rss_list_head; 646 }; 647 648 /* Statistics collected by each port, VSI, VEB, and S-channel */ 649 struct ice_eth_stats { 650 u64 rx_bytes; /* gorc */ 651 u64 rx_unicast; /* uprc */ 652 u64 rx_multicast; /* mprc */ 653 u64 rx_broadcast; /* bprc */ 654 u64 rx_discards; /* rdpc */ 655 u64 rx_unknown_protocol; /* rupp */ 656 u64 tx_bytes; /* gotc */ 657 u64 tx_unicast; /* uptc */ 658 u64 tx_multicast; /* mptc */ 659 u64 tx_broadcast; /* bptc */ 660 u64 tx_discards; /* tdpc */ 661 u64 tx_errors; /* tepc */ 662 }; 663 664 #define ICE_MAX_UP 8 665 666 /* Statistics collected by the MAC */ 667 struct ice_hw_port_stats { 668 /* eth stats collected by the port */ 669 struct ice_eth_stats eth; 670 /* additional port specific stats */ 671 u64 tx_dropped_link_down; /* tdold */ 672 u64 crc_errors; /* crcerrs */ 673 u64 illegal_bytes; /* illerrc */ 674 u64 error_bytes; /* errbc */ 675 u64 mac_local_faults; /* mlfc */ 676 u64 mac_remote_faults; /* mrfc */ 677 u64 rx_len_errors; /* rlec */ 678 u64 link_xon_rx; /* lxonrxc */ 679 u64 link_xoff_rx; /* lxoffrxc */ 680 u64 link_xon_tx; /* lxontxc */ 681 u64 link_xoff_tx; /* lxofftxc */ 682 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 683 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 684 u64 priority_xon_tx[8]; /* pxontxc[8] */ 685 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 686 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 687 u64 rx_size_64; /* prc64 */ 688 u64 rx_size_127; /* prc127 */ 689 u64 rx_size_255; /* prc255 */ 690 u64 rx_size_511; /* prc511 */ 691 u64 rx_size_1023; /* prc1023 */ 692 u64 rx_size_1522; /* prc1522 */ 693 u64 rx_size_big; /* prc9522 */ 694 u64 rx_undersize; /* ruc */ 695 u64 rx_fragments; /* rfc */ 696 u64 rx_oversize; /* roc */ 697 u64 rx_jabber; /* rjc */ 698 u64 tx_size_64; /* ptc64 */ 699 u64 tx_size_127; /* ptc127 */ 700 u64 tx_size_255; /* ptc255 */ 701 u64 tx_size_511; /* ptc511 */ 702 u64 tx_size_1023; /* ptc1023 */ 703 u64 tx_size_1522; /* ptc1522 */ 704 u64 tx_size_big; /* ptc9522 */ 705 /* flow director stats */ 706 u32 fd_sb_status; 707 u64 fd_sb_match; 708 }; 709 710 /* Checksum and Shadow RAM pointers */ 711 #define ICE_SR_BOOT_CFG_PTR 0x132 712 #define ICE_NVM_OROM_VER_OFF 0x02 713 #define ICE_SR_PBA_BLOCK_PTR 0x16 714 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 715 #define ICE_SR_NVM_EETRACK_LO 0x2D 716 #define ICE_SR_NVM_EETRACK_HI 0x2E 717 #define ICE_NVM_VER_LO_SHIFT 0 718 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 719 #define ICE_NVM_VER_HI_SHIFT 12 720 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 721 #define ICE_OROM_VER_PATCH_SHIFT 0 722 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 723 #define ICE_OROM_VER_BUILD_SHIFT 8 724 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 725 #define ICE_OROM_VER_SHIFT 24 726 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 727 #define ICE_SR_PFA_PTR 0x40 728 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 729 #define ICE_SR_WORDS_IN_1KB 512 730 731 /* Hash redirection LUT for VSI - maximum array size */ 732 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 733 734 #endif /* _ICE_TYPE_H_ */ 735