1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_LAN_TX_RX_H_ 5 #define _ICE_LAN_TX_RX_H_ 6 7 union ice_32byte_rx_desc { 8 struct { 9 __le64 pkt_addr; /* Packet buffer address */ 10 __le64 hdr_addr; /* Header buffer address */ 11 /* bit 0 of hdr_addr is DD bit */ 12 __le64 rsvd1; 13 __le64 rsvd2; 14 } read; 15 struct { 16 struct { 17 struct { 18 __le16 mirroring_status; 19 __le16 l2tag1; 20 } lo_dword; 21 union { 22 __le32 rss; /* RSS Hash */ 23 __le32 fd_id; /* Flow Director filter ID */ 24 } hi_dword; 25 } qword0; 26 struct { 27 /* status/error/PTYPE/length */ 28 __le64 status_error_len; 29 } qword1; 30 struct { 31 __le16 ext_status; /* extended status */ 32 __le16 rsvd; 33 __le16 l2tag2_1; 34 __le16 l2tag2_2; 35 } qword2; 36 struct { 37 __le32 reserved; 38 __le32 fd_id; 39 } qword3; 40 } wb; /* writeback */ 41 }; 42 43 struct ice_rx_ptype_decoded { 44 u32 ptype:10; 45 u32 known:1; 46 u32 outer_ip:1; 47 u32 outer_ip_ver:2; 48 u32 outer_frag:1; 49 u32 tunnel_type:3; 50 u32 tunnel_end_prot:2; 51 u32 tunnel_end_frag:1; 52 u32 inner_prot:4; 53 u32 payload_layer:3; 54 }; 55 56 enum ice_rx_ptype_outer_ip { 57 ICE_RX_PTYPE_OUTER_L2 = 0, 58 ICE_RX_PTYPE_OUTER_IP = 1, 59 }; 60 61 enum ice_rx_ptype_outer_ip_ver { 62 ICE_RX_PTYPE_OUTER_NONE = 0, 63 ICE_RX_PTYPE_OUTER_IPV4 = 1, 64 ICE_RX_PTYPE_OUTER_IPV6 = 2, 65 }; 66 67 enum ice_rx_ptype_outer_fragmented { 68 ICE_RX_PTYPE_NOT_FRAG = 0, 69 ICE_RX_PTYPE_FRAG = 1, 70 }; 71 72 enum ice_rx_ptype_tunnel_type { 73 ICE_RX_PTYPE_TUNNEL_NONE = 0, 74 ICE_RX_PTYPE_TUNNEL_IP_IP = 1, 75 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 76 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 77 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 78 }; 79 80 enum ice_rx_ptype_tunnel_end_prot { 81 ICE_RX_PTYPE_TUNNEL_END_NONE = 0, 82 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, 83 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, 84 }; 85 86 enum ice_rx_ptype_inner_prot { 87 ICE_RX_PTYPE_INNER_PROT_NONE = 0, 88 ICE_RX_PTYPE_INNER_PROT_UDP = 1, 89 ICE_RX_PTYPE_INNER_PROT_TCP = 2, 90 ICE_RX_PTYPE_INNER_PROT_SCTP = 3, 91 ICE_RX_PTYPE_INNER_PROT_ICMP = 4, 92 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, 93 }; 94 95 enum ice_rx_ptype_payload_layer { 96 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 97 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 98 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 99 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 100 }; 101 102 /* Rx Flex Descriptor 103 * This descriptor is used instead of the legacy version descriptor when 104 * ice_rlan_ctx.adv_desc is set 105 */ 106 union ice_32b_rx_flex_desc { 107 struct { 108 __le64 pkt_addr; /* Packet buffer address */ 109 __le64 hdr_addr; /* Header buffer address */ 110 /* bit 0 of hdr_addr is DD bit */ 111 __le64 rsvd1; 112 __le64 rsvd2; 113 } read; 114 struct { 115 /* Qword 0 */ 116 u8 rxdid; /* descriptor builder profile ID */ 117 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 118 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 119 __le16 pkt_len; /* [15:14] are reserved */ 120 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 121 /* sph=[11:11] */ 122 /* ff1/ext=[15:12] */ 123 124 /* Qword 1 */ 125 __le16 status_error0; 126 __le16 l2tag1; 127 __le16 flex_meta0; 128 __le16 flex_meta1; 129 130 /* Qword 2 */ 131 __le16 status_error1; 132 u8 flex_flags2; 133 u8 time_stamp_low; 134 __le16 l2tag2_1st; 135 __le16 l2tag2_2nd; 136 137 /* Qword 3 */ 138 __le16 flex_meta2; 139 __le16 flex_meta3; 140 union { 141 struct { 142 __le16 flex_meta4; 143 __le16 flex_meta5; 144 } flex; 145 __le32 ts_high; 146 } flex_ts; 147 } wb; /* writeback */ 148 }; 149 150 /* Rx Flex Descriptor NIC Profile 151 * This descriptor corresponds to RxDID 2 which contains 152 * metadata fields for RSS, flow ID and timestamp info 153 */ 154 struct ice_32b_rx_flex_desc_nic { 155 /* Qword 0 */ 156 u8 rxdid; 157 u8 mir_id_umb_cast; 158 __le16 ptype_flexi_flags0; 159 __le16 pkt_len; 160 __le16 hdr_len_sph_flex_flags1; 161 162 /* Qword 1 */ 163 __le16 status_error0; 164 __le16 l2tag1; 165 __le32 rss_hash; 166 167 /* Qword 2 */ 168 __le16 status_error1; 169 u8 flexi_flags2; 170 u8 ts_low; 171 __le16 l2tag2_1st; 172 __le16 l2tag2_2nd; 173 174 /* Qword 3 */ 175 __le32 flow_id; 176 union { 177 struct { 178 __le16 vlan_id; 179 __le16 flow_id_ipv6; 180 } flex; 181 __le32 ts_high; 182 } flex_ts; 183 }; 184 185 /* Receive Flex Descriptor profile IDs: There are a total 186 * of 64 profiles where profile IDs 0/1 are for legacy; and 187 * profiles 2-63 are flex profiles that can be programmed 188 * with a specific metadata (profile 7 reserved for HW) 189 */ 190 enum ice_rxdid { 191 ICE_RXDID_LEGACY_0 = 0, 192 ICE_RXDID_LEGACY_1 = 1, 193 ICE_RXDID_FLEX_NIC = 2, 194 ICE_RXDID_FLEX_NIC_2 = 6, 195 ICE_RXDID_HW = 7, 196 ICE_RXDID_LAST = 63, 197 }; 198 199 /* Receive Flex Descriptor Rx opcode values */ 200 #define ICE_RX_OPC_MDID 0x01 201 202 /* Receive Descriptor MDID values that access packet flags */ 203 enum ice_flex_mdid_pkt_flags { 204 ICE_RX_MDID_PKT_FLAGS_15_0 = 20, 205 ICE_RX_MDID_PKT_FLAGS_31_16, 206 ICE_RX_MDID_PKT_FLAGS_47_32, 207 ICE_RX_MDID_PKT_FLAGS_63_48, 208 }; 209 210 /* Receive Descriptor MDID values */ 211 enum ice_flex_rx_mdid { 212 ICE_RX_MDID_FLOW_ID_LOWER = 5, 213 ICE_RX_MDID_FLOW_ID_HIGH, 214 ICE_RX_MDID_SRC_VSI = 19, 215 ICE_RX_MDID_HASH_LOW = 56, 216 ICE_RX_MDID_HASH_HIGH, 217 }; 218 219 /* Rx/Tx Flag64 packet flag bits */ 220 enum ice_flg64_bits { 221 ICE_FLG_PKT_DSI = 0, 222 ICE_FLG_EVLAN_x8100 = 14, 223 ICE_FLG_EVLAN_x9100, 224 ICE_FLG_VLAN_x8100, 225 ICE_FLG_TNL_MAC = 22, 226 ICE_FLG_TNL_VLAN, 227 ICE_FLG_PKT_FRG, 228 ICE_FLG_FIN = 32, 229 ICE_FLG_SYN, 230 ICE_FLG_RST, 231 ICE_FLG_TNL0 = 38, 232 ICE_FLG_TNL1, 233 ICE_FLG_TNL2, 234 ICE_FLG_UDP_GRE, 235 ICE_FLG_RSVD = 63 236 }; 237 238 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ 239 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ 240 241 /* for ice_32byte_rx_flex_desc.pkt_length member */ 242 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ 243 244 enum ice_rx_flex_desc_status_error_0_bits { 245 /* Note: These are predefined bit offsets */ 246 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, 247 ICE_RX_FLEX_DESC_STATUS0_EOF_S, 248 ICE_RX_FLEX_DESC_STATUS0_HBO_S, 249 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, 250 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 251 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 252 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 253 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 254 ICE_RX_FLEX_DESC_STATUS0_LPBK_S, 255 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 256 ICE_RX_FLEX_DESC_STATUS0_RXE_S, 257 ICE_RX_FLEX_DESC_STATUS0_CRCP_S, 258 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 259 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 260 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 261 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 262 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 263 }; 264 265 #define ICE_RXQ_CTX_SIZE_DWORDS 8 266 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 267 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 268 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 269 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) 270 271 /* RLAN Rx queue context data 272 * 273 * The sizes of the variables may be larger than needed due to crossing byte 274 * boundaries. If we do not have the width of the variable set to the correct 275 * size then we could end up shifting bits off the top of the variable when the 276 * variable is at the top of a byte and crosses over into the next byte. 277 */ 278 struct ice_rlan_ctx { 279 u16 head; 280 u16 cpuid; /* bigger than needed, see above for reason */ 281 #define ICE_RLAN_BASE_S 7 282 u64 base; 283 u16 qlen; 284 #define ICE_RLAN_CTX_DBUF_S 7 285 u16 dbuf; /* bigger than needed, see above for reason */ 286 #define ICE_RLAN_CTX_HBUF_S 6 287 u16 hbuf; /* bigger than needed, see above for reason */ 288 u8 dtype; 289 u8 dsize; 290 u8 crcstrip; 291 u8 l2tsel; 292 u8 hsplit_0; 293 u8 hsplit_1; 294 u8 showiv; 295 u32 rxmax; /* bigger than needed, see above for reason */ 296 u8 tphrdesc_ena; 297 u8 tphwdesc_ena; 298 u8 tphdata_ena; 299 u8 tphhead_ena; 300 u16 lrxqthresh; /* bigger than needed, see above for reason */ 301 u8 prefena; /* NOTE: normally must be set to 1 at init */ 302 }; 303 304 struct ice_ctx_ele { 305 u16 offset; 306 u16 size_of; 307 u16 width; 308 u16 lsb; 309 }; 310 311 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ 312 .offset = offsetof(struct _struct, _ele), \ 313 .size_of = sizeof_field(struct _struct, _ele), \ 314 .width = _width, \ 315 .lsb = _lsb, \ 316 } 317 318 /* for hsplit_0 field of Rx RLAN context */ 319 enum ice_rlan_ctx_rx_hsplit_0 { 320 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, 321 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, 322 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, 323 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 324 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, 325 }; 326 327 /* for hsplit_1 field of Rx RLAN context */ 328 enum ice_rlan_ctx_rx_hsplit_1 { 329 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, 330 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, 331 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, 332 }; 333 334 /* Tx Descriptor */ 335 struct ice_tx_desc { 336 __le64 buf_addr; /* Address of descriptor's data buf */ 337 __le64 cmd_type_offset_bsz; 338 }; 339 340 enum ice_tx_desc_dtype_value { 341 ICE_TX_DESC_DTYPE_DATA = 0x0, 342 ICE_TX_DESC_DTYPE_CTX = 0x1, 343 /* DESC_DONE - HW has completed write-back of descriptor */ 344 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, 345 }; 346 347 #define ICE_TXD_QW1_CMD_S 4 348 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) 349 350 enum ice_tx_desc_cmd_bits { 351 ICE_TX_DESC_CMD_EOP = 0x0001, 352 ICE_TX_DESC_CMD_RS = 0x0002, 353 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, 354 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, 355 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, 356 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, 357 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, 358 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, 359 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, 360 }; 361 362 #define ICE_TXD_QW1_OFFSET_S 16 363 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) 364 365 enum ice_tx_desc_len_fields { 366 /* Note: These are predefined bit offsets */ 367 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 368 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 369 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 370 }; 371 372 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) 373 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) 374 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) 375 376 /* Tx descriptor field limits in bytes */ 377 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ 378 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) 379 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ 380 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) 381 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ 382 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) 383 384 #define ICE_TXD_QW1_TX_BUF_SZ_S 34 385 #define ICE_TXD_QW1_L2TAG1_S 48 386 387 /* Context descriptors */ 388 struct ice_tx_ctx_desc { 389 __le32 tunneling_params; 390 __le16 l2tag2; 391 __le16 rsvd; 392 __le64 qw1; 393 }; 394 395 #define ICE_TXD_CTX_QW1_CMD_S 4 396 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) 397 398 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 399 #define ICE_TXD_CTX_QW1_TSO_LEN_M \ 400 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) 401 402 #define ICE_TXD_CTX_QW1_MSS_S 50 403 404 enum ice_tx_ctx_desc_cmd_bits { 405 ICE_TX_CTX_DESC_TSO = 0x01, 406 ICE_TX_CTX_DESC_TSYN = 0x02, 407 ICE_TX_CTX_DESC_IL2TAG2 = 0x04, 408 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 409 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 410 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 411 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 412 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, 413 ICE_TX_CTX_DESC_RESERVED = 0x40 414 }; 415 416 #define ICE_LAN_TXQ_MAX_QGRPS 127 417 #define ICE_LAN_TXQ_MAX_QDIS 1023 418 419 /* Tx queue context data 420 * 421 * The sizes of the variables may be larger than needed due to crossing byte 422 * boundaries. If we do not have the width of the variable set to the correct 423 * size then we could end up shifting bits off the top of the variable when the 424 * variable is at the top of a byte and crosses over into the next byte. 425 */ 426 struct ice_tlan_ctx { 427 #define ICE_TLAN_CTX_BASE_S 7 428 u64 base; /* base is defined in 128-byte units */ 429 u8 port_num; 430 u16 cgd_num; /* bigger than needed, see above for reason */ 431 u8 pf_num; 432 u16 vmvf_num; 433 u8 vmvf_type; 434 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0 435 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 436 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 437 u16 src_vsi; 438 u8 tsyn_ena; 439 u8 internal_usage_flag; 440 u8 alt_vlan; 441 u16 cpuid; /* bigger than needed, see above for reason */ 442 u8 wb_mode; 443 u8 tphrd_desc; 444 u8 tphrd; 445 u8 tphwr_desc; 446 u16 cmpq_id; 447 u16 qnum_in_func; 448 u8 itr_notification_mode; 449 u8 adjust_prof_id; 450 u32 qlen; /* bigger than needed, see above for reason */ 451 u8 quanta_prof_idx; 452 u8 tso_ena; 453 u16 tso_qnum; 454 u8 legacy_int; 455 u8 drop_ena; 456 u8 cache_prof_idx; 457 u8 pkt_shaper_prof_idx; 458 u8 int_q_state; /* width not needed - internal do not write */ 459 }; 460 461 /* macro to make the table lines short */ 462 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 463 { PTYPE, \ 464 1, \ 465 ICE_RX_PTYPE_OUTER_##OUTER_IP, \ 466 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 467 ICE_RX_PTYPE_##OUTER_FRAG, \ 468 ICE_RX_PTYPE_TUNNEL_##T, \ 469 ICE_RX_PTYPE_TUNNEL_END_##TE, \ 470 ICE_RX_PTYPE_##TEF, \ 471 ICE_RX_PTYPE_INNER_PROT_##I, \ 472 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } 473 474 #define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 475 476 /* shorter macros makes the table fit but are terse */ 477 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG 478 479 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 480 static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { 481 /* L2 Packet types */ 482 ICE_PTT_UNUSED_ENTRY(0), 483 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 484 ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 485 }; 486 487 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) 488 { 489 return ice_ptype_lkup[ptype]; 490 } 491 492 #define ICE_LINK_SPEED_UNKNOWN 0 493 #define ICE_LINK_SPEED_10MBPS 10 494 #define ICE_LINK_SPEED_100MBPS 100 495 #define ICE_LINK_SPEED_1000MBPS 1000 496 #define ICE_LINK_SPEED_2500MBPS 2500 497 #define ICE_LINK_SPEED_5000MBPS 5000 498 #define ICE_LINK_SPEED_10000MBPS 10000 499 #define ICE_LINK_SPEED_20000MBPS 20000 500 #define ICE_LINK_SPEED_25000MBPS 25000 501 #define ICE_LINK_SPEED_40000MBPS 40000 502 #define ICE_LINK_SPEED_50000MBPS 50000 503 #define ICE_LINK_SPEED_100000MBPS 100000 504 505 #endif /* _ICE_LAN_TX_RX_H_ */ 506