1 /* Intel(R) Ethernet Switch Host Interface Driver 2 * Copyright(c) 2013 - 2016 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19 */ 20 21 #include "fm10k_pf.h" 22 #include "fm10k_vf.h" 23 24 /** 25 * fm10k_reset_hw_pf - PF hardware reset 26 * @hw: pointer to hardware structure 27 * 28 * This function should return the hardware to a state similar to the 29 * one it is in after being powered on. 30 **/ 31 static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) 32 { 33 s32 err; 34 u32 reg; 35 u16 i; 36 37 /* Disable interrupts */ 38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); 39 40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ 41 fm10k_write_reg(hw, FM10K_ITR2(0), 0); 42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 43 44 /* We assume here Tx and Rx queue 0 are owned by the PF */ 45 46 /* Shut off VF access to their queues forcing them to queue 0 */ 47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { 48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 50 } 51 52 /* shut down all rings */ 53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); 54 if (err) 55 return err; 56 57 /* Verify that DMA is no longer active */ 58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); 59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) 60 return FM10K_ERR_DMA_PENDING; 61 62 /* verify the switch is ready for reset */ 63 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 64 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY)) 65 goto out; 66 67 /* Inititate data path reset */ 68 reg |= FM10K_DMA_CTRL_DATAPATH_RESET; 69 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); 70 71 /* Flush write and allow 100us for reset to complete */ 72 fm10k_write_flush(hw); 73 udelay(FM10K_RESET_TIMEOUT); 74 75 /* Verify we made it out of reset */ 76 reg = fm10k_read_reg(hw, FM10K_IP); 77 if (!(reg & FM10K_IP_NOTINRESET)) 78 err = FM10K_ERR_RESET_FAILED; 79 80 out: 81 return err; 82 } 83 84 /** 85 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support 86 * @hw: pointer to hardware structure 87 * 88 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. 89 **/ 90 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) 91 { 92 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); 93 94 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); 95 } 96 97 /** 98 * fm10k_init_hw_pf - PF hardware initialization 99 * @hw: pointer to hardware structure 100 * 101 **/ 102 static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) 103 { 104 u32 dma_ctrl, txqctl; 105 u16 i; 106 107 /* Establish default VSI as valid */ 108 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); 109 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), 110 FM10K_DGLORTMAP_ANY); 111 112 /* Invalidate all other GLORT entries */ 113 for (i = 1; i < FM10K_DGLORT_COUNT; i++) 114 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); 115 116 /* reset ITR2(0) to point to itself */ 117 fm10k_write_reg(hw, FM10K_ITR2(0), 0); 118 119 /* reset VF ITR2(0) to point to 0 avoid PF registers */ 120 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); 121 122 /* loop through all PF ITR2 registers pointing them to the previous */ 123 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) 124 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 125 126 /* Enable interrupt moderator if not already enabled */ 127 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 128 129 /* compute the default txqctl configuration */ 130 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | 131 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); 132 133 for (i = 0; i < FM10K_MAX_QUEUES; i++) { 134 /* configure rings for 256 Queue / 32 Descriptor cache mode */ 135 fm10k_write_reg(hw, FM10K_TQDLOC(i), 136 (i * FM10K_TQDLOC_BASE_32_DESC) | 137 FM10K_TQDLOC_SIZE_32_DESC); 138 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 139 140 /* configure rings to provide TPH processing hints */ 141 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), 142 FM10K_TPH_TXCTRL_DESC_TPHEN | 143 FM10K_TPH_TXCTRL_DESC_RROEN | 144 FM10K_TPH_TXCTRL_DESC_WROEN | 145 FM10K_TPH_TXCTRL_DATA_RROEN); 146 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), 147 FM10K_TPH_RXCTRL_DESC_TPHEN | 148 FM10K_TPH_RXCTRL_DESC_RROEN | 149 FM10K_TPH_RXCTRL_DATA_WROEN | 150 FM10K_TPH_RXCTRL_HDR_WROEN); 151 } 152 153 /* set max hold interval to align with 1.024 usec in all modes and 154 * store ITR scale 155 */ 156 switch (hw->bus.speed) { 157 case fm10k_bus_speed_2500: 158 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; 159 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1; 160 break; 161 case fm10k_bus_speed_5000: 162 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; 163 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2; 164 break; 165 case fm10k_bus_speed_8000: 166 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; 167 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; 168 break; 169 default: 170 dma_ctrl = 0; 171 /* just in case, assume Gen3 ITR scale */ 172 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; 173 break; 174 } 175 176 /* Configure TSO flags */ 177 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); 178 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); 179 180 /* Enable DMA engine 181 * Set Rx Descriptor size to 32 182 * Set Minimum MSS to 64 183 * Set Maximum number of Rx queues to 256 / 32 Descriptor 184 */ 185 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | 186 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | 187 FM10K_DMA_CTRL_32_DESC; 188 189 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); 190 191 /* record maximum queue count, we limit ourselves to 128 */ 192 hw->mac.max_queues = FM10K_MAX_QUEUES_PF; 193 194 /* We support either 64 VFs or 7 VFs depending on if we have ARI */ 195 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; 196 197 return 0; 198 } 199 200 /** 201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table 202 * @hw: pointer to hardware structure 203 * @vid: VLAN ID to add to table 204 * @vsi: Index indicating VF ID or PF ID in table 205 * @set: Indicates if this is a set or clear operation 206 * 207 * This function adds or removes the corresponding VLAN ID from the VLAN 208 * filter table for the corresponding function. In addition to the 209 * standard set/clear that supports one bit a multi-bit write is 210 * supported to set 64 bits at a time. 211 **/ 212 static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) 213 { 214 u32 vlan_table, reg, mask, bit, len; 215 216 /* verify the VSI index is valid */ 217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX) 218 return FM10K_ERR_PARAM; 219 220 /* VLAN multi-bit write: 221 * The multi-bit write has several parts to it. 222 * 24 16 8 0 223 * 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 225 * | RSVD0 | Length |C|RSVD0| VLAN ID | 226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 227 * 228 * VLAN ID: Vlan Starting value 229 * RSVD0: Reserved section, must be 0 230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) 231 * Length: Number of times to repeat the bit being set 232 */ 233 len = vid >> 16; 234 vid = (vid << 17) >> 17; 235 236 /* verify the reserved 0 fields are 0 */ 237 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) 238 return FM10K_ERR_PARAM; 239 240 /* Loop through the table updating all required VLANs */ 241 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; 242 len < FM10K_VLAN_TABLE_VID_MAX; 243 len -= 32 - bit, reg++, bit = 0) { 244 /* record the initial state of the register */ 245 vlan_table = fm10k_read_reg(hw, reg); 246 247 /* truncate mask if we are at the start or end of the run */ 248 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; 249 250 /* make necessary modifications to the register */ 251 mask &= set ? ~vlan_table : vlan_table; 252 if (mask) 253 fm10k_write_reg(hw, reg, vlan_table ^ mask); 254 } 255 256 return 0; 257 } 258 259 /** 260 * fm10k_read_mac_addr_pf - Read device MAC address 261 * @hw: pointer to the HW structure 262 * 263 * Reads the device MAC address from the SM_AREA and stores the value. 264 **/ 265 static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) 266 { 267 u8 perm_addr[ETH_ALEN]; 268 u32 serial_num; 269 270 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); 271 272 /* last byte should be all 1's */ 273 if ((~serial_num) << 24) 274 return FM10K_ERR_INVALID_MAC_ADDR; 275 276 perm_addr[0] = (u8)(serial_num >> 24); 277 perm_addr[1] = (u8)(serial_num >> 16); 278 perm_addr[2] = (u8)(serial_num >> 8); 279 280 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); 281 282 /* first byte should be all 1's */ 283 if ((~serial_num) >> 24) 284 return FM10K_ERR_INVALID_MAC_ADDR; 285 286 perm_addr[3] = (u8)(serial_num >> 16); 287 perm_addr[4] = (u8)(serial_num >> 8); 288 perm_addr[5] = (u8)(serial_num); 289 290 ether_addr_copy(hw->mac.perm_addr, perm_addr); 291 ether_addr_copy(hw->mac.addr, perm_addr); 292 293 return 0; 294 } 295 296 /** 297 * fm10k_glort_valid_pf - Validate that the provided glort is valid 298 * @hw: pointer to the HW structure 299 * @glort: base glort to be validated 300 * 301 * This function will return an error if the provided glort is invalid 302 **/ 303 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) 304 { 305 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; 306 307 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); 308 } 309 310 /** 311 * fm10k_update_xc_addr_pf - Update device addresses 312 * @hw: pointer to the HW structure 313 * @glort: base resource tag for this request 314 * @mac: MAC address to add/remove from table 315 * @vid: VLAN ID to add/remove from table 316 * @add: Indicates if this is an add or remove operation 317 * @flags: flags field to indicate add and secure 318 * 319 * This function generates a message to the Switch API requesting 320 * that the given logical port add/remove the given L2 MAC/VLAN address. 321 **/ 322 static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, 323 const u8 *mac, u16 vid, bool add, u8 flags) 324 { 325 struct fm10k_mbx_info *mbx = &hw->mbx; 326 struct fm10k_mac_update mac_update; 327 u32 msg[5]; 328 329 /* clear set bit from VLAN ID */ 330 vid &= ~FM10K_VLAN_CLEAR; 331 332 /* if glort or VLAN are not valid return error */ 333 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) 334 return FM10K_ERR_PARAM; 335 336 /* record fields */ 337 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | 338 ((u32)mac[3] << 16) | 339 ((u32)mac[4] << 8) | 340 ((u32)mac[5])); 341 mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) | 342 ((u16)mac[1])); 343 mac_update.vlan = cpu_to_le16(vid); 344 mac_update.glort = cpu_to_le16(glort); 345 mac_update.action = add ? 0 : 1; 346 mac_update.flags = flags; 347 348 /* populate mac_update fields */ 349 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); 350 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, 351 &mac_update, sizeof(mac_update)); 352 353 /* load onto outgoing mailbox */ 354 return mbx->ops.enqueue_tx(hw, mbx, msg); 355 } 356 357 /** 358 * fm10k_update_uc_addr_pf - Update device unicast addresses 359 * @hw: pointer to the HW structure 360 * @glort: base resource tag for this request 361 * @mac: MAC address to add/remove from table 362 * @vid: VLAN ID to add/remove from table 363 * @add: Indicates if this is an add or remove operation 364 * @flags: flags field to indicate add and secure 365 * 366 * This function is used to add or remove unicast addresses for 367 * the PF. 368 **/ 369 static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, 370 const u8 *mac, u16 vid, bool add, u8 flags) 371 { 372 /* verify MAC address is valid */ 373 if (!is_valid_ether_addr(mac)) 374 return FM10K_ERR_PARAM; 375 376 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); 377 } 378 379 /** 380 * fm10k_update_mc_addr_pf - Update device multicast addresses 381 * @hw: pointer to the HW structure 382 * @glort: base resource tag for this request 383 * @mac: MAC address to add/remove from table 384 * @vid: VLAN ID to add/remove from table 385 * @add: Indicates if this is an add or remove operation 386 * 387 * This function is used to add or remove multicast MAC addresses for 388 * the PF. 389 **/ 390 static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, 391 const u8 *mac, u16 vid, bool add) 392 { 393 /* verify multicast address is valid */ 394 if (!is_multicast_ether_addr(mac)) 395 return FM10K_ERR_PARAM; 396 397 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); 398 } 399 400 /** 401 * fm10k_update_xcast_mode_pf - Request update of multicast mode 402 * @hw: pointer to hardware structure 403 * @glort: base resource tag for this request 404 * @mode: integer value indicating mode being requested 405 * 406 * This function will attempt to request a higher mode for the port 407 * so that it can enable either multicast, multicast promiscuous, or 408 * promiscuous mode of operation. 409 **/ 410 static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) 411 { 412 struct fm10k_mbx_info *mbx = &hw->mbx; 413 u32 msg[3], xcast_mode; 414 415 if (mode > FM10K_XCAST_MODE_NONE) 416 return FM10K_ERR_PARAM; 417 418 /* if glort is not valid return error */ 419 if (!fm10k_glort_valid_pf(hw, glort)) 420 return FM10K_ERR_PARAM; 421 422 /* write xcast mode as a single u32 value, 423 * lower 16 bits: glort 424 * upper 16 bits: mode 425 */ 426 xcast_mode = ((u32)mode << 16) | glort; 427 428 /* generate message requesting to change xcast mode */ 429 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); 430 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); 431 432 /* load onto outgoing mailbox */ 433 return mbx->ops.enqueue_tx(hw, mbx, msg); 434 } 435 436 /** 437 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list 438 * @hw: pointer to hardware structure 439 * 440 * This function walks through the MSI-X vector table to determine the 441 * number of active interrupts and based on that information updates the 442 * interrupt moderator linked list. 443 **/ 444 static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) 445 { 446 u32 i; 447 448 /* Disable interrupt moderator */ 449 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 450 451 /* loop through PF from last to first looking enabled vectors */ 452 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { 453 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 454 break; 455 } 456 457 /* always reset VFITR2[0] to point to last enabled PF vector */ 458 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); 459 460 /* reset ITR2[0] to point to last enabled PF vector */ 461 if (!hw->iov.num_vfs) 462 fm10k_write_reg(hw, FM10K_ITR2(0), i); 463 464 /* Enable interrupt moderator */ 465 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 466 } 467 468 /** 469 * fm10k_update_lport_state_pf - Notify the switch of a change in port state 470 * @hw: pointer to the HW structure 471 * @glort: base resource tag for this request 472 * @count: number of logical ports being updated 473 * @enable: boolean value indicating enable or disable 474 * 475 * This function is used to add/remove a logical port from the switch. 476 **/ 477 static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, 478 u16 count, bool enable) 479 { 480 struct fm10k_mbx_info *mbx = &hw->mbx; 481 u32 msg[3], lport_msg; 482 483 /* do nothing if we are being asked to create or destroy 0 ports */ 484 if (!count) 485 return 0; 486 487 /* if glort is not valid return error */ 488 if (!fm10k_glort_valid_pf(hw, glort)) 489 return FM10K_ERR_PARAM; 490 491 /* reset multicast mode if deleting lport */ 492 if (!enable) 493 fm10k_update_xcast_mode_pf(hw, glort, FM10K_XCAST_MODE_NONE); 494 495 /* construct the lport message from the 2 pieces of data we have */ 496 lport_msg = ((u32)count << 16) | glort; 497 498 /* generate lport create/delete message */ 499 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : 500 FM10K_PF_MSG_ID_LPORT_DELETE); 501 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); 502 503 /* load onto outgoing mailbox */ 504 return mbx->ops.enqueue_tx(hw, mbx, msg); 505 } 506 507 /** 508 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues 509 * @hw: pointer to hardware structure 510 * @dglort: pointer to dglort configuration structure 511 * 512 * Reads the configuration structure contained in dglort_cfg and uses 513 * that information to then populate a DGLORTMAP/DEC entry and the queues 514 * to which it has been assigned. 515 **/ 516 static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, 517 struct fm10k_dglort_cfg *dglort) 518 { 519 u16 glort, queue_count, vsi_count, pc_count; 520 u16 vsi, queue, pc, q_idx; 521 u32 txqctl, dglortdec, dglortmap; 522 523 /* verify the dglort pointer */ 524 if (!dglort) 525 return FM10K_ERR_PARAM; 526 527 /* verify the dglort values */ 528 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || 529 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || 530 (dglort->queue_l > 8) || (dglort->queue_b >= 256)) 531 return FM10K_ERR_PARAM; 532 533 /* determine count of VSIs and queues */ 534 queue_count = BIT(dglort->rss_l + dglort->pc_l); 535 vsi_count = BIT(dglort->vsi_l + dglort->queue_l); 536 glort = dglort->glort; 537 q_idx = dglort->queue_b; 538 539 /* configure SGLORT for queues */ 540 for (vsi = 0; vsi < vsi_count; vsi++, glort++) { 541 for (queue = 0; queue < queue_count; queue++, q_idx++) { 542 if (q_idx >= FM10K_MAX_QUEUES) 543 break; 544 545 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); 546 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); 547 } 548 } 549 550 /* determine count of PCs and queues */ 551 queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l); 552 pc_count = BIT(dglort->pc_l); 553 554 /* configure PC for Tx queues */ 555 for (pc = 0; pc < pc_count; pc++) { 556 q_idx = pc + dglort->queue_b; 557 for (queue = 0; queue < queue_count; queue++) { 558 if (q_idx >= FM10K_MAX_QUEUES) 559 break; 560 561 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); 562 txqctl &= ~FM10K_TXQCTL_PC_MASK; 563 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; 564 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); 565 566 q_idx += pc_count; 567 } 568 } 569 570 /* configure DGLORTDEC */ 571 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | 572 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | 573 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | 574 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | 575 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | 576 ((u32)(dglort->queue_l)); 577 if (dglort->inner_rss) 578 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; 579 580 /* configure DGLORTMAP */ 581 dglortmap = (dglort->idx == fm10k_dglort_default) ? 582 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; 583 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; 584 dglortmap |= dglort->glort; 585 586 /* write values to hardware */ 587 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); 588 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); 589 590 return 0; 591 } 592 593 u16 fm10k_queues_per_pool(struct fm10k_hw *hw) 594 { 595 u16 num_pools = hw->iov.num_pools; 596 597 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? 598 8 : FM10K_MAX_QUEUES_POOL; 599 } 600 601 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) 602 { 603 u16 num_vfs = hw->iov.num_vfs; 604 u16 vf_q_idx = FM10K_MAX_QUEUES; 605 606 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); 607 608 return vf_q_idx; 609 } 610 611 static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) 612 { 613 u16 num_pools = hw->iov.num_pools; 614 615 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : 616 FM10K_MAX_VECTORS_POOL; 617 } 618 619 static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) 620 { 621 u16 vf_v_idx = FM10K_MAX_VECTORS_PF; 622 623 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; 624 625 return vf_v_idx; 626 } 627 628 /** 629 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization 630 * @hw: pointer to the HW structure 631 * @num_vfs: number of VFs to be allocated 632 * @num_pools: number of virtualization pools to be allocated 633 * 634 * Allocates queues and traffic classes to virtualization entities to prepare 635 * the PF for SR-IOV and VMDq 636 **/ 637 static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, 638 u16 num_pools) 639 { 640 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; 641 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; 642 int i, j; 643 644 /* hardware only supports up to 64 pools */ 645 if (num_pools > 64) 646 return FM10K_ERR_PARAM; 647 648 /* the number of VFs cannot exceed the number of pools */ 649 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) 650 return FM10K_ERR_PARAM; 651 652 /* record number of virtualization entities */ 653 hw->iov.num_vfs = num_vfs; 654 hw->iov.num_pools = num_pools; 655 656 /* determine qmap offsets and counts */ 657 qmap_stride = (num_vfs > 8) ? 32 : 256; 658 qpp = fm10k_queues_per_pool(hw); 659 vpp = fm10k_vectors_per_pool(hw); 660 661 /* calculate starting index for queues */ 662 vf_q_idx = fm10k_vf_queue_index(hw, 0); 663 qmap_idx = 0; 664 665 /* establish TCs with -1 credits and no quanta to prevent transmit */ 666 for (i = 0; i < num_vfs; i++) { 667 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); 668 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); 669 fm10k_write_reg(hw, FM10K_TC_CREDIT(i), 670 FM10K_TC_CREDIT_CREDIT_MASK); 671 } 672 673 /* zero out all mbmem registers */ 674 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) 675 fm10k_write_reg(hw, FM10K_MBMEM(i), 0); 676 677 /* clear event notification of VF FLR */ 678 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); 679 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); 680 681 /* loop through unallocated rings assigning them back to PF */ 682 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { 683 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 684 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | 685 FM10K_TXQCTL_UNLIMITED_BW | vid); 686 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); 687 } 688 689 /* PF should have already updated VFITR2[0] */ 690 691 /* update all ITR registers to flow to VFITR2[0] */ 692 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { 693 if (!(i & (vpp - 1))) 694 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); 695 else 696 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 697 } 698 699 /* update PF ITR2[0] to reference the last vector */ 700 fm10k_write_reg(hw, FM10K_ITR2(0), 701 fm10k_vf_vector_index(hw, num_vfs - 1)); 702 703 /* loop through rings populating rings and TCs */ 704 for (i = 0; i < num_vfs; i++) { 705 /* record index for VF queue 0 for use in end of loop */ 706 vf_q_idx0 = vf_q_idx; 707 708 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { 709 /* assign VF and locked TC to queues */ 710 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 711 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), 712 (i << FM10K_TXQCTL_TC_SHIFT) | i | 713 FM10K_TXQCTL_VF | vid); 714 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), 715 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 716 FM10K_RXDCTL_DROP_ON_EMPTY); 717 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), 718 (i << FM10K_RXQCTL_VF_SHIFT) | 719 FM10K_RXQCTL_VF); 720 721 /* map queue pair to VF */ 722 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 723 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); 724 } 725 726 /* repeat the first ring for all of the remaining VF rings */ 727 for (; j < qmap_stride; j++, qmap_idx++) { 728 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); 729 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); 730 } 731 } 732 733 /* loop through remaining indexes assigning all to queue 0 */ 734 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { 735 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 736 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); 737 qmap_idx++; 738 } 739 740 return 0; 741 } 742 743 /** 744 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF 745 * @hw: pointer to the HW structure 746 * @vf_idx: index of VF receiving GLORT 747 * @rate: Rate indicated in Mb/s 748 * 749 * Configured the TC for a given VF to allow only up to a given number 750 * of Mb/s of outgoing Tx throughput. 751 **/ 752 static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) 753 { 754 /* configure defaults */ 755 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; 756 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; 757 758 /* verify vf is in range */ 759 if (vf_idx >= hw->iov.num_vfs) 760 return FM10K_ERR_PARAM; 761 762 /* set interval to align with 4.096 usec in all modes */ 763 switch (hw->bus.speed) { 764 case fm10k_bus_speed_2500: 765 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; 766 break; 767 case fm10k_bus_speed_5000: 768 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; 769 break; 770 default: 771 break; 772 } 773 774 if (rate) { 775 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) 776 return FM10K_ERR_PARAM; 777 778 /* The quanta is measured in Bytes per 4.096 or 8.192 usec 779 * The rate is provided in Mbits per second 780 * To tralslate from rate to quanta we need to multiply the 781 * rate by 8.192 usec and divide by 8 bits/byte. To avoid 782 * dealing with floating point we can round the values up 783 * to the nearest whole number ratio which gives us 128 / 125. 784 */ 785 tc_rate = (rate * 128) / 125; 786 787 /* try to keep the rate limiting accurate by increasing 788 * the number of credits and interval for rates less than 4Gb/s 789 */ 790 if (rate < 4000) 791 interval <<= 1; 792 else 793 tc_rate >>= 1; 794 } 795 796 /* update rate limiter with new values */ 797 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); 798 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 799 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 800 801 return 0; 802 } 803 804 /** 805 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list 806 * @hw: pointer to the HW structure 807 * @vf_idx: index of VF receiving GLORT 808 * 809 * Update the interrupt moderator linked list to include any MSI-X 810 * interrupts which the VF has enabled in the MSI-X vector table. 811 **/ 812 static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) 813 { 814 u16 vf_v_idx, vf_v_limit, i; 815 816 /* verify vf is in range */ 817 if (vf_idx >= hw->iov.num_vfs) 818 return FM10K_ERR_PARAM; 819 820 /* determine vector offset and count */ 821 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 822 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 823 824 /* search for first vector that is not masked */ 825 for (i = vf_v_limit - 1; i > vf_v_idx; i--) { 826 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 827 break; 828 } 829 830 /* reset linked list so it now includes our active vectors */ 831 if (vf_idx == (hw->iov.num_vfs - 1)) 832 fm10k_write_reg(hw, FM10K_ITR2(0), i); 833 else 834 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); 835 836 return 0; 837 } 838 839 /** 840 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF 841 * @hw: pointer to the HW structure 842 * @vf_info: pointer to VF information structure 843 * 844 * Assign a MAC address and default VLAN to a VF and notify it of the update 845 **/ 846 static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, 847 struct fm10k_vf_info *vf_info) 848 { 849 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; 850 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; 851 s32 err = 0; 852 u16 vf_idx, vf_vid; 853 854 /* verify vf is in range */ 855 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) 856 return FM10K_ERR_PARAM; 857 858 /* determine qmap offsets and counts */ 859 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 860 queues_per_pool = fm10k_queues_per_pool(hw); 861 862 /* calculate starting index for queues */ 863 vf_idx = vf_info->vf_idx; 864 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 865 qmap_idx = qmap_stride * vf_idx; 866 867 /* MAP Tx queue back to 0 temporarily, and disable it */ 868 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 869 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 870 871 /* Determine correct default VLAN ID. The FM10K_VLAN_OVERRIDE bit is 872 * used here to indicate to the VF that it will not have privilege to 873 * write VLAN_TABLE. All policy is enforced on the PF but this allows 874 * the VF to correctly report errors to userspace rqeuests. 875 */ 876 if (vf_info->pf_vid) 877 vf_vid = vf_info->pf_vid | FM10K_VLAN_OVERRIDE; 878 else 879 vf_vid = vf_info->sw_vid; 880 881 /* generate MAC_ADDR request */ 882 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); 883 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, 884 vf_info->mac, vf_vid); 885 886 /* load onto outgoing mailbox, ignore any errors on enqueue */ 887 if (vf_info->mbx.ops.enqueue_tx) 888 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 889 890 /* verify ring has disabled before modifying base address registers */ 891 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 892 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { 893 /* limit ourselves to a 1ms timeout */ 894 if (timeout == 10) { 895 err = FM10K_ERR_DMA_PENDING; 896 goto err_out; 897 } 898 899 usleep_range(100, 200); 900 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 901 } 902 903 /* Update base address registers to contain MAC address */ 904 if (is_valid_ether_addr(vf_info->mac)) { 905 tdbal = (((u32)vf_info->mac[3]) << 24) | 906 (((u32)vf_info->mac[4]) << 16) | 907 (((u32)vf_info->mac[5]) << 8); 908 909 tdbah = (((u32)0xFF) << 24) | 910 (((u32)vf_info->mac[0]) << 16) | 911 (((u32)vf_info->mac[1]) << 8) | 912 ((u32)vf_info->mac[2]); 913 } 914 915 /* Record the base address into queue 0 */ 916 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); 917 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); 918 919 /* Provide the VF the ITR scale, using software-defined fields in TDLEN 920 * to pass the information during VF initialization. See definition of 921 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details. 922 */ 923 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale << 924 FM10K_TDLEN_ITR_SCALE_SHIFT); 925 926 err_out: 927 /* configure Queue control register */ 928 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & 929 FM10K_TXQCTL_VID_MASK; 930 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 931 FM10K_TXQCTL_VF | vf_idx; 932 933 /* assign VLAN ID */ 934 for (i = 0; i < queues_per_pool; i++) 935 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); 936 937 /* restore the queue back to VF ownership */ 938 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 939 return err; 940 } 941 942 /** 943 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF 944 * @hw: pointer to the HW structure 945 * @vf_info: pointer to VF information structure 946 * 947 * Reassign the interrupts and queues to a VF following an FLR 948 **/ 949 static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, 950 struct fm10k_vf_info *vf_info) 951 { 952 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; 953 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; 954 u16 vf_v_idx, vf_v_limit, vf_vid; 955 u8 vf_idx = vf_info->vf_idx; 956 int i; 957 958 /* verify vf is in range */ 959 if (vf_idx >= hw->iov.num_vfs) 960 return FM10K_ERR_PARAM; 961 962 /* clear event notification of VF FLR */ 963 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32)); 964 965 /* force timeout and then disconnect the mailbox */ 966 vf_info->mbx.timeout = 0; 967 if (vf_info->mbx.ops.disconnect) 968 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); 969 970 /* determine vector offset and count */ 971 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 972 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 973 974 /* determine qmap offsets and counts */ 975 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 976 queues_per_pool = fm10k_queues_per_pool(hw); 977 qmap_idx = qmap_stride * vf_idx; 978 979 /* make all the queues inaccessible to the VF */ 980 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { 981 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 982 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 983 } 984 985 /* calculate starting index for queues */ 986 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 987 988 /* determine correct default VLAN ID */ 989 if (vf_info->pf_vid) 990 vf_vid = vf_info->pf_vid; 991 else 992 vf_vid = vf_info->sw_vid; 993 994 /* configure Queue control register */ 995 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | 996 (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 997 FM10K_TXQCTL_VF | vf_idx; 998 rxqctl = (vf_idx << FM10K_RXQCTL_VF_SHIFT) | FM10K_RXQCTL_VF; 999 1000 /* stop further DMA and reset queue ownership back to VF */ 1001 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { 1002 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 1003 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 1004 fm10k_write_reg(hw, FM10K_RXDCTL(i), 1005 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 1006 FM10K_RXDCTL_DROP_ON_EMPTY); 1007 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); 1008 } 1009 1010 /* reset TC with -1 credits and no quanta to prevent transmit */ 1011 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); 1012 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); 1013 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), 1014 FM10K_TC_CREDIT_CREDIT_MASK); 1015 1016 /* update our first entry in the table based on previous VF */ 1017 if (!vf_idx) 1018 hw->mac.ops.update_int_moderator(hw); 1019 else 1020 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); 1021 1022 /* reset linked list so it now includes our active vectors */ 1023 if (vf_idx == (hw->iov.num_vfs - 1)) 1024 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); 1025 else 1026 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); 1027 1028 /* link remaining vectors so that next points to previous */ 1029 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) 1030 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); 1031 1032 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ 1033 for (i = FM10K_VFMBMEM_LEN; i--;) 1034 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); 1035 for (i = FM10K_VLAN_TABLE_SIZE; i--;) 1036 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); 1037 for (i = FM10K_RETA_SIZE; i--;) 1038 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); 1039 for (i = FM10K_RSSRK_SIZE; i--;) 1040 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); 1041 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); 1042 1043 /* Update base address registers to contain MAC address */ 1044 if (is_valid_ether_addr(vf_info->mac)) { 1045 tdbal = (((u32)vf_info->mac[3]) << 24) | 1046 (((u32)vf_info->mac[4]) << 16) | 1047 (((u32)vf_info->mac[5]) << 8); 1048 tdbah = (((u32)0xFF) << 24) | 1049 (((u32)vf_info->mac[0]) << 16) | 1050 (((u32)vf_info->mac[1]) << 8) | 1051 ((u32)vf_info->mac[2]); 1052 } 1053 1054 /* map queue pairs back to VF from last to first */ 1055 for (i = queues_per_pool; i--;) { 1056 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); 1057 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); 1058 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an 1059 * explanation of how TDLEN is used. 1060 */ 1061 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i), 1062 hw->mac.itr_scale << 1063 FM10K_TDLEN_ITR_SCALE_SHIFT); 1064 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); 1065 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); 1066 } 1067 1068 /* repeat the first ring for all the remaining VF rings */ 1069 for (i = queues_per_pool; i < qmap_stride; i++) { 1070 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); 1071 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); 1072 } 1073 1074 return 0; 1075 } 1076 1077 /** 1078 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF 1079 * @hw: pointer to hardware structure 1080 * @vf_info: pointer to VF information structure 1081 * @lport_idx: Logical port offset from the hardware glort 1082 * @flags: Set of capability flags to extend port beyond basic functionality 1083 * 1084 * This function allows enabling a VF port by assigning it a GLORT and 1085 * setting the flags so that it can enable an Rx mode. 1086 **/ 1087 static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, 1088 struct fm10k_vf_info *vf_info, 1089 u16 lport_idx, u8 flags) 1090 { 1091 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; 1092 1093 /* if glort is not valid return error */ 1094 if (!fm10k_glort_valid_pf(hw, glort)) 1095 return FM10K_ERR_PARAM; 1096 1097 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; 1098 vf_info->glort = glort; 1099 1100 return 0; 1101 } 1102 1103 /** 1104 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF 1105 * @hw: pointer to hardware structure 1106 * @vf_info: pointer to VF information structure 1107 * 1108 * This function disables a VF port by stripping it of a GLORT and 1109 * setting the flags so that it cannot enable any Rx mode. 1110 **/ 1111 static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, 1112 struct fm10k_vf_info *vf_info) 1113 { 1114 u32 msg[1]; 1115 1116 /* need to disable the port if it is already enabled */ 1117 if (FM10K_VF_FLAG_ENABLED(vf_info)) { 1118 /* notify switch that this port has been disabled */ 1119 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); 1120 1121 /* generate port state response to notify VF it is not ready */ 1122 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1123 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 1124 } 1125 1126 /* clear flags and glort if it exists */ 1127 vf_info->vf_flags = 0; 1128 vf_info->glort = 0; 1129 } 1130 1131 /** 1132 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs 1133 * @hw: pointer to hardware structure 1134 * @q: stats for all queues of a VF 1135 * @vf_idx: index of VF 1136 * 1137 * This function collects queue stats for VFs. 1138 **/ 1139 static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, 1140 struct fm10k_hw_stats_q *q, 1141 u16 vf_idx) 1142 { 1143 u32 idx, qpp; 1144 1145 /* get stats for all of the queues */ 1146 qpp = fm10k_queues_per_pool(hw); 1147 idx = fm10k_vf_queue_index(hw, vf_idx); 1148 fm10k_update_hw_stats_q(hw, q, idx, qpp); 1149 } 1150 1151 /** 1152 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF 1153 * @hw: Pointer to hardware structure 1154 * @results: Pointer array to message, results[0] is pointer to message 1155 * @mbx: Pointer to mailbox information structure 1156 * 1157 * This function is a default handler for MSI-X requests from the VF. The 1158 * assumption is that in this case it is acceptable to just directly 1159 * hand off the message from the VF to the underlying shared code. 1160 **/ 1161 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, 1162 struct fm10k_mbx_info *mbx) 1163 { 1164 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1165 u8 vf_idx = vf_info->vf_idx; 1166 1167 return hw->iov.ops.assign_int_moderator(hw, vf_idx); 1168 } 1169 1170 /** 1171 * fm10k_iov_select_vid - Select correct default VLAN ID 1172 * @hw: Pointer to hardware structure 1173 * @vid: VLAN ID to correct 1174 * 1175 * Will report an error if the VLAN ID is out of range. For VID = 0, it will 1176 * return either the pf_vid or sw_vid depending on which one is set. 1177 */ 1178 static s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid) 1179 { 1180 if (!vid) 1181 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid; 1182 else if (vf_info->pf_vid && vid != vf_info->pf_vid) 1183 return FM10K_ERR_PARAM; 1184 else 1185 return vid; 1186 } 1187 1188 /** 1189 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF 1190 * @hw: Pointer to hardware structure 1191 * @results: Pointer array to message, results[0] is pointer to message 1192 * @mbx: Pointer to mailbox information structure 1193 * 1194 * This function is a default handler for MAC/VLAN requests from the VF. 1195 * The assumption is that in this case it is acceptable to just directly 1196 * hand off the message from the VF to the underlying shared code. 1197 **/ 1198 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, 1199 struct fm10k_mbx_info *mbx) 1200 { 1201 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1202 u8 mac[ETH_ALEN]; 1203 u32 *result; 1204 int err = 0; 1205 bool set; 1206 u16 vlan; 1207 u32 vid; 1208 1209 /* we shouldn't be updating rules on a disabled interface */ 1210 if (!FM10K_VF_FLAG_ENABLED(vf_info)) 1211 err = FM10K_ERR_PARAM; 1212 1213 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { 1214 result = results[FM10K_MAC_VLAN_MSG_VLAN]; 1215 1216 /* record VLAN id requested */ 1217 err = fm10k_tlv_attr_get_u32(result, &vid); 1218 if (err) 1219 return err; 1220 1221 set = !(vid & FM10K_VLAN_CLEAR); 1222 vid &= ~FM10K_VLAN_CLEAR; 1223 1224 /* if the length field has been set, this is a multi-bit 1225 * update request. For multi-bit requests, simply disallow 1226 * them when the pf_vid has been set. In this case, the PF 1227 * should have already cleared the VLAN_TABLE, and if we 1228 * allowed them, it could allow a rogue VF to receive traffic 1229 * on a VLAN it was not assigned. In the single-bit case, we 1230 * need to modify requests for VLAN 0 to use the default PF or 1231 * SW vid when assigned. 1232 */ 1233 1234 if (vid >> 16) { 1235 /* prevent multi-bit requests when PF has 1236 * administratively set the VLAN for this VF 1237 */ 1238 if (vf_info->pf_vid) 1239 return FM10K_ERR_PARAM; 1240 } else { 1241 err = fm10k_iov_select_vid(vf_info, (u16)vid); 1242 if (err < 0) 1243 return err; 1244 1245 vid = err; 1246 } 1247 1248 /* update VSI info for VF in regards to VLAN table */ 1249 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set); 1250 } 1251 1252 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { 1253 result = results[FM10K_MAC_VLAN_MSG_MAC]; 1254 1255 /* record unicast MAC address requested */ 1256 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1257 if (err) 1258 return err; 1259 1260 /* block attempts to set MAC for a locked device */ 1261 if (is_valid_ether_addr(vf_info->mac) && 1262 !ether_addr_equal(mac, vf_info->mac)) 1263 return FM10K_ERR_PARAM; 1264 1265 set = !(vlan & FM10K_VLAN_CLEAR); 1266 vlan &= ~FM10K_VLAN_CLEAR; 1267 1268 err = fm10k_iov_select_vid(vf_info, vlan); 1269 if (err < 0) 1270 return err; 1271 1272 vlan = (u16)err; 1273 1274 /* notify switch of request for new unicast address */ 1275 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, 1276 mac, vlan, set, 0); 1277 } 1278 1279 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { 1280 result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; 1281 1282 /* record multicast MAC address requested */ 1283 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1284 if (err) 1285 return err; 1286 1287 /* verify that the VF is allowed to request multicast */ 1288 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) 1289 return FM10K_ERR_PARAM; 1290 1291 set = !(vlan & FM10K_VLAN_CLEAR); 1292 vlan &= ~FM10K_VLAN_CLEAR; 1293 1294 err = fm10k_iov_select_vid(vf_info, vlan); 1295 if (err < 0) 1296 return err; 1297 1298 vlan = (u16)err; 1299 1300 /* notify switch of request for new multicast address */ 1301 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, 1302 mac, vlan, set); 1303 } 1304 1305 return err; 1306 } 1307 1308 /** 1309 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode 1310 * @vf_info: VF info structure containing capability flags 1311 * @mode: Requested xcast mode 1312 * 1313 * This function outputs the mode that most closely matches the requested 1314 * mode. If not modes match it will request we disable the port 1315 **/ 1316 static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, 1317 u8 mode) 1318 { 1319 u8 vf_flags = vf_info->vf_flags; 1320 1321 /* match up mode to capabilities as best as possible */ 1322 switch (mode) { 1323 case FM10K_XCAST_MODE_PROMISC: 1324 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) 1325 return FM10K_XCAST_MODE_PROMISC; 1326 /* fallthough */ 1327 case FM10K_XCAST_MODE_ALLMULTI: 1328 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) 1329 return FM10K_XCAST_MODE_ALLMULTI; 1330 /* fallthough */ 1331 case FM10K_XCAST_MODE_MULTI: 1332 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) 1333 return FM10K_XCAST_MODE_MULTI; 1334 /* fallthough */ 1335 case FM10K_XCAST_MODE_NONE: 1336 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) 1337 return FM10K_XCAST_MODE_NONE; 1338 /* fallthough */ 1339 default: 1340 break; 1341 } 1342 1343 /* disable interface as it should not be able to request any */ 1344 return FM10K_XCAST_MODE_DISABLE; 1345 } 1346 1347 /** 1348 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests 1349 * @hw: Pointer to hardware structure 1350 * @results: Pointer array to message, results[0] is pointer to message 1351 * @mbx: Pointer to mailbox information structure 1352 * 1353 * This function is a default handler for port state requests. The port 1354 * state requests for now are basic and consist of enabling or disabling 1355 * the port. 1356 **/ 1357 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, 1358 struct fm10k_mbx_info *mbx) 1359 { 1360 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1361 u32 *result; 1362 s32 err = 0; 1363 u32 msg[2]; 1364 u8 mode = 0; 1365 1366 /* verify VF is allowed to enable even minimal mode */ 1367 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) 1368 return FM10K_ERR_PARAM; 1369 1370 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { 1371 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; 1372 1373 /* XCAST mode update requested */ 1374 err = fm10k_tlv_attr_get_u8(result, &mode); 1375 if (err) 1376 return FM10K_ERR_PARAM; 1377 1378 /* prep for possible demotion depending on capabilities */ 1379 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); 1380 1381 /* if mode is not currently enabled, enable it */ 1382 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode))) 1383 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); 1384 1385 /* swap mode back to a bit flag */ 1386 mode = FM10K_VF_FLAG_SET_MODE(mode); 1387 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { 1388 /* need to disable the port if it is already enabled */ 1389 if (FM10K_VF_FLAG_ENABLED(vf_info)) 1390 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1391 1, false); 1392 1393 /* we need to clear VF_FLAG_ENABLED flags in order to ensure 1394 * that we actually re-enable the LPORT state below. Note that 1395 * this has no impact if the VF is already disabled, as the 1396 * flags are already cleared. 1397 */ 1398 if (!err) 1399 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info); 1400 1401 /* when enabling the port we should reset the rate limiters */ 1402 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); 1403 1404 /* set mode for minimal functionality */ 1405 mode = FM10K_VF_FLAG_SET_MODE_NONE; 1406 1407 /* generate port state response to notify VF it is ready */ 1408 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1409 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); 1410 mbx->ops.enqueue_tx(hw, mbx, msg); 1411 } 1412 1413 /* if enable state toggled note the update */ 1414 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) 1415 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, 1416 !!mode); 1417 1418 /* if state change succeeded, then update our stored state */ 1419 mode |= FM10K_VF_FLAG_CAPABLE(vf_info); 1420 if (!err) 1421 vf_info->vf_flags = mode; 1422 1423 return err; 1424 } 1425 1426 /** 1427 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF 1428 * @hw: pointer to hardware structure 1429 * @stats: pointer to the stats structure to update 1430 * 1431 * This function collects and aggregates global and per queue hardware 1432 * statistics. 1433 **/ 1434 static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, 1435 struct fm10k_hw_stats *stats) 1436 { 1437 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; 1438 u32 id, id_prev; 1439 1440 /* Use Tx queue 0 as a canary to detect a reset */ 1441 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1442 1443 /* Read Global Statistics */ 1444 do { 1445 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, 1446 &stats->timeout); 1447 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); 1448 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); 1449 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); 1450 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); 1451 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, 1452 &stats->vlan_drop); 1453 loopback_drop = 1454 fm10k_read_hw_stats_32b(hw, 1455 FM10K_STATS_LOOPBACK_DROP, 1456 &stats->loopback_drop); 1457 nodesc_drop = fm10k_read_hw_stats_32b(hw, 1458 FM10K_STATS_NODESC_DROP, 1459 &stats->nodesc_drop); 1460 1461 /* if value has not changed then we have consistent data */ 1462 id_prev = id; 1463 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1464 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); 1465 1466 /* drop non-ID bits and set VALID ID bit */ 1467 id &= FM10K_TXQCTL_ID_MASK; 1468 id |= FM10K_STAT_VALID; 1469 1470 /* Update Global Statistics */ 1471 if (stats->stats_idx == id) { 1472 stats->timeout.count += timeout; 1473 stats->ur.count += ur; 1474 stats->ca.count += ca; 1475 stats->um.count += um; 1476 stats->xec.count += xec; 1477 stats->vlan_drop.count += vlan_drop; 1478 stats->loopback_drop.count += loopback_drop; 1479 stats->nodesc_drop.count += nodesc_drop; 1480 } 1481 1482 /* Update bases and record current PF id */ 1483 fm10k_update_hw_base_32b(&stats->timeout, timeout); 1484 fm10k_update_hw_base_32b(&stats->ur, ur); 1485 fm10k_update_hw_base_32b(&stats->ca, ca); 1486 fm10k_update_hw_base_32b(&stats->um, um); 1487 fm10k_update_hw_base_32b(&stats->xec, xec); 1488 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); 1489 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); 1490 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); 1491 stats->stats_idx = id; 1492 1493 /* Update Queue Statistics */ 1494 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); 1495 } 1496 1497 /** 1498 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF 1499 * @hw: pointer to hardware structure 1500 * @stats: pointer to the stats structure to update 1501 * 1502 * This function resets the base for global and per queue hardware 1503 * statistics. 1504 **/ 1505 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, 1506 struct fm10k_hw_stats *stats) 1507 { 1508 /* Unbind Global Statistics */ 1509 fm10k_unbind_hw_stats_32b(&stats->timeout); 1510 fm10k_unbind_hw_stats_32b(&stats->ur); 1511 fm10k_unbind_hw_stats_32b(&stats->ca); 1512 fm10k_unbind_hw_stats_32b(&stats->um); 1513 fm10k_unbind_hw_stats_32b(&stats->xec); 1514 fm10k_unbind_hw_stats_32b(&stats->vlan_drop); 1515 fm10k_unbind_hw_stats_32b(&stats->loopback_drop); 1516 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); 1517 1518 /* Unbind Queue Statistics */ 1519 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); 1520 1521 /* Reinitialize bases for all stats */ 1522 fm10k_update_hw_stats_pf(hw, stats); 1523 } 1524 1525 /** 1526 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system 1527 * @hw: pointer to hardware structure 1528 * @dma_mask: 64 bit DMA mask required for platform 1529 * 1530 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order 1531 * to limit the access to memory beyond what is physically in the system. 1532 **/ 1533 static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) 1534 { 1535 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ 1536 u32 phyaddr = (u32)(dma_mask >> 32); 1537 1538 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); 1539 } 1540 1541 /** 1542 * fm10k_get_fault_pf - Record a fault in one of the interface units 1543 * @hw: pointer to hardware structure 1544 * @type: pointer to fault type register offset 1545 * @fault: pointer to memory location to record the fault 1546 * 1547 * Record the fault register contents to the fault data structure and 1548 * clear the entry from the register. 1549 * 1550 * Returns ERR_PARAM if invalid register is specified or no error is present. 1551 **/ 1552 static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, 1553 struct fm10k_fault *fault) 1554 { 1555 u32 func; 1556 1557 /* verify the fault register is in range and is aligned */ 1558 switch (type) { 1559 case FM10K_PCA_FAULT: 1560 case FM10K_THI_FAULT: 1561 case FM10K_FUM_FAULT: 1562 break; 1563 default: 1564 return FM10K_ERR_PARAM; 1565 } 1566 1567 /* only service faults that are valid */ 1568 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); 1569 if (!(func & FM10K_FAULT_FUNC_VALID)) 1570 return FM10K_ERR_PARAM; 1571 1572 /* read remaining fields */ 1573 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); 1574 fault->address <<= 32; 1575 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); 1576 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); 1577 1578 /* clear valid bit to allow for next error */ 1579 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); 1580 1581 /* Record which function triggered the error */ 1582 if (func & FM10K_FAULT_FUNC_PF) 1583 fault->func = 0; 1584 else 1585 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> 1586 FM10K_FAULT_FUNC_VF_SHIFT); 1587 1588 /* record fault type */ 1589 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; 1590 1591 return 0; 1592 } 1593 1594 /** 1595 * fm10k_request_lport_map_pf - Request LPORT map from the switch API 1596 * @hw: pointer to hardware structure 1597 * 1598 **/ 1599 static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) 1600 { 1601 struct fm10k_mbx_info *mbx = &hw->mbx; 1602 u32 msg[1]; 1603 1604 /* issue request asking for LPORT map */ 1605 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); 1606 1607 /* load onto outgoing mailbox */ 1608 return mbx->ops.enqueue_tx(hw, mbx, msg); 1609 } 1610 1611 /** 1612 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox 1613 * @hw: pointer to hardware structure 1614 * @switch_ready: pointer to boolean value that will record switch state 1615 * 1616 * This function will check the DMA_CTRL2 register and mailbox in order 1617 * to determine if the switch is ready for the PF to begin requesting 1618 * addresses and mapping traffic to the local interface. 1619 **/ 1620 static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) 1621 { 1622 s32 ret_val = 0; 1623 u32 dma_ctrl2; 1624 1625 /* verify the switch is ready for interaction */ 1626 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 1627 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) 1628 goto out; 1629 1630 /* retrieve generic host state info */ 1631 ret_val = fm10k_get_host_state_generic(hw, switch_ready); 1632 if (ret_val) 1633 goto out; 1634 1635 /* interface cannot receive traffic without logical ports */ 1636 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) 1637 ret_val = fm10k_request_lport_map_pf(hw); 1638 1639 out: 1640 return ret_val; 1641 } 1642 1643 /* This structure defines the attibutes to be parsed below */ 1644 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { 1645 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, 1646 sizeof(struct fm10k_swapi_error)), 1647 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), 1648 FM10K_TLV_ATTR_LAST 1649 }; 1650 1651 /** 1652 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM 1653 * @hw: Pointer to hardware structure 1654 * @results: pointer array containing parsed data 1655 * @mbx: Pointer to mailbox information structure 1656 * 1657 * This handler configures the lport mapping based on the reply from the 1658 * switch API. 1659 **/ 1660 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, 1661 struct fm10k_mbx_info *mbx) 1662 { 1663 u16 glort, mask; 1664 u32 dglort_map; 1665 s32 err; 1666 1667 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], 1668 &dglort_map); 1669 if (err) 1670 return err; 1671 1672 /* extract values out of the header */ 1673 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); 1674 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); 1675 1676 /* verify mask is set and none of the masked bits in glort are set */ 1677 if (!mask || (glort & ~mask)) 1678 return FM10K_ERR_PARAM; 1679 1680 /* verify the mask is contiguous, and that it is 1's followed by 0's */ 1681 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) 1682 return FM10K_ERR_PARAM; 1683 1684 /* record the glort, mask, and port count */ 1685 hw->mac.dglort_map = dglort_map; 1686 1687 return 0; 1688 } 1689 1690 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { 1691 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), 1692 FM10K_TLV_ATTR_LAST 1693 }; 1694 1695 /** 1696 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM 1697 * @hw: Pointer to hardware structure 1698 * @results: pointer array containing parsed data 1699 * @mbx: Pointer to mailbox information structure 1700 * 1701 * This handler configures the default VLAN for the PF 1702 **/ 1703 static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, 1704 struct fm10k_mbx_info *mbx) 1705 { 1706 u16 glort, pvid; 1707 u32 pvid_update; 1708 s32 err; 1709 1710 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], 1711 &pvid_update); 1712 if (err) 1713 return err; 1714 1715 /* extract values from the pvid update */ 1716 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); 1717 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); 1718 1719 /* if glort is not valid return error */ 1720 if (!fm10k_glort_valid_pf(hw, glort)) 1721 return FM10K_ERR_PARAM; 1722 1723 /* verify VLAN ID is valid */ 1724 if (pvid >= FM10K_VLAN_TABLE_VID_MAX) 1725 return FM10K_ERR_PARAM; 1726 1727 /* record the port VLAN ID value */ 1728 hw->mac.default_vid = pvid; 1729 1730 return 0; 1731 } 1732 1733 /** 1734 * fm10k_record_global_table_data - Move global table data to swapi table info 1735 * @from: pointer to source table data structure 1736 * @to: pointer to destination table info structure 1737 * 1738 * This function is will copy table_data to the table_info contained in 1739 * the hw struct. 1740 **/ 1741 static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, 1742 struct fm10k_swapi_table_info *to) 1743 { 1744 /* convert from le32 struct to CPU byte ordered values */ 1745 to->used = le32_to_cpu(from->used); 1746 to->avail = le32_to_cpu(from->avail); 1747 } 1748 1749 const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { 1750 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, 1751 sizeof(struct fm10k_swapi_error)), 1752 FM10K_TLV_ATTR_LAST 1753 }; 1754 1755 /** 1756 * fm10k_msg_err_pf - Message handler for error reply 1757 * @hw: Pointer to hardware structure 1758 * @results: pointer array containing parsed data 1759 * @mbx: Pointer to mailbox information structure 1760 * 1761 * This handler will capture the data for any error replies to previous 1762 * messages that the PF has sent. 1763 **/ 1764 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, 1765 struct fm10k_mbx_info *mbx) 1766 { 1767 struct fm10k_swapi_error err_msg; 1768 s32 err; 1769 1770 /* extract structure from message */ 1771 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], 1772 &err_msg, sizeof(err_msg)); 1773 if (err) 1774 return err; 1775 1776 /* record table status */ 1777 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); 1778 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); 1779 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); 1780 1781 /* record SW API status value */ 1782 hw->swapi.status = le32_to_cpu(err_msg.status); 1783 1784 return 0; 1785 } 1786 1787 static const struct fm10k_msg_data fm10k_msg_data_pf[] = { 1788 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), 1789 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), 1790 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), 1791 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), 1792 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), 1793 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), 1794 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), 1795 }; 1796 1797 static const struct fm10k_mac_ops mac_ops_pf = { 1798 .get_bus_info = fm10k_get_bus_info_generic, 1799 .reset_hw = fm10k_reset_hw_pf, 1800 .init_hw = fm10k_init_hw_pf, 1801 .start_hw = fm10k_start_hw_generic, 1802 .stop_hw = fm10k_stop_hw_generic, 1803 .update_vlan = fm10k_update_vlan_pf, 1804 .read_mac_addr = fm10k_read_mac_addr_pf, 1805 .update_uc_addr = fm10k_update_uc_addr_pf, 1806 .update_mc_addr = fm10k_update_mc_addr_pf, 1807 .update_xcast_mode = fm10k_update_xcast_mode_pf, 1808 .update_int_moderator = fm10k_update_int_moderator_pf, 1809 .update_lport_state = fm10k_update_lport_state_pf, 1810 .update_hw_stats = fm10k_update_hw_stats_pf, 1811 .rebind_hw_stats = fm10k_rebind_hw_stats_pf, 1812 .configure_dglort_map = fm10k_configure_dglort_map_pf, 1813 .set_dma_mask = fm10k_set_dma_mask_pf, 1814 .get_fault = fm10k_get_fault_pf, 1815 .get_host_state = fm10k_get_host_state_pf, 1816 }; 1817 1818 static const struct fm10k_iov_ops iov_ops_pf = { 1819 .assign_resources = fm10k_iov_assign_resources_pf, 1820 .configure_tc = fm10k_iov_configure_tc_pf, 1821 .assign_int_moderator = fm10k_iov_assign_int_moderator_pf, 1822 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, 1823 .reset_resources = fm10k_iov_reset_resources_pf, 1824 .set_lport = fm10k_iov_set_lport_pf, 1825 .reset_lport = fm10k_iov_reset_lport_pf, 1826 .update_stats = fm10k_iov_update_stats_pf, 1827 }; 1828 1829 static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) 1830 { 1831 fm10k_get_invariants_generic(hw); 1832 1833 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); 1834 } 1835 1836 const struct fm10k_info fm10k_pf_info = { 1837 .mac = fm10k_mac_pf, 1838 .get_invariants = fm10k_get_invariants_pf, 1839 .mac_ops = &mac_ops_pf, 1840 .iov_ops = &iov_ops_pf, 1841 }; 1842