1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* 82571EB Gigabit Ethernet Controller 30 * 82571EB Gigabit Ethernet Controller (Copper) 31 * 82571EB Gigabit Ethernet Controller (Fiber) 32 * 82571EB Dual Port Gigabit Mezzanine Adapter 33 * 82571EB Quad Port Gigabit Mezzanine Adapter 34 * 82571PT Gigabit PT Quad Port Server ExpressModule 35 * 82572EI Gigabit Ethernet Controller (Copper) 36 * 82572EI Gigabit Ethernet Controller (Fiber) 37 * 82572EI Gigabit Ethernet Controller 38 * 82573V Gigabit Ethernet Controller (Copper) 39 * 82573E Gigabit Ethernet Controller (Copper) 40 * 82573L Gigabit Ethernet Controller 41 * 82574L Gigabit Network Connection 42 * 82583V Gigabit Network Connection 43 */ 44 45 #include "e1000.h" 46 47 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 48 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 49 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 50 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 51 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 52 u16 words, u16 *data); 53 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 54 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 55 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 56 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 57 static s32 e1000_led_on_82574(struct e1000_hw *hw); 58 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 59 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 60 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 61 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 62 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 63 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); 64 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); 65 66 /** 67 * e1000_init_phy_params_82571 - Init PHY func ptrs. 68 * @hw: pointer to the HW structure 69 **/ 70 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 s32 ret_val; 74 75 if (hw->phy.media_type != e1000_media_type_copper) { 76 phy->type = e1000_phy_none; 77 return 0; 78 } 79 80 phy->addr = 1; 81 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 82 phy->reset_delay_us = 100; 83 84 phy->ops.power_up = e1000_power_up_phy_copper; 85 phy->ops.power_down = e1000_power_down_phy_copper_82571; 86 87 switch (hw->mac.type) { 88 case e1000_82571: 89 case e1000_82572: 90 phy->type = e1000_phy_igp_2; 91 break; 92 case e1000_82573: 93 phy->type = e1000_phy_m88; 94 break; 95 case e1000_82574: 96 case e1000_82583: 97 phy->type = e1000_phy_bm; 98 phy->ops.acquire = e1000_get_hw_semaphore_82574; 99 phy->ops.release = e1000_put_hw_semaphore_82574; 100 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 101 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 102 break; 103 default: 104 return -E1000_ERR_PHY; 105 break; 106 } 107 108 /* This can only be done after all function pointers are setup. */ 109 ret_val = e1000_get_phy_id_82571(hw); 110 if (ret_val) { 111 e_dbg("Error getting PHY ID\n"); 112 return ret_val; 113 } 114 115 /* Verify phy id */ 116 switch (hw->mac.type) { 117 case e1000_82571: 118 case e1000_82572: 119 if (phy->id != IGP01E1000_I_PHY_ID) 120 ret_val = -E1000_ERR_PHY; 121 break; 122 case e1000_82573: 123 if (phy->id != M88E1111_I_PHY_ID) 124 ret_val = -E1000_ERR_PHY; 125 break; 126 case e1000_82574: 127 case e1000_82583: 128 if (phy->id != BME1000_E_PHY_ID_R2) 129 ret_val = -E1000_ERR_PHY; 130 break; 131 default: 132 ret_val = -E1000_ERR_PHY; 133 break; 134 } 135 136 if (ret_val) 137 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); 138 139 return ret_val; 140 } 141 142 /** 143 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 144 * @hw: pointer to the HW structure 145 **/ 146 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 147 { 148 struct e1000_nvm_info *nvm = &hw->nvm; 149 u32 eecd = er32(EECD); 150 u16 size; 151 152 nvm->opcode_bits = 8; 153 nvm->delay_usec = 1; 154 switch (nvm->override) { 155 case e1000_nvm_override_spi_large: 156 nvm->page_size = 32; 157 nvm->address_bits = 16; 158 break; 159 case e1000_nvm_override_spi_small: 160 nvm->page_size = 8; 161 nvm->address_bits = 8; 162 break; 163 default: 164 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 165 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 166 break; 167 } 168 169 switch (hw->mac.type) { 170 case e1000_82573: 171 case e1000_82574: 172 case e1000_82583: 173 if (((eecd >> 15) & 0x3) == 0x3) { 174 nvm->type = e1000_nvm_flash_hw; 175 nvm->word_size = 2048; 176 /* Autonomous Flash update bit must be cleared due 177 * to Flash update issue. 178 */ 179 eecd &= ~E1000_EECD_AUPDEN; 180 ew32(EECD, eecd); 181 break; 182 } 183 /* Fall Through */ 184 default: 185 nvm->type = e1000_nvm_eeprom_spi; 186 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 187 E1000_EECD_SIZE_EX_SHIFT); 188 /* Added to a constant, "size" becomes the left-shift value 189 * for setting word_size. 190 */ 191 size += NVM_WORD_SIZE_BASE_SHIFT; 192 193 /* EEPROM access above 16k is unsupported */ 194 if (size > 14) 195 size = 14; 196 nvm->word_size = 1 << size; 197 break; 198 } 199 200 /* Function Pointers */ 201 switch (hw->mac.type) { 202 case e1000_82574: 203 case e1000_82583: 204 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 205 nvm->ops.release = e1000_put_hw_semaphore_82574; 206 break; 207 default: 208 break; 209 } 210 211 return 0; 212 } 213 214 /** 215 * e1000_init_mac_params_82571 - Init MAC func ptrs. 216 * @hw: pointer to the HW structure 217 **/ 218 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 219 { 220 struct e1000_mac_info *mac = &hw->mac; 221 u32 swsm = 0; 222 u32 swsm2 = 0; 223 bool force_clear_smbi = false; 224 225 /* Set media type and media-dependent function pointers */ 226 switch (hw->adapter->pdev->device) { 227 case E1000_DEV_ID_82571EB_FIBER: 228 case E1000_DEV_ID_82572EI_FIBER: 229 case E1000_DEV_ID_82571EB_QUAD_FIBER: 230 hw->phy.media_type = e1000_media_type_fiber; 231 mac->ops.setup_physical_interface = 232 e1000_setup_fiber_serdes_link_82571; 233 mac->ops.check_for_link = e1000e_check_for_fiber_link; 234 mac->ops.get_link_up_info = 235 e1000e_get_speed_and_duplex_fiber_serdes; 236 break; 237 case E1000_DEV_ID_82571EB_SERDES: 238 case E1000_DEV_ID_82571EB_SERDES_DUAL: 239 case E1000_DEV_ID_82571EB_SERDES_QUAD: 240 case E1000_DEV_ID_82572EI_SERDES: 241 hw->phy.media_type = e1000_media_type_internal_serdes; 242 mac->ops.setup_physical_interface = 243 e1000_setup_fiber_serdes_link_82571; 244 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 245 mac->ops.get_link_up_info = 246 e1000e_get_speed_and_duplex_fiber_serdes; 247 break; 248 default: 249 hw->phy.media_type = e1000_media_type_copper; 250 mac->ops.setup_physical_interface = 251 e1000_setup_copper_link_82571; 252 mac->ops.check_for_link = e1000e_check_for_copper_link; 253 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper; 254 break; 255 } 256 257 /* Set mta register count */ 258 mac->mta_reg_count = 128; 259 /* Set rar entry count */ 260 mac->rar_entry_count = E1000_RAR_ENTRIES; 261 /* Adaptive IFS supported */ 262 mac->adaptive_ifs = true; 263 264 /* MAC-specific function pointers */ 265 switch (hw->mac.type) { 266 case e1000_82573: 267 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 268 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 269 mac->ops.led_on = e1000e_led_on_generic; 270 mac->ops.blink_led = e1000e_blink_led_generic; 271 272 /* FWSM register */ 273 mac->has_fwsm = true; 274 /* ARC supported; valid only if manageability features are 275 * enabled. 276 */ 277 mac->arc_subsystem_valid = !!(er32(FWSM) & 278 E1000_FWSM_MODE_MASK); 279 break; 280 case e1000_82574: 281 case e1000_82583: 282 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 283 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 284 mac->ops.led_on = e1000_led_on_82574; 285 break; 286 default: 287 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 288 mac->ops.led_on = e1000e_led_on_generic; 289 mac->ops.blink_led = e1000e_blink_led_generic; 290 291 /* FWSM register */ 292 mac->has_fwsm = true; 293 break; 294 } 295 296 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 297 * first NVM or PHY access. This should be done for single-port 298 * devices, and for one port only on dual-port devices so that 299 * for those devices we can still use the SMBI lock to synchronize 300 * inter-port accesses to the PHY & NVM. 301 */ 302 switch (hw->mac.type) { 303 case e1000_82571: 304 case e1000_82572: 305 swsm2 = er32(SWSM2); 306 307 if (!(swsm2 & E1000_SWSM2_LOCK)) { 308 /* Only do this for the first interface on this card */ 309 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); 310 force_clear_smbi = true; 311 } else { 312 force_clear_smbi = false; 313 } 314 break; 315 default: 316 force_clear_smbi = true; 317 break; 318 } 319 320 if (force_clear_smbi) { 321 /* Make sure SWSM.SMBI is clear */ 322 swsm = er32(SWSM); 323 if (swsm & E1000_SWSM_SMBI) { 324 /* This bit should not be set on a first interface, and 325 * indicates that the bootagent or EFI code has 326 * improperly left this bit enabled 327 */ 328 e_dbg("Please update your 82571 Bootagent\n"); 329 } 330 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 331 } 332 333 /* Initialize device specific counter of SMBI acquisition timeouts. */ 334 hw->dev_spec.e82571.smb_counter = 0; 335 336 return 0; 337 } 338 339 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) 340 { 341 struct e1000_hw *hw = &adapter->hw; 342 static int global_quad_port_a; /* global port a indication */ 343 struct pci_dev *pdev = adapter->pdev; 344 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; 345 s32 rc; 346 347 rc = e1000_init_mac_params_82571(hw); 348 if (rc) 349 return rc; 350 351 rc = e1000_init_nvm_params_82571(hw); 352 if (rc) 353 return rc; 354 355 rc = e1000_init_phy_params_82571(hw); 356 if (rc) 357 return rc; 358 359 /* tag quad port adapters first, it's used below */ 360 switch (pdev->device) { 361 case E1000_DEV_ID_82571EB_QUAD_COPPER: 362 case E1000_DEV_ID_82571EB_QUAD_FIBER: 363 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 364 case E1000_DEV_ID_82571PT_QUAD_COPPER: 365 adapter->flags |= FLAG_IS_QUAD_PORT; 366 /* mark the first port */ 367 if (global_quad_port_a == 0) 368 adapter->flags |= FLAG_IS_QUAD_PORT_A; 369 /* Reset for multiple quad port adapters */ 370 global_quad_port_a++; 371 if (global_quad_port_a == 4) 372 global_quad_port_a = 0; 373 break; 374 default: 375 break; 376 } 377 378 switch (adapter->hw.mac.type) { 379 case e1000_82571: 380 /* these dual ports don't have WoL on port B at all */ 381 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || 382 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || 383 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && 384 (is_port_b)) 385 adapter->flags &= ~FLAG_HAS_WOL; 386 /* quad ports only support WoL on port A */ 387 if (adapter->flags & FLAG_IS_QUAD_PORT && 388 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) 389 adapter->flags &= ~FLAG_HAS_WOL; 390 /* Does not support WoL on any port */ 391 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) 392 adapter->flags &= ~FLAG_HAS_WOL; 393 break; 394 case e1000_82573: 395 if (pdev->device == E1000_DEV_ID_82573L) { 396 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; 397 adapter->max_hw_frame_size = DEFAULT_JUMBO; 398 } 399 break; 400 default: 401 break; 402 } 403 404 return 0; 405 } 406 407 /** 408 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 409 * @hw: pointer to the HW structure 410 * 411 * Reads the PHY registers and stores the PHY ID and possibly the PHY 412 * revision in the hardware structure. 413 **/ 414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 415 { 416 struct e1000_phy_info *phy = &hw->phy; 417 s32 ret_val; 418 u16 phy_id = 0; 419 420 switch (hw->mac.type) { 421 case e1000_82571: 422 case e1000_82572: 423 /* The 82571 firmware may still be configuring the PHY. 424 * In this case, we cannot access the PHY until the 425 * configuration is done. So we explicitly set the 426 * PHY ID. 427 */ 428 phy->id = IGP01E1000_I_PHY_ID; 429 break; 430 case e1000_82573: 431 return e1000e_get_phy_id(hw); 432 break; 433 case e1000_82574: 434 case e1000_82583: 435 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); 436 if (ret_val) 437 return ret_val; 438 439 phy->id = (u32)(phy_id << 16); 440 udelay(20); 441 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); 442 if (ret_val) 443 return ret_val; 444 445 phy->id |= (u32)(phy_id); 446 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 447 break; 448 default: 449 return -E1000_ERR_PHY; 450 break; 451 } 452 453 return 0; 454 } 455 456 /** 457 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 458 * @hw: pointer to the HW structure 459 * 460 * Acquire the HW semaphore to access the PHY or NVM 461 **/ 462 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 463 { 464 u32 swsm; 465 s32 sw_timeout = hw->nvm.word_size + 1; 466 s32 fw_timeout = hw->nvm.word_size + 1; 467 s32 i = 0; 468 469 /* If we have timedout 3 times on trying to acquire 470 * the inter-port SMBI semaphore, there is old code 471 * operating on the other port, and it is not 472 * releasing SMBI. Modify the number of times that 473 * we try for the semaphore to interwork with this 474 * older code. 475 */ 476 if (hw->dev_spec.e82571.smb_counter > 2) 477 sw_timeout = 1; 478 479 /* Get the SW semaphore */ 480 while (i < sw_timeout) { 481 swsm = er32(SWSM); 482 if (!(swsm & E1000_SWSM_SMBI)) 483 break; 484 485 udelay(50); 486 i++; 487 } 488 489 if (i == sw_timeout) { 490 e_dbg("Driver can't access device - SMBI bit is set.\n"); 491 hw->dev_spec.e82571.smb_counter++; 492 } 493 /* Get the FW semaphore. */ 494 for (i = 0; i < fw_timeout; i++) { 495 swsm = er32(SWSM); 496 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 497 498 /* Semaphore acquired if bit latched */ 499 if (er32(SWSM) & E1000_SWSM_SWESMBI) 500 break; 501 502 udelay(50); 503 } 504 505 if (i == fw_timeout) { 506 /* Release semaphores */ 507 e1000_put_hw_semaphore_82571(hw); 508 e_dbg("Driver can't access the NVM\n"); 509 return -E1000_ERR_NVM; 510 } 511 512 return 0; 513 } 514 515 /** 516 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 517 * @hw: pointer to the HW structure 518 * 519 * Release hardware semaphore used to access the PHY or NVM 520 **/ 521 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 522 { 523 u32 swsm; 524 525 swsm = er32(SWSM); 526 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 527 ew32(SWSM, swsm); 528 } 529 /** 530 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 531 * @hw: pointer to the HW structure 532 * 533 * Acquire the HW semaphore during reset. 534 * 535 **/ 536 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 537 { 538 u32 extcnf_ctrl; 539 s32 i = 0; 540 541 extcnf_ctrl = er32(EXTCNF_CTRL); 542 do { 543 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 544 ew32(EXTCNF_CTRL, extcnf_ctrl); 545 extcnf_ctrl = er32(EXTCNF_CTRL); 546 547 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 548 break; 549 550 usleep_range(2000, 4000); 551 i++; 552 } while (i < MDIO_OWNERSHIP_TIMEOUT); 553 554 if (i == MDIO_OWNERSHIP_TIMEOUT) { 555 /* Release semaphores */ 556 e1000_put_hw_semaphore_82573(hw); 557 e_dbg("Driver can't access the PHY\n"); 558 return -E1000_ERR_PHY; 559 } 560 561 return 0; 562 } 563 564 /** 565 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 566 * @hw: pointer to the HW structure 567 * 568 * Release hardware semaphore used during reset. 569 * 570 **/ 571 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 572 { 573 u32 extcnf_ctrl; 574 575 extcnf_ctrl = er32(EXTCNF_CTRL); 576 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 577 ew32(EXTCNF_CTRL, extcnf_ctrl); 578 } 579 580 static DEFINE_MUTEX(swflag_mutex); 581 582 /** 583 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 584 * @hw: pointer to the HW structure 585 * 586 * Acquire the HW semaphore to access the PHY or NVM. 587 * 588 **/ 589 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 590 { 591 s32 ret_val; 592 593 mutex_lock(&swflag_mutex); 594 ret_val = e1000_get_hw_semaphore_82573(hw); 595 if (ret_val) 596 mutex_unlock(&swflag_mutex); 597 return ret_val; 598 } 599 600 /** 601 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 602 * @hw: pointer to the HW structure 603 * 604 * Release hardware semaphore used to access the PHY or NVM 605 * 606 **/ 607 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 608 { 609 e1000_put_hw_semaphore_82573(hw); 610 mutex_unlock(&swflag_mutex); 611 } 612 613 /** 614 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 615 * @hw: pointer to the HW structure 616 * @active: true to enable LPLU, false to disable 617 * 618 * Sets the LPLU D0 state according to the active flag. 619 * LPLU will not be activated unless the 620 * device autonegotiation advertisement meets standards of 621 * either 10 or 10/100 or 10/100/1000 at all duplexes. 622 * This is a function pointer entry point only called by 623 * PHY setup routines. 624 **/ 625 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 626 { 627 u32 data = er32(POEMB); 628 629 if (active) 630 data |= E1000_PHY_CTRL_D0A_LPLU; 631 else 632 data &= ~E1000_PHY_CTRL_D0A_LPLU; 633 634 ew32(POEMB, data); 635 return 0; 636 } 637 638 /** 639 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 640 * @hw: pointer to the HW structure 641 * @active: boolean used to enable/disable lplu 642 * 643 * The low power link up (lplu) state is set to the power management level D3 644 * when active is true, else clear lplu for D3. LPLU 645 * is used during Dx states where the power conservation is most important. 646 * During driver activity, SmartSpeed should be enabled so performance is 647 * maintained. 648 **/ 649 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 650 { 651 u32 data = er32(POEMB); 652 653 if (!active) { 654 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 655 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 656 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 657 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 658 data |= E1000_PHY_CTRL_NOND0A_LPLU; 659 } 660 661 ew32(POEMB, data); 662 return 0; 663 } 664 665 /** 666 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 667 * @hw: pointer to the HW structure 668 * 669 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 670 * Then for non-82573 hardware, set the EEPROM access request bit and wait 671 * for EEPROM access grant bit. If the access grant bit is not set, release 672 * hardware semaphore. 673 **/ 674 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 675 { 676 s32 ret_val; 677 678 ret_val = e1000_get_hw_semaphore_82571(hw); 679 if (ret_val) 680 return ret_val; 681 682 switch (hw->mac.type) { 683 case e1000_82573: 684 break; 685 default: 686 ret_val = e1000e_acquire_nvm(hw); 687 break; 688 } 689 690 if (ret_val) 691 e1000_put_hw_semaphore_82571(hw); 692 693 return ret_val; 694 } 695 696 /** 697 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 698 * @hw: pointer to the HW structure 699 * 700 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 701 **/ 702 static void e1000_release_nvm_82571(struct e1000_hw *hw) 703 { 704 e1000e_release_nvm(hw); 705 e1000_put_hw_semaphore_82571(hw); 706 } 707 708 /** 709 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 710 * @hw: pointer to the HW structure 711 * @offset: offset within the EEPROM to be written to 712 * @words: number of words to write 713 * @data: 16 bit word(s) to be written to the EEPROM 714 * 715 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 716 * 717 * If e1000e_update_nvm_checksum is not called after this function, the 718 * EEPROM will most likely contain an invalid checksum. 719 **/ 720 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 721 u16 *data) 722 { 723 s32 ret_val; 724 725 switch (hw->mac.type) { 726 case e1000_82573: 727 case e1000_82574: 728 case e1000_82583: 729 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 730 break; 731 case e1000_82571: 732 case e1000_82572: 733 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); 734 break; 735 default: 736 ret_val = -E1000_ERR_NVM; 737 break; 738 } 739 740 return ret_val; 741 } 742 743 /** 744 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 745 * @hw: pointer to the HW structure 746 * 747 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 748 * up to the checksum. Then calculates the EEPROM checksum and writes the 749 * value to the EEPROM. 750 **/ 751 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 752 { 753 u32 eecd; 754 s32 ret_val; 755 u16 i; 756 757 ret_val = e1000e_update_nvm_checksum_generic(hw); 758 if (ret_val) 759 return ret_val; 760 761 /* If our nvm is an EEPROM, then we're done 762 * otherwise, commit the checksum to the flash NVM. 763 */ 764 if (hw->nvm.type != e1000_nvm_flash_hw) 765 return 0; 766 767 /* Check for pending operations. */ 768 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 769 usleep_range(1000, 2000); 770 if (!(er32(EECD) & E1000_EECD_FLUPD)) 771 break; 772 } 773 774 if (i == E1000_FLASH_UPDATES) 775 return -E1000_ERR_NVM; 776 777 /* Reset the firmware if using STM opcode. */ 778 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 779 /* The enabling of and the actual reset must be done 780 * in two write cycles. 781 */ 782 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 783 e1e_flush(); 784 ew32(HICR, E1000_HICR_FW_RESET); 785 } 786 787 /* Commit the write to flash */ 788 eecd = er32(EECD) | E1000_EECD_FLUPD; 789 ew32(EECD, eecd); 790 791 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 792 usleep_range(1000, 2000); 793 if (!(er32(EECD) & E1000_EECD_FLUPD)) 794 break; 795 } 796 797 if (i == E1000_FLASH_UPDATES) 798 return -E1000_ERR_NVM; 799 800 return 0; 801 } 802 803 /** 804 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 805 * @hw: pointer to the HW structure 806 * 807 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 808 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 809 **/ 810 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 811 { 812 if (hw->nvm.type == e1000_nvm_flash_hw) 813 e1000_fix_nvm_checksum_82571(hw); 814 815 return e1000e_validate_nvm_checksum_generic(hw); 816 } 817 818 /** 819 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 820 * @hw: pointer to the HW structure 821 * @offset: offset within the EEPROM to be written to 822 * @words: number of words to write 823 * @data: 16 bit word(s) to be written to the EEPROM 824 * 825 * After checking for invalid values, poll the EEPROM to ensure the previous 826 * command has completed before trying to write the next word. After write 827 * poll for completion. 828 * 829 * If e1000e_update_nvm_checksum is not called after this function, the 830 * EEPROM will most likely contain an invalid checksum. 831 **/ 832 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 833 u16 words, u16 *data) 834 { 835 struct e1000_nvm_info *nvm = &hw->nvm; 836 u32 i, eewr = 0; 837 s32 ret_val = 0; 838 839 /* A check for invalid values: offset too large, too many words, 840 * and not enough words. 841 */ 842 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 843 (words == 0)) { 844 e_dbg("nvm parameter(s) out of bounds\n"); 845 return -E1000_ERR_NVM; 846 } 847 848 for (i = 0; i < words; i++) { 849 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 850 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 851 E1000_NVM_RW_REG_START; 852 853 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 854 if (ret_val) 855 break; 856 857 ew32(EEWR, eewr); 858 859 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 860 if (ret_val) 861 break; 862 } 863 864 return ret_val; 865 } 866 867 /** 868 * e1000_get_cfg_done_82571 - Poll for configuration done 869 * @hw: pointer to the HW structure 870 * 871 * Reads the management control register for the config done bit to be set. 872 **/ 873 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 874 { 875 s32 timeout = PHY_CFG_TIMEOUT; 876 877 while (timeout) { 878 if (er32(EEMNGCTL) & 879 E1000_NVM_CFG_DONE_PORT_0) 880 break; 881 usleep_range(1000, 2000); 882 timeout--; 883 } 884 if (!timeout) { 885 e_dbg("MNG configuration cycle has not completed.\n"); 886 return -E1000_ERR_RESET; 887 } 888 889 return 0; 890 } 891 892 /** 893 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 894 * @hw: pointer to the HW structure 895 * @active: true to enable LPLU, false to disable 896 * 897 * Sets the LPLU D0 state according to the active flag. When activating LPLU 898 * this function also disables smart speed and vice versa. LPLU will not be 899 * activated unless the device autonegotiation advertisement meets standards 900 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 901 * pointer entry point only called by PHY setup routines. 902 **/ 903 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 904 { 905 struct e1000_phy_info *phy = &hw->phy; 906 s32 ret_val; 907 u16 data; 908 909 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 910 if (ret_val) 911 return ret_val; 912 913 if (active) { 914 data |= IGP02E1000_PM_D0_LPLU; 915 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 916 if (ret_val) 917 return ret_val; 918 919 /* When LPLU is enabled, we should disable SmartSpeed */ 920 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 921 if (ret_val) 922 return ret_val; 923 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 924 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 925 if (ret_val) 926 return ret_val; 927 } else { 928 data &= ~IGP02E1000_PM_D0_LPLU; 929 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 930 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 931 * during Dx states where the power conservation is most 932 * important. During driver activity we should enable 933 * SmartSpeed, so performance is maintained. 934 */ 935 if (phy->smart_speed == e1000_smart_speed_on) { 936 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 937 &data); 938 if (ret_val) 939 return ret_val; 940 941 data |= IGP01E1000_PSCFR_SMART_SPEED; 942 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 943 data); 944 if (ret_val) 945 return ret_val; 946 } else if (phy->smart_speed == e1000_smart_speed_off) { 947 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 948 &data); 949 if (ret_val) 950 return ret_val; 951 952 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 953 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 954 data); 955 if (ret_val) 956 return ret_val; 957 } 958 } 959 960 return 0; 961 } 962 963 /** 964 * e1000_reset_hw_82571 - Reset hardware 965 * @hw: pointer to the HW structure 966 * 967 * This resets the hardware into a known state. 968 **/ 969 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 970 { 971 u32 ctrl, ctrl_ext, eecd, tctl; 972 s32 ret_val; 973 974 /* Prevent the PCI-E bus from sticking if there is no TLP connection 975 * on the last TLP read/write transaction when MAC is reset. 976 */ 977 ret_val = e1000e_disable_pcie_master(hw); 978 if (ret_val) 979 e_dbg("PCI-E Master disable polling has failed.\n"); 980 981 e_dbg("Masking off all interrupts\n"); 982 ew32(IMC, 0xffffffff); 983 984 ew32(RCTL, 0); 985 tctl = er32(TCTL); 986 tctl &= ~E1000_TCTL_EN; 987 ew32(TCTL, tctl); 988 e1e_flush(); 989 990 usleep_range(10000, 20000); 991 992 /* Must acquire the MDIO ownership before MAC reset. 993 * Ownership defaults to firmware after a reset. 994 */ 995 switch (hw->mac.type) { 996 case e1000_82573: 997 ret_val = e1000_get_hw_semaphore_82573(hw); 998 break; 999 case e1000_82574: 1000 case e1000_82583: 1001 ret_val = e1000_get_hw_semaphore_82574(hw); 1002 break; 1003 default: 1004 break; 1005 } 1006 if (ret_val) 1007 e_dbg("Cannot acquire MDIO ownership\n"); 1008 1009 ctrl = er32(CTRL); 1010 1011 e_dbg("Issuing a global reset to MAC\n"); 1012 ew32(CTRL, ctrl | E1000_CTRL_RST); 1013 1014 /* Must release MDIO ownership and mutex after MAC reset. */ 1015 switch (hw->mac.type) { 1016 case e1000_82574: 1017 case e1000_82583: 1018 e1000_put_hw_semaphore_82574(hw); 1019 break; 1020 default: 1021 break; 1022 } 1023 1024 if (hw->nvm.type == e1000_nvm_flash_hw) { 1025 udelay(10); 1026 ctrl_ext = er32(CTRL_EXT); 1027 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1028 ew32(CTRL_EXT, ctrl_ext); 1029 e1e_flush(); 1030 } 1031 1032 ret_val = e1000e_get_auto_rd_done(hw); 1033 if (ret_val) 1034 /* We don't want to continue accessing MAC registers. */ 1035 return ret_val; 1036 1037 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1038 * Need to wait for Phy configuration completion before accessing 1039 * NVM and Phy. 1040 */ 1041 1042 switch (hw->mac.type) { 1043 case e1000_82571: 1044 case e1000_82572: 1045 /* REQ and GNT bits need to be cleared when using AUTO_RD 1046 * to access the EEPROM. 1047 */ 1048 eecd = er32(EECD); 1049 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1050 ew32(EECD, eecd); 1051 break; 1052 case e1000_82573: 1053 case e1000_82574: 1054 case e1000_82583: 1055 msleep(25); 1056 break; 1057 default: 1058 break; 1059 } 1060 1061 /* Clear any pending interrupt events. */ 1062 ew32(IMC, 0xffffffff); 1063 er32(ICR); 1064 1065 if (hw->mac.type == e1000_82571) { 1066 /* Install any alternate MAC address into RAR0 */ 1067 ret_val = e1000_check_alt_mac_addr_generic(hw); 1068 if (ret_val) 1069 return ret_val; 1070 1071 e1000e_set_laa_state_82571(hw, true); 1072 } 1073 1074 /* Reinitialize the 82571 serdes link state machine */ 1075 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1076 hw->mac.serdes_link_state = e1000_serdes_link_down; 1077 1078 return 0; 1079 } 1080 1081 /** 1082 * e1000_init_hw_82571 - Initialize hardware 1083 * @hw: pointer to the HW structure 1084 * 1085 * This inits the hardware readying it for operation. 1086 **/ 1087 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1088 { 1089 struct e1000_mac_info *mac = &hw->mac; 1090 u32 reg_data; 1091 s32 ret_val; 1092 u16 i, rar_count = mac->rar_entry_count; 1093 1094 e1000_initialize_hw_bits_82571(hw); 1095 1096 /* Initialize identification LED */ 1097 ret_val = mac->ops.id_led_init(hw); 1098 if (ret_val) 1099 e_dbg("Error initializing identification LED\n"); 1100 /* This is not fatal and we should not stop init due to this */ 1101 1102 /* Disabling VLAN filtering */ 1103 e_dbg("Initializing the IEEE VLAN\n"); 1104 mac->ops.clear_vfta(hw); 1105 1106 /* Setup the receive address. 1107 * If, however, a locally administered address was assigned to the 1108 * 82571, we must reserve a RAR for it to work around an issue where 1109 * resetting one port will reload the MAC on the other port. 1110 */ 1111 if (e1000e_get_laa_state_82571(hw)) 1112 rar_count--; 1113 e1000e_init_rx_addrs(hw, rar_count); 1114 1115 /* Zero out the Multicast HASH table */ 1116 e_dbg("Zeroing the MTA\n"); 1117 for (i = 0; i < mac->mta_reg_count; i++) 1118 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1119 1120 /* Setup link and flow control */ 1121 ret_val = mac->ops.setup_link(hw); 1122 1123 /* Set the transmit descriptor write-back policy */ 1124 reg_data = er32(TXDCTL(0)); 1125 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1126 E1000_TXDCTL_FULL_TX_DESC_WB | 1127 E1000_TXDCTL_COUNT_DESC; 1128 ew32(TXDCTL(0), reg_data); 1129 1130 /* ...for both queues. */ 1131 switch (mac->type) { 1132 case e1000_82573: 1133 e1000e_enable_tx_pkt_filtering(hw); 1134 /* fall through */ 1135 case e1000_82574: 1136 case e1000_82583: 1137 reg_data = er32(GCR); 1138 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1139 ew32(GCR, reg_data); 1140 break; 1141 default: 1142 reg_data = er32(TXDCTL(1)); 1143 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1144 E1000_TXDCTL_FULL_TX_DESC_WB | 1145 E1000_TXDCTL_COUNT_DESC; 1146 ew32(TXDCTL(1), reg_data); 1147 break; 1148 } 1149 1150 /* Clear all of the statistics registers (clear on read). It is 1151 * important that we do this after we have tried to establish link 1152 * because the symbol error count will increment wildly if there 1153 * is no link. 1154 */ 1155 e1000_clear_hw_cntrs_82571(hw); 1156 1157 return ret_val; 1158 } 1159 1160 /** 1161 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1162 * @hw: pointer to the HW structure 1163 * 1164 * Initializes required hardware-dependent bits needed for normal operation. 1165 **/ 1166 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1167 { 1168 u32 reg; 1169 1170 /* Transmit Descriptor Control 0 */ 1171 reg = er32(TXDCTL(0)); 1172 reg |= (1 << 22); 1173 ew32(TXDCTL(0), reg); 1174 1175 /* Transmit Descriptor Control 1 */ 1176 reg = er32(TXDCTL(1)); 1177 reg |= (1 << 22); 1178 ew32(TXDCTL(1), reg); 1179 1180 /* Transmit Arbitration Control 0 */ 1181 reg = er32(TARC(0)); 1182 reg &= ~(0xF << 27); /* 30:27 */ 1183 switch (hw->mac.type) { 1184 case e1000_82571: 1185 case e1000_82572: 1186 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1187 break; 1188 case e1000_82574: 1189 case e1000_82583: 1190 reg |= (1 << 26); 1191 break; 1192 default: 1193 break; 1194 } 1195 ew32(TARC(0), reg); 1196 1197 /* Transmit Arbitration Control 1 */ 1198 reg = er32(TARC(1)); 1199 switch (hw->mac.type) { 1200 case e1000_82571: 1201 case e1000_82572: 1202 reg &= ~((1 << 29) | (1 << 30)); 1203 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1204 if (er32(TCTL) & E1000_TCTL_MULR) 1205 reg &= ~(1 << 28); 1206 else 1207 reg |= (1 << 28); 1208 ew32(TARC(1), reg); 1209 break; 1210 default: 1211 break; 1212 } 1213 1214 /* Device Control */ 1215 switch (hw->mac.type) { 1216 case e1000_82573: 1217 case e1000_82574: 1218 case e1000_82583: 1219 reg = er32(CTRL); 1220 reg &= ~(1 << 29); 1221 ew32(CTRL, reg); 1222 break; 1223 default: 1224 break; 1225 } 1226 1227 /* Extended Device Control */ 1228 switch (hw->mac.type) { 1229 case e1000_82573: 1230 case e1000_82574: 1231 case e1000_82583: 1232 reg = er32(CTRL_EXT); 1233 reg &= ~(1 << 23); 1234 reg |= (1 << 22); 1235 ew32(CTRL_EXT, reg); 1236 break; 1237 default: 1238 break; 1239 } 1240 1241 if (hw->mac.type == e1000_82571) { 1242 reg = er32(PBA_ECC); 1243 reg |= E1000_PBA_ECC_CORR_EN; 1244 ew32(PBA_ECC, reg); 1245 } 1246 1247 /* Workaround for hardware errata. 1248 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1249 */ 1250 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 1251 reg = er32(CTRL_EXT); 1252 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1253 ew32(CTRL_EXT, reg); 1254 } 1255 1256 /* Disable IPv6 extension header parsing because some malformed 1257 * IPv6 headers can hang the Rx. 1258 */ 1259 if (hw->mac.type <= e1000_82573) { 1260 reg = er32(RFCTL); 1261 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1262 ew32(RFCTL, reg); 1263 } 1264 1265 /* PCI-Ex Control Registers */ 1266 switch (hw->mac.type) { 1267 case e1000_82574: 1268 case e1000_82583: 1269 reg = er32(GCR); 1270 reg |= (1 << 22); 1271 ew32(GCR, reg); 1272 1273 /* Workaround for hardware errata. 1274 * apply workaround for hardware errata documented in errata 1275 * docs Fixes issue where some error prone or unreliable PCIe 1276 * completions are occurring, particularly with ASPM enabled. 1277 * Without fix, issue can cause Tx timeouts. 1278 */ 1279 reg = er32(GCR2); 1280 reg |= 1; 1281 ew32(GCR2, reg); 1282 break; 1283 default: 1284 break; 1285 } 1286 } 1287 1288 /** 1289 * e1000_clear_vfta_82571 - Clear VLAN filter table 1290 * @hw: pointer to the HW structure 1291 * 1292 * Clears the register array which contains the VLAN filter table by 1293 * setting all the values to 0. 1294 **/ 1295 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1296 { 1297 u32 offset; 1298 u32 vfta_value = 0; 1299 u32 vfta_offset = 0; 1300 u32 vfta_bit_in_reg = 0; 1301 1302 switch (hw->mac.type) { 1303 case e1000_82573: 1304 case e1000_82574: 1305 case e1000_82583: 1306 if (hw->mng_cookie.vlan_id != 0) { 1307 /* The VFTA is a 4096b bit-field, each identifying 1308 * a single VLAN ID. The following operations 1309 * determine which 32b entry (i.e. offset) into the 1310 * array we want to set the VLAN ID (i.e. bit) of 1311 * the manageability unit. 1312 */ 1313 vfta_offset = (hw->mng_cookie.vlan_id >> 1314 E1000_VFTA_ENTRY_SHIFT) & 1315 E1000_VFTA_ENTRY_MASK; 1316 vfta_bit_in_reg = 1317 1 << (hw->mng_cookie.vlan_id & 1318 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1319 } 1320 break; 1321 default: 1322 break; 1323 } 1324 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1325 /* If the offset we want to clear is the same offset of the 1326 * manageability VLAN ID, then clear all bits except that of 1327 * the manageability unit. 1328 */ 1329 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1330 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1331 e1e_flush(); 1332 } 1333 } 1334 1335 /** 1336 * e1000_check_mng_mode_82574 - Check manageability is enabled 1337 * @hw: pointer to the HW structure 1338 * 1339 * Reads the NVM Initialization Control Word 2 and returns true 1340 * (>0) if any manageability is enabled, else false (0). 1341 **/ 1342 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1343 { 1344 u16 data; 1345 1346 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1347 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1348 } 1349 1350 /** 1351 * e1000_led_on_82574 - Turn LED on 1352 * @hw: pointer to the HW structure 1353 * 1354 * Turn LED on. 1355 **/ 1356 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1357 { 1358 u32 ctrl; 1359 u32 i; 1360 1361 ctrl = hw->mac.ledctl_mode2; 1362 if (!(E1000_STATUS_LU & er32(STATUS))) { 1363 /* If no link, then turn LED on by setting the invert bit 1364 * for each LED that's "on" (0x0E) in ledctl_mode2. 1365 */ 1366 for (i = 0; i < 4; i++) 1367 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1368 E1000_LEDCTL_MODE_LED_ON) 1369 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1370 } 1371 ew32(LEDCTL, ctrl); 1372 1373 return 0; 1374 } 1375 1376 /** 1377 * e1000_check_phy_82574 - check 82574 phy hung state 1378 * @hw: pointer to the HW structure 1379 * 1380 * Returns whether phy is hung or not 1381 **/ 1382 bool e1000_check_phy_82574(struct e1000_hw *hw) 1383 { 1384 u16 status_1kbt = 0; 1385 u16 receive_errors = 0; 1386 s32 ret_val; 1387 1388 /* Read PHY Receive Error counter first, if its is max - all F's then 1389 * read the Base1000T status register If both are max then PHY is hung. 1390 */ 1391 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); 1392 if (ret_val) 1393 return false; 1394 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1395 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); 1396 if (ret_val) 1397 return false; 1398 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1399 E1000_IDLE_ERROR_COUNT_MASK) 1400 return true; 1401 } 1402 1403 return false; 1404 } 1405 1406 /** 1407 * e1000_setup_link_82571 - Setup flow control and link settings 1408 * @hw: pointer to the HW structure 1409 * 1410 * Determines which flow control settings to use, then configures flow 1411 * control. Calls the appropriate media-specific link configuration 1412 * function. Assuming the adapter has a valid link partner, a valid link 1413 * should be established. Assumes the hardware has previously been reset 1414 * and the transmitter and receiver are not enabled. 1415 **/ 1416 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1417 { 1418 /* 82573 does not have a word in the NVM to determine 1419 * the default flow control setting, so we explicitly 1420 * set it to full. 1421 */ 1422 switch (hw->mac.type) { 1423 case e1000_82573: 1424 case e1000_82574: 1425 case e1000_82583: 1426 if (hw->fc.requested_mode == e1000_fc_default) 1427 hw->fc.requested_mode = e1000_fc_full; 1428 break; 1429 default: 1430 break; 1431 } 1432 1433 return e1000e_setup_link_generic(hw); 1434 } 1435 1436 /** 1437 * e1000_setup_copper_link_82571 - Configure copper link settings 1438 * @hw: pointer to the HW structure 1439 * 1440 * Configures the link for auto-neg or forced speed and duplex. Then we check 1441 * for link, once link is established calls to configure collision distance 1442 * and flow control are called. 1443 **/ 1444 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1445 { 1446 u32 ctrl; 1447 s32 ret_val; 1448 1449 ctrl = er32(CTRL); 1450 ctrl |= E1000_CTRL_SLU; 1451 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1452 ew32(CTRL, ctrl); 1453 1454 switch (hw->phy.type) { 1455 case e1000_phy_m88: 1456 case e1000_phy_bm: 1457 ret_val = e1000e_copper_link_setup_m88(hw); 1458 break; 1459 case e1000_phy_igp_2: 1460 ret_val = e1000e_copper_link_setup_igp(hw); 1461 break; 1462 default: 1463 return -E1000_ERR_PHY; 1464 break; 1465 } 1466 1467 if (ret_val) 1468 return ret_val; 1469 1470 return e1000e_setup_copper_link(hw); 1471 } 1472 1473 /** 1474 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1475 * @hw: pointer to the HW structure 1476 * 1477 * Configures collision distance and flow control for fiber and serdes links. 1478 * Upon successful setup, poll for link. 1479 **/ 1480 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1481 { 1482 switch (hw->mac.type) { 1483 case e1000_82571: 1484 case e1000_82572: 1485 /* If SerDes loopback mode is entered, there is no form 1486 * of reset to take the adapter out of that mode. So we 1487 * have to explicitly take the adapter out of loopback 1488 * mode. This prevents drivers from twiddling their thumbs 1489 * if another tool failed to take it out of loopback mode. 1490 */ 1491 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1492 break; 1493 default: 1494 break; 1495 } 1496 1497 return e1000e_setup_fiber_serdes_link(hw); 1498 } 1499 1500 /** 1501 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1502 * @hw: pointer to the HW structure 1503 * 1504 * Reports the link state as up or down. 1505 * 1506 * If autonegotiation is supported by the link partner, the link state is 1507 * determined by the result of autonegotiation. This is the most likely case. 1508 * If autonegotiation is not supported by the link partner, and the link 1509 * has a valid signal, force the link up. 1510 * 1511 * The link state is represented internally here by 4 states: 1512 * 1513 * 1) down 1514 * 2) autoneg_progress 1515 * 3) autoneg_complete (the link successfully autonegotiated) 1516 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1517 * 1518 **/ 1519 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1520 { 1521 struct e1000_mac_info *mac = &hw->mac; 1522 u32 rxcw; 1523 u32 ctrl; 1524 u32 status; 1525 u32 txcw; 1526 u32 i; 1527 s32 ret_val = 0; 1528 1529 ctrl = er32(CTRL); 1530 status = er32(STATUS); 1531 er32(RXCW); 1532 /* SYNCH bit and IV bit are sticky */ 1533 udelay(10); 1534 rxcw = er32(RXCW); 1535 1536 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1537 /* Receiver is synchronized with no invalid bits. */ 1538 switch (mac->serdes_link_state) { 1539 case e1000_serdes_link_autoneg_complete: 1540 if (!(status & E1000_STATUS_LU)) { 1541 /* We have lost link, retry autoneg before 1542 * reporting link failure 1543 */ 1544 mac->serdes_link_state = 1545 e1000_serdes_link_autoneg_progress; 1546 mac->serdes_has_link = false; 1547 e_dbg("AN_UP -> AN_PROG\n"); 1548 } else { 1549 mac->serdes_has_link = true; 1550 } 1551 break; 1552 1553 case e1000_serdes_link_forced_up: 1554 /* If we are receiving /C/ ordered sets, re-enable 1555 * auto-negotiation in the TXCW register and disable 1556 * forced link in the Device Control register in an 1557 * attempt to auto-negotiate with our link partner. 1558 */ 1559 if (rxcw & E1000_RXCW_C) { 1560 /* Enable autoneg, and unforce link up */ 1561 ew32(TXCW, mac->txcw); 1562 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1563 mac->serdes_link_state = 1564 e1000_serdes_link_autoneg_progress; 1565 mac->serdes_has_link = false; 1566 e_dbg("FORCED_UP -> AN_PROG\n"); 1567 } else { 1568 mac->serdes_has_link = true; 1569 } 1570 break; 1571 1572 case e1000_serdes_link_autoneg_progress: 1573 if (rxcw & E1000_RXCW_C) { 1574 /* We received /C/ ordered sets, meaning the 1575 * link partner has autonegotiated, and we can 1576 * trust the Link Up (LU) status bit. 1577 */ 1578 if (status & E1000_STATUS_LU) { 1579 mac->serdes_link_state = 1580 e1000_serdes_link_autoneg_complete; 1581 e_dbg("AN_PROG -> AN_UP\n"); 1582 mac->serdes_has_link = true; 1583 } else { 1584 /* Autoneg completed, but failed. */ 1585 mac->serdes_link_state = 1586 e1000_serdes_link_down; 1587 e_dbg("AN_PROG -> DOWN\n"); 1588 } 1589 } else { 1590 /* The link partner did not autoneg. 1591 * Force link up and full duplex, and change 1592 * state to forced. 1593 */ 1594 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1595 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1596 ew32(CTRL, ctrl); 1597 1598 /* Configure Flow Control after link up. */ 1599 ret_val = e1000e_config_fc_after_link_up(hw); 1600 if (ret_val) { 1601 e_dbg("Error config flow control\n"); 1602 break; 1603 } 1604 mac->serdes_link_state = 1605 e1000_serdes_link_forced_up; 1606 mac->serdes_has_link = true; 1607 e_dbg("AN_PROG -> FORCED_UP\n"); 1608 } 1609 break; 1610 1611 case e1000_serdes_link_down: 1612 default: 1613 /* The link was down but the receiver has now gained 1614 * valid sync, so lets see if we can bring the link 1615 * up. 1616 */ 1617 ew32(TXCW, mac->txcw); 1618 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1619 mac->serdes_link_state = 1620 e1000_serdes_link_autoneg_progress; 1621 mac->serdes_has_link = false; 1622 e_dbg("DOWN -> AN_PROG\n"); 1623 break; 1624 } 1625 } else { 1626 if (!(rxcw & E1000_RXCW_SYNCH)) { 1627 mac->serdes_has_link = false; 1628 mac->serdes_link_state = e1000_serdes_link_down; 1629 e_dbg("ANYSTATE -> DOWN\n"); 1630 } else { 1631 /* Check several times, if SYNCH bit and CONFIG 1632 * bit both are consistently 1 then simply ignore 1633 * the IV bit and restart Autoneg 1634 */ 1635 for (i = 0; i < AN_RETRY_COUNT; i++) { 1636 udelay(10); 1637 rxcw = er32(RXCW); 1638 if ((rxcw & E1000_RXCW_SYNCH) && 1639 (rxcw & E1000_RXCW_C)) 1640 continue; 1641 1642 if (rxcw & E1000_RXCW_IV) { 1643 mac->serdes_has_link = false; 1644 mac->serdes_link_state = 1645 e1000_serdes_link_down; 1646 e_dbg("ANYSTATE -> DOWN\n"); 1647 break; 1648 } 1649 } 1650 1651 if (i == AN_RETRY_COUNT) { 1652 txcw = er32(TXCW); 1653 txcw |= E1000_TXCW_ANE; 1654 ew32(TXCW, txcw); 1655 mac->serdes_link_state = 1656 e1000_serdes_link_autoneg_progress; 1657 mac->serdes_has_link = false; 1658 e_dbg("ANYSTATE -> AN_PROG\n"); 1659 } 1660 } 1661 } 1662 1663 return ret_val; 1664 } 1665 1666 /** 1667 * e1000_valid_led_default_82571 - Verify a valid default LED config 1668 * @hw: pointer to the HW structure 1669 * @data: pointer to the NVM (EEPROM) 1670 * 1671 * Read the EEPROM for the current default LED configuration. If the 1672 * LED configuration is not valid, set to a valid LED configuration. 1673 **/ 1674 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1675 { 1676 s32 ret_val; 1677 1678 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1679 if (ret_val) { 1680 e_dbg("NVM Read Error\n"); 1681 return ret_val; 1682 } 1683 1684 switch (hw->mac.type) { 1685 case e1000_82573: 1686 case e1000_82574: 1687 case e1000_82583: 1688 if (*data == ID_LED_RESERVED_F746) 1689 *data = ID_LED_DEFAULT_82573; 1690 break; 1691 default: 1692 if (*data == ID_LED_RESERVED_0000 || 1693 *data == ID_LED_RESERVED_FFFF) 1694 *data = ID_LED_DEFAULT; 1695 break; 1696 } 1697 1698 return 0; 1699 } 1700 1701 /** 1702 * e1000e_get_laa_state_82571 - Get locally administered address state 1703 * @hw: pointer to the HW structure 1704 * 1705 * Retrieve and return the current locally administered address state. 1706 **/ 1707 bool e1000e_get_laa_state_82571(struct e1000_hw *hw) 1708 { 1709 if (hw->mac.type != e1000_82571) 1710 return false; 1711 1712 return hw->dev_spec.e82571.laa_is_present; 1713 } 1714 1715 /** 1716 * e1000e_set_laa_state_82571 - Set locally administered address state 1717 * @hw: pointer to the HW structure 1718 * @state: enable/disable locally administered address 1719 * 1720 * Enable/Disable the current locally administered address state. 1721 **/ 1722 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 1723 { 1724 if (hw->mac.type != e1000_82571) 1725 return; 1726 1727 hw->dev_spec.e82571.laa_is_present = state; 1728 1729 /* If workaround is activated... */ 1730 if (state) 1731 /* Hold a copy of the LAA in RAR[14] This is done so that 1732 * between the time RAR[0] gets clobbered and the time it 1733 * gets fixed, the actual LAA is in one of the RARs and no 1734 * incoming packets directed to this port are dropped. 1735 * Eventually the LAA will be in RAR[0] and RAR[14]. 1736 */ 1737 hw->mac.ops.rar_set(hw, hw->mac.addr, 1738 hw->mac.rar_entry_count - 1); 1739 } 1740 1741 /** 1742 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1743 * @hw: pointer to the HW structure 1744 * 1745 * Verifies that the EEPROM has completed the update. After updating the 1746 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1747 * the checksum fix is not implemented, we need to set the bit and update 1748 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1749 * we need to return bad checksum. 1750 **/ 1751 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1752 { 1753 struct e1000_nvm_info *nvm = &hw->nvm; 1754 s32 ret_val; 1755 u16 data; 1756 1757 if (nvm->type != e1000_nvm_flash_hw) 1758 return 0; 1759 1760 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1761 * 10h-12h. Checksum may need to be fixed. 1762 */ 1763 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1764 if (ret_val) 1765 return ret_val; 1766 1767 if (!(data & 0x10)) { 1768 /* Read 0x23 and check bit 15. This bit is a 1 1769 * when the checksum has already been fixed. If 1770 * the checksum is still wrong and this bit is a 1771 * 1, we need to return bad checksum. Otherwise, 1772 * we need to set this bit to a 1 and update the 1773 * checksum. 1774 */ 1775 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1776 if (ret_val) 1777 return ret_val; 1778 1779 if (!(data & 0x8000)) { 1780 data |= 0x8000; 1781 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1782 if (ret_val) 1783 return ret_val; 1784 ret_val = e1000e_update_nvm_checksum(hw); 1785 if (ret_val) 1786 return ret_val; 1787 } 1788 } 1789 1790 return 0; 1791 } 1792 1793 /** 1794 * e1000_read_mac_addr_82571 - Read device MAC address 1795 * @hw: pointer to the HW structure 1796 **/ 1797 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1798 { 1799 if (hw->mac.type == e1000_82571) { 1800 s32 ret_val; 1801 1802 /* If there's an alternate MAC address place it in RAR0 1803 * so that it will override the Si installed default perm 1804 * address. 1805 */ 1806 ret_val = e1000_check_alt_mac_addr_generic(hw); 1807 if (ret_val) 1808 return ret_val; 1809 } 1810 1811 return e1000_read_mac_addr_generic(hw); 1812 } 1813 1814 /** 1815 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1816 * @hw: pointer to the HW structure 1817 * 1818 * In the case of a PHY power down to save power, or to turn off link during a 1819 * driver unload, or wake on lan is not enabled, remove the link. 1820 **/ 1821 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1822 { 1823 struct e1000_phy_info *phy = &hw->phy; 1824 struct e1000_mac_info *mac = &hw->mac; 1825 1826 if (!phy->ops.check_reset_block) 1827 return; 1828 1829 /* If the management interface is not enabled, then power down */ 1830 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1831 e1000_power_down_phy_copper(hw); 1832 } 1833 1834 /** 1835 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1836 * @hw: pointer to the HW structure 1837 * 1838 * Clears the hardware counters by reading the counter registers. 1839 **/ 1840 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1841 { 1842 e1000e_clear_hw_cntrs_base(hw); 1843 1844 er32(PRC64); 1845 er32(PRC127); 1846 er32(PRC255); 1847 er32(PRC511); 1848 er32(PRC1023); 1849 er32(PRC1522); 1850 er32(PTC64); 1851 er32(PTC127); 1852 er32(PTC255); 1853 er32(PTC511); 1854 er32(PTC1023); 1855 er32(PTC1522); 1856 1857 er32(ALGNERRC); 1858 er32(RXERRC); 1859 er32(TNCRS); 1860 er32(CEXTERR); 1861 er32(TSCTC); 1862 er32(TSCTFC); 1863 1864 er32(MGTPRC); 1865 er32(MGTPDC); 1866 er32(MGTPTC); 1867 1868 er32(IAC); 1869 er32(ICRXOC); 1870 1871 er32(ICRXPTC); 1872 er32(ICRXATC); 1873 er32(ICTXPTC); 1874 er32(ICTXATC); 1875 er32(ICTXQEC); 1876 er32(ICTXQMTC); 1877 er32(ICRXDMTC); 1878 } 1879 1880 static const struct e1000_mac_operations e82571_mac_ops = { 1881 /* .check_mng_mode: mac type dependent */ 1882 /* .check_for_link: media type dependent */ 1883 .id_led_init = e1000e_id_led_init_generic, 1884 .cleanup_led = e1000e_cleanup_led_generic, 1885 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, 1886 .get_bus_info = e1000e_get_bus_info_pcie, 1887 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1888 /* .get_link_up_info: media type dependent */ 1889 /* .led_on: mac type dependent */ 1890 .led_off = e1000e_led_off_generic, 1891 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1892 .write_vfta = e1000_write_vfta_generic, 1893 .clear_vfta = e1000_clear_vfta_82571, 1894 .reset_hw = e1000_reset_hw_82571, 1895 .init_hw = e1000_init_hw_82571, 1896 .setup_link = e1000_setup_link_82571, 1897 /* .setup_physical_interface: media type dependent */ 1898 .setup_led = e1000e_setup_led_generic, 1899 .config_collision_dist = e1000e_config_collision_dist_generic, 1900 .read_mac_addr = e1000_read_mac_addr_82571, 1901 .rar_set = e1000e_rar_set_generic, 1902 }; 1903 1904 static const struct e1000_phy_operations e82_phy_ops_igp = { 1905 .acquire = e1000_get_hw_semaphore_82571, 1906 .check_polarity = e1000_check_polarity_igp, 1907 .check_reset_block = e1000e_check_reset_block_generic, 1908 .commit = NULL, 1909 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, 1910 .get_cfg_done = e1000_get_cfg_done_82571, 1911 .get_cable_length = e1000e_get_cable_length_igp_2, 1912 .get_info = e1000e_get_phy_info_igp, 1913 .read_reg = e1000e_read_phy_reg_igp, 1914 .release = e1000_put_hw_semaphore_82571, 1915 .reset = e1000e_phy_hw_reset_generic, 1916 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1917 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1918 .write_reg = e1000e_write_phy_reg_igp, 1919 .cfg_on_link_up = NULL, 1920 }; 1921 1922 static const struct e1000_phy_operations e82_phy_ops_m88 = { 1923 .acquire = e1000_get_hw_semaphore_82571, 1924 .check_polarity = e1000_check_polarity_m88, 1925 .check_reset_block = e1000e_check_reset_block_generic, 1926 .commit = e1000e_phy_sw_reset, 1927 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1928 .get_cfg_done = e1000e_get_cfg_done_generic, 1929 .get_cable_length = e1000e_get_cable_length_m88, 1930 .get_info = e1000e_get_phy_info_m88, 1931 .read_reg = e1000e_read_phy_reg_m88, 1932 .release = e1000_put_hw_semaphore_82571, 1933 .reset = e1000e_phy_hw_reset_generic, 1934 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1935 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1936 .write_reg = e1000e_write_phy_reg_m88, 1937 .cfg_on_link_up = NULL, 1938 }; 1939 1940 static const struct e1000_phy_operations e82_phy_ops_bm = { 1941 .acquire = e1000_get_hw_semaphore_82571, 1942 .check_polarity = e1000_check_polarity_m88, 1943 .check_reset_block = e1000e_check_reset_block_generic, 1944 .commit = e1000e_phy_sw_reset, 1945 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1946 .get_cfg_done = e1000e_get_cfg_done_generic, 1947 .get_cable_length = e1000e_get_cable_length_m88, 1948 .get_info = e1000e_get_phy_info_m88, 1949 .read_reg = e1000e_read_phy_reg_bm2, 1950 .release = e1000_put_hw_semaphore_82571, 1951 .reset = e1000e_phy_hw_reset_generic, 1952 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1953 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1954 .write_reg = e1000e_write_phy_reg_bm2, 1955 .cfg_on_link_up = NULL, 1956 }; 1957 1958 static const struct e1000_nvm_operations e82571_nvm_ops = { 1959 .acquire = e1000_acquire_nvm_82571, 1960 .read = e1000e_read_nvm_eerd, 1961 .release = e1000_release_nvm_82571, 1962 .reload = e1000e_reload_nvm_generic, 1963 .update = e1000_update_nvm_checksum_82571, 1964 .valid_led_default = e1000_valid_led_default_82571, 1965 .validate = e1000_validate_nvm_checksum_82571, 1966 .write = e1000_write_nvm_82571, 1967 }; 1968 1969 const struct e1000_info e1000_82571_info = { 1970 .mac = e1000_82571, 1971 .flags = FLAG_HAS_HW_VLAN_FILTER 1972 | FLAG_HAS_JUMBO_FRAMES 1973 | FLAG_HAS_WOL 1974 | FLAG_APME_IN_CTRL3 1975 | FLAG_HAS_CTRLEXT_ON_LOAD 1976 | FLAG_HAS_SMART_POWER_DOWN 1977 | FLAG_RESET_OVERWRITES_LAA /* errata */ 1978 | FLAG_TARC_SPEED_MODE_BIT /* errata */ 1979 | FLAG_APME_CHECK_PORT_B, 1980 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1981 | FLAG2_DMA_BURST, 1982 .pba = 38, 1983 .max_hw_frame_size = DEFAULT_JUMBO, 1984 .get_variants = e1000_get_variants_82571, 1985 .mac_ops = &e82571_mac_ops, 1986 .phy_ops = &e82_phy_ops_igp, 1987 .nvm_ops = &e82571_nvm_ops, 1988 }; 1989 1990 const struct e1000_info e1000_82572_info = { 1991 .mac = e1000_82572, 1992 .flags = FLAG_HAS_HW_VLAN_FILTER 1993 | FLAG_HAS_JUMBO_FRAMES 1994 | FLAG_HAS_WOL 1995 | FLAG_APME_IN_CTRL3 1996 | FLAG_HAS_CTRLEXT_ON_LOAD 1997 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ 1998 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1999 | FLAG2_DMA_BURST, 2000 .pba = 38, 2001 .max_hw_frame_size = DEFAULT_JUMBO, 2002 .get_variants = e1000_get_variants_82571, 2003 .mac_ops = &e82571_mac_ops, 2004 .phy_ops = &e82_phy_ops_igp, 2005 .nvm_ops = &e82571_nvm_ops, 2006 }; 2007 2008 const struct e1000_info e1000_82573_info = { 2009 .mac = e1000_82573, 2010 .flags = FLAG_HAS_HW_VLAN_FILTER 2011 | FLAG_HAS_WOL 2012 | FLAG_APME_IN_CTRL3 2013 | FLAG_HAS_SMART_POWER_DOWN 2014 | FLAG_HAS_AMT 2015 | FLAG_HAS_SWSM_ON_LOAD, 2016 .flags2 = FLAG2_DISABLE_ASPM_L1 2017 | FLAG2_DISABLE_ASPM_L0S, 2018 .pba = 20, 2019 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 2020 .get_variants = e1000_get_variants_82571, 2021 .mac_ops = &e82571_mac_ops, 2022 .phy_ops = &e82_phy_ops_m88, 2023 .nvm_ops = &e82571_nvm_ops, 2024 }; 2025 2026 const struct e1000_info e1000_82574_info = { 2027 .mac = e1000_82574, 2028 .flags = FLAG_HAS_HW_VLAN_FILTER 2029 | FLAG_HAS_MSIX 2030 | FLAG_HAS_JUMBO_FRAMES 2031 | FLAG_HAS_WOL 2032 | FLAG_HAS_HW_TIMESTAMP 2033 | FLAG_APME_IN_CTRL3 2034 | FLAG_HAS_SMART_POWER_DOWN 2035 | FLAG_HAS_AMT 2036 | FLAG_HAS_CTRLEXT_ON_LOAD, 2037 .flags2 = FLAG2_CHECK_PHY_HANG 2038 | FLAG2_DISABLE_ASPM_L0S 2039 | FLAG2_DISABLE_ASPM_L1 2040 | FLAG2_NO_DISABLE_RX 2041 | FLAG2_DMA_BURST, 2042 .pba = 32, 2043 .max_hw_frame_size = DEFAULT_JUMBO, 2044 .get_variants = e1000_get_variants_82571, 2045 .mac_ops = &e82571_mac_ops, 2046 .phy_ops = &e82_phy_ops_bm, 2047 .nvm_ops = &e82571_nvm_ops, 2048 }; 2049 2050 const struct e1000_info e1000_82583_info = { 2051 .mac = e1000_82583, 2052 .flags = FLAG_HAS_HW_VLAN_FILTER 2053 | FLAG_HAS_WOL 2054 | FLAG_HAS_HW_TIMESTAMP 2055 | FLAG_APME_IN_CTRL3 2056 | FLAG_HAS_SMART_POWER_DOWN 2057 | FLAG_HAS_AMT 2058 | FLAG_HAS_JUMBO_FRAMES 2059 | FLAG_HAS_CTRLEXT_ON_LOAD, 2060 .flags2 = FLAG2_DISABLE_ASPM_L0S 2061 | FLAG2_NO_DISABLE_RX, 2062 .pba = 32, 2063 .max_hw_frame_size = DEFAULT_JUMBO, 2064 .get_variants = e1000_get_variants_82571, 2065 .mac_ops = &e82571_mac_ops, 2066 .phy_ops = &e82_phy_ops_bm, 2067 .nvm_ops = &e82571_nvm_ops, 2068 }; 2069 2070