1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 static void hclge_update_fec_stats(struct hclge_dev *hdev); 75 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 76 int wait_cnt); 77 78 static struct hnae3_ae_algo ae_algo; 79 80 static struct workqueue_struct *hclge_wq; 81 82 static const struct pci_device_id ae_algo_pci_tbl[] = { 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 91 /* required last entry */ 92 {0, } 93 }; 94 95 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 96 97 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 98 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 99 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 100 HCLGE_COMM_NIC_CSQ_TAIL_REG, 101 HCLGE_COMM_NIC_CSQ_HEAD_REG, 102 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 103 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 104 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 105 HCLGE_COMM_NIC_CRQ_TAIL_REG, 106 HCLGE_COMM_NIC_CRQ_HEAD_REG, 107 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 108 HCLGE_COMM_CMDQ_INTR_STS_REG, 109 HCLGE_COMM_CMDQ_INTR_EN_REG, 110 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 111 112 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 113 HCLGE_PF_OTHER_INT_REG, 114 HCLGE_MISC_RESET_STS_REG, 115 HCLGE_MISC_VECTOR_INT_STS, 116 HCLGE_GLOBAL_RESET_REG, 117 HCLGE_FUN_RST_ING, 118 HCLGE_GRO_EN_REG}; 119 120 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 121 HCLGE_RING_RX_ADDR_H_REG, 122 HCLGE_RING_RX_BD_NUM_REG, 123 HCLGE_RING_RX_BD_LENGTH_REG, 124 HCLGE_RING_RX_MERGE_EN_REG, 125 HCLGE_RING_RX_TAIL_REG, 126 HCLGE_RING_RX_HEAD_REG, 127 HCLGE_RING_RX_FBD_NUM_REG, 128 HCLGE_RING_RX_OFFSET_REG, 129 HCLGE_RING_RX_FBD_OFFSET_REG, 130 HCLGE_RING_RX_STASH_REG, 131 HCLGE_RING_RX_BD_ERR_REG, 132 HCLGE_RING_TX_ADDR_L_REG, 133 HCLGE_RING_TX_ADDR_H_REG, 134 HCLGE_RING_TX_BD_NUM_REG, 135 HCLGE_RING_TX_PRIORITY_REG, 136 HCLGE_RING_TX_TC_REG, 137 HCLGE_RING_TX_MERGE_EN_REG, 138 HCLGE_RING_TX_TAIL_REG, 139 HCLGE_RING_TX_HEAD_REG, 140 HCLGE_RING_TX_FBD_NUM_REG, 141 HCLGE_RING_TX_OFFSET_REG, 142 HCLGE_RING_TX_EBD_NUM_REG, 143 HCLGE_RING_TX_EBD_OFFSET_REG, 144 HCLGE_RING_TX_BD_ERR_REG, 145 HCLGE_RING_EN_REG}; 146 147 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 148 HCLGE_TQP_INTR_GL0_REG, 149 HCLGE_TQP_INTR_GL1_REG, 150 HCLGE_TQP_INTR_GL2_REG, 151 HCLGE_TQP_INTR_RL_REG}; 152 153 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 154 "External Loopback test", 155 "App Loopback test", 156 "Serdes serial Loopback test", 157 "Serdes parallel Loopback test", 158 "Phy Loopback test" 159 }; 160 161 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 162 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 164 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 166 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 168 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 170 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 172 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 174 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 176 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 178 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 180 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 182 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 184 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 186 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 188 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 190 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 192 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 194 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 196 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 198 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 200 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 202 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 204 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 206 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 208 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 210 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 212 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 214 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 216 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 218 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 220 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 222 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 224 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 226 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 228 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 230 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 232 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 234 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 236 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 238 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 240 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 242 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 244 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 246 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 248 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 250 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 252 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 254 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 256 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 258 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 260 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 262 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 264 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 266 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 268 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 270 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 272 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 274 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 276 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 278 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 280 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 282 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 284 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 286 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 288 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 290 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 292 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 294 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 296 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 298 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 300 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 302 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 304 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 306 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 308 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 310 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 312 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 314 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 316 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 318 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 320 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 322 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 324 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 326 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 328 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 330 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 332 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 334 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 336 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 338 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 340 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 342 343 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 345 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 347 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 349 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 350 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 351 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 352 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 353 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 354 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 355 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 357 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 359 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 361 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 363 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 365 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 367 }; 368 369 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 370 { 371 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 372 .ethter_type = cpu_to_le16(ETH_P_LLDP), 373 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 374 .i_port_bitmap = 0x1, 375 }, 376 }; 377 378 static const u32 hclge_dfx_bd_offset_list[] = { 379 HCLGE_DFX_BIOS_BD_OFFSET, 380 HCLGE_DFX_SSU_0_BD_OFFSET, 381 HCLGE_DFX_SSU_1_BD_OFFSET, 382 HCLGE_DFX_IGU_BD_OFFSET, 383 HCLGE_DFX_RPU_0_BD_OFFSET, 384 HCLGE_DFX_RPU_1_BD_OFFSET, 385 HCLGE_DFX_NCSI_BD_OFFSET, 386 HCLGE_DFX_RTC_BD_OFFSET, 387 HCLGE_DFX_PPP_BD_OFFSET, 388 HCLGE_DFX_RCB_BD_OFFSET, 389 HCLGE_DFX_TQP_BD_OFFSET, 390 HCLGE_DFX_SSU_2_BD_OFFSET 391 }; 392 393 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 394 HCLGE_OPC_DFX_BIOS_COMMON_REG, 395 HCLGE_OPC_DFX_SSU_REG_0, 396 HCLGE_OPC_DFX_SSU_REG_1, 397 HCLGE_OPC_DFX_IGU_EGU_REG, 398 HCLGE_OPC_DFX_RPU_REG_0, 399 HCLGE_OPC_DFX_RPU_REG_1, 400 HCLGE_OPC_DFX_NCSI_REG, 401 HCLGE_OPC_DFX_RTC_REG, 402 HCLGE_OPC_DFX_PPP_REG, 403 HCLGE_OPC_DFX_RCB_REG, 404 HCLGE_OPC_DFX_TQP_REG, 405 HCLGE_OPC_DFX_SSU_REG_2 406 }; 407 408 static const struct key_info meta_data_key_info[] = { 409 { PACKET_TYPE_ID, 6 }, 410 { IP_FRAGEMENT, 1 }, 411 { ROCE_TYPE, 1 }, 412 { NEXT_KEY, 5 }, 413 { VLAN_NUMBER, 2 }, 414 { SRC_VPORT, 12 }, 415 { DST_VPORT, 12 }, 416 { TUNNEL_PACKET, 1 }, 417 }; 418 419 static const struct key_info tuple_key_info[] = { 420 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 421 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 422 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 423 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 424 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 425 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 426 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 427 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 428 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 429 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 430 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 431 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 432 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 433 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 434 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 435 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 436 { INNER_DST_MAC, 48, KEY_OPT_MAC, 437 offsetof(struct hclge_fd_rule, tuples.dst_mac), 438 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 439 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 440 offsetof(struct hclge_fd_rule, tuples.src_mac), 441 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 442 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 443 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 444 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 445 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 446 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 447 offsetof(struct hclge_fd_rule, tuples.ether_proto), 448 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 449 { INNER_L2_RSV, 16, KEY_OPT_LE16, 450 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 451 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 452 { INNER_IP_TOS, 8, KEY_OPT_U8, 453 offsetof(struct hclge_fd_rule, tuples.ip_tos), 454 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 455 { INNER_IP_PROTO, 8, KEY_OPT_U8, 456 offsetof(struct hclge_fd_rule, tuples.ip_proto), 457 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 458 { INNER_SRC_IP, 32, KEY_OPT_IP, 459 offsetof(struct hclge_fd_rule, tuples.src_ip), 460 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 461 { INNER_DST_IP, 32, KEY_OPT_IP, 462 offsetof(struct hclge_fd_rule, tuples.dst_ip), 463 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 464 { INNER_L3_RSV, 16, KEY_OPT_LE16, 465 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 466 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 467 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 468 offsetof(struct hclge_fd_rule, tuples.src_port), 469 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 470 { INNER_DST_PORT, 16, KEY_OPT_LE16, 471 offsetof(struct hclge_fd_rule, tuples.dst_port), 472 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 473 { INNER_L4_RSV, 32, KEY_OPT_LE32, 474 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 475 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 476 }; 477 478 /** 479 * hclge_cmd_send - send command to command queue 480 * @hw: pointer to the hw struct 481 * @desc: prefilled descriptor for describing the command 482 * @num : the number of descriptors to be sent 483 * 484 * This is the main send command for command queue, it 485 * sends the queue, cleans the queue, etc 486 **/ 487 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 488 { 489 return hclge_comm_cmd_send(&hw->hw, desc, num); 490 } 491 492 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 493 { 494 #define HCLGE_MAC_CMD_NUM 21 495 496 u64 *data = (u64 *)(&hdev->mac_stats); 497 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 498 __le64 *desc_data; 499 u32 data_size; 500 int ret; 501 u32 i; 502 503 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 504 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 505 if (ret) { 506 dev_err(&hdev->pdev->dev, 507 "Get MAC pkt stats fail, status = %d.\n", ret); 508 509 return ret; 510 } 511 512 /* The first desc has a 64-bit header, so data size need to minus 1 */ 513 data_size = sizeof(desc) / (sizeof(u64)) - 1; 514 515 desc_data = (__le64 *)(&desc[0].data[0]); 516 for (i = 0; i < data_size; i++) { 517 /* data memory is continuous becase only the first desc has a 518 * header in this command 519 */ 520 *data += le64_to_cpu(*desc_data); 521 data++; 522 desc_data++; 523 } 524 525 return 0; 526 } 527 528 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 529 { 530 #define HCLGE_REG_NUM_PER_DESC 4 531 532 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 533 u64 *data = (u64 *)(&hdev->mac_stats); 534 struct hclge_desc *desc; 535 __le64 *desc_data; 536 u32 data_size; 537 u32 desc_num; 538 int ret; 539 u32 i; 540 541 /* The first desc has a 64-bit header, so need to consider it */ 542 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 543 544 /* This may be called inside atomic sections, 545 * so GFP_ATOMIC is more suitalbe here 546 */ 547 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 548 if (!desc) 549 return -ENOMEM; 550 551 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 552 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 553 if (ret) { 554 kfree(desc); 555 return ret; 556 } 557 558 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 559 560 desc_data = (__le64 *)(&desc[0].data[0]); 561 for (i = 0; i < data_size; i++) { 562 /* data memory is continuous becase only the first desc has a 563 * header in this command 564 */ 565 *data += le64_to_cpu(*desc_data); 566 data++; 567 desc_data++; 568 } 569 570 kfree(desc); 571 572 return 0; 573 } 574 575 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 576 { 577 struct hclge_desc desc; 578 int ret; 579 580 /* Driver needs total register number of both valid registers and 581 * reserved registers, but the old firmware only returns number 582 * of valid registers in device V2. To be compatible with these 583 * devices, driver uses a fixed value. 584 */ 585 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 586 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 587 return 0; 588 } 589 590 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 591 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 592 if (ret) { 593 dev_err(&hdev->pdev->dev, 594 "failed to query mac statistic reg number, ret = %d\n", 595 ret); 596 return ret; 597 } 598 599 *reg_num = le32_to_cpu(desc.data[0]); 600 if (*reg_num == 0) { 601 dev_err(&hdev->pdev->dev, 602 "mac statistic reg number is invalid!\n"); 603 return -ENODATA; 604 } 605 606 return 0; 607 } 608 609 int hclge_mac_update_stats(struct hclge_dev *hdev) 610 { 611 /* The firmware supports the new statistics acquisition method */ 612 if (hdev->ae_dev->dev_specs.mac_stats_num) 613 return hclge_mac_update_stats_complete(hdev); 614 else 615 return hclge_mac_update_stats_defective(hdev); 616 } 617 618 static int hclge_comm_get_count(struct hclge_dev *hdev, 619 const struct hclge_comm_stats_str strs[], 620 u32 size) 621 { 622 int count = 0; 623 u32 i; 624 625 for (i = 0; i < size; i++) 626 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 627 count++; 628 629 return count; 630 } 631 632 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 633 const struct hclge_comm_stats_str strs[], 634 int size, u64 *data) 635 { 636 u64 *buf = data; 637 u32 i; 638 639 for (i = 0; i < size; i++) { 640 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 641 continue; 642 643 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 644 buf++; 645 } 646 647 return buf; 648 } 649 650 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 651 const struct hclge_comm_stats_str strs[], 652 int size, u8 *data) 653 { 654 char *buff = (char *)data; 655 u32 i; 656 657 if (stringset != ETH_SS_STATS) 658 return buff; 659 660 for (i = 0; i < size; i++) { 661 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 662 continue; 663 664 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 665 buff = buff + ETH_GSTRING_LEN; 666 } 667 668 return (u8 *)buff; 669 } 670 671 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 672 { 673 struct hnae3_handle *handle; 674 int status; 675 676 handle = &hdev->vport[0].nic; 677 if (handle->client) { 678 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 679 if (status) { 680 dev_err(&hdev->pdev->dev, 681 "Update TQPS stats fail, status = %d.\n", 682 status); 683 } 684 } 685 686 hclge_update_fec_stats(hdev); 687 688 status = hclge_mac_update_stats(hdev); 689 if (status) 690 dev_err(&hdev->pdev->dev, 691 "Update MAC stats fail, status = %d.\n", status); 692 } 693 694 static void hclge_update_stats(struct hnae3_handle *handle) 695 { 696 struct hclge_vport *vport = hclge_get_vport(handle); 697 struct hclge_dev *hdev = vport->back; 698 int status; 699 700 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 701 return; 702 703 status = hclge_mac_update_stats(hdev); 704 if (status) 705 dev_err(&hdev->pdev->dev, 706 "Update MAC stats fail, status = %d.\n", 707 status); 708 709 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 710 if (status) 711 dev_err(&hdev->pdev->dev, 712 "Update TQPS stats fail, status = %d.\n", 713 status); 714 715 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 716 } 717 718 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 719 { 720 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 721 HNAE3_SUPPORT_PHY_LOOPBACK | \ 722 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 723 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 724 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 725 726 struct hclge_vport *vport = hclge_get_vport(handle); 727 struct hclge_dev *hdev = vport->back; 728 int count = 0; 729 730 /* Loopback test support rules: 731 * mac: only GE mode support 732 * serdes: all mac mode will support include GE/XGE/LGE/CGE 733 * phy: only support when phy device exist on board 734 */ 735 if (stringset == ETH_SS_TEST) { 736 /* clear loopback bit flags at first */ 737 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 738 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 740 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 741 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 742 count += 1; 743 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 744 } 745 746 count += 1; 747 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 748 count += 1; 749 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 750 count += 1; 751 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 752 753 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 754 hdev->hw.mac.phydev->drv->set_loopback) || 755 hnae3_dev_phy_imp_supported(hdev)) { 756 count += 1; 757 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 758 } 759 } else if (stringset == ETH_SS_STATS) { 760 count = hclge_comm_get_count(hdev, g_mac_stats_string, 761 ARRAY_SIZE(g_mac_stats_string)) + 762 hclge_comm_tqps_get_sset_count(handle); 763 } 764 765 return count; 766 } 767 768 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 769 u8 *data) 770 { 771 struct hclge_vport *vport = hclge_get_vport(handle); 772 struct hclge_dev *hdev = vport->back; 773 u8 *p = (char *)data; 774 int size; 775 776 if (stringset == ETH_SS_STATS) { 777 size = ARRAY_SIZE(g_mac_stats_string); 778 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 779 size, p); 780 p = hclge_comm_tqps_get_strings(handle, p); 781 } else if (stringset == ETH_SS_TEST) { 782 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 783 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 784 ETH_GSTRING_LEN); 785 p += ETH_GSTRING_LEN; 786 } 787 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 788 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 789 ETH_GSTRING_LEN); 790 p += ETH_GSTRING_LEN; 791 } 792 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 793 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 794 ETH_GSTRING_LEN); 795 p += ETH_GSTRING_LEN; 796 } 797 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 798 memcpy(p, 799 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 800 ETH_GSTRING_LEN); 801 p += ETH_GSTRING_LEN; 802 } 803 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 804 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 805 ETH_GSTRING_LEN); 806 p += ETH_GSTRING_LEN; 807 } 808 } 809 } 810 811 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 812 { 813 struct hclge_vport *vport = hclge_get_vport(handle); 814 struct hclge_dev *hdev = vport->back; 815 u64 *p; 816 817 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 818 ARRAY_SIZE(g_mac_stats_string), data); 819 p = hclge_comm_tqps_get_stats(handle, p); 820 } 821 822 static void hclge_get_mac_stat(struct hnae3_handle *handle, 823 struct hns3_mac_stats *mac_stats) 824 { 825 struct hclge_vport *vport = hclge_get_vport(handle); 826 struct hclge_dev *hdev = vport->back; 827 828 hclge_update_stats(handle); 829 830 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 831 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 832 } 833 834 static int hclge_parse_func_status(struct hclge_dev *hdev, 835 struct hclge_func_status_cmd *status) 836 { 837 #define HCLGE_MAC_ID_MASK 0xF 838 839 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 840 return -EINVAL; 841 842 /* Set the pf to main pf */ 843 if (status->pf_state & HCLGE_PF_STATE_MAIN) 844 hdev->flag |= HCLGE_FLAG_MAIN; 845 else 846 hdev->flag &= ~HCLGE_FLAG_MAIN; 847 848 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 849 return 0; 850 } 851 852 static int hclge_query_function_status(struct hclge_dev *hdev) 853 { 854 #define HCLGE_QUERY_MAX_CNT 5 855 856 struct hclge_func_status_cmd *req; 857 struct hclge_desc desc; 858 int timeout = 0; 859 int ret; 860 861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 862 req = (struct hclge_func_status_cmd *)desc.data; 863 864 do { 865 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 866 if (ret) { 867 dev_err(&hdev->pdev->dev, 868 "query function status failed %d.\n", ret); 869 return ret; 870 } 871 872 /* Check pf reset is done */ 873 if (req->pf_state) 874 break; 875 usleep_range(1000, 2000); 876 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 877 878 return hclge_parse_func_status(hdev, req); 879 } 880 881 static int hclge_query_pf_resource(struct hclge_dev *hdev) 882 { 883 struct hclge_pf_res_cmd *req; 884 struct hclge_desc desc; 885 int ret; 886 887 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 888 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 889 if (ret) { 890 dev_err(&hdev->pdev->dev, 891 "query pf resource failed %d.\n", ret); 892 return ret; 893 } 894 895 req = (struct hclge_pf_res_cmd *)desc.data; 896 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 897 le16_to_cpu(req->ext_tqp_num); 898 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 899 900 if (req->tx_buf_size) 901 hdev->tx_buf_size = 902 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 903 else 904 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 905 906 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 907 908 if (req->dv_buf_size) 909 hdev->dv_buf_size = 910 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 911 else 912 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 913 914 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 915 916 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 917 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 918 dev_err(&hdev->pdev->dev, 919 "only %u msi resources available, not enough for pf(min:2).\n", 920 hdev->num_nic_msi); 921 return -EINVAL; 922 } 923 924 if (hnae3_dev_roce_supported(hdev)) { 925 hdev->num_roce_msi = 926 le16_to_cpu(req->pf_intr_vector_number_roce); 927 928 /* PF should have NIC vectors and Roce vectors, 929 * NIC vectors are queued before Roce vectors. 930 */ 931 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 932 } else { 933 hdev->num_msi = hdev->num_nic_msi; 934 } 935 936 return 0; 937 } 938 939 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 940 { 941 switch (speed_cmd) { 942 case HCLGE_FW_MAC_SPEED_10M: 943 *speed = HCLGE_MAC_SPEED_10M; 944 break; 945 case HCLGE_FW_MAC_SPEED_100M: 946 *speed = HCLGE_MAC_SPEED_100M; 947 break; 948 case HCLGE_FW_MAC_SPEED_1G: 949 *speed = HCLGE_MAC_SPEED_1G; 950 break; 951 case HCLGE_FW_MAC_SPEED_10G: 952 *speed = HCLGE_MAC_SPEED_10G; 953 break; 954 case HCLGE_FW_MAC_SPEED_25G: 955 *speed = HCLGE_MAC_SPEED_25G; 956 break; 957 case HCLGE_FW_MAC_SPEED_40G: 958 *speed = HCLGE_MAC_SPEED_40G; 959 break; 960 case HCLGE_FW_MAC_SPEED_50G: 961 *speed = HCLGE_MAC_SPEED_50G; 962 break; 963 case HCLGE_FW_MAC_SPEED_100G: 964 *speed = HCLGE_MAC_SPEED_100G; 965 break; 966 case HCLGE_FW_MAC_SPEED_200G: 967 *speed = HCLGE_MAC_SPEED_200G; 968 break; 969 default: 970 return -EINVAL; 971 } 972 973 return 0; 974 } 975 976 static const struct hclge_speed_bit_map speed_bit_map[] = { 977 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 978 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 979 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 980 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 981 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 982 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 983 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 984 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 985 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 986 }; 987 988 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 989 { 990 u16 i; 991 992 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 993 if (speed == speed_bit_map[i].speed) { 994 *speed_bit = speed_bit_map[i].speed_bit; 995 return 0; 996 } 997 } 998 999 return -EINVAL; 1000 } 1001 1002 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 1003 { 1004 struct hclge_vport *vport = hclge_get_vport(handle); 1005 struct hclge_dev *hdev = vport->back; 1006 u32 speed_ability = hdev->hw.mac.speed_ability; 1007 u32 speed_bit = 0; 1008 int ret; 1009 1010 ret = hclge_get_speed_bit(speed, &speed_bit); 1011 if (ret) 1012 return ret; 1013 1014 if (speed_bit & speed_ability) 1015 return 0; 1016 1017 return -EINVAL; 1018 } 1019 1020 static void hclge_update_fec_support(struct hclge_mac *mac) 1021 { 1022 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1023 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1024 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 1025 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1026 1027 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 1028 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1029 mac->supported); 1030 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 1031 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1032 mac->supported); 1033 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 1034 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1035 mac->supported); 1036 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 1037 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1038 mac->supported); 1039 } 1040 1041 static void hclge_convert_setting_sr(u16 speed_ability, 1042 unsigned long *link_mode) 1043 { 1044 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1045 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1046 link_mode); 1047 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1048 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1049 link_mode); 1050 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1051 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1052 link_mode); 1053 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1054 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1055 link_mode); 1056 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1057 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1058 link_mode); 1059 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1060 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1061 link_mode); 1062 } 1063 1064 static void hclge_convert_setting_lr(u16 speed_ability, 1065 unsigned long *link_mode) 1066 { 1067 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1068 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1069 link_mode); 1070 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1071 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1072 link_mode); 1073 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1074 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1075 link_mode); 1076 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1077 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1078 link_mode); 1079 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1080 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1081 link_mode); 1082 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1083 linkmode_set_bit( 1084 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1085 link_mode); 1086 } 1087 1088 static void hclge_convert_setting_cr(u16 speed_ability, 1089 unsigned long *link_mode) 1090 { 1091 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1093 link_mode); 1094 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1095 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1096 link_mode); 1097 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1099 link_mode); 1100 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1101 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1102 link_mode); 1103 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1104 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1105 link_mode); 1106 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1108 link_mode); 1109 } 1110 1111 static void hclge_convert_setting_kr(u16 speed_ability, 1112 unsigned long *link_mode) 1113 { 1114 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1115 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1116 link_mode); 1117 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1118 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1119 link_mode); 1120 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1121 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1122 link_mode); 1123 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1124 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1125 link_mode); 1126 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1127 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1128 link_mode); 1129 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1130 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1131 link_mode); 1132 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1134 link_mode); 1135 } 1136 1137 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1138 { 1139 /* If firmware has reported fec_ability, don't need to convert by speed */ 1140 if (mac->fec_ability) 1141 goto out; 1142 1143 switch (mac->speed) { 1144 case HCLGE_MAC_SPEED_10G: 1145 case HCLGE_MAC_SPEED_40G: 1146 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1147 BIT(HNAE3_FEC_NONE); 1148 break; 1149 case HCLGE_MAC_SPEED_25G: 1150 case HCLGE_MAC_SPEED_50G: 1151 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1152 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1153 break; 1154 case HCLGE_MAC_SPEED_100G: 1155 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1156 BIT(HNAE3_FEC_NONE); 1157 break; 1158 case HCLGE_MAC_SPEED_200G: 1159 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1160 BIT(HNAE3_FEC_LLRS); 1161 break; 1162 default: 1163 mac->fec_ability = 0; 1164 break; 1165 } 1166 1167 out: 1168 hclge_update_fec_support(mac); 1169 } 1170 1171 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1172 u16 speed_ability) 1173 { 1174 struct hclge_mac *mac = &hdev->hw.mac; 1175 1176 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1177 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1178 mac->supported); 1179 1180 hclge_convert_setting_sr(speed_ability, mac->supported); 1181 hclge_convert_setting_lr(speed_ability, mac->supported); 1182 hclge_convert_setting_cr(speed_ability, mac->supported); 1183 if (hnae3_dev_fec_supported(hdev)) 1184 hclge_convert_setting_fec(mac); 1185 1186 if (hnae3_dev_pause_supported(hdev)) 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1188 1189 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1190 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1191 } 1192 1193 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1194 u16 speed_ability) 1195 { 1196 struct hclge_mac *mac = &hdev->hw.mac; 1197 1198 hclge_convert_setting_kr(speed_ability, mac->supported); 1199 if (hnae3_dev_fec_supported(hdev)) 1200 hclge_convert_setting_fec(mac); 1201 1202 if (hnae3_dev_pause_supported(hdev)) 1203 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1204 1205 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1206 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1207 } 1208 1209 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1210 u16 speed_ability) 1211 { 1212 unsigned long *supported = hdev->hw.mac.supported; 1213 1214 /* default to support all speed for GE port */ 1215 if (!speed_ability) 1216 speed_ability = HCLGE_SUPPORT_GE; 1217 1218 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1219 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1220 supported); 1221 1222 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1223 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1224 supported); 1225 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1226 supported); 1227 } 1228 1229 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1230 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1231 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1232 } 1233 1234 if (hnae3_dev_pause_supported(hdev)) { 1235 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1236 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1237 } 1238 1239 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1240 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1241 } 1242 1243 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1244 { 1245 u8 media_type = hdev->hw.mac.media_type; 1246 1247 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1248 hclge_parse_fiber_link_mode(hdev, speed_ability); 1249 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1250 hclge_parse_copper_link_mode(hdev, speed_ability); 1251 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1252 hclge_parse_backplane_link_mode(hdev, speed_ability); 1253 } 1254 1255 static u32 hclge_get_max_speed(u16 speed_ability) 1256 { 1257 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1258 return HCLGE_MAC_SPEED_200G; 1259 1260 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1261 return HCLGE_MAC_SPEED_100G; 1262 1263 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1264 return HCLGE_MAC_SPEED_50G; 1265 1266 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1267 return HCLGE_MAC_SPEED_40G; 1268 1269 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1270 return HCLGE_MAC_SPEED_25G; 1271 1272 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1273 return HCLGE_MAC_SPEED_10G; 1274 1275 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1276 return HCLGE_MAC_SPEED_1G; 1277 1278 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1279 return HCLGE_MAC_SPEED_100M; 1280 1281 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1282 return HCLGE_MAC_SPEED_10M; 1283 1284 return HCLGE_MAC_SPEED_1G; 1285 } 1286 1287 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1288 { 1289 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1290 #define SPEED_ABILITY_EXT_SHIFT 8 1291 1292 struct hclge_cfg_param_cmd *req; 1293 u64 mac_addr_tmp_high; 1294 u16 speed_ability_ext; 1295 u64 mac_addr_tmp; 1296 unsigned int i; 1297 1298 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1299 1300 /* get the configuration */ 1301 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1302 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1303 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1304 HCLGE_CFG_TQP_DESC_N_M, 1305 HCLGE_CFG_TQP_DESC_N_S); 1306 1307 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1308 HCLGE_CFG_PHY_ADDR_M, 1309 HCLGE_CFG_PHY_ADDR_S); 1310 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1311 HCLGE_CFG_MEDIA_TP_M, 1312 HCLGE_CFG_MEDIA_TP_S); 1313 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1314 HCLGE_CFG_RX_BUF_LEN_M, 1315 HCLGE_CFG_RX_BUF_LEN_S); 1316 /* get mac_address */ 1317 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1318 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1319 HCLGE_CFG_MAC_ADDR_H_M, 1320 HCLGE_CFG_MAC_ADDR_H_S); 1321 1322 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1323 1324 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1325 HCLGE_CFG_DEFAULT_SPEED_M, 1326 HCLGE_CFG_DEFAULT_SPEED_S); 1327 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1328 HCLGE_CFG_RSS_SIZE_M, 1329 HCLGE_CFG_RSS_SIZE_S); 1330 1331 for (i = 0; i < ETH_ALEN; i++) 1332 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1333 1334 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1335 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1336 1337 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1338 HCLGE_CFG_SPEED_ABILITY_M, 1339 HCLGE_CFG_SPEED_ABILITY_S); 1340 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1341 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1342 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1343 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1344 1345 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1346 HCLGE_CFG_VLAN_FLTR_CAP_M, 1347 HCLGE_CFG_VLAN_FLTR_CAP_S); 1348 1349 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1350 HCLGE_CFG_UMV_TBL_SPACE_M, 1351 HCLGE_CFG_UMV_TBL_SPACE_S); 1352 1353 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1354 HCLGE_CFG_PF_RSS_SIZE_M, 1355 HCLGE_CFG_PF_RSS_SIZE_S); 1356 1357 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1358 * power of 2, instead of reading out directly. This would 1359 * be more flexible for future changes and expansions. 1360 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1361 * it does not make sense if PF's field is 0. In this case, PF and VF 1362 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1363 */ 1364 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1365 1U << cfg->pf_rss_size_max : 1366 cfg->vf_rss_size_max; 1367 1368 /* The unit of the tx spare buffer size queried from configuration 1369 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1370 * needed here. 1371 */ 1372 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1373 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1374 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1375 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1376 } 1377 1378 /* hclge_get_cfg: query the static parameter from flash 1379 * @hdev: pointer to struct hclge_dev 1380 * @hcfg: the config structure to be getted 1381 */ 1382 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1383 { 1384 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1385 struct hclge_cfg_param_cmd *req; 1386 unsigned int i; 1387 int ret; 1388 1389 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1390 u32 offset = 0; 1391 1392 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1393 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1394 true); 1395 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1396 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1397 /* Len should be united by 4 bytes when send to hardware */ 1398 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1399 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1400 req->offset = cpu_to_le32(offset); 1401 } 1402 1403 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1404 if (ret) { 1405 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1406 return ret; 1407 } 1408 1409 hclge_parse_cfg(hcfg, desc); 1410 1411 return 0; 1412 } 1413 1414 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1415 { 1416 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1417 1418 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1419 1420 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1421 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1422 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1423 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1424 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1425 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1426 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1427 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1428 } 1429 1430 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1431 struct hclge_desc *desc) 1432 { 1433 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1434 struct hclge_dev_specs_0_cmd *req0; 1435 struct hclge_dev_specs_1_cmd *req1; 1436 1437 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1438 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1439 1440 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1441 ae_dev->dev_specs.rss_ind_tbl_size = 1442 le16_to_cpu(req0->rss_ind_tbl_size); 1443 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1444 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1445 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1446 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1447 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1448 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1449 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1450 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1451 } 1452 1453 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1454 { 1455 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1456 1457 if (!dev_specs->max_non_tso_bd_num) 1458 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1459 if (!dev_specs->rss_ind_tbl_size) 1460 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1461 if (!dev_specs->rss_key_size) 1462 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1463 if (!dev_specs->max_tm_rate) 1464 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1465 if (!dev_specs->max_qset_num) 1466 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1467 if (!dev_specs->max_int_gl) 1468 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1469 if (!dev_specs->max_frm_size) 1470 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1471 if (!dev_specs->umv_size) 1472 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1473 } 1474 1475 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1476 { 1477 u32 reg_num = 0; 1478 int ret; 1479 1480 ret = hclge_mac_query_reg_num(hdev, ®_num); 1481 if (ret && ret != -EOPNOTSUPP) 1482 return ret; 1483 1484 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1485 return 0; 1486 } 1487 1488 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1489 { 1490 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1491 int ret; 1492 int i; 1493 1494 ret = hclge_query_mac_stats_num(hdev); 1495 if (ret) 1496 return ret; 1497 1498 /* set default specifications as devices lower than version V3 do not 1499 * support querying specifications from firmware. 1500 */ 1501 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1502 hclge_set_default_dev_specs(hdev); 1503 return 0; 1504 } 1505 1506 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1507 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1508 true); 1509 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1510 } 1511 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1512 1513 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1514 if (ret) 1515 return ret; 1516 1517 hclge_parse_dev_specs(hdev, desc); 1518 hclge_check_dev_specs(hdev); 1519 1520 return 0; 1521 } 1522 1523 static int hclge_get_cap(struct hclge_dev *hdev) 1524 { 1525 int ret; 1526 1527 ret = hclge_query_function_status(hdev); 1528 if (ret) { 1529 dev_err(&hdev->pdev->dev, 1530 "query function status error %d.\n", ret); 1531 return ret; 1532 } 1533 1534 /* get pf resource */ 1535 return hclge_query_pf_resource(hdev); 1536 } 1537 1538 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1539 { 1540 #define HCLGE_MIN_TX_DESC 64 1541 #define HCLGE_MIN_RX_DESC 64 1542 1543 if (!is_kdump_kernel()) 1544 return; 1545 1546 dev_info(&hdev->pdev->dev, 1547 "Running kdump kernel. Using minimal resources\n"); 1548 1549 /* minimal queue pairs equals to the number of vports */ 1550 hdev->num_tqps = hdev->num_req_vfs + 1; 1551 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1552 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1553 } 1554 1555 static void hclge_init_tc_config(struct hclge_dev *hdev) 1556 { 1557 unsigned int i; 1558 1559 if (hdev->tc_max > HNAE3_MAX_TC || 1560 hdev->tc_max < 1) { 1561 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1562 hdev->tc_max); 1563 hdev->tc_max = 1; 1564 } 1565 1566 /* Dev does not support DCB */ 1567 if (!hnae3_dev_dcb_supported(hdev)) { 1568 hdev->tc_max = 1; 1569 hdev->pfc_max = 0; 1570 } else { 1571 hdev->pfc_max = hdev->tc_max; 1572 } 1573 1574 hdev->tm_info.num_tc = 1; 1575 1576 /* Currently not support uncontiuous tc */ 1577 for (i = 0; i < hdev->tm_info.num_tc; i++) 1578 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1579 1580 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1581 } 1582 1583 static int hclge_configure(struct hclge_dev *hdev) 1584 { 1585 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1586 struct hclge_cfg cfg; 1587 int ret; 1588 1589 ret = hclge_get_cfg(hdev, &cfg); 1590 if (ret) 1591 return ret; 1592 1593 hdev->base_tqp_pid = 0; 1594 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1595 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1596 hdev->rx_buf_len = cfg.rx_buf_len; 1597 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1598 hdev->hw.mac.media_type = cfg.media_type; 1599 hdev->hw.mac.phy_addr = cfg.phy_addr; 1600 hdev->num_tx_desc = cfg.tqp_desc_num; 1601 hdev->num_rx_desc = cfg.tqp_desc_num; 1602 hdev->tm_info.num_pg = 1; 1603 hdev->tc_max = cfg.tc_num; 1604 hdev->tm_info.hw_pfc_map = 0; 1605 if (cfg.umv_space) 1606 hdev->wanted_umv_size = cfg.umv_space; 1607 else 1608 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1609 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1610 hdev->gro_en = true; 1611 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1612 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1613 1614 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1615 hdev->fd_en = true; 1616 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1617 } 1618 1619 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1620 if (ret) { 1621 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1622 cfg.default_speed, ret); 1623 return ret; 1624 } 1625 1626 hclge_parse_link_mode(hdev, cfg.speed_ability); 1627 1628 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1629 1630 hclge_init_tc_config(hdev); 1631 hclge_init_kdump_kernel_config(hdev); 1632 1633 return ret; 1634 } 1635 1636 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1637 u16 tso_mss_max) 1638 { 1639 struct hclge_cfg_tso_status_cmd *req; 1640 struct hclge_desc desc; 1641 1642 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1643 1644 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1645 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1646 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1647 1648 return hclge_cmd_send(&hdev->hw, &desc, 1); 1649 } 1650 1651 static int hclge_config_gro(struct hclge_dev *hdev) 1652 { 1653 struct hclge_cfg_gro_status_cmd *req; 1654 struct hclge_desc desc; 1655 int ret; 1656 1657 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1658 return 0; 1659 1660 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1661 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1662 1663 req->gro_en = hdev->gro_en ? 1 : 0; 1664 1665 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1666 if (ret) 1667 dev_err(&hdev->pdev->dev, 1668 "GRO hardware config cmd failed, ret = %d\n", ret); 1669 1670 return ret; 1671 } 1672 1673 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1674 { 1675 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1676 struct hclge_comm_tqp *tqp; 1677 int i; 1678 1679 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1680 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1681 if (!hdev->htqp) 1682 return -ENOMEM; 1683 1684 tqp = hdev->htqp; 1685 1686 for (i = 0; i < hdev->num_tqps; i++) { 1687 tqp->dev = &hdev->pdev->dev; 1688 tqp->index = i; 1689 1690 tqp->q.ae_algo = &ae_algo; 1691 tqp->q.buf_size = hdev->rx_buf_len; 1692 tqp->q.tx_desc_num = hdev->num_tx_desc; 1693 tqp->q.rx_desc_num = hdev->num_rx_desc; 1694 1695 /* need an extended offset to configure queues >= 1696 * HCLGE_TQP_MAX_SIZE_DEV_V2 1697 */ 1698 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1699 tqp->q.io_base = hdev->hw.hw.io_base + 1700 HCLGE_TQP_REG_OFFSET + 1701 i * HCLGE_TQP_REG_SIZE; 1702 else 1703 tqp->q.io_base = hdev->hw.hw.io_base + 1704 HCLGE_TQP_REG_OFFSET + 1705 HCLGE_TQP_EXT_REG_OFFSET + 1706 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1707 HCLGE_TQP_REG_SIZE; 1708 1709 /* when device supports tx push and has device memory, 1710 * the queue can execute push mode or doorbell mode on 1711 * device memory. 1712 */ 1713 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1714 tqp->q.mem_base = hdev->hw.hw.mem_base + 1715 HCLGE_TQP_MEM_OFFSET(hdev, i); 1716 1717 tqp++; 1718 } 1719 1720 return 0; 1721 } 1722 1723 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1724 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1725 { 1726 struct hclge_tqp_map_cmd *req; 1727 struct hclge_desc desc; 1728 int ret; 1729 1730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1731 1732 req = (struct hclge_tqp_map_cmd *)desc.data; 1733 req->tqp_id = cpu_to_le16(tqp_pid); 1734 req->tqp_vf = func_id; 1735 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1736 if (!is_pf) 1737 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1738 req->tqp_vid = cpu_to_le16(tqp_vid); 1739 1740 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1741 if (ret) 1742 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1743 1744 return ret; 1745 } 1746 1747 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1748 { 1749 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1750 struct hclge_dev *hdev = vport->back; 1751 int i, alloced; 1752 1753 for (i = 0, alloced = 0; i < hdev->num_tqps && 1754 alloced < num_tqps; i++) { 1755 if (!hdev->htqp[i].alloced) { 1756 hdev->htqp[i].q.handle = &vport->nic; 1757 hdev->htqp[i].q.tqp_index = alloced; 1758 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1759 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1760 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1761 hdev->htqp[i].alloced = true; 1762 alloced++; 1763 } 1764 } 1765 vport->alloc_tqps = alloced; 1766 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1767 vport->alloc_tqps / hdev->tm_info.num_tc); 1768 1769 /* ensure one to one mapping between irq and queue at default */ 1770 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1771 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1772 1773 return 0; 1774 } 1775 1776 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1777 u16 num_tx_desc, u16 num_rx_desc) 1778 1779 { 1780 struct hnae3_handle *nic = &vport->nic; 1781 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1782 struct hclge_dev *hdev = vport->back; 1783 int ret; 1784 1785 kinfo->num_tx_desc = num_tx_desc; 1786 kinfo->num_rx_desc = num_rx_desc; 1787 1788 kinfo->rx_buf_len = hdev->rx_buf_len; 1789 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1790 1791 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1792 sizeof(struct hnae3_queue *), GFP_KERNEL); 1793 if (!kinfo->tqp) 1794 return -ENOMEM; 1795 1796 ret = hclge_assign_tqp(vport, num_tqps); 1797 if (ret) 1798 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1799 1800 return ret; 1801 } 1802 1803 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1804 struct hclge_vport *vport) 1805 { 1806 struct hnae3_handle *nic = &vport->nic; 1807 struct hnae3_knic_private_info *kinfo; 1808 u16 i; 1809 1810 kinfo = &nic->kinfo; 1811 for (i = 0; i < vport->alloc_tqps; i++) { 1812 struct hclge_comm_tqp *q = 1813 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1814 bool is_pf; 1815 int ret; 1816 1817 is_pf = !(vport->vport_id); 1818 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1819 i, is_pf); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static int hclge_map_tqp(struct hclge_dev *hdev) 1828 { 1829 struct hclge_vport *vport = hdev->vport; 1830 u16 i, num_vport; 1831 1832 num_vport = hdev->num_req_vfs + 1; 1833 for (i = 0; i < num_vport; i++) { 1834 int ret; 1835 1836 ret = hclge_map_tqp_to_vport(hdev, vport); 1837 if (ret) 1838 return ret; 1839 1840 vport++; 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1847 { 1848 struct hnae3_handle *nic = &vport->nic; 1849 struct hclge_dev *hdev = vport->back; 1850 int ret; 1851 1852 nic->pdev = hdev->pdev; 1853 nic->ae_algo = &ae_algo; 1854 nic->numa_node_mask = hdev->numa_node_mask; 1855 nic->kinfo.io_base = hdev->hw.hw.io_base; 1856 1857 ret = hclge_knic_setup(vport, num_tqps, 1858 hdev->num_tx_desc, hdev->num_rx_desc); 1859 if (ret) 1860 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1861 1862 return ret; 1863 } 1864 1865 static int hclge_alloc_vport(struct hclge_dev *hdev) 1866 { 1867 struct pci_dev *pdev = hdev->pdev; 1868 struct hclge_vport *vport; 1869 u32 tqp_main_vport; 1870 u32 tqp_per_vport; 1871 int num_vport, i; 1872 int ret; 1873 1874 /* We need to alloc a vport for main NIC of PF */ 1875 num_vport = hdev->num_req_vfs + 1; 1876 1877 if (hdev->num_tqps < num_vport) { 1878 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1879 hdev->num_tqps, num_vport); 1880 return -EINVAL; 1881 } 1882 1883 /* Alloc the same number of TQPs for every vport */ 1884 tqp_per_vport = hdev->num_tqps / num_vport; 1885 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1886 1887 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1888 GFP_KERNEL); 1889 if (!vport) 1890 return -ENOMEM; 1891 1892 hdev->vport = vport; 1893 hdev->num_alloc_vport = num_vport; 1894 1895 if (IS_ENABLED(CONFIG_PCI_IOV)) 1896 hdev->num_alloc_vfs = hdev->num_req_vfs; 1897 1898 for (i = 0; i < num_vport; i++) { 1899 vport->back = hdev; 1900 vport->vport_id = i; 1901 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1902 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1903 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1904 vport->port_base_vlan_cfg.tbl_sta = true; 1905 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1906 vport->req_vlan_fltr_en = true; 1907 INIT_LIST_HEAD(&vport->vlan_list); 1908 INIT_LIST_HEAD(&vport->uc_mac_list); 1909 INIT_LIST_HEAD(&vport->mc_mac_list); 1910 spin_lock_init(&vport->mac_list_lock); 1911 1912 if (i == 0) 1913 ret = hclge_vport_setup(vport, tqp_main_vport); 1914 else 1915 ret = hclge_vport_setup(vport, tqp_per_vport); 1916 if (ret) { 1917 dev_err(&pdev->dev, 1918 "vport setup failed for vport %d, %d\n", 1919 i, ret); 1920 return ret; 1921 } 1922 1923 vport++; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1930 struct hclge_pkt_buf_alloc *buf_alloc) 1931 { 1932 /* TX buffer size is unit by 128 byte */ 1933 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1934 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1935 struct hclge_tx_buff_alloc_cmd *req; 1936 struct hclge_desc desc; 1937 int ret; 1938 u8 i; 1939 1940 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1941 1942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1943 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1944 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1945 1946 req->tx_pkt_buff[i] = 1947 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1948 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1949 } 1950 1951 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1952 if (ret) 1953 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1954 ret); 1955 1956 return ret; 1957 } 1958 1959 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1960 struct hclge_pkt_buf_alloc *buf_alloc) 1961 { 1962 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1963 1964 if (ret) 1965 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1966 1967 return ret; 1968 } 1969 1970 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1971 { 1972 unsigned int i; 1973 u32 cnt = 0; 1974 1975 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1976 if (hdev->hw_tc_map & BIT(i)) 1977 cnt++; 1978 return cnt; 1979 } 1980 1981 /* Get the number of pfc enabled TCs, which have private buffer */ 1982 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1983 struct hclge_pkt_buf_alloc *buf_alloc) 1984 { 1985 struct hclge_priv_buf *priv; 1986 unsigned int i; 1987 int cnt = 0; 1988 1989 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1990 priv = &buf_alloc->priv_buf[i]; 1991 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1992 priv->enable) 1993 cnt++; 1994 } 1995 1996 return cnt; 1997 } 1998 1999 /* Get the number of pfc disabled TCs, which have private buffer */ 2000 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 2001 struct hclge_pkt_buf_alloc *buf_alloc) 2002 { 2003 struct hclge_priv_buf *priv; 2004 unsigned int i; 2005 int cnt = 0; 2006 2007 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2008 priv = &buf_alloc->priv_buf[i]; 2009 if (hdev->hw_tc_map & BIT(i) && 2010 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 2011 priv->enable) 2012 cnt++; 2013 } 2014 2015 return cnt; 2016 } 2017 2018 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2019 { 2020 struct hclge_priv_buf *priv; 2021 u32 rx_priv = 0; 2022 int i; 2023 2024 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2025 priv = &buf_alloc->priv_buf[i]; 2026 if (priv->enable) 2027 rx_priv += priv->buf_size; 2028 } 2029 return rx_priv; 2030 } 2031 2032 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2033 { 2034 u32 i, total_tx_size = 0; 2035 2036 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2037 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2038 2039 return total_tx_size; 2040 } 2041 2042 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2043 struct hclge_pkt_buf_alloc *buf_alloc, 2044 u32 rx_all) 2045 { 2046 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2047 u32 tc_num = hclge_get_tc_num(hdev); 2048 u32 shared_buf, aligned_mps; 2049 u32 rx_priv; 2050 int i; 2051 2052 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2053 2054 if (hnae3_dev_dcb_supported(hdev)) 2055 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2056 hdev->dv_buf_size; 2057 else 2058 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2059 + hdev->dv_buf_size; 2060 2061 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2062 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2063 HCLGE_BUF_SIZE_UNIT); 2064 2065 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2066 if (rx_all < rx_priv + shared_std) 2067 return false; 2068 2069 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2070 buf_alloc->s_buf.buf_size = shared_buf; 2071 if (hnae3_dev_dcb_supported(hdev)) { 2072 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2073 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2074 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2075 HCLGE_BUF_SIZE_UNIT); 2076 } else { 2077 buf_alloc->s_buf.self.high = aligned_mps + 2078 HCLGE_NON_DCB_ADDITIONAL_BUF; 2079 buf_alloc->s_buf.self.low = aligned_mps; 2080 } 2081 2082 if (hnae3_dev_dcb_supported(hdev)) { 2083 hi_thrd = shared_buf - hdev->dv_buf_size; 2084 2085 if (tc_num <= NEED_RESERVE_TC_NUM) 2086 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2087 / BUF_MAX_PERCENT; 2088 2089 if (tc_num) 2090 hi_thrd = hi_thrd / tc_num; 2091 2092 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2093 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2094 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2095 } else { 2096 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2097 lo_thrd = aligned_mps; 2098 } 2099 2100 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2101 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2102 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2103 } 2104 2105 return true; 2106 } 2107 2108 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2109 struct hclge_pkt_buf_alloc *buf_alloc) 2110 { 2111 u32 i, total_size; 2112 2113 total_size = hdev->pkt_buf_size; 2114 2115 /* alloc tx buffer for all enabled tc */ 2116 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2117 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2118 2119 if (hdev->hw_tc_map & BIT(i)) { 2120 if (total_size < hdev->tx_buf_size) 2121 return -ENOMEM; 2122 2123 priv->tx_buf_size = hdev->tx_buf_size; 2124 } else { 2125 priv->tx_buf_size = 0; 2126 } 2127 2128 total_size -= priv->tx_buf_size; 2129 } 2130 2131 return 0; 2132 } 2133 2134 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2135 struct hclge_pkt_buf_alloc *buf_alloc) 2136 { 2137 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2138 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2139 unsigned int i; 2140 2141 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2142 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2143 2144 priv->enable = 0; 2145 priv->wl.low = 0; 2146 priv->wl.high = 0; 2147 priv->buf_size = 0; 2148 2149 if (!(hdev->hw_tc_map & BIT(i))) 2150 continue; 2151 2152 priv->enable = 1; 2153 2154 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2155 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2156 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2157 HCLGE_BUF_SIZE_UNIT); 2158 } else { 2159 priv->wl.low = 0; 2160 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2161 aligned_mps; 2162 } 2163 2164 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2165 } 2166 2167 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2168 } 2169 2170 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2171 struct hclge_pkt_buf_alloc *buf_alloc) 2172 { 2173 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2174 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2175 int i; 2176 2177 /* let the last to be cleared first */ 2178 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2179 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2180 unsigned int mask = BIT((unsigned int)i); 2181 2182 if (hdev->hw_tc_map & mask && 2183 !(hdev->tm_info.hw_pfc_map & mask)) { 2184 /* Clear the no pfc TC private buffer */ 2185 priv->wl.low = 0; 2186 priv->wl.high = 0; 2187 priv->buf_size = 0; 2188 priv->enable = 0; 2189 no_pfc_priv_num--; 2190 } 2191 2192 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2193 no_pfc_priv_num == 0) 2194 break; 2195 } 2196 2197 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2198 } 2199 2200 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2201 struct hclge_pkt_buf_alloc *buf_alloc) 2202 { 2203 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2204 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2205 int i; 2206 2207 /* let the last to be cleared first */ 2208 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2209 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2210 unsigned int mask = BIT((unsigned int)i); 2211 2212 if (hdev->hw_tc_map & mask && 2213 hdev->tm_info.hw_pfc_map & mask) { 2214 /* Reduce the number of pfc TC with private buffer */ 2215 priv->wl.low = 0; 2216 priv->enable = 0; 2217 priv->wl.high = 0; 2218 priv->buf_size = 0; 2219 pfc_priv_num--; 2220 } 2221 2222 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2223 pfc_priv_num == 0) 2224 break; 2225 } 2226 2227 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2228 } 2229 2230 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2231 struct hclge_pkt_buf_alloc *buf_alloc) 2232 { 2233 #define COMPENSATE_BUFFER 0x3C00 2234 #define COMPENSATE_HALF_MPS_NUM 5 2235 #define PRIV_WL_GAP 0x1800 2236 2237 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2238 u32 tc_num = hclge_get_tc_num(hdev); 2239 u32 half_mps = hdev->mps >> 1; 2240 u32 min_rx_priv; 2241 unsigned int i; 2242 2243 if (tc_num) 2244 rx_priv = rx_priv / tc_num; 2245 2246 if (tc_num <= NEED_RESERVE_TC_NUM) 2247 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2248 2249 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2250 COMPENSATE_HALF_MPS_NUM * half_mps; 2251 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2252 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2253 if (rx_priv < min_rx_priv) 2254 return false; 2255 2256 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2257 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2258 2259 priv->enable = 0; 2260 priv->wl.low = 0; 2261 priv->wl.high = 0; 2262 priv->buf_size = 0; 2263 2264 if (!(hdev->hw_tc_map & BIT(i))) 2265 continue; 2266 2267 priv->enable = 1; 2268 priv->buf_size = rx_priv; 2269 priv->wl.high = rx_priv - hdev->dv_buf_size; 2270 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2271 } 2272 2273 buf_alloc->s_buf.buf_size = 0; 2274 2275 return true; 2276 } 2277 2278 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2279 * @hdev: pointer to struct hclge_dev 2280 * @buf_alloc: pointer to buffer calculation data 2281 * @return: 0: calculate successful, negative: fail 2282 */ 2283 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2284 struct hclge_pkt_buf_alloc *buf_alloc) 2285 { 2286 /* When DCB is not supported, rx private buffer is not allocated. */ 2287 if (!hnae3_dev_dcb_supported(hdev)) { 2288 u32 rx_all = hdev->pkt_buf_size; 2289 2290 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2291 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2292 return -ENOMEM; 2293 2294 return 0; 2295 } 2296 2297 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2298 return 0; 2299 2300 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2301 return 0; 2302 2303 /* try to decrease the buffer size */ 2304 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2305 return 0; 2306 2307 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2308 return 0; 2309 2310 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2311 return 0; 2312 2313 return -ENOMEM; 2314 } 2315 2316 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2317 struct hclge_pkt_buf_alloc *buf_alloc) 2318 { 2319 struct hclge_rx_priv_buff_cmd *req; 2320 struct hclge_desc desc; 2321 int ret; 2322 int i; 2323 2324 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2325 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2326 2327 /* Alloc private buffer TCs */ 2328 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2329 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2330 2331 req->buf_num[i] = 2332 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2333 req->buf_num[i] |= 2334 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2335 } 2336 2337 req->shared_buf = 2338 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2339 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2340 2341 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2342 if (ret) 2343 dev_err(&hdev->pdev->dev, 2344 "rx private buffer alloc cmd failed %d\n", ret); 2345 2346 return ret; 2347 } 2348 2349 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2350 struct hclge_pkt_buf_alloc *buf_alloc) 2351 { 2352 struct hclge_rx_priv_wl_buf *req; 2353 struct hclge_priv_buf *priv; 2354 struct hclge_desc desc[2]; 2355 int i, j; 2356 int ret; 2357 2358 for (i = 0; i < 2; i++) { 2359 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2360 false); 2361 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2362 2363 /* The first descriptor set the NEXT bit to 1 */ 2364 if (i == 0) 2365 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2366 else 2367 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2368 2369 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2370 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2371 2372 priv = &buf_alloc->priv_buf[idx]; 2373 req->tc_wl[j].high = 2374 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2375 req->tc_wl[j].high |= 2376 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2377 req->tc_wl[j].low = 2378 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2379 req->tc_wl[j].low |= 2380 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2381 } 2382 } 2383 2384 /* Send 2 descriptor at one time */ 2385 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2386 if (ret) 2387 dev_err(&hdev->pdev->dev, 2388 "rx private waterline config cmd failed %d\n", 2389 ret); 2390 return ret; 2391 } 2392 2393 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2394 struct hclge_pkt_buf_alloc *buf_alloc) 2395 { 2396 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2397 struct hclge_rx_com_thrd *req; 2398 struct hclge_desc desc[2]; 2399 struct hclge_tc_thrd *tc; 2400 int i, j; 2401 int ret; 2402 2403 for (i = 0; i < 2; i++) { 2404 hclge_cmd_setup_basic_desc(&desc[i], 2405 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2406 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2407 2408 /* The first descriptor set the NEXT bit to 1 */ 2409 if (i == 0) 2410 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2411 else 2412 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2413 2414 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2415 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2416 2417 req->com_thrd[j].high = 2418 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2419 req->com_thrd[j].high |= 2420 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2421 req->com_thrd[j].low = 2422 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2423 req->com_thrd[j].low |= 2424 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2425 } 2426 } 2427 2428 /* Send 2 descriptors at one time */ 2429 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2430 if (ret) 2431 dev_err(&hdev->pdev->dev, 2432 "common threshold config cmd failed %d\n", ret); 2433 return ret; 2434 } 2435 2436 static int hclge_common_wl_config(struct hclge_dev *hdev, 2437 struct hclge_pkt_buf_alloc *buf_alloc) 2438 { 2439 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2440 struct hclge_rx_com_wl *req; 2441 struct hclge_desc desc; 2442 int ret; 2443 2444 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2445 2446 req = (struct hclge_rx_com_wl *)desc.data; 2447 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2448 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2449 2450 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2451 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2452 2453 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2454 if (ret) 2455 dev_err(&hdev->pdev->dev, 2456 "common waterline config cmd failed %d\n", ret); 2457 2458 return ret; 2459 } 2460 2461 int hclge_buffer_alloc(struct hclge_dev *hdev) 2462 { 2463 struct hclge_pkt_buf_alloc *pkt_buf; 2464 int ret; 2465 2466 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2467 if (!pkt_buf) 2468 return -ENOMEM; 2469 2470 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2471 if (ret) { 2472 dev_err(&hdev->pdev->dev, 2473 "could not calc tx buffer size for all TCs %d\n", ret); 2474 goto out; 2475 } 2476 2477 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2478 if (ret) { 2479 dev_err(&hdev->pdev->dev, 2480 "could not alloc tx buffers %d\n", ret); 2481 goto out; 2482 } 2483 2484 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2485 if (ret) { 2486 dev_err(&hdev->pdev->dev, 2487 "could not calc rx priv buffer size for all TCs %d\n", 2488 ret); 2489 goto out; 2490 } 2491 2492 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2493 if (ret) { 2494 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2495 ret); 2496 goto out; 2497 } 2498 2499 if (hnae3_dev_dcb_supported(hdev)) { 2500 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2501 if (ret) { 2502 dev_err(&hdev->pdev->dev, 2503 "could not configure rx private waterline %d\n", 2504 ret); 2505 goto out; 2506 } 2507 2508 ret = hclge_common_thrd_config(hdev, pkt_buf); 2509 if (ret) { 2510 dev_err(&hdev->pdev->dev, 2511 "could not configure common threshold %d\n", 2512 ret); 2513 goto out; 2514 } 2515 } 2516 2517 ret = hclge_common_wl_config(hdev, pkt_buf); 2518 if (ret) 2519 dev_err(&hdev->pdev->dev, 2520 "could not configure common waterline %d\n", ret); 2521 2522 out: 2523 kfree(pkt_buf); 2524 return ret; 2525 } 2526 2527 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2528 { 2529 struct hnae3_handle *roce = &vport->roce; 2530 struct hnae3_handle *nic = &vport->nic; 2531 struct hclge_dev *hdev = vport->back; 2532 2533 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2534 2535 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2536 return -EINVAL; 2537 2538 roce->rinfo.base_vector = hdev->num_nic_msi; 2539 2540 roce->rinfo.netdev = nic->kinfo.netdev; 2541 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2542 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2543 2544 roce->pdev = nic->pdev; 2545 roce->ae_algo = nic->ae_algo; 2546 roce->numa_node_mask = nic->numa_node_mask; 2547 2548 return 0; 2549 } 2550 2551 static int hclge_init_msi(struct hclge_dev *hdev) 2552 { 2553 struct pci_dev *pdev = hdev->pdev; 2554 int vectors; 2555 int i; 2556 2557 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2558 hdev->num_msi, 2559 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2560 if (vectors < 0) { 2561 dev_err(&pdev->dev, 2562 "failed(%d) to allocate MSI/MSI-X vectors\n", 2563 vectors); 2564 return vectors; 2565 } 2566 if (vectors < hdev->num_msi) 2567 dev_warn(&hdev->pdev->dev, 2568 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2569 hdev->num_msi, vectors); 2570 2571 hdev->num_msi = vectors; 2572 hdev->num_msi_left = vectors; 2573 2574 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2575 sizeof(u16), GFP_KERNEL); 2576 if (!hdev->vector_status) { 2577 pci_free_irq_vectors(pdev); 2578 return -ENOMEM; 2579 } 2580 2581 for (i = 0; i < hdev->num_msi; i++) 2582 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2583 2584 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2585 sizeof(int), GFP_KERNEL); 2586 if (!hdev->vector_irq) { 2587 pci_free_irq_vectors(pdev); 2588 return -ENOMEM; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2595 { 2596 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2597 duplex = HCLGE_MAC_FULL; 2598 2599 return duplex; 2600 } 2601 2602 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2603 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2604 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2605 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2606 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2607 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2608 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2609 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2610 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2611 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2612 }; 2613 2614 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2615 { 2616 u16 i; 2617 2618 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2619 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2620 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2621 return 0; 2622 } 2623 } 2624 2625 return -EINVAL; 2626 } 2627 2628 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2629 u8 duplex, u8 lane_num) 2630 { 2631 struct hclge_config_mac_speed_dup_cmd *req; 2632 struct hclge_desc desc; 2633 u32 speed_fw; 2634 int ret; 2635 2636 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2637 2638 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2639 2640 if (duplex) 2641 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2642 2643 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2644 if (ret) { 2645 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2646 return ret; 2647 } 2648 2649 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2650 speed_fw); 2651 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2652 1); 2653 req->lane_num = lane_num; 2654 2655 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2656 if (ret) { 2657 dev_err(&hdev->pdev->dev, 2658 "mac speed/duplex config cmd failed %d.\n", ret); 2659 return ret; 2660 } 2661 2662 return 0; 2663 } 2664 2665 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2666 { 2667 struct hclge_mac *mac = &hdev->hw.mac; 2668 int ret; 2669 2670 duplex = hclge_check_speed_dup(duplex, speed); 2671 if (!mac->support_autoneg && mac->speed == speed && 2672 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2673 return 0; 2674 2675 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2676 if (ret) 2677 return ret; 2678 2679 hdev->hw.mac.speed = speed; 2680 hdev->hw.mac.duplex = duplex; 2681 if (!lane_num) 2682 hdev->hw.mac.lane_num = lane_num; 2683 2684 return 0; 2685 } 2686 2687 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2688 u8 duplex, u8 lane_num) 2689 { 2690 struct hclge_vport *vport = hclge_get_vport(handle); 2691 struct hclge_dev *hdev = vport->back; 2692 2693 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2694 } 2695 2696 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2697 { 2698 struct hclge_config_auto_neg_cmd *req; 2699 struct hclge_desc desc; 2700 u32 flag = 0; 2701 int ret; 2702 2703 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2704 2705 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2706 if (enable) 2707 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2708 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2709 2710 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2711 if (ret) 2712 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2713 ret); 2714 2715 return ret; 2716 } 2717 2718 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2719 { 2720 struct hclge_vport *vport = hclge_get_vport(handle); 2721 struct hclge_dev *hdev = vport->back; 2722 2723 if (!hdev->hw.mac.support_autoneg) { 2724 if (enable) { 2725 dev_err(&hdev->pdev->dev, 2726 "autoneg is not supported by current port\n"); 2727 return -EOPNOTSUPP; 2728 } else { 2729 return 0; 2730 } 2731 } 2732 2733 return hclge_set_autoneg_en(hdev, enable); 2734 } 2735 2736 static int hclge_get_autoneg(struct hnae3_handle *handle) 2737 { 2738 struct hclge_vport *vport = hclge_get_vport(handle); 2739 struct hclge_dev *hdev = vport->back; 2740 struct phy_device *phydev = hdev->hw.mac.phydev; 2741 2742 if (phydev) 2743 return phydev->autoneg; 2744 2745 return hdev->hw.mac.autoneg; 2746 } 2747 2748 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2749 { 2750 struct hclge_vport *vport = hclge_get_vport(handle); 2751 struct hclge_dev *hdev = vport->back; 2752 int ret; 2753 2754 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2755 2756 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2757 if (ret) 2758 return ret; 2759 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2760 } 2761 2762 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2763 { 2764 struct hclge_vport *vport = hclge_get_vport(handle); 2765 struct hclge_dev *hdev = vport->back; 2766 2767 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2768 return hclge_set_autoneg_en(hdev, !halt); 2769 2770 return 0; 2771 } 2772 2773 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2774 struct hclge_desc *desc, u32 desc_len) 2775 { 2776 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2777 u32 desc_index = 0; 2778 u32 data_index = 0; 2779 u32 i; 2780 2781 for (i = 0; i < lane_size; i++) { 2782 if (data_index >= HCLGE_DESC_DATA_LEN) { 2783 desc_index++; 2784 data_index = 0; 2785 } 2786 2787 if (desc_index >= desc_len) 2788 return; 2789 2790 hdev->fec_stats.per_lanes[i] += 2791 le32_to_cpu(desc[desc_index].data[data_index]); 2792 data_index++; 2793 } 2794 } 2795 2796 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2797 struct hclge_desc *desc, u32 desc_len) 2798 { 2799 struct hclge_query_fec_stats_cmd *req; 2800 2801 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2802 2803 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2804 hdev->fec_stats.rs_corr_blocks += 2805 le32_to_cpu(req->rs_fec_corr_blocks); 2806 hdev->fec_stats.rs_uncorr_blocks += 2807 le32_to_cpu(req->rs_fec_uncorr_blocks); 2808 hdev->fec_stats.rs_error_blocks += 2809 le32_to_cpu(req->rs_fec_error_blocks); 2810 hdev->fec_stats.base_r_corr_blocks += 2811 le32_to_cpu(req->base_r_fec_corr_blocks); 2812 hdev->fec_stats.base_r_uncorr_blocks += 2813 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2814 2815 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2816 } 2817 2818 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2819 { 2820 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2821 int ret; 2822 u32 i; 2823 2824 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2825 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2826 true); 2827 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2828 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2829 } 2830 2831 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2832 if (ret) 2833 return ret; 2834 2835 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2836 2837 return 0; 2838 } 2839 2840 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2841 { 2842 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2843 int ret; 2844 2845 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2846 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2847 return; 2848 2849 ret = hclge_update_fec_stats_hw(hdev); 2850 if (ret) 2851 dev_err(&hdev->pdev->dev, 2852 "failed to update fec stats, ret = %d\n", ret); 2853 2854 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2855 } 2856 2857 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2858 struct ethtool_fec_stats *fec_stats) 2859 { 2860 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2861 fec_stats->uncorrectable_blocks.total = 2862 hdev->fec_stats.rs_uncorr_blocks; 2863 } 2864 2865 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2866 struct ethtool_fec_stats *fec_stats) 2867 { 2868 u32 i; 2869 2870 if (hdev->fec_stats.base_r_lane_num == 0 || 2871 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2872 dev_err(&hdev->pdev->dev, 2873 "fec stats lane number(%llu) is invalid\n", 2874 hdev->fec_stats.base_r_lane_num); 2875 return; 2876 } 2877 2878 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2879 fec_stats->corrected_blocks.lanes[i] = 2880 hdev->fec_stats.base_r_corr_per_lanes[i]; 2881 fec_stats->uncorrectable_blocks.lanes[i] = 2882 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2883 } 2884 } 2885 2886 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2887 struct ethtool_fec_stats *fec_stats) 2888 { 2889 u32 fec_mode = hdev->hw.mac.fec_mode; 2890 2891 switch (fec_mode) { 2892 case BIT(HNAE3_FEC_RS): 2893 case BIT(HNAE3_FEC_LLRS): 2894 hclge_get_fec_stats_total(hdev, fec_stats); 2895 break; 2896 case BIT(HNAE3_FEC_BASER): 2897 hclge_get_fec_stats_lanes(hdev, fec_stats); 2898 break; 2899 default: 2900 dev_err(&hdev->pdev->dev, 2901 "fec stats is not supported by current fec mode(0x%x)\n", 2902 fec_mode); 2903 break; 2904 } 2905 } 2906 2907 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2908 struct ethtool_fec_stats *fec_stats) 2909 { 2910 struct hclge_vport *vport = hclge_get_vport(handle); 2911 struct hclge_dev *hdev = vport->back; 2912 u32 fec_mode = hdev->hw.mac.fec_mode; 2913 2914 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2915 fec_mode == BIT(HNAE3_FEC_AUTO) || 2916 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2917 return; 2918 2919 hclge_update_fec_stats(hdev); 2920 2921 hclge_comm_get_fec_stats(hdev, fec_stats); 2922 } 2923 2924 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2925 { 2926 struct hclge_config_fec_cmd *req; 2927 struct hclge_desc desc; 2928 int ret; 2929 2930 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2931 2932 req = (struct hclge_config_fec_cmd *)desc.data; 2933 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2934 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2935 if (fec_mode & BIT(HNAE3_FEC_RS)) 2936 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2937 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2938 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2939 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2940 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2941 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2942 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2943 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2944 2945 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2946 if (ret) 2947 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2948 2949 return ret; 2950 } 2951 2952 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2953 { 2954 struct hclge_vport *vport = hclge_get_vport(handle); 2955 struct hclge_dev *hdev = vport->back; 2956 struct hclge_mac *mac = &hdev->hw.mac; 2957 int ret; 2958 2959 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2960 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2961 return -EINVAL; 2962 } 2963 2964 ret = hclge_set_fec_hw(hdev, fec_mode); 2965 if (ret) 2966 return ret; 2967 2968 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2969 return 0; 2970 } 2971 2972 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2973 u8 *fec_mode) 2974 { 2975 struct hclge_vport *vport = hclge_get_vport(handle); 2976 struct hclge_dev *hdev = vport->back; 2977 struct hclge_mac *mac = &hdev->hw.mac; 2978 2979 if (fec_ability) 2980 *fec_ability = mac->fec_ability; 2981 if (fec_mode) 2982 *fec_mode = mac->fec_mode; 2983 } 2984 2985 static int hclge_mac_init(struct hclge_dev *hdev) 2986 { 2987 struct hclge_mac *mac = &hdev->hw.mac; 2988 int ret; 2989 2990 hdev->support_sfp_query = true; 2991 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2992 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2993 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2994 if (ret) 2995 return ret; 2996 2997 if (hdev->hw.mac.support_autoneg) { 2998 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2999 if (ret) 3000 return ret; 3001 } 3002 3003 mac->link = 0; 3004 3005 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 3006 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 3007 if (ret) 3008 return ret; 3009 } 3010 3011 ret = hclge_set_mac_mtu(hdev, hdev->mps); 3012 if (ret) { 3013 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 3014 return ret; 3015 } 3016 3017 ret = hclge_set_default_loopback(hdev); 3018 if (ret) 3019 return ret; 3020 3021 ret = hclge_buffer_alloc(hdev); 3022 if (ret) 3023 dev_err(&hdev->pdev->dev, 3024 "allocate buffer fail, ret=%d\n", ret); 3025 3026 return ret; 3027 } 3028 3029 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3030 { 3031 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3032 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3033 hdev->last_mbx_scheduled = jiffies; 3034 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3035 } 3036 } 3037 3038 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3039 { 3040 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3041 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3042 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3043 hdev->last_rst_scheduled = jiffies; 3044 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3045 } 3046 } 3047 3048 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3049 { 3050 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3051 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3052 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3053 } 3054 3055 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3056 { 3057 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3058 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3059 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3060 } 3061 3062 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3063 { 3064 struct hclge_link_status_cmd *req; 3065 struct hclge_desc desc; 3066 int ret; 3067 3068 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3069 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3070 if (ret) { 3071 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3072 ret); 3073 return ret; 3074 } 3075 3076 req = (struct hclge_link_status_cmd *)desc.data; 3077 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3078 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3079 3080 return 0; 3081 } 3082 3083 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3084 { 3085 struct phy_device *phydev = hdev->hw.mac.phydev; 3086 3087 *link_status = HCLGE_LINK_STATUS_DOWN; 3088 3089 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3090 return 0; 3091 3092 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3093 return 0; 3094 3095 return hclge_get_mac_link_status(hdev, link_status); 3096 } 3097 3098 static void hclge_push_link_status(struct hclge_dev *hdev) 3099 { 3100 struct hclge_vport *vport; 3101 int ret; 3102 u16 i; 3103 3104 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3105 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3106 3107 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3108 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3109 continue; 3110 3111 ret = hclge_push_vf_link_status(vport); 3112 if (ret) { 3113 dev_err(&hdev->pdev->dev, 3114 "failed to push link status to vf%u, ret = %d\n", 3115 i, ret); 3116 } 3117 } 3118 } 3119 3120 static void hclge_update_link_status(struct hclge_dev *hdev) 3121 { 3122 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3123 struct hnae3_handle *handle = &hdev->vport[0].nic; 3124 struct hnae3_client *rclient = hdev->roce_client; 3125 struct hnae3_client *client = hdev->nic_client; 3126 int state; 3127 int ret; 3128 3129 if (!client) 3130 return; 3131 3132 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3133 return; 3134 3135 ret = hclge_get_mac_phy_link(hdev, &state); 3136 if (ret) { 3137 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3138 return; 3139 } 3140 3141 if (state != hdev->hw.mac.link) { 3142 hdev->hw.mac.link = state; 3143 client->ops->link_status_change(handle, state); 3144 hclge_config_mac_tnl_int(hdev, state); 3145 if (rclient && rclient->ops->link_status_change) 3146 rclient->ops->link_status_change(rhandle, state); 3147 3148 hclge_push_link_status(hdev); 3149 } 3150 3151 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3152 } 3153 3154 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3155 { 3156 u32 speed_ability; 3157 3158 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3159 return; 3160 3161 switch (mac->module_type) { 3162 case HNAE3_MODULE_TYPE_FIBRE_LR: 3163 hclge_convert_setting_lr(speed_ability, mac->advertising); 3164 break; 3165 case HNAE3_MODULE_TYPE_FIBRE_SR: 3166 case HNAE3_MODULE_TYPE_AOC: 3167 hclge_convert_setting_sr(speed_ability, mac->advertising); 3168 break; 3169 case HNAE3_MODULE_TYPE_CR: 3170 hclge_convert_setting_cr(speed_ability, mac->advertising); 3171 break; 3172 case HNAE3_MODULE_TYPE_KR: 3173 hclge_convert_setting_kr(speed_ability, mac->advertising); 3174 break; 3175 default: 3176 break; 3177 } 3178 } 3179 3180 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3181 { 3182 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3183 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3184 mac->advertising); 3185 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3186 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3187 mac->advertising); 3188 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3189 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3190 mac->advertising); 3191 else 3192 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3193 mac->advertising); 3194 } 3195 3196 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3197 { 3198 struct hclge_mac *mac = &hdev->hw.mac; 3199 bool rx_en, tx_en; 3200 3201 switch (hdev->fc_mode_last_time) { 3202 case HCLGE_FC_RX_PAUSE: 3203 rx_en = true; 3204 tx_en = false; 3205 break; 3206 case HCLGE_FC_TX_PAUSE: 3207 rx_en = false; 3208 tx_en = true; 3209 break; 3210 case HCLGE_FC_FULL: 3211 rx_en = true; 3212 tx_en = true; 3213 break; 3214 default: 3215 rx_en = false; 3216 tx_en = false; 3217 break; 3218 } 3219 3220 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3221 } 3222 3223 static void hclge_update_advertising(struct hclge_dev *hdev) 3224 { 3225 struct hclge_mac *mac = &hdev->hw.mac; 3226 3227 linkmode_zero(mac->advertising); 3228 hclge_update_speed_advertising(mac); 3229 hclge_update_fec_advertising(mac); 3230 hclge_update_pause_advertising(hdev); 3231 } 3232 3233 static void hclge_update_port_capability(struct hclge_dev *hdev, 3234 struct hclge_mac *mac) 3235 { 3236 if (hnae3_dev_fec_supported(hdev)) 3237 hclge_convert_setting_fec(mac); 3238 3239 /* firmware can not identify back plane type, the media type 3240 * read from configuration can help deal it 3241 */ 3242 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3243 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3244 mac->module_type = HNAE3_MODULE_TYPE_KR; 3245 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3246 mac->module_type = HNAE3_MODULE_TYPE_TP; 3247 3248 if (mac->support_autoneg) { 3249 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3250 linkmode_copy(mac->advertising, mac->supported); 3251 } else { 3252 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3253 mac->supported); 3254 hclge_update_advertising(hdev); 3255 } 3256 } 3257 3258 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3259 { 3260 struct hclge_sfp_info_cmd *resp; 3261 struct hclge_desc desc; 3262 int ret; 3263 3264 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3265 resp = (struct hclge_sfp_info_cmd *)desc.data; 3266 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3267 if (ret == -EOPNOTSUPP) { 3268 dev_warn(&hdev->pdev->dev, 3269 "IMP do not support get SFP speed %d\n", ret); 3270 return ret; 3271 } else if (ret) { 3272 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3273 return ret; 3274 } 3275 3276 *speed = le32_to_cpu(resp->speed); 3277 3278 return 0; 3279 } 3280 3281 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3282 { 3283 struct hclge_sfp_info_cmd *resp; 3284 struct hclge_desc desc; 3285 int ret; 3286 3287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3288 resp = (struct hclge_sfp_info_cmd *)desc.data; 3289 3290 resp->query_type = QUERY_ACTIVE_SPEED; 3291 3292 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3293 if (ret == -EOPNOTSUPP) { 3294 dev_warn(&hdev->pdev->dev, 3295 "IMP does not support get SFP info %d\n", ret); 3296 return ret; 3297 } else if (ret) { 3298 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3299 return ret; 3300 } 3301 3302 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3303 * set to mac->speed. 3304 */ 3305 if (!le32_to_cpu(resp->speed)) 3306 return 0; 3307 3308 mac->speed = le32_to_cpu(resp->speed); 3309 /* if resp->speed_ability is 0, it means it's an old version 3310 * firmware, do not update these params 3311 */ 3312 if (resp->speed_ability) { 3313 mac->module_type = le32_to_cpu(resp->module_type); 3314 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3315 mac->autoneg = resp->autoneg; 3316 mac->support_autoneg = resp->autoneg_ability; 3317 mac->speed_type = QUERY_ACTIVE_SPEED; 3318 mac->lane_num = resp->lane_num; 3319 if (!resp->active_fec) 3320 mac->fec_mode = 0; 3321 else 3322 mac->fec_mode = BIT(resp->active_fec); 3323 mac->fec_ability = resp->fec_ability; 3324 } else { 3325 mac->speed_type = QUERY_SFP_SPEED; 3326 } 3327 3328 return 0; 3329 } 3330 3331 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3332 struct ethtool_link_ksettings *cmd) 3333 { 3334 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3335 struct hclge_vport *vport = hclge_get_vport(handle); 3336 struct hclge_phy_link_ksetting_0_cmd *req0; 3337 struct hclge_phy_link_ksetting_1_cmd *req1; 3338 u32 supported, advertising, lp_advertising; 3339 struct hclge_dev *hdev = vport->back; 3340 int ret; 3341 3342 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3343 true); 3344 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3345 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3346 true); 3347 3348 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3349 if (ret) { 3350 dev_err(&hdev->pdev->dev, 3351 "failed to get phy link ksetting, ret = %d.\n", ret); 3352 return ret; 3353 } 3354 3355 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3356 cmd->base.autoneg = req0->autoneg; 3357 cmd->base.speed = le32_to_cpu(req0->speed); 3358 cmd->base.duplex = req0->duplex; 3359 cmd->base.port = req0->port; 3360 cmd->base.transceiver = req0->transceiver; 3361 cmd->base.phy_address = req0->phy_address; 3362 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3363 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3364 supported = le32_to_cpu(req0->supported); 3365 advertising = le32_to_cpu(req0->advertising); 3366 lp_advertising = le32_to_cpu(req0->lp_advertising); 3367 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3368 supported); 3369 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3370 advertising); 3371 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3372 lp_advertising); 3373 3374 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3375 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3376 cmd->base.master_slave_state = req1->master_slave_state; 3377 3378 return 0; 3379 } 3380 3381 static int 3382 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3383 const struct ethtool_link_ksettings *cmd) 3384 { 3385 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3386 struct hclge_vport *vport = hclge_get_vport(handle); 3387 struct hclge_phy_link_ksetting_0_cmd *req0; 3388 struct hclge_phy_link_ksetting_1_cmd *req1; 3389 struct hclge_dev *hdev = vport->back; 3390 u32 advertising; 3391 int ret; 3392 3393 if (cmd->base.autoneg == AUTONEG_DISABLE && 3394 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3395 (cmd->base.duplex != DUPLEX_HALF && 3396 cmd->base.duplex != DUPLEX_FULL))) 3397 return -EINVAL; 3398 3399 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3400 false); 3401 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3402 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3403 false); 3404 3405 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3406 req0->autoneg = cmd->base.autoneg; 3407 req0->speed = cpu_to_le32(cmd->base.speed); 3408 req0->duplex = cmd->base.duplex; 3409 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3410 cmd->link_modes.advertising); 3411 req0->advertising = cpu_to_le32(advertising); 3412 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3413 3414 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3415 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3416 3417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3418 if (ret) { 3419 dev_err(&hdev->pdev->dev, 3420 "failed to set phy link ksettings, ret = %d.\n", ret); 3421 return ret; 3422 } 3423 3424 hdev->hw.mac.autoneg = cmd->base.autoneg; 3425 hdev->hw.mac.speed = cmd->base.speed; 3426 hdev->hw.mac.duplex = cmd->base.duplex; 3427 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3428 3429 return 0; 3430 } 3431 3432 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3433 { 3434 struct ethtool_link_ksettings cmd; 3435 int ret; 3436 3437 if (!hnae3_dev_phy_imp_supported(hdev)) 3438 return 0; 3439 3440 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3441 if (ret) 3442 return ret; 3443 3444 hdev->hw.mac.autoneg = cmd.base.autoneg; 3445 hdev->hw.mac.speed = cmd.base.speed; 3446 hdev->hw.mac.duplex = cmd.base.duplex; 3447 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3448 3449 return 0; 3450 } 3451 3452 static int hclge_tp_port_init(struct hclge_dev *hdev) 3453 { 3454 struct ethtool_link_ksettings cmd; 3455 3456 if (!hnae3_dev_phy_imp_supported(hdev)) 3457 return 0; 3458 3459 cmd.base.autoneg = hdev->hw.mac.autoneg; 3460 cmd.base.speed = hdev->hw.mac.speed; 3461 cmd.base.duplex = hdev->hw.mac.duplex; 3462 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3463 3464 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3465 } 3466 3467 static int hclge_update_port_info(struct hclge_dev *hdev) 3468 { 3469 struct hclge_mac *mac = &hdev->hw.mac; 3470 int speed; 3471 int ret; 3472 3473 /* get the port info from SFP cmd if not copper port */ 3474 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3475 return hclge_update_tp_port_info(hdev); 3476 3477 /* if IMP does not support get SFP/qSFP info, return directly */ 3478 if (!hdev->support_sfp_query) 3479 return 0; 3480 3481 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3482 speed = mac->speed; 3483 ret = hclge_get_sfp_info(hdev, mac); 3484 } else { 3485 speed = HCLGE_MAC_SPEED_UNKNOWN; 3486 ret = hclge_get_sfp_speed(hdev, &speed); 3487 } 3488 3489 if (ret == -EOPNOTSUPP) { 3490 hdev->support_sfp_query = false; 3491 return ret; 3492 } else if (ret) { 3493 return ret; 3494 } 3495 3496 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3497 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3498 hclge_update_port_capability(hdev, mac); 3499 if (mac->speed != speed) 3500 (void)hclge_tm_port_shaper_cfg(hdev); 3501 return 0; 3502 } 3503 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3504 HCLGE_MAC_FULL, mac->lane_num); 3505 } else { 3506 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3507 return 0; /* do nothing if no SFP */ 3508 3509 /* must config full duplex for SFP */ 3510 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3511 } 3512 } 3513 3514 static int hclge_get_status(struct hnae3_handle *handle) 3515 { 3516 struct hclge_vport *vport = hclge_get_vport(handle); 3517 struct hclge_dev *hdev = vport->back; 3518 3519 hclge_update_link_status(hdev); 3520 3521 return hdev->hw.mac.link; 3522 } 3523 3524 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3525 { 3526 if (!pci_num_vf(hdev->pdev)) { 3527 dev_err(&hdev->pdev->dev, 3528 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3529 return NULL; 3530 } 3531 3532 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3533 dev_err(&hdev->pdev->dev, 3534 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3535 vf, pci_num_vf(hdev->pdev)); 3536 return NULL; 3537 } 3538 3539 /* VF start from 1 in vport */ 3540 vf += HCLGE_VF_VPORT_START_NUM; 3541 return &hdev->vport[vf]; 3542 } 3543 3544 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3545 struct ifla_vf_info *ivf) 3546 { 3547 struct hclge_vport *vport = hclge_get_vport(handle); 3548 struct hclge_dev *hdev = vport->back; 3549 3550 vport = hclge_get_vf_vport(hdev, vf); 3551 if (!vport) 3552 return -EINVAL; 3553 3554 ivf->vf = vf; 3555 ivf->linkstate = vport->vf_info.link_state; 3556 ivf->spoofchk = vport->vf_info.spoofchk; 3557 ivf->trusted = vport->vf_info.trusted; 3558 ivf->min_tx_rate = 0; 3559 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3560 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3561 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3562 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3563 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3564 3565 return 0; 3566 } 3567 3568 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3569 int link_state) 3570 { 3571 struct hclge_vport *vport = hclge_get_vport(handle); 3572 struct hclge_dev *hdev = vport->back; 3573 int link_state_old; 3574 int ret; 3575 3576 vport = hclge_get_vf_vport(hdev, vf); 3577 if (!vport) 3578 return -EINVAL; 3579 3580 link_state_old = vport->vf_info.link_state; 3581 vport->vf_info.link_state = link_state; 3582 3583 /* return success directly if the VF is unalive, VF will 3584 * query link state itself when it starts work. 3585 */ 3586 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3587 return 0; 3588 3589 ret = hclge_push_vf_link_status(vport); 3590 if (ret) { 3591 vport->vf_info.link_state = link_state_old; 3592 dev_err(&hdev->pdev->dev, 3593 "failed to push vf%d link status, ret = %d\n", vf, ret); 3594 } 3595 3596 return ret; 3597 } 3598 3599 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3600 { 3601 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3602 3603 /* fetch the events from their corresponding regs */ 3604 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3605 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3606 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3607 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3608 3609 /* Assumption: If by any chance reset and mailbox events are reported 3610 * together then we will only process reset event in this go and will 3611 * defer the processing of the mailbox events. Since, we would have not 3612 * cleared RX CMDQ event this time we would receive again another 3613 * interrupt from H/W just for the mailbox. 3614 * 3615 * check for vector0 reset event sources 3616 */ 3617 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3618 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3619 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3620 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3621 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3622 hdev->rst_stats.imp_rst_cnt++; 3623 return HCLGE_VECTOR0_EVENT_RST; 3624 } 3625 3626 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3627 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3628 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3629 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3630 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3631 hdev->rst_stats.global_rst_cnt++; 3632 return HCLGE_VECTOR0_EVENT_RST; 3633 } 3634 3635 /* check for vector0 msix event and hardware error event source */ 3636 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3637 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3638 return HCLGE_VECTOR0_EVENT_ERR; 3639 3640 /* check for vector0 ptp event source */ 3641 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3642 *clearval = msix_src_reg; 3643 return HCLGE_VECTOR0_EVENT_PTP; 3644 } 3645 3646 /* check for vector0 mailbox(=CMDQ RX) event source */ 3647 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3648 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3649 *clearval = cmdq_src_reg; 3650 return HCLGE_VECTOR0_EVENT_MBX; 3651 } 3652 3653 /* print other vector0 event source */ 3654 dev_info(&hdev->pdev->dev, 3655 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3656 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3657 3658 return HCLGE_VECTOR0_EVENT_OTHER; 3659 } 3660 3661 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3662 u32 regclr) 3663 { 3664 switch (event_type) { 3665 case HCLGE_VECTOR0_EVENT_PTP: 3666 case HCLGE_VECTOR0_EVENT_RST: 3667 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3668 break; 3669 case HCLGE_VECTOR0_EVENT_MBX: 3670 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3671 break; 3672 default: 3673 break; 3674 } 3675 } 3676 3677 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3678 { 3679 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3680 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3681 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3682 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3683 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3684 } 3685 3686 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3687 { 3688 writel(enable ? 1 : 0, vector->addr); 3689 } 3690 3691 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3692 { 3693 struct hclge_dev *hdev = data; 3694 unsigned long flags; 3695 u32 clearval = 0; 3696 u32 event_cause; 3697 3698 hclge_enable_vector(&hdev->misc_vector, false); 3699 event_cause = hclge_check_event_cause(hdev, &clearval); 3700 3701 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3702 switch (event_cause) { 3703 case HCLGE_VECTOR0_EVENT_ERR: 3704 hclge_errhand_task_schedule(hdev); 3705 break; 3706 case HCLGE_VECTOR0_EVENT_RST: 3707 hclge_reset_task_schedule(hdev); 3708 break; 3709 case HCLGE_VECTOR0_EVENT_PTP: 3710 spin_lock_irqsave(&hdev->ptp->lock, flags); 3711 hclge_ptp_clean_tx_hwts(hdev); 3712 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3713 break; 3714 case HCLGE_VECTOR0_EVENT_MBX: 3715 /* If we are here then, 3716 * 1. Either we are not handling any mbx task and we are not 3717 * scheduled as well 3718 * OR 3719 * 2. We could be handling a mbx task but nothing more is 3720 * scheduled. 3721 * In both cases, we should schedule mbx task as there are more 3722 * mbx messages reported by this interrupt. 3723 */ 3724 hclge_mbx_task_schedule(hdev); 3725 break; 3726 default: 3727 dev_warn(&hdev->pdev->dev, 3728 "received unknown or unhandled event of vector0\n"); 3729 break; 3730 } 3731 3732 hclge_clear_event_cause(hdev, event_cause, clearval); 3733 3734 /* Enable interrupt if it is not caused by reset event or error event */ 3735 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3736 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3737 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3738 hclge_enable_vector(&hdev->misc_vector, true); 3739 3740 return IRQ_HANDLED; 3741 } 3742 3743 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3744 { 3745 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3746 dev_warn(&hdev->pdev->dev, 3747 "vector(vector_id %d) has been freed.\n", vector_id); 3748 return; 3749 } 3750 3751 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3752 hdev->num_msi_left += 1; 3753 hdev->num_msi_used -= 1; 3754 } 3755 3756 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3757 { 3758 struct hclge_misc_vector *vector = &hdev->misc_vector; 3759 3760 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3761 3762 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3763 hdev->vector_status[0] = 0; 3764 3765 hdev->num_msi_left -= 1; 3766 hdev->num_msi_used += 1; 3767 } 3768 3769 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3770 { 3771 int ret; 3772 3773 hclge_get_misc_vector(hdev); 3774 3775 /* this would be explicitly freed in the end */ 3776 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3777 HCLGE_NAME, pci_name(hdev->pdev)); 3778 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3779 0, hdev->misc_vector.name, hdev); 3780 if (ret) { 3781 hclge_free_vector(hdev, 0); 3782 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3783 hdev->misc_vector.vector_irq); 3784 } 3785 3786 return ret; 3787 } 3788 3789 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3790 { 3791 free_irq(hdev->misc_vector.vector_irq, hdev); 3792 hclge_free_vector(hdev, 0); 3793 } 3794 3795 int hclge_notify_client(struct hclge_dev *hdev, 3796 enum hnae3_reset_notify_type type) 3797 { 3798 struct hnae3_handle *handle = &hdev->vport[0].nic; 3799 struct hnae3_client *client = hdev->nic_client; 3800 int ret; 3801 3802 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3803 return 0; 3804 3805 if (!client->ops->reset_notify) 3806 return -EOPNOTSUPP; 3807 3808 ret = client->ops->reset_notify(handle, type); 3809 if (ret) 3810 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3811 type, ret); 3812 3813 return ret; 3814 } 3815 3816 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3817 enum hnae3_reset_notify_type type) 3818 { 3819 struct hnae3_handle *handle = &hdev->vport[0].roce; 3820 struct hnae3_client *client = hdev->roce_client; 3821 int ret; 3822 3823 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3824 return 0; 3825 3826 if (!client->ops->reset_notify) 3827 return -EOPNOTSUPP; 3828 3829 ret = client->ops->reset_notify(handle, type); 3830 if (ret) 3831 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3832 type, ret); 3833 3834 return ret; 3835 } 3836 3837 static int hclge_reset_wait(struct hclge_dev *hdev) 3838 { 3839 #define HCLGE_RESET_WATI_MS 100 3840 #define HCLGE_RESET_WAIT_CNT 350 3841 3842 u32 val, reg, reg_bit; 3843 u32 cnt = 0; 3844 3845 switch (hdev->reset_type) { 3846 case HNAE3_IMP_RESET: 3847 reg = HCLGE_GLOBAL_RESET_REG; 3848 reg_bit = HCLGE_IMP_RESET_BIT; 3849 break; 3850 case HNAE3_GLOBAL_RESET: 3851 reg = HCLGE_GLOBAL_RESET_REG; 3852 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3853 break; 3854 case HNAE3_FUNC_RESET: 3855 reg = HCLGE_FUN_RST_ING; 3856 reg_bit = HCLGE_FUN_RST_ING_B; 3857 break; 3858 default: 3859 dev_err(&hdev->pdev->dev, 3860 "Wait for unsupported reset type: %d\n", 3861 hdev->reset_type); 3862 return -EINVAL; 3863 } 3864 3865 val = hclge_read_dev(&hdev->hw, reg); 3866 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3867 msleep(HCLGE_RESET_WATI_MS); 3868 val = hclge_read_dev(&hdev->hw, reg); 3869 cnt++; 3870 } 3871 3872 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3873 dev_warn(&hdev->pdev->dev, 3874 "Wait for reset timeout: %d\n", hdev->reset_type); 3875 return -EBUSY; 3876 } 3877 3878 return 0; 3879 } 3880 3881 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3882 { 3883 struct hclge_vf_rst_cmd *req; 3884 struct hclge_desc desc; 3885 3886 req = (struct hclge_vf_rst_cmd *)desc.data; 3887 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3888 req->dest_vfid = func_id; 3889 3890 if (reset) 3891 req->vf_rst = 0x1; 3892 3893 return hclge_cmd_send(&hdev->hw, &desc, 1); 3894 } 3895 3896 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3897 { 3898 int i; 3899 3900 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3901 struct hclge_vport *vport = &hdev->vport[i]; 3902 int ret; 3903 3904 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3905 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3906 if (ret) { 3907 dev_err(&hdev->pdev->dev, 3908 "set vf(%u) rst failed %d!\n", 3909 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3910 ret); 3911 return ret; 3912 } 3913 3914 if (!reset || 3915 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3916 continue; 3917 3918 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3919 hdev->reset_type == HNAE3_FUNC_RESET) { 3920 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3921 &vport->need_notify); 3922 continue; 3923 } 3924 3925 /* Inform VF to process the reset. 3926 * hclge_inform_reset_assert_to_vf may fail if VF 3927 * driver is not loaded. 3928 */ 3929 ret = hclge_inform_reset_assert_to_vf(vport); 3930 if (ret) 3931 dev_warn(&hdev->pdev->dev, 3932 "inform reset to vf(%u) failed %d!\n", 3933 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3934 ret); 3935 } 3936 3937 return 0; 3938 } 3939 3940 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3941 { 3942 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3943 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3944 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3945 return; 3946 3947 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3948 HCLGE_MBX_SCHED_TIMEOUT)) 3949 dev_warn(&hdev->pdev->dev, 3950 "mbx service task is scheduled after %ums on cpu%u!\n", 3951 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3952 smp_processor_id()); 3953 3954 hclge_mbx_handler(hdev); 3955 3956 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3957 } 3958 3959 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3960 { 3961 struct hclge_pf_rst_sync_cmd *req; 3962 struct hclge_desc desc; 3963 int cnt = 0; 3964 int ret; 3965 3966 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3967 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3968 3969 do { 3970 /* vf need to down netdev by mbx during PF or FLR reset */ 3971 hclge_mailbox_service_task(hdev); 3972 3973 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3974 /* for compatible with old firmware, wait 3975 * 100 ms for VF to stop IO 3976 */ 3977 if (ret == -EOPNOTSUPP) { 3978 msleep(HCLGE_RESET_SYNC_TIME); 3979 return; 3980 } else if (ret) { 3981 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3982 ret); 3983 return; 3984 } else if (req->all_vf_ready) { 3985 return; 3986 } 3987 msleep(HCLGE_PF_RESET_SYNC_TIME); 3988 hclge_comm_cmd_reuse_desc(&desc, true); 3989 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3990 3991 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3992 } 3993 3994 void hclge_report_hw_error(struct hclge_dev *hdev, 3995 enum hnae3_hw_error_type type) 3996 { 3997 struct hnae3_client *client = hdev->nic_client; 3998 3999 if (!client || !client->ops->process_hw_error || 4000 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 4001 return; 4002 4003 client->ops->process_hw_error(&hdev->vport[0].nic, type); 4004 } 4005 4006 static void hclge_handle_imp_error(struct hclge_dev *hdev) 4007 { 4008 u32 reg_val; 4009 4010 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4011 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4012 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4013 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4014 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4015 } 4016 4017 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4018 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4019 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4020 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4021 } 4022 } 4023 4024 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4025 { 4026 struct hclge_desc desc; 4027 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4028 int ret; 4029 4030 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4031 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4032 req->fun_reset_vfid = func_id; 4033 4034 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4035 if (ret) 4036 dev_err(&hdev->pdev->dev, 4037 "send function reset cmd fail, status =%d\n", ret); 4038 4039 return ret; 4040 } 4041 4042 static void hclge_do_reset(struct hclge_dev *hdev) 4043 { 4044 struct hnae3_handle *handle = &hdev->vport[0].nic; 4045 struct pci_dev *pdev = hdev->pdev; 4046 u32 val; 4047 4048 if (hclge_get_hw_reset_stat(handle)) { 4049 dev_info(&pdev->dev, "hardware reset not finish\n"); 4050 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4051 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4052 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4053 return; 4054 } 4055 4056 switch (hdev->reset_type) { 4057 case HNAE3_IMP_RESET: 4058 dev_info(&pdev->dev, "IMP reset requested\n"); 4059 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4060 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4061 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4062 break; 4063 case HNAE3_GLOBAL_RESET: 4064 dev_info(&pdev->dev, "global reset requested\n"); 4065 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4066 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4067 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4068 break; 4069 case HNAE3_FUNC_RESET: 4070 dev_info(&pdev->dev, "PF reset requested\n"); 4071 /* schedule again to check later */ 4072 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4073 hclge_reset_task_schedule(hdev); 4074 break; 4075 default: 4076 dev_warn(&pdev->dev, 4077 "unsupported reset type: %d\n", hdev->reset_type); 4078 break; 4079 } 4080 } 4081 4082 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4083 unsigned long *addr) 4084 { 4085 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4086 struct hclge_dev *hdev = ae_dev->priv; 4087 4088 /* return the highest priority reset level amongst all */ 4089 if (test_bit(HNAE3_IMP_RESET, addr)) { 4090 rst_level = HNAE3_IMP_RESET; 4091 clear_bit(HNAE3_IMP_RESET, addr); 4092 clear_bit(HNAE3_GLOBAL_RESET, addr); 4093 clear_bit(HNAE3_FUNC_RESET, addr); 4094 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4095 rst_level = HNAE3_GLOBAL_RESET; 4096 clear_bit(HNAE3_GLOBAL_RESET, addr); 4097 clear_bit(HNAE3_FUNC_RESET, addr); 4098 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4099 rst_level = HNAE3_FUNC_RESET; 4100 clear_bit(HNAE3_FUNC_RESET, addr); 4101 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4102 rst_level = HNAE3_FLR_RESET; 4103 clear_bit(HNAE3_FLR_RESET, addr); 4104 } 4105 4106 if (hdev->reset_type != HNAE3_NONE_RESET && 4107 rst_level < hdev->reset_type) 4108 return HNAE3_NONE_RESET; 4109 4110 return rst_level; 4111 } 4112 4113 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4114 { 4115 u32 clearval = 0; 4116 4117 switch (hdev->reset_type) { 4118 case HNAE3_IMP_RESET: 4119 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4120 break; 4121 case HNAE3_GLOBAL_RESET: 4122 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4123 break; 4124 default: 4125 break; 4126 } 4127 4128 if (!clearval) 4129 return; 4130 4131 /* For revision 0x20, the reset interrupt source 4132 * can only be cleared after hardware reset done 4133 */ 4134 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4135 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4136 clearval); 4137 4138 hclge_enable_vector(&hdev->misc_vector, true); 4139 } 4140 4141 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4142 { 4143 u32 reg_val; 4144 4145 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4146 if (enable) 4147 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4148 else 4149 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4150 4151 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4152 } 4153 4154 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4155 { 4156 int ret; 4157 4158 ret = hclge_set_all_vf_rst(hdev, true); 4159 if (ret) 4160 return ret; 4161 4162 hclge_func_reset_sync_vf(hdev); 4163 4164 return 0; 4165 } 4166 4167 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4168 { 4169 u32 reg_val; 4170 int ret = 0; 4171 4172 switch (hdev->reset_type) { 4173 case HNAE3_FUNC_RESET: 4174 ret = hclge_func_reset_notify_vf(hdev); 4175 if (ret) 4176 return ret; 4177 4178 ret = hclge_func_reset_cmd(hdev, 0); 4179 if (ret) { 4180 dev_err(&hdev->pdev->dev, 4181 "asserting function reset fail %d!\n", ret); 4182 return ret; 4183 } 4184 4185 /* After performaning pf reset, it is not necessary to do the 4186 * mailbox handling or send any command to firmware, because 4187 * any mailbox handling or command to firmware is only valid 4188 * after hclge_comm_cmd_init is called. 4189 */ 4190 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4191 hdev->rst_stats.pf_rst_cnt++; 4192 break; 4193 case HNAE3_FLR_RESET: 4194 ret = hclge_func_reset_notify_vf(hdev); 4195 if (ret) 4196 return ret; 4197 break; 4198 case HNAE3_IMP_RESET: 4199 hclge_handle_imp_error(hdev); 4200 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4201 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4202 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4203 break; 4204 default: 4205 break; 4206 } 4207 4208 /* inform hardware that preparatory work is done */ 4209 msleep(HCLGE_RESET_SYNC_TIME); 4210 hclge_reset_handshake(hdev, true); 4211 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4212 4213 return ret; 4214 } 4215 4216 static void hclge_show_rst_info(struct hclge_dev *hdev) 4217 { 4218 char *buf; 4219 4220 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4221 if (!buf) 4222 return; 4223 4224 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4225 4226 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4227 4228 kfree(buf); 4229 } 4230 4231 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4232 { 4233 #define MAX_RESET_FAIL_CNT 5 4234 4235 if (hdev->reset_pending) { 4236 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4237 hdev->reset_pending); 4238 return true; 4239 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4240 HCLGE_RESET_INT_M) { 4241 dev_info(&hdev->pdev->dev, 4242 "reset failed because new reset interrupt\n"); 4243 hclge_clear_reset_cause(hdev); 4244 return false; 4245 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4246 hdev->rst_stats.reset_fail_cnt++; 4247 set_bit(hdev->reset_type, &hdev->reset_pending); 4248 dev_info(&hdev->pdev->dev, 4249 "re-schedule reset task(%u)\n", 4250 hdev->rst_stats.reset_fail_cnt); 4251 return true; 4252 } 4253 4254 hclge_clear_reset_cause(hdev); 4255 4256 /* recover the handshake status when reset fail */ 4257 hclge_reset_handshake(hdev, true); 4258 4259 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4260 4261 hclge_show_rst_info(hdev); 4262 4263 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4264 4265 return false; 4266 } 4267 4268 static void hclge_update_reset_level(struct hclge_dev *hdev) 4269 { 4270 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4271 enum hnae3_reset_type reset_level; 4272 4273 /* reset request will not be set during reset, so clear 4274 * pending reset request to avoid unnecessary reset 4275 * caused by the same reason. 4276 */ 4277 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4278 4279 /* if default_reset_request has a higher level reset request, 4280 * it should be handled as soon as possible. since some errors 4281 * need this kind of reset to fix. 4282 */ 4283 reset_level = hclge_get_reset_level(ae_dev, 4284 &hdev->default_reset_request); 4285 if (reset_level != HNAE3_NONE_RESET) 4286 set_bit(reset_level, &hdev->reset_request); 4287 } 4288 4289 static int hclge_set_rst_done(struct hclge_dev *hdev) 4290 { 4291 struct hclge_pf_rst_done_cmd *req; 4292 struct hclge_desc desc; 4293 int ret; 4294 4295 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4296 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4297 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4298 4299 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4300 /* To be compatible with the old firmware, which does not support 4301 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4302 * return success 4303 */ 4304 if (ret == -EOPNOTSUPP) { 4305 dev_warn(&hdev->pdev->dev, 4306 "current firmware does not support command(0x%x)!\n", 4307 HCLGE_OPC_PF_RST_DONE); 4308 return 0; 4309 } else if (ret) { 4310 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4311 ret); 4312 } 4313 4314 return ret; 4315 } 4316 4317 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4318 { 4319 int ret = 0; 4320 4321 switch (hdev->reset_type) { 4322 case HNAE3_FUNC_RESET: 4323 case HNAE3_FLR_RESET: 4324 ret = hclge_set_all_vf_rst(hdev, false); 4325 break; 4326 case HNAE3_GLOBAL_RESET: 4327 case HNAE3_IMP_RESET: 4328 ret = hclge_set_rst_done(hdev); 4329 break; 4330 default: 4331 break; 4332 } 4333 4334 /* clear up the handshake status after re-initialize done */ 4335 hclge_reset_handshake(hdev, false); 4336 4337 return ret; 4338 } 4339 4340 static int hclge_reset_stack(struct hclge_dev *hdev) 4341 { 4342 int ret; 4343 4344 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4345 if (ret) 4346 return ret; 4347 4348 ret = hclge_reset_ae_dev(hdev->ae_dev); 4349 if (ret) 4350 return ret; 4351 4352 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4353 } 4354 4355 static int hclge_reset_prepare(struct hclge_dev *hdev) 4356 { 4357 int ret; 4358 4359 hdev->rst_stats.reset_cnt++; 4360 /* perform reset of the stack & ae device for a client */ 4361 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4362 if (ret) 4363 return ret; 4364 4365 rtnl_lock(); 4366 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4367 rtnl_unlock(); 4368 if (ret) 4369 return ret; 4370 4371 return hclge_reset_prepare_wait(hdev); 4372 } 4373 4374 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4375 { 4376 int ret; 4377 4378 hdev->rst_stats.hw_reset_done_cnt++; 4379 4380 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4381 if (ret) 4382 return ret; 4383 4384 rtnl_lock(); 4385 ret = hclge_reset_stack(hdev); 4386 rtnl_unlock(); 4387 if (ret) 4388 return ret; 4389 4390 hclge_clear_reset_cause(hdev); 4391 4392 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4393 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4394 * times 4395 */ 4396 if (ret && 4397 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4398 return ret; 4399 4400 ret = hclge_reset_prepare_up(hdev); 4401 if (ret) 4402 return ret; 4403 4404 rtnl_lock(); 4405 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4406 rtnl_unlock(); 4407 if (ret) 4408 return ret; 4409 4410 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4411 if (ret) 4412 return ret; 4413 4414 hdev->last_reset_time = jiffies; 4415 hdev->rst_stats.reset_fail_cnt = 0; 4416 hdev->rst_stats.reset_done_cnt++; 4417 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4418 4419 hclge_update_reset_level(hdev); 4420 4421 return 0; 4422 } 4423 4424 static void hclge_reset(struct hclge_dev *hdev) 4425 { 4426 if (hclge_reset_prepare(hdev)) 4427 goto err_reset; 4428 4429 if (hclge_reset_wait(hdev)) 4430 goto err_reset; 4431 4432 if (hclge_reset_rebuild(hdev)) 4433 goto err_reset; 4434 4435 return; 4436 4437 err_reset: 4438 if (hclge_reset_err_handle(hdev)) 4439 hclge_reset_task_schedule(hdev); 4440 } 4441 4442 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4443 { 4444 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4445 struct hclge_dev *hdev = ae_dev->priv; 4446 4447 /* We might end up getting called broadly because of 2 below cases: 4448 * 1. Recoverable error was conveyed through APEI and only way to bring 4449 * normalcy is to reset. 4450 * 2. A new reset request from the stack due to timeout 4451 * 4452 * check if this is a new reset request and we are not here just because 4453 * last reset attempt did not succeed and watchdog hit us again. We will 4454 * know this if last reset request did not occur very recently (watchdog 4455 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4456 * In case of new request we reset the "reset level" to PF reset. 4457 * And if it is a repeat reset request of the most recent one then we 4458 * want to make sure we throttle the reset request. Therefore, we will 4459 * not allow it again before 3*HZ times. 4460 */ 4461 4462 if (time_before(jiffies, (hdev->last_reset_time + 4463 HCLGE_RESET_INTERVAL))) { 4464 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4465 return; 4466 } 4467 4468 if (hdev->default_reset_request) { 4469 hdev->reset_level = 4470 hclge_get_reset_level(ae_dev, 4471 &hdev->default_reset_request); 4472 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4473 hdev->reset_level = HNAE3_FUNC_RESET; 4474 } 4475 4476 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4477 hdev->reset_level); 4478 4479 /* request reset & schedule reset task */ 4480 set_bit(hdev->reset_level, &hdev->reset_request); 4481 hclge_reset_task_schedule(hdev); 4482 4483 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4484 hdev->reset_level++; 4485 } 4486 4487 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4488 enum hnae3_reset_type rst_type) 4489 { 4490 struct hclge_dev *hdev = ae_dev->priv; 4491 4492 set_bit(rst_type, &hdev->default_reset_request); 4493 } 4494 4495 static void hclge_reset_timer(struct timer_list *t) 4496 { 4497 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4498 4499 /* if default_reset_request has no value, it means that this reset 4500 * request has already be handled, so just return here 4501 */ 4502 if (!hdev->default_reset_request) 4503 return; 4504 4505 dev_info(&hdev->pdev->dev, 4506 "triggering reset in reset timer\n"); 4507 hclge_reset_event(hdev->pdev, NULL); 4508 } 4509 4510 static void hclge_reset_subtask(struct hclge_dev *hdev) 4511 { 4512 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4513 4514 /* check if there is any ongoing reset in the hardware. This status can 4515 * be checked from reset_pending. If there is then, we need to wait for 4516 * hardware to complete reset. 4517 * a. If we are able to figure out in reasonable time that hardware 4518 * has fully resetted then, we can proceed with driver, client 4519 * reset. 4520 * b. else, we can come back later to check this status so re-sched 4521 * now. 4522 */ 4523 hdev->last_reset_time = jiffies; 4524 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4525 if (hdev->reset_type != HNAE3_NONE_RESET) 4526 hclge_reset(hdev); 4527 4528 /* check if we got any *new* reset requests to be honored */ 4529 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4530 if (hdev->reset_type != HNAE3_NONE_RESET) 4531 hclge_do_reset(hdev); 4532 4533 hdev->reset_type = HNAE3_NONE_RESET; 4534 } 4535 4536 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4537 { 4538 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4539 enum hnae3_reset_type reset_type; 4540 4541 if (ae_dev->hw_err_reset_req) { 4542 reset_type = hclge_get_reset_level(ae_dev, 4543 &ae_dev->hw_err_reset_req); 4544 hclge_set_def_reset_request(ae_dev, reset_type); 4545 } 4546 4547 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4548 ae_dev->ops->reset_event(hdev->pdev, NULL); 4549 4550 /* enable interrupt after error handling complete */ 4551 hclge_enable_vector(&hdev->misc_vector, true); 4552 } 4553 4554 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4555 { 4556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4557 4558 ae_dev->hw_err_reset_req = 0; 4559 4560 if (hclge_find_error_source(hdev)) { 4561 hclge_handle_error_info_log(ae_dev); 4562 hclge_handle_mac_tnl(hdev); 4563 } 4564 4565 hclge_handle_err_reset_request(hdev); 4566 } 4567 4568 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4569 { 4570 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4571 struct device *dev = &hdev->pdev->dev; 4572 u32 msix_sts_reg; 4573 4574 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4575 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4576 if (hclge_handle_hw_msix_error 4577 (hdev, &hdev->default_reset_request)) 4578 dev_info(dev, "received msix interrupt 0x%x\n", 4579 msix_sts_reg); 4580 } 4581 4582 hclge_handle_hw_ras_error(ae_dev); 4583 4584 hclge_handle_err_reset_request(hdev); 4585 } 4586 4587 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4588 { 4589 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4590 return; 4591 4592 if (hnae3_dev_ras_imp_supported(hdev)) 4593 hclge_handle_err_recovery(hdev); 4594 else 4595 hclge_misc_err_recovery(hdev); 4596 } 4597 4598 static void hclge_reset_service_task(struct hclge_dev *hdev) 4599 { 4600 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4601 return; 4602 4603 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4604 HCLGE_RESET_SCHED_TIMEOUT)) 4605 dev_warn(&hdev->pdev->dev, 4606 "reset service task is scheduled after %ums on cpu%u!\n", 4607 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4608 smp_processor_id()); 4609 4610 down(&hdev->reset_sem); 4611 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4612 4613 hclge_reset_subtask(hdev); 4614 4615 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4616 up(&hdev->reset_sem); 4617 } 4618 4619 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4620 { 4621 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4622 4623 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4624 int i; 4625 4626 /* start from vport 1 for PF is always alive */ 4627 for (i = 1; i < hdev->num_alloc_vport; i++) { 4628 struct hclge_vport *vport = &hdev->vport[i]; 4629 4630 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4631 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4632 continue; 4633 if (time_after(jiffies, vport->last_active_jiffies + 4634 alive_time)) { 4635 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4636 dev_warn(&hdev->pdev->dev, 4637 "VF %u heartbeat timeout\n", 4638 i - HCLGE_VF_VPORT_START_NUM); 4639 } 4640 } 4641 } 4642 4643 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4644 { 4645 unsigned long delta = round_jiffies_relative(HZ); 4646 4647 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4648 return; 4649 4650 /* Always handle the link updating to make sure link state is 4651 * updated when it is triggered by mbx. 4652 */ 4653 hclge_update_link_status(hdev); 4654 hclge_sync_mac_table(hdev); 4655 hclge_sync_promisc_mode(hdev); 4656 hclge_sync_fd_table(hdev); 4657 4658 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4659 delta = jiffies - hdev->last_serv_processed; 4660 4661 if (delta < round_jiffies_relative(HZ)) { 4662 delta = round_jiffies_relative(HZ) - delta; 4663 goto out; 4664 } 4665 } 4666 4667 hdev->serv_processed_cnt++; 4668 hclge_update_vport_alive(hdev); 4669 4670 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4671 hdev->last_serv_processed = jiffies; 4672 goto out; 4673 } 4674 4675 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4676 hclge_update_stats_for_all(hdev); 4677 4678 hclge_update_port_info(hdev); 4679 hclge_sync_vlan_filter(hdev); 4680 4681 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4682 hclge_rfs_filter_expire(hdev); 4683 4684 hdev->last_serv_processed = jiffies; 4685 4686 out: 4687 hclge_task_schedule(hdev, delta); 4688 } 4689 4690 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4691 { 4692 unsigned long flags; 4693 4694 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4695 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4696 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4697 return; 4698 4699 /* to prevent concurrence with the irq handler */ 4700 spin_lock_irqsave(&hdev->ptp->lock, flags); 4701 4702 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4703 * handler may handle it just before spin_lock_irqsave(). 4704 */ 4705 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4706 hclge_ptp_clean_tx_hwts(hdev); 4707 4708 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4709 } 4710 4711 static void hclge_service_task(struct work_struct *work) 4712 { 4713 struct hclge_dev *hdev = 4714 container_of(work, struct hclge_dev, service_task.work); 4715 4716 hclge_errhand_service_task(hdev); 4717 hclge_reset_service_task(hdev); 4718 hclge_ptp_service_task(hdev); 4719 hclge_mailbox_service_task(hdev); 4720 hclge_periodic_service_task(hdev); 4721 4722 /* Handle error recovery, reset and mbx again in case periodical task 4723 * delays the handling by calling hclge_task_schedule() in 4724 * hclge_periodic_service_task(). 4725 */ 4726 hclge_errhand_service_task(hdev); 4727 hclge_reset_service_task(hdev); 4728 hclge_mailbox_service_task(hdev); 4729 } 4730 4731 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4732 { 4733 /* VF handle has no client */ 4734 if (!handle->client) 4735 return container_of(handle, struct hclge_vport, nic); 4736 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4737 return container_of(handle, struct hclge_vport, roce); 4738 else 4739 return container_of(handle, struct hclge_vport, nic); 4740 } 4741 4742 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4743 struct hnae3_vector_info *vector_info) 4744 { 4745 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4746 4747 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4748 4749 /* need an extend offset to config vector >= 64 */ 4750 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4751 vector_info->io_addr = hdev->hw.hw.io_base + 4752 HCLGE_VECTOR_REG_BASE + 4753 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4754 else 4755 vector_info->io_addr = hdev->hw.hw.io_base + 4756 HCLGE_VECTOR_EXT_REG_BASE + 4757 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4758 HCLGE_VECTOR_REG_OFFSET_H + 4759 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4760 HCLGE_VECTOR_REG_OFFSET; 4761 4762 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4763 hdev->vector_irq[idx] = vector_info->vector; 4764 } 4765 4766 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4767 struct hnae3_vector_info *vector_info) 4768 { 4769 struct hclge_vport *vport = hclge_get_vport(handle); 4770 struct hnae3_vector_info *vector = vector_info; 4771 struct hclge_dev *hdev = vport->back; 4772 int alloc = 0; 4773 u16 i = 0; 4774 u16 j; 4775 4776 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4777 vector_num = min(hdev->num_msi_left, vector_num); 4778 4779 for (j = 0; j < vector_num; j++) { 4780 while (++i < hdev->num_nic_msi) { 4781 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4782 hclge_get_vector_info(hdev, i, vector); 4783 vector++; 4784 alloc++; 4785 4786 break; 4787 } 4788 } 4789 } 4790 hdev->num_msi_left -= alloc; 4791 hdev->num_msi_used += alloc; 4792 4793 return alloc; 4794 } 4795 4796 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4797 { 4798 int i; 4799 4800 for (i = 0; i < hdev->num_msi; i++) 4801 if (vector == hdev->vector_irq[i]) 4802 return i; 4803 4804 return -EINVAL; 4805 } 4806 4807 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4808 { 4809 struct hclge_vport *vport = hclge_get_vport(handle); 4810 struct hclge_dev *hdev = vport->back; 4811 int vector_id; 4812 4813 vector_id = hclge_get_vector_index(hdev, vector); 4814 if (vector_id < 0) { 4815 dev_err(&hdev->pdev->dev, 4816 "Get vector index fail. vector = %d\n", vector); 4817 return vector_id; 4818 } 4819 4820 hclge_free_vector(hdev, vector_id); 4821 4822 return 0; 4823 } 4824 4825 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4826 u8 *key, u8 *hfunc) 4827 { 4828 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4829 struct hclge_vport *vport = hclge_get_vport(handle); 4830 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4831 4832 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4833 4834 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4835 ae_dev->dev_specs.rss_ind_tbl_size); 4836 4837 return 0; 4838 } 4839 4840 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4841 const u8 *key, const u8 hfunc) 4842 { 4843 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4844 struct hclge_vport *vport = hclge_get_vport(handle); 4845 struct hclge_dev *hdev = vport->back; 4846 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4847 int ret, i; 4848 4849 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4850 if (ret) { 4851 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4852 return ret; 4853 } 4854 4855 /* Update the shadow RSS table with user specified qids */ 4856 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4857 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4858 4859 /* Update the hardware */ 4860 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4861 rss_cfg->rss_indirection_tbl); 4862 } 4863 4864 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4865 struct ethtool_rxnfc *nfc) 4866 { 4867 struct hclge_vport *vport = hclge_get_vport(handle); 4868 struct hclge_dev *hdev = vport->back; 4869 int ret; 4870 4871 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4872 &hdev->rss_cfg, nfc); 4873 if (ret) { 4874 dev_err(&hdev->pdev->dev, 4875 "failed to set rss tuple, ret = %d.\n", ret); 4876 return ret; 4877 } 4878 4879 return 0; 4880 } 4881 4882 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4883 struct ethtool_rxnfc *nfc) 4884 { 4885 struct hclge_vport *vport = hclge_get_vport(handle); 4886 u8 tuple_sets; 4887 int ret; 4888 4889 nfc->data = 0; 4890 4891 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4892 &tuple_sets); 4893 if (ret || !tuple_sets) 4894 return ret; 4895 4896 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4897 4898 return 0; 4899 } 4900 4901 static int hclge_get_tc_size(struct hnae3_handle *handle) 4902 { 4903 struct hclge_vport *vport = hclge_get_vport(handle); 4904 struct hclge_dev *hdev = vport->back; 4905 4906 return hdev->pf_rss_size_max; 4907 } 4908 4909 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4910 { 4911 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4912 struct hclge_vport *vport = hdev->vport; 4913 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4914 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4915 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4916 struct hnae3_tc_info *tc_info; 4917 u16 roundup_size; 4918 u16 rss_size; 4919 int i; 4920 4921 tc_info = &vport->nic.kinfo.tc_info; 4922 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4923 rss_size = tc_info->tqp_count[i]; 4924 tc_valid[i] = 0; 4925 4926 if (!(hdev->hw_tc_map & BIT(i))) 4927 continue; 4928 4929 /* tc_size set to hardware is the log2 of roundup power of two 4930 * of rss_size, the acutal queue size is limited by indirection 4931 * table. 4932 */ 4933 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4934 rss_size == 0) { 4935 dev_err(&hdev->pdev->dev, 4936 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4937 rss_size); 4938 return -EINVAL; 4939 } 4940 4941 roundup_size = roundup_pow_of_two(rss_size); 4942 roundup_size = ilog2(roundup_size); 4943 4944 tc_valid[i] = 1; 4945 tc_size[i] = roundup_size; 4946 tc_offset[i] = tc_info->tqp_offset[i]; 4947 } 4948 4949 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4950 tc_size); 4951 } 4952 4953 int hclge_rss_init_hw(struct hclge_dev *hdev) 4954 { 4955 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4956 u8 *key = hdev->rss_cfg.rss_hash_key; 4957 u8 hfunc = hdev->rss_cfg.rss_algo; 4958 int ret; 4959 4960 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4961 rss_indir); 4962 if (ret) 4963 return ret; 4964 4965 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4966 if (ret) 4967 return ret; 4968 4969 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4970 if (ret) 4971 return ret; 4972 4973 return hclge_init_rss_tc_mode(hdev); 4974 } 4975 4976 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4977 int vector_id, bool en, 4978 struct hnae3_ring_chain_node *ring_chain) 4979 { 4980 struct hclge_dev *hdev = vport->back; 4981 struct hnae3_ring_chain_node *node; 4982 struct hclge_desc desc; 4983 struct hclge_ctrl_vector_chain_cmd *req = 4984 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4985 enum hclge_comm_cmd_status status; 4986 enum hclge_opcode_type op; 4987 u16 tqp_type_and_id; 4988 int i; 4989 4990 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4991 hclge_cmd_setup_basic_desc(&desc, op, false); 4992 req->int_vector_id_l = hnae3_get_field(vector_id, 4993 HCLGE_VECTOR_ID_L_M, 4994 HCLGE_VECTOR_ID_L_S); 4995 req->int_vector_id_h = hnae3_get_field(vector_id, 4996 HCLGE_VECTOR_ID_H_M, 4997 HCLGE_VECTOR_ID_H_S); 4998 4999 i = 0; 5000 for (node = ring_chain; node; node = node->next) { 5001 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5002 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5003 HCLGE_INT_TYPE_S, 5004 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5005 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5006 HCLGE_TQP_ID_S, node->tqp_index); 5007 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5008 HCLGE_INT_GL_IDX_S, 5009 hnae3_get_field(node->int_gl_idx, 5010 HNAE3_RING_GL_IDX_M, 5011 HNAE3_RING_GL_IDX_S)); 5012 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5013 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5014 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5015 req->vfid = vport->vport_id; 5016 5017 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5018 if (status) { 5019 dev_err(&hdev->pdev->dev, 5020 "Map TQP fail, status is %d.\n", 5021 status); 5022 return -EIO; 5023 } 5024 i = 0; 5025 5026 hclge_cmd_setup_basic_desc(&desc, 5027 op, 5028 false); 5029 req->int_vector_id_l = 5030 hnae3_get_field(vector_id, 5031 HCLGE_VECTOR_ID_L_M, 5032 HCLGE_VECTOR_ID_L_S); 5033 req->int_vector_id_h = 5034 hnae3_get_field(vector_id, 5035 HCLGE_VECTOR_ID_H_M, 5036 HCLGE_VECTOR_ID_H_S); 5037 } 5038 } 5039 5040 if (i > 0) { 5041 req->int_cause_num = i; 5042 req->vfid = vport->vport_id; 5043 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5044 if (status) { 5045 dev_err(&hdev->pdev->dev, 5046 "Map TQP fail, status is %d.\n", status); 5047 return -EIO; 5048 } 5049 } 5050 5051 return 0; 5052 } 5053 5054 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5055 struct hnae3_ring_chain_node *ring_chain) 5056 { 5057 struct hclge_vport *vport = hclge_get_vport(handle); 5058 struct hclge_dev *hdev = vport->back; 5059 int vector_id; 5060 5061 vector_id = hclge_get_vector_index(hdev, vector); 5062 if (vector_id < 0) { 5063 dev_err(&hdev->pdev->dev, 5064 "failed to get vector index. vector=%d\n", vector); 5065 return vector_id; 5066 } 5067 5068 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5069 } 5070 5071 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5072 struct hnae3_ring_chain_node *ring_chain) 5073 { 5074 struct hclge_vport *vport = hclge_get_vport(handle); 5075 struct hclge_dev *hdev = vport->back; 5076 int vector_id, ret; 5077 5078 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5079 return 0; 5080 5081 vector_id = hclge_get_vector_index(hdev, vector); 5082 if (vector_id < 0) { 5083 dev_err(&handle->pdev->dev, 5084 "Get vector index fail. ret =%d\n", vector_id); 5085 return vector_id; 5086 } 5087 5088 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5089 if (ret) 5090 dev_err(&handle->pdev->dev, 5091 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5092 vector_id, ret); 5093 5094 return ret; 5095 } 5096 5097 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5098 bool en_uc, bool en_mc, bool en_bc) 5099 { 5100 struct hclge_vport *vport = &hdev->vport[vf_id]; 5101 struct hnae3_handle *handle = &vport->nic; 5102 struct hclge_promisc_cfg_cmd *req; 5103 struct hclge_desc desc; 5104 bool uc_tx_en = en_uc; 5105 u8 promisc_cfg = 0; 5106 int ret; 5107 5108 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5109 5110 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5111 req->vf_id = vf_id; 5112 5113 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5114 uc_tx_en = false; 5115 5116 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5117 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5118 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5119 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5120 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5121 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5122 req->extend_promisc = promisc_cfg; 5123 5124 /* to be compatible with DEVICE_VERSION_V1/2 */ 5125 promisc_cfg = 0; 5126 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5129 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5130 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5131 req->promisc = promisc_cfg; 5132 5133 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5134 if (ret) 5135 dev_err(&hdev->pdev->dev, 5136 "failed to set vport %u promisc mode, ret = %d.\n", 5137 vf_id, ret); 5138 5139 return ret; 5140 } 5141 5142 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5143 bool en_mc_pmc, bool en_bc_pmc) 5144 { 5145 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5146 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5147 } 5148 5149 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5150 bool en_mc_pmc) 5151 { 5152 struct hclge_vport *vport = hclge_get_vport(handle); 5153 struct hclge_dev *hdev = vport->back; 5154 bool en_bc_pmc = true; 5155 5156 /* For device whose version below V2, if broadcast promisc enabled, 5157 * vlan filter is always bypassed. So broadcast promisc should be 5158 * disabled until user enable promisc mode 5159 */ 5160 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5161 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5162 5163 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5164 en_bc_pmc); 5165 } 5166 5167 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5168 { 5169 struct hclge_vport *vport = hclge_get_vport(handle); 5170 5171 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5172 } 5173 5174 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5175 { 5176 if (hlist_empty(&hdev->fd_rule_list)) 5177 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5178 } 5179 5180 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5181 { 5182 if (!test_bit(location, hdev->fd_bmap)) { 5183 set_bit(location, hdev->fd_bmap); 5184 hdev->hclge_fd_rule_num++; 5185 } 5186 } 5187 5188 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5189 { 5190 if (test_bit(location, hdev->fd_bmap)) { 5191 clear_bit(location, hdev->fd_bmap); 5192 hdev->hclge_fd_rule_num--; 5193 } 5194 } 5195 5196 static void hclge_fd_free_node(struct hclge_dev *hdev, 5197 struct hclge_fd_rule *rule) 5198 { 5199 hlist_del(&rule->rule_node); 5200 kfree(rule); 5201 hclge_sync_fd_state(hdev); 5202 } 5203 5204 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5205 struct hclge_fd_rule *old_rule, 5206 struct hclge_fd_rule *new_rule, 5207 enum HCLGE_FD_NODE_STATE state) 5208 { 5209 switch (state) { 5210 case HCLGE_FD_TO_ADD: 5211 case HCLGE_FD_ACTIVE: 5212 /* 1) if the new state is TO_ADD, just replace the old rule 5213 * with the same location, no matter its state, because the 5214 * new rule will be configured to the hardware. 5215 * 2) if the new state is ACTIVE, it means the new rule 5216 * has been configured to the hardware, so just replace 5217 * the old rule node with the same location. 5218 * 3) for it doesn't add a new node to the list, so it's 5219 * unnecessary to update the rule number and fd_bmap. 5220 */ 5221 new_rule->rule_node.next = old_rule->rule_node.next; 5222 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5223 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5224 kfree(new_rule); 5225 break; 5226 case HCLGE_FD_DELETED: 5227 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5228 hclge_fd_free_node(hdev, old_rule); 5229 break; 5230 case HCLGE_FD_TO_DEL: 5231 /* if new request is TO_DEL, and old rule is existent 5232 * 1) the state of old rule is TO_DEL, we need do nothing, 5233 * because we delete rule by location, other rule content 5234 * is unncessary. 5235 * 2) the state of old rule is ACTIVE, we need to change its 5236 * state to TO_DEL, so the rule will be deleted when periodic 5237 * task being scheduled. 5238 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5239 * been added to hardware, so we just delete the rule node from 5240 * fd_rule_list directly. 5241 */ 5242 if (old_rule->state == HCLGE_FD_TO_ADD) { 5243 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5244 hclge_fd_free_node(hdev, old_rule); 5245 return; 5246 } 5247 old_rule->state = HCLGE_FD_TO_DEL; 5248 break; 5249 } 5250 } 5251 5252 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5253 u16 location, 5254 struct hclge_fd_rule **parent) 5255 { 5256 struct hclge_fd_rule *rule; 5257 struct hlist_node *node; 5258 5259 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5260 if (rule->location == location) 5261 return rule; 5262 else if (rule->location > location) 5263 return NULL; 5264 /* record the parent node, use to keep the nodes in fd_rule_list 5265 * in ascend order. 5266 */ 5267 *parent = rule; 5268 } 5269 5270 return NULL; 5271 } 5272 5273 /* insert fd rule node in ascend order according to rule->location */ 5274 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5275 struct hclge_fd_rule *rule, 5276 struct hclge_fd_rule *parent) 5277 { 5278 INIT_HLIST_NODE(&rule->rule_node); 5279 5280 if (parent) 5281 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5282 else 5283 hlist_add_head(&rule->rule_node, hlist); 5284 } 5285 5286 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5287 struct hclge_fd_user_def_cfg *cfg) 5288 { 5289 struct hclge_fd_user_def_cfg_cmd *req; 5290 struct hclge_desc desc; 5291 u16 data = 0; 5292 int ret; 5293 5294 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5295 5296 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5297 5298 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5299 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5300 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5301 req->ol2_cfg = cpu_to_le16(data); 5302 5303 data = 0; 5304 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5305 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5306 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5307 req->ol3_cfg = cpu_to_le16(data); 5308 5309 data = 0; 5310 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5311 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5312 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5313 req->ol4_cfg = cpu_to_le16(data); 5314 5315 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5316 if (ret) 5317 dev_err(&hdev->pdev->dev, 5318 "failed to set fd user def data, ret= %d\n", ret); 5319 return ret; 5320 } 5321 5322 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5323 { 5324 int ret; 5325 5326 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5327 return; 5328 5329 if (!locked) 5330 spin_lock_bh(&hdev->fd_rule_lock); 5331 5332 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5333 if (ret) 5334 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5335 5336 if (!locked) 5337 spin_unlock_bh(&hdev->fd_rule_lock); 5338 } 5339 5340 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5341 struct hclge_fd_rule *rule) 5342 { 5343 struct hlist_head *hlist = &hdev->fd_rule_list; 5344 struct hclge_fd_rule *fd_rule, *parent = NULL; 5345 struct hclge_fd_user_def_info *info, *old_info; 5346 struct hclge_fd_user_def_cfg *cfg; 5347 5348 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5349 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5350 return 0; 5351 5352 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5353 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5354 info = &rule->ep.user_def; 5355 5356 if (!cfg->ref_cnt || cfg->offset == info->offset) 5357 return 0; 5358 5359 if (cfg->ref_cnt > 1) 5360 goto error; 5361 5362 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5363 if (fd_rule) { 5364 old_info = &fd_rule->ep.user_def; 5365 if (info->layer == old_info->layer) 5366 return 0; 5367 } 5368 5369 error: 5370 dev_err(&hdev->pdev->dev, 5371 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5372 info->layer + 1); 5373 return -ENOSPC; 5374 } 5375 5376 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5377 struct hclge_fd_rule *rule) 5378 { 5379 struct hclge_fd_user_def_cfg *cfg; 5380 5381 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5382 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5383 return; 5384 5385 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5386 if (!cfg->ref_cnt) { 5387 cfg->offset = rule->ep.user_def.offset; 5388 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5389 } 5390 cfg->ref_cnt++; 5391 } 5392 5393 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5394 struct hclge_fd_rule *rule) 5395 { 5396 struct hclge_fd_user_def_cfg *cfg; 5397 5398 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5399 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5400 return; 5401 5402 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5403 if (!cfg->ref_cnt) 5404 return; 5405 5406 cfg->ref_cnt--; 5407 if (!cfg->ref_cnt) { 5408 cfg->offset = 0; 5409 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5410 } 5411 } 5412 5413 static void hclge_update_fd_list(struct hclge_dev *hdev, 5414 enum HCLGE_FD_NODE_STATE state, u16 location, 5415 struct hclge_fd_rule *new_rule) 5416 { 5417 struct hlist_head *hlist = &hdev->fd_rule_list; 5418 struct hclge_fd_rule *fd_rule, *parent = NULL; 5419 5420 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5421 if (fd_rule) { 5422 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5423 if (state == HCLGE_FD_ACTIVE) 5424 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5425 hclge_sync_fd_user_def_cfg(hdev, true); 5426 5427 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5428 return; 5429 } 5430 5431 /* it's unlikely to fail here, because we have checked the rule 5432 * exist before. 5433 */ 5434 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5435 dev_warn(&hdev->pdev->dev, 5436 "failed to delete fd rule %u, it's inexistent\n", 5437 location); 5438 return; 5439 } 5440 5441 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5442 hclge_sync_fd_user_def_cfg(hdev, true); 5443 5444 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5445 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5446 5447 if (state == HCLGE_FD_TO_ADD) { 5448 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5449 hclge_task_schedule(hdev, 0); 5450 } 5451 } 5452 5453 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5454 { 5455 struct hclge_get_fd_mode_cmd *req; 5456 struct hclge_desc desc; 5457 int ret; 5458 5459 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5460 5461 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5462 5463 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5464 if (ret) { 5465 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5466 return ret; 5467 } 5468 5469 *fd_mode = req->mode; 5470 5471 return ret; 5472 } 5473 5474 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5475 u32 *stage1_entry_num, 5476 u32 *stage2_entry_num, 5477 u16 *stage1_counter_num, 5478 u16 *stage2_counter_num) 5479 { 5480 struct hclge_get_fd_allocation_cmd *req; 5481 struct hclge_desc desc; 5482 int ret; 5483 5484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5485 5486 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5487 5488 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5489 if (ret) { 5490 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5491 ret); 5492 return ret; 5493 } 5494 5495 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5496 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5497 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5498 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5499 5500 return ret; 5501 } 5502 5503 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5504 enum HCLGE_FD_STAGE stage_num) 5505 { 5506 struct hclge_set_fd_key_config_cmd *req; 5507 struct hclge_fd_key_cfg *stage; 5508 struct hclge_desc desc; 5509 int ret; 5510 5511 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5512 5513 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5514 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5515 req->stage = stage_num; 5516 req->key_select = stage->key_sel; 5517 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5518 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5519 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5520 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5521 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5522 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5523 5524 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5525 if (ret) 5526 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5527 5528 return ret; 5529 } 5530 5531 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5532 { 5533 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5534 5535 spin_lock_bh(&hdev->fd_rule_lock); 5536 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5537 spin_unlock_bh(&hdev->fd_rule_lock); 5538 5539 hclge_fd_set_user_def_cmd(hdev, cfg); 5540 } 5541 5542 static int hclge_init_fd_config(struct hclge_dev *hdev) 5543 { 5544 #define LOW_2_WORDS 0x03 5545 struct hclge_fd_key_cfg *key_cfg; 5546 int ret; 5547 5548 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5549 return 0; 5550 5551 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5552 if (ret) 5553 return ret; 5554 5555 switch (hdev->fd_cfg.fd_mode) { 5556 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5557 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5558 break; 5559 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5560 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5561 break; 5562 default: 5563 dev_err(&hdev->pdev->dev, 5564 "Unsupported flow director mode %u\n", 5565 hdev->fd_cfg.fd_mode); 5566 return -EOPNOTSUPP; 5567 } 5568 5569 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5570 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5571 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5572 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5573 key_cfg->outer_sipv6_word_en = 0; 5574 key_cfg->outer_dipv6_word_en = 0; 5575 5576 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5577 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5578 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5579 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5580 5581 /* If use max 400bit key, we can support tuples for ether type */ 5582 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5583 key_cfg->tuple_active |= 5584 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5585 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5586 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5587 } 5588 5589 /* roce_type is used to filter roce frames 5590 * dst_vport is used to specify the rule 5591 */ 5592 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5593 5594 ret = hclge_get_fd_allocation(hdev, 5595 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5596 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5597 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5598 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5599 if (ret) 5600 return ret; 5601 5602 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5603 } 5604 5605 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5606 int loc, u8 *key, bool is_add) 5607 { 5608 struct hclge_fd_tcam_config_1_cmd *req1; 5609 struct hclge_fd_tcam_config_2_cmd *req2; 5610 struct hclge_fd_tcam_config_3_cmd *req3; 5611 struct hclge_desc desc[3]; 5612 int ret; 5613 5614 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5615 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5616 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5617 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5618 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5619 5620 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5621 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5622 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5623 5624 req1->stage = stage; 5625 req1->xy_sel = sel_x ? 1 : 0; 5626 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5627 req1->index = cpu_to_le32(loc); 5628 req1->entry_vld = sel_x ? is_add : 0; 5629 5630 if (key) { 5631 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5632 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5633 sizeof(req2->tcam_data)); 5634 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5635 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5636 } 5637 5638 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5639 if (ret) 5640 dev_err(&hdev->pdev->dev, 5641 "config tcam key fail, ret=%d\n", 5642 ret); 5643 5644 return ret; 5645 } 5646 5647 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5648 struct hclge_fd_ad_data *action) 5649 { 5650 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5651 struct hclge_fd_ad_config_cmd *req; 5652 struct hclge_desc desc; 5653 u64 ad_data = 0; 5654 int ret; 5655 5656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5657 5658 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5659 req->index = cpu_to_le32(loc); 5660 req->stage = stage; 5661 5662 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5663 action->write_rule_id_to_bd); 5664 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5665 action->rule_id); 5666 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5667 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5668 action->override_tc); 5669 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5670 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5671 } 5672 ad_data <<= 32; 5673 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5674 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5675 action->forward_to_direct_queue); 5676 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5677 action->queue_id); 5678 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5679 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5680 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5681 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5682 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5683 action->counter_id); 5684 5685 req->ad_data = cpu_to_le64(ad_data); 5686 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5687 if (ret) 5688 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5689 5690 return ret; 5691 } 5692 5693 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5694 struct hclge_fd_rule *rule) 5695 { 5696 int offset, moffset, ip_offset; 5697 enum HCLGE_FD_KEY_OPT key_opt; 5698 u16 tmp_x_s, tmp_y_s; 5699 u32 tmp_x_l, tmp_y_l; 5700 u8 *p = (u8 *)rule; 5701 int i; 5702 5703 if (rule->unused_tuple & BIT(tuple_bit)) 5704 return true; 5705 5706 key_opt = tuple_key_info[tuple_bit].key_opt; 5707 offset = tuple_key_info[tuple_bit].offset; 5708 moffset = tuple_key_info[tuple_bit].moffset; 5709 5710 switch (key_opt) { 5711 case KEY_OPT_U8: 5712 calc_x(*key_x, p[offset], p[moffset]); 5713 calc_y(*key_y, p[offset], p[moffset]); 5714 5715 return true; 5716 case KEY_OPT_LE16: 5717 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5718 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5719 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5720 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5721 5722 return true; 5723 case KEY_OPT_LE32: 5724 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5725 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5726 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5727 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5728 5729 return true; 5730 case KEY_OPT_MAC: 5731 for (i = 0; i < ETH_ALEN; i++) { 5732 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5733 p[moffset + i]); 5734 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5735 p[moffset + i]); 5736 } 5737 5738 return true; 5739 case KEY_OPT_IP: 5740 ip_offset = IPV4_INDEX * sizeof(u32); 5741 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5742 *(u32 *)(&p[moffset + ip_offset])); 5743 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5744 *(u32 *)(&p[moffset + ip_offset])); 5745 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5746 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5747 5748 return true; 5749 default: 5750 return false; 5751 } 5752 } 5753 5754 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5755 u8 vf_id, u8 network_port_id) 5756 { 5757 u32 port_number = 0; 5758 5759 if (port_type == HOST_PORT) { 5760 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5761 pf_id); 5762 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5763 vf_id); 5764 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5765 } else { 5766 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5767 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5768 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5769 } 5770 5771 return port_number; 5772 } 5773 5774 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5775 __le32 *key_x, __le32 *key_y, 5776 struct hclge_fd_rule *rule) 5777 { 5778 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5779 u8 cur_pos = 0, tuple_size, shift_bits; 5780 unsigned int i; 5781 5782 for (i = 0; i < MAX_META_DATA; i++) { 5783 tuple_size = meta_data_key_info[i].key_length; 5784 tuple_bit = key_cfg->meta_data_active & BIT(i); 5785 5786 switch (tuple_bit) { 5787 case BIT(ROCE_TYPE): 5788 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5789 cur_pos += tuple_size; 5790 break; 5791 case BIT(DST_VPORT): 5792 port_number = hclge_get_port_number(HOST_PORT, 0, 5793 rule->vf_id, 0); 5794 hnae3_set_field(meta_data, 5795 GENMASK(cur_pos + tuple_size, cur_pos), 5796 cur_pos, port_number); 5797 cur_pos += tuple_size; 5798 break; 5799 default: 5800 break; 5801 } 5802 } 5803 5804 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5805 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5806 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5807 5808 *key_x = cpu_to_le32(tmp_x << shift_bits); 5809 *key_y = cpu_to_le32(tmp_y << shift_bits); 5810 } 5811 5812 /* A complete key is combined with meta data key and tuple key. 5813 * Meta data key is stored at the MSB region, and tuple key is stored at 5814 * the LSB region, unused bits will be filled 0. 5815 */ 5816 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5817 struct hclge_fd_rule *rule) 5818 { 5819 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5820 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5821 u8 *cur_key_x, *cur_key_y; 5822 u8 meta_data_region; 5823 u8 tuple_size; 5824 int ret; 5825 u32 i; 5826 5827 memset(key_x, 0, sizeof(key_x)); 5828 memset(key_y, 0, sizeof(key_y)); 5829 cur_key_x = key_x; 5830 cur_key_y = key_y; 5831 5832 for (i = 0; i < MAX_TUPLE; i++) { 5833 bool tuple_valid; 5834 5835 tuple_size = tuple_key_info[i].key_length / 8; 5836 if (!(key_cfg->tuple_active & BIT(i))) 5837 continue; 5838 5839 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5840 cur_key_y, rule); 5841 if (tuple_valid) { 5842 cur_key_x += tuple_size; 5843 cur_key_y += tuple_size; 5844 } 5845 } 5846 5847 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5848 MAX_META_DATA_LENGTH / 8; 5849 5850 hclge_fd_convert_meta_data(key_cfg, 5851 (__le32 *)(key_x + meta_data_region), 5852 (__le32 *)(key_y + meta_data_region), 5853 rule); 5854 5855 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5856 true); 5857 if (ret) { 5858 dev_err(&hdev->pdev->dev, 5859 "fd key_y config fail, loc=%u, ret=%d\n", 5860 rule->queue_id, ret); 5861 return ret; 5862 } 5863 5864 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5865 true); 5866 if (ret) 5867 dev_err(&hdev->pdev->dev, 5868 "fd key_x config fail, loc=%u, ret=%d\n", 5869 rule->queue_id, ret); 5870 return ret; 5871 } 5872 5873 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5874 struct hclge_fd_rule *rule) 5875 { 5876 struct hclge_vport *vport = hdev->vport; 5877 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5878 struct hclge_fd_ad_data ad_data; 5879 5880 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5881 ad_data.ad_id = rule->location; 5882 5883 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5884 ad_data.drop_packet = true; 5885 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5886 ad_data.override_tc = true; 5887 ad_data.queue_id = 5888 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5889 ad_data.tc_size = 5890 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5891 } else { 5892 ad_data.forward_to_direct_queue = true; 5893 ad_data.queue_id = rule->queue_id; 5894 } 5895 5896 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5897 ad_data.use_counter = true; 5898 ad_data.counter_id = rule->vf_id % 5899 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5900 } else { 5901 ad_data.use_counter = false; 5902 ad_data.counter_id = 0; 5903 } 5904 5905 ad_data.use_next_stage = false; 5906 ad_data.next_input_key = 0; 5907 5908 ad_data.write_rule_id_to_bd = true; 5909 ad_data.rule_id = rule->location; 5910 5911 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5912 } 5913 5914 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5915 u32 *unused_tuple) 5916 { 5917 if (!spec || !unused_tuple) 5918 return -EINVAL; 5919 5920 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5921 5922 if (!spec->ip4src) 5923 *unused_tuple |= BIT(INNER_SRC_IP); 5924 5925 if (!spec->ip4dst) 5926 *unused_tuple |= BIT(INNER_DST_IP); 5927 5928 if (!spec->psrc) 5929 *unused_tuple |= BIT(INNER_SRC_PORT); 5930 5931 if (!spec->pdst) 5932 *unused_tuple |= BIT(INNER_DST_PORT); 5933 5934 if (!spec->tos) 5935 *unused_tuple |= BIT(INNER_IP_TOS); 5936 5937 return 0; 5938 } 5939 5940 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5941 u32 *unused_tuple) 5942 { 5943 if (!spec || !unused_tuple) 5944 return -EINVAL; 5945 5946 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5947 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5948 5949 if (!spec->ip4src) 5950 *unused_tuple |= BIT(INNER_SRC_IP); 5951 5952 if (!spec->ip4dst) 5953 *unused_tuple |= BIT(INNER_DST_IP); 5954 5955 if (!spec->tos) 5956 *unused_tuple |= BIT(INNER_IP_TOS); 5957 5958 if (!spec->proto) 5959 *unused_tuple |= BIT(INNER_IP_PROTO); 5960 5961 if (spec->l4_4_bytes) 5962 return -EOPNOTSUPP; 5963 5964 if (spec->ip_ver != ETH_RX_NFC_IP4) 5965 return -EOPNOTSUPP; 5966 5967 return 0; 5968 } 5969 5970 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5971 u32 *unused_tuple) 5972 { 5973 if (!spec || !unused_tuple) 5974 return -EINVAL; 5975 5976 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5977 5978 /* check whether src/dst ip address used */ 5979 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5980 *unused_tuple |= BIT(INNER_SRC_IP); 5981 5982 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5983 *unused_tuple |= BIT(INNER_DST_IP); 5984 5985 if (!spec->psrc) 5986 *unused_tuple |= BIT(INNER_SRC_PORT); 5987 5988 if (!spec->pdst) 5989 *unused_tuple |= BIT(INNER_DST_PORT); 5990 5991 if (!spec->tclass) 5992 *unused_tuple |= BIT(INNER_IP_TOS); 5993 5994 return 0; 5995 } 5996 5997 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5998 u32 *unused_tuple) 5999 { 6000 if (!spec || !unused_tuple) 6001 return -EINVAL; 6002 6003 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6004 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 6005 6006 /* check whether src/dst ip address used */ 6007 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6008 *unused_tuple |= BIT(INNER_SRC_IP); 6009 6010 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6011 *unused_tuple |= BIT(INNER_DST_IP); 6012 6013 if (!spec->l4_proto) 6014 *unused_tuple |= BIT(INNER_IP_PROTO); 6015 6016 if (!spec->tclass) 6017 *unused_tuple |= BIT(INNER_IP_TOS); 6018 6019 if (spec->l4_4_bytes) 6020 return -EOPNOTSUPP; 6021 6022 return 0; 6023 } 6024 6025 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6026 { 6027 if (!spec || !unused_tuple) 6028 return -EINVAL; 6029 6030 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6031 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6032 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6033 6034 if (is_zero_ether_addr(spec->h_source)) 6035 *unused_tuple |= BIT(INNER_SRC_MAC); 6036 6037 if (is_zero_ether_addr(spec->h_dest)) 6038 *unused_tuple |= BIT(INNER_DST_MAC); 6039 6040 if (!spec->h_proto) 6041 *unused_tuple |= BIT(INNER_ETH_TYPE); 6042 6043 return 0; 6044 } 6045 6046 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6047 struct ethtool_rx_flow_spec *fs, 6048 u32 *unused_tuple) 6049 { 6050 if (fs->flow_type & FLOW_EXT) { 6051 if (fs->h_ext.vlan_etype) { 6052 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6053 return -EOPNOTSUPP; 6054 } 6055 6056 if (!fs->h_ext.vlan_tci) 6057 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6058 6059 if (fs->m_ext.vlan_tci && 6060 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6061 dev_err(&hdev->pdev->dev, 6062 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6063 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6064 return -EINVAL; 6065 } 6066 } else { 6067 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6068 } 6069 6070 if (fs->flow_type & FLOW_MAC_EXT) { 6071 if (hdev->fd_cfg.fd_mode != 6072 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6073 dev_err(&hdev->pdev->dev, 6074 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6075 return -EOPNOTSUPP; 6076 } 6077 6078 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6079 *unused_tuple |= BIT(INNER_DST_MAC); 6080 else 6081 *unused_tuple &= ~BIT(INNER_DST_MAC); 6082 } 6083 6084 return 0; 6085 } 6086 6087 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6088 struct hclge_fd_user_def_info *info) 6089 { 6090 switch (flow_type) { 6091 case ETHER_FLOW: 6092 info->layer = HCLGE_FD_USER_DEF_L2; 6093 *unused_tuple &= ~BIT(INNER_L2_RSV); 6094 break; 6095 case IP_USER_FLOW: 6096 case IPV6_USER_FLOW: 6097 info->layer = HCLGE_FD_USER_DEF_L3; 6098 *unused_tuple &= ~BIT(INNER_L3_RSV); 6099 break; 6100 case TCP_V4_FLOW: 6101 case UDP_V4_FLOW: 6102 case TCP_V6_FLOW: 6103 case UDP_V6_FLOW: 6104 info->layer = HCLGE_FD_USER_DEF_L4; 6105 *unused_tuple &= ~BIT(INNER_L4_RSV); 6106 break; 6107 default: 6108 return -EOPNOTSUPP; 6109 } 6110 6111 return 0; 6112 } 6113 6114 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6115 { 6116 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6117 } 6118 6119 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6120 struct ethtool_rx_flow_spec *fs, 6121 u32 *unused_tuple, 6122 struct hclge_fd_user_def_info *info) 6123 { 6124 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6125 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6126 u16 data, offset, data_mask, offset_mask; 6127 int ret; 6128 6129 info->layer = HCLGE_FD_USER_DEF_NONE; 6130 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6131 6132 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6133 return 0; 6134 6135 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6136 * for data, and bit32~47 is used for offset. 6137 */ 6138 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6139 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6140 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6141 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6142 6143 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6144 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6145 return -EOPNOTSUPP; 6146 } 6147 6148 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6149 dev_err(&hdev->pdev->dev, 6150 "user-def offset[%u] should be no more than %u\n", 6151 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6152 return -EINVAL; 6153 } 6154 6155 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6156 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6157 return -EINVAL; 6158 } 6159 6160 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6161 if (ret) { 6162 dev_err(&hdev->pdev->dev, 6163 "unsupported flow type for user-def bytes, ret = %d\n", 6164 ret); 6165 return ret; 6166 } 6167 6168 info->data = data; 6169 info->data_mask = data_mask; 6170 info->offset = offset; 6171 6172 return 0; 6173 } 6174 6175 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6176 struct ethtool_rx_flow_spec *fs, 6177 u32 *unused_tuple, 6178 struct hclge_fd_user_def_info *info) 6179 { 6180 u32 flow_type; 6181 int ret; 6182 6183 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6184 dev_err(&hdev->pdev->dev, 6185 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6186 fs->location, 6187 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6188 return -EINVAL; 6189 } 6190 6191 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6192 if (ret) 6193 return ret; 6194 6195 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6196 switch (flow_type) { 6197 case SCTP_V4_FLOW: 6198 case TCP_V4_FLOW: 6199 case UDP_V4_FLOW: 6200 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6201 unused_tuple); 6202 break; 6203 case IP_USER_FLOW: 6204 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6205 unused_tuple); 6206 break; 6207 case SCTP_V6_FLOW: 6208 case TCP_V6_FLOW: 6209 case UDP_V6_FLOW: 6210 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6211 unused_tuple); 6212 break; 6213 case IPV6_USER_FLOW: 6214 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6215 unused_tuple); 6216 break; 6217 case ETHER_FLOW: 6218 if (hdev->fd_cfg.fd_mode != 6219 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6220 dev_err(&hdev->pdev->dev, 6221 "ETHER_FLOW is not supported in current fd mode!\n"); 6222 return -EOPNOTSUPP; 6223 } 6224 6225 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6226 unused_tuple); 6227 break; 6228 default: 6229 dev_err(&hdev->pdev->dev, 6230 "unsupported protocol type, protocol type = %#x\n", 6231 flow_type); 6232 return -EOPNOTSUPP; 6233 } 6234 6235 if (ret) { 6236 dev_err(&hdev->pdev->dev, 6237 "failed to check flow union tuple, ret = %d\n", 6238 ret); 6239 return ret; 6240 } 6241 6242 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6243 } 6244 6245 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6246 struct hclge_fd_rule *rule, u8 ip_proto) 6247 { 6248 rule->tuples.src_ip[IPV4_INDEX] = 6249 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6250 rule->tuples_mask.src_ip[IPV4_INDEX] = 6251 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6252 6253 rule->tuples.dst_ip[IPV4_INDEX] = 6254 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6255 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6256 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6257 6258 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6259 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6260 6261 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6262 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6263 6264 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6265 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6266 6267 rule->tuples.ether_proto = ETH_P_IP; 6268 rule->tuples_mask.ether_proto = 0xFFFF; 6269 6270 rule->tuples.ip_proto = ip_proto; 6271 rule->tuples_mask.ip_proto = 0xFF; 6272 } 6273 6274 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6275 struct hclge_fd_rule *rule) 6276 { 6277 rule->tuples.src_ip[IPV4_INDEX] = 6278 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6279 rule->tuples_mask.src_ip[IPV4_INDEX] = 6280 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6281 6282 rule->tuples.dst_ip[IPV4_INDEX] = 6283 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6284 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6285 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6286 6287 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6288 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6289 6290 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6291 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6292 6293 rule->tuples.ether_proto = ETH_P_IP; 6294 rule->tuples_mask.ether_proto = 0xFFFF; 6295 } 6296 6297 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6298 struct hclge_fd_rule *rule, u8 ip_proto) 6299 { 6300 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6301 IPV6_SIZE); 6302 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6303 IPV6_SIZE); 6304 6305 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6306 IPV6_SIZE); 6307 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6308 IPV6_SIZE); 6309 6310 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6311 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6312 6313 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6314 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6315 6316 rule->tuples.ether_proto = ETH_P_IPV6; 6317 rule->tuples_mask.ether_proto = 0xFFFF; 6318 6319 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6320 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6321 6322 rule->tuples.ip_proto = ip_proto; 6323 rule->tuples_mask.ip_proto = 0xFF; 6324 } 6325 6326 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6327 struct hclge_fd_rule *rule) 6328 { 6329 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6330 IPV6_SIZE); 6331 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6332 IPV6_SIZE); 6333 6334 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6335 IPV6_SIZE); 6336 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6337 IPV6_SIZE); 6338 6339 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6340 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6341 6342 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6343 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6344 6345 rule->tuples.ether_proto = ETH_P_IPV6; 6346 rule->tuples_mask.ether_proto = 0xFFFF; 6347 } 6348 6349 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6350 struct hclge_fd_rule *rule) 6351 { 6352 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6353 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6354 6355 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6356 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6357 6358 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6359 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6360 } 6361 6362 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6363 struct hclge_fd_rule *rule) 6364 { 6365 switch (info->layer) { 6366 case HCLGE_FD_USER_DEF_L2: 6367 rule->tuples.l2_user_def = info->data; 6368 rule->tuples_mask.l2_user_def = info->data_mask; 6369 break; 6370 case HCLGE_FD_USER_DEF_L3: 6371 rule->tuples.l3_user_def = info->data; 6372 rule->tuples_mask.l3_user_def = info->data_mask; 6373 break; 6374 case HCLGE_FD_USER_DEF_L4: 6375 rule->tuples.l4_user_def = (u32)info->data << 16; 6376 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6377 break; 6378 default: 6379 break; 6380 } 6381 6382 rule->ep.user_def = *info; 6383 } 6384 6385 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6386 struct hclge_fd_rule *rule, 6387 struct hclge_fd_user_def_info *info) 6388 { 6389 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6390 6391 switch (flow_type) { 6392 case SCTP_V4_FLOW: 6393 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6394 break; 6395 case TCP_V4_FLOW: 6396 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6397 break; 6398 case UDP_V4_FLOW: 6399 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6400 break; 6401 case IP_USER_FLOW: 6402 hclge_fd_get_ip4_tuple(fs, rule); 6403 break; 6404 case SCTP_V6_FLOW: 6405 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6406 break; 6407 case TCP_V6_FLOW: 6408 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6409 break; 6410 case UDP_V6_FLOW: 6411 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6412 break; 6413 case IPV6_USER_FLOW: 6414 hclge_fd_get_ip6_tuple(fs, rule); 6415 break; 6416 case ETHER_FLOW: 6417 hclge_fd_get_ether_tuple(fs, rule); 6418 break; 6419 default: 6420 return -EOPNOTSUPP; 6421 } 6422 6423 if (fs->flow_type & FLOW_EXT) { 6424 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6425 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6426 hclge_fd_get_user_def_tuple(info, rule); 6427 } 6428 6429 if (fs->flow_type & FLOW_MAC_EXT) { 6430 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6431 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6432 } 6433 6434 return 0; 6435 } 6436 6437 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6438 struct hclge_fd_rule *rule) 6439 { 6440 int ret; 6441 6442 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6443 if (ret) 6444 return ret; 6445 6446 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6447 } 6448 6449 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6450 struct hclge_fd_rule *rule) 6451 { 6452 int ret; 6453 6454 spin_lock_bh(&hdev->fd_rule_lock); 6455 6456 if (hdev->fd_active_type != rule->rule_type && 6457 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6458 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6459 dev_err(&hdev->pdev->dev, 6460 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6461 rule->rule_type, hdev->fd_active_type); 6462 spin_unlock_bh(&hdev->fd_rule_lock); 6463 return -EINVAL; 6464 } 6465 6466 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6467 if (ret) 6468 goto out; 6469 6470 ret = hclge_clear_arfs_rules(hdev); 6471 if (ret) 6472 goto out; 6473 6474 ret = hclge_fd_config_rule(hdev, rule); 6475 if (ret) 6476 goto out; 6477 6478 rule->state = HCLGE_FD_ACTIVE; 6479 hdev->fd_active_type = rule->rule_type; 6480 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6481 6482 out: 6483 spin_unlock_bh(&hdev->fd_rule_lock); 6484 return ret; 6485 } 6486 6487 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6488 { 6489 struct hclge_vport *vport = hclge_get_vport(handle); 6490 struct hclge_dev *hdev = vport->back; 6491 6492 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6493 } 6494 6495 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6496 u16 *vport_id, u8 *action, u16 *queue_id) 6497 { 6498 struct hclge_vport *vport = hdev->vport; 6499 6500 if (ring_cookie == RX_CLS_FLOW_DISC) { 6501 *action = HCLGE_FD_ACTION_DROP_PACKET; 6502 } else { 6503 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6504 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6505 u16 tqps; 6506 6507 /* To keep consistent with user's configuration, minus 1 when 6508 * printing 'vf', because vf id from ethtool is added 1 for vf. 6509 */ 6510 if (vf > hdev->num_req_vfs) { 6511 dev_err(&hdev->pdev->dev, 6512 "Error: vf id (%u) should be less than %u\n", 6513 vf - 1U, hdev->num_req_vfs); 6514 return -EINVAL; 6515 } 6516 6517 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6518 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6519 6520 if (ring >= tqps) { 6521 dev_err(&hdev->pdev->dev, 6522 "Error: queue id (%u) > max tqp num (%u)\n", 6523 ring, tqps - 1U); 6524 return -EINVAL; 6525 } 6526 6527 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6528 *queue_id = ring; 6529 } 6530 6531 return 0; 6532 } 6533 6534 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6535 struct ethtool_rxnfc *cmd) 6536 { 6537 struct hclge_vport *vport = hclge_get_vport(handle); 6538 struct hclge_dev *hdev = vport->back; 6539 struct hclge_fd_user_def_info info; 6540 u16 dst_vport_id = 0, q_index = 0; 6541 struct ethtool_rx_flow_spec *fs; 6542 struct hclge_fd_rule *rule; 6543 u32 unused = 0; 6544 u8 action; 6545 int ret; 6546 6547 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6548 dev_err(&hdev->pdev->dev, 6549 "flow table director is not supported\n"); 6550 return -EOPNOTSUPP; 6551 } 6552 6553 if (!hdev->fd_en) { 6554 dev_err(&hdev->pdev->dev, 6555 "please enable flow director first\n"); 6556 return -EOPNOTSUPP; 6557 } 6558 6559 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6560 6561 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6562 if (ret) 6563 return ret; 6564 6565 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6566 &action, &q_index); 6567 if (ret) 6568 return ret; 6569 6570 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6571 if (!rule) 6572 return -ENOMEM; 6573 6574 ret = hclge_fd_get_tuple(fs, rule, &info); 6575 if (ret) { 6576 kfree(rule); 6577 return ret; 6578 } 6579 6580 rule->flow_type = fs->flow_type; 6581 rule->location = fs->location; 6582 rule->unused_tuple = unused; 6583 rule->vf_id = dst_vport_id; 6584 rule->queue_id = q_index; 6585 rule->action = action; 6586 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6587 6588 ret = hclge_add_fd_entry_common(hdev, rule); 6589 if (ret) 6590 kfree(rule); 6591 6592 return ret; 6593 } 6594 6595 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6596 struct ethtool_rxnfc *cmd) 6597 { 6598 struct hclge_vport *vport = hclge_get_vport(handle); 6599 struct hclge_dev *hdev = vport->back; 6600 struct ethtool_rx_flow_spec *fs; 6601 int ret; 6602 6603 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6604 return -EOPNOTSUPP; 6605 6606 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6607 6608 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6609 return -EINVAL; 6610 6611 spin_lock_bh(&hdev->fd_rule_lock); 6612 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6613 !test_bit(fs->location, hdev->fd_bmap)) { 6614 dev_err(&hdev->pdev->dev, 6615 "Delete fail, rule %u is inexistent\n", fs->location); 6616 spin_unlock_bh(&hdev->fd_rule_lock); 6617 return -ENOENT; 6618 } 6619 6620 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6621 NULL, false); 6622 if (ret) 6623 goto out; 6624 6625 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6626 6627 out: 6628 spin_unlock_bh(&hdev->fd_rule_lock); 6629 return ret; 6630 } 6631 6632 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6633 bool clear_list) 6634 { 6635 struct hclge_fd_rule *rule; 6636 struct hlist_node *node; 6637 u16 location; 6638 6639 spin_lock_bh(&hdev->fd_rule_lock); 6640 6641 for_each_set_bit(location, hdev->fd_bmap, 6642 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6643 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6644 NULL, false); 6645 6646 if (clear_list) { 6647 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6648 rule_node) { 6649 hlist_del(&rule->rule_node); 6650 kfree(rule); 6651 } 6652 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6653 hdev->hclge_fd_rule_num = 0; 6654 bitmap_zero(hdev->fd_bmap, 6655 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6656 } 6657 6658 spin_unlock_bh(&hdev->fd_rule_lock); 6659 } 6660 6661 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6662 { 6663 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6664 return; 6665 6666 hclge_clear_fd_rules_in_list(hdev, true); 6667 hclge_fd_disable_user_def(hdev); 6668 } 6669 6670 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6671 { 6672 struct hclge_vport *vport = hclge_get_vport(handle); 6673 struct hclge_dev *hdev = vport->back; 6674 struct hclge_fd_rule *rule; 6675 struct hlist_node *node; 6676 6677 /* Return ok here, because reset error handling will check this 6678 * return value. If error is returned here, the reset process will 6679 * fail. 6680 */ 6681 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6682 return 0; 6683 6684 /* if fd is disabled, should not restore it when reset */ 6685 if (!hdev->fd_en) 6686 return 0; 6687 6688 spin_lock_bh(&hdev->fd_rule_lock); 6689 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6690 if (rule->state == HCLGE_FD_ACTIVE) 6691 rule->state = HCLGE_FD_TO_ADD; 6692 } 6693 spin_unlock_bh(&hdev->fd_rule_lock); 6694 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6695 6696 return 0; 6697 } 6698 6699 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6700 struct ethtool_rxnfc *cmd) 6701 { 6702 struct hclge_vport *vport = hclge_get_vport(handle); 6703 struct hclge_dev *hdev = vport->back; 6704 6705 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6706 return -EOPNOTSUPP; 6707 6708 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6709 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6710 6711 return 0; 6712 } 6713 6714 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6715 struct ethtool_tcpip4_spec *spec, 6716 struct ethtool_tcpip4_spec *spec_mask) 6717 { 6718 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6719 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6720 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6721 6722 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6723 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6724 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6725 6726 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6727 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6728 0 : cpu_to_be16(rule->tuples_mask.src_port); 6729 6730 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6731 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6732 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6733 6734 spec->tos = rule->tuples.ip_tos; 6735 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6736 0 : rule->tuples_mask.ip_tos; 6737 } 6738 6739 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6740 struct ethtool_usrip4_spec *spec, 6741 struct ethtool_usrip4_spec *spec_mask) 6742 { 6743 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6744 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6745 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6746 6747 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6748 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6749 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6750 6751 spec->tos = rule->tuples.ip_tos; 6752 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6753 0 : rule->tuples_mask.ip_tos; 6754 6755 spec->proto = rule->tuples.ip_proto; 6756 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6757 0 : rule->tuples_mask.ip_proto; 6758 6759 spec->ip_ver = ETH_RX_NFC_IP4; 6760 } 6761 6762 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6763 struct ethtool_tcpip6_spec *spec, 6764 struct ethtool_tcpip6_spec *spec_mask) 6765 { 6766 cpu_to_be32_array(spec->ip6src, 6767 rule->tuples.src_ip, IPV6_SIZE); 6768 cpu_to_be32_array(spec->ip6dst, 6769 rule->tuples.dst_ip, IPV6_SIZE); 6770 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6771 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6772 else 6773 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6774 IPV6_SIZE); 6775 6776 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6777 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6778 else 6779 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6780 IPV6_SIZE); 6781 6782 spec->tclass = rule->tuples.ip_tos; 6783 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6784 0 : rule->tuples_mask.ip_tos; 6785 6786 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6787 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6788 0 : cpu_to_be16(rule->tuples_mask.src_port); 6789 6790 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6791 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6792 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6793 } 6794 6795 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6796 struct ethtool_usrip6_spec *spec, 6797 struct ethtool_usrip6_spec *spec_mask) 6798 { 6799 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6800 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6801 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6802 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6803 else 6804 cpu_to_be32_array(spec_mask->ip6src, 6805 rule->tuples_mask.src_ip, IPV6_SIZE); 6806 6807 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6808 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6809 else 6810 cpu_to_be32_array(spec_mask->ip6dst, 6811 rule->tuples_mask.dst_ip, IPV6_SIZE); 6812 6813 spec->tclass = rule->tuples.ip_tos; 6814 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6815 0 : rule->tuples_mask.ip_tos; 6816 6817 spec->l4_proto = rule->tuples.ip_proto; 6818 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6819 0 : rule->tuples_mask.ip_proto; 6820 } 6821 6822 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6823 struct ethhdr *spec, 6824 struct ethhdr *spec_mask) 6825 { 6826 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6827 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6828 6829 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6830 eth_zero_addr(spec_mask->h_source); 6831 else 6832 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6833 6834 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6835 eth_zero_addr(spec_mask->h_dest); 6836 else 6837 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6838 6839 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6840 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6841 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6842 } 6843 6844 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6845 struct hclge_fd_rule *rule) 6846 { 6847 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6848 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6849 fs->h_ext.data[0] = 0; 6850 fs->h_ext.data[1] = 0; 6851 fs->m_ext.data[0] = 0; 6852 fs->m_ext.data[1] = 0; 6853 } else { 6854 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6855 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6856 fs->m_ext.data[0] = 6857 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6858 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6859 } 6860 } 6861 6862 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6863 struct hclge_fd_rule *rule) 6864 { 6865 if (fs->flow_type & FLOW_EXT) { 6866 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6867 fs->m_ext.vlan_tci = 6868 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6869 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6870 6871 hclge_fd_get_user_def_info(fs, rule); 6872 } 6873 6874 if (fs->flow_type & FLOW_MAC_EXT) { 6875 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6876 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6877 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6878 else 6879 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6880 rule->tuples_mask.dst_mac); 6881 } 6882 } 6883 6884 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6885 u16 location) 6886 { 6887 struct hclge_fd_rule *rule = NULL; 6888 struct hlist_node *node2; 6889 6890 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6891 if (rule->location == location) 6892 return rule; 6893 else if (rule->location > location) 6894 return NULL; 6895 } 6896 6897 return NULL; 6898 } 6899 6900 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6901 struct hclge_fd_rule *rule) 6902 { 6903 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6904 fs->ring_cookie = RX_CLS_FLOW_DISC; 6905 } else { 6906 u64 vf_id; 6907 6908 fs->ring_cookie = rule->queue_id; 6909 vf_id = rule->vf_id; 6910 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6911 fs->ring_cookie |= vf_id; 6912 } 6913 } 6914 6915 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6916 struct ethtool_rxnfc *cmd) 6917 { 6918 struct hclge_vport *vport = hclge_get_vport(handle); 6919 struct hclge_fd_rule *rule = NULL; 6920 struct hclge_dev *hdev = vport->back; 6921 struct ethtool_rx_flow_spec *fs; 6922 6923 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6924 return -EOPNOTSUPP; 6925 6926 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6927 6928 spin_lock_bh(&hdev->fd_rule_lock); 6929 6930 rule = hclge_get_fd_rule(hdev, fs->location); 6931 if (!rule) { 6932 spin_unlock_bh(&hdev->fd_rule_lock); 6933 return -ENOENT; 6934 } 6935 6936 fs->flow_type = rule->flow_type; 6937 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6938 case SCTP_V4_FLOW: 6939 case TCP_V4_FLOW: 6940 case UDP_V4_FLOW: 6941 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6942 &fs->m_u.tcp_ip4_spec); 6943 break; 6944 case IP_USER_FLOW: 6945 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6946 &fs->m_u.usr_ip4_spec); 6947 break; 6948 case SCTP_V6_FLOW: 6949 case TCP_V6_FLOW: 6950 case UDP_V6_FLOW: 6951 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6952 &fs->m_u.tcp_ip6_spec); 6953 break; 6954 case IPV6_USER_FLOW: 6955 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6956 &fs->m_u.usr_ip6_spec); 6957 break; 6958 /* The flow type of fd rule has been checked before adding in to rule 6959 * list. As other flow types have been handled, it must be ETHER_FLOW 6960 * for the default case 6961 */ 6962 default: 6963 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6964 &fs->m_u.ether_spec); 6965 break; 6966 } 6967 6968 hclge_fd_get_ext_info(fs, rule); 6969 6970 hclge_fd_get_ring_cookie(fs, rule); 6971 6972 spin_unlock_bh(&hdev->fd_rule_lock); 6973 6974 return 0; 6975 } 6976 6977 static int hclge_get_all_rules(struct hnae3_handle *handle, 6978 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6979 { 6980 struct hclge_vport *vport = hclge_get_vport(handle); 6981 struct hclge_dev *hdev = vport->back; 6982 struct hclge_fd_rule *rule; 6983 struct hlist_node *node2; 6984 int cnt = 0; 6985 6986 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6987 return -EOPNOTSUPP; 6988 6989 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6990 6991 spin_lock_bh(&hdev->fd_rule_lock); 6992 hlist_for_each_entry_safe(rule, node2, 6993 &hdev->fd_rule_list, rule_node) { 6994 if (cnt == cmd->rule_cnt) { 6995 spin_unlock_bh(&hdev->fd_rule_lock); 6996 return -EMSGSIZE; 6997 } 6998 6999 if (rule->state == HCLGE_FD_TO_DEL) 7000 continue; 7001 7002 rule_locs[cnt] = rule->location; 7003 cnt++; 7004 } 7005 7006 spin_unlock_bh(&hdev->fd_rule_lock); 7007 7008 cmd->rule_cnt = cnt; 7009 7010 return 0; 7011 } 7012 7013 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7014 struct hclge_fd_rule_tuples *tuples) 7015 { 7016 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7017 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7018 7019 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7020 tuples->ip_proto = fkeys->basic.ip_proto; 7021 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7022 7023 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7024 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7025 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7026 } else { 7027 int i; 7028 7029 for (i = 0; i < IPV6_SIZE; i++) { 7030 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7031 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7032 } 7033 } 7034 } 7035 7036 /* traverse all rules, check whether an existed rule has the same tuples */ 7037 static struct hclge_fd_rule * 7038 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7039 const struct hclge_fd_rule_tuples *tuples) 7040 { 7041 struct hclge_fd_rule *rule = NULL; 7042 struct hlist_node *node; 7043 7044 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7045 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7046 return rule; 7047 } 7048 7049 return NULL; 7050 } 7051 7052 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7053 struct hclge_fd_rule *rule) 7054 { 7055 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7056 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7057 BIT(INNER_SRC_PORT); 7058 rule->action = 0; 7059 rule->vf_id = 0; 7060 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7061 rule->state = HCLGE_FD_TO_ADD; 7062 if (tuples->ether_proto == ETH_P_IP) { 7063 if (tuples->ip_proto == IPPROTO_TCP) 7064 rule->flow_type = TCP_V4_FLOW; 7065 else 7066 rule->flow_type = UDP_V4_FLOW; 7067 } else { 7068 if (tuples->ip_proto == IPPROTO_TCP) 7069 rule->flow_type = TCP_V6_FLOW; 7070 else 7071 rule->flow_type = UDP_V6_FLOW; 7072 } 7073 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7074 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7075 } 7076 7077 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7078 u16 flow_id, struct flow_keys *fkeys) 7079 { 7080 struct hclge_vport *vport = hclge_get_vport(handle); 7081 struct hclge_fd_rule_tuples new_tuples = {}; 7082 struct hclge_dev *hdev = vport->back; 7083 struct hclge_fd_rule *rule; 7084 u16 bit_id; 7085 7086 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7087 return -EOPNOTSUPP; 7088 7089 /* when there is already fd rule existed add by user, 7090 * arfs should not work 7091 */ 7092 spin_lock_bh(&hdev->fd_rule_lock); 7093 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7094 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7095 spin_unlock_bh(&hdev->fd_rule_lock); 7096 return -EOPNOTSUPP; 7097 } 7098 7099 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7100 7101 /* check is there flow director filter existed for this flow, 7102 * if not, create a new filter for it; 7103 * if filter exist with different queue id, modify the filter; 7104 * if filter exist with same queue id, do nothing 7105 */ 7106 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7107 if (!rule) { 7108 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7109 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7110 spin_unlock_bh(&hdev->fd_rule_lock); 7111 return -ENOSPC; 7112 } 7113 7114 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7115 if (!rule) { 7116 spin_unlock_bh(&hdev->fd_rule_lock); 7117 return -ENOMEM; 7118 } 7119 7120 rule->location = bit_id; 7121 rule->arfs.flow_id = flow_id; 7122 rule->queue_id = queue_id; 7123 hclge_fd_build_arfs_rule(&new_tuples, rule); 7124 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7125 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7126 } else if (rule->queue_id != queue_id) { 7127 rule->queue_id = queue_id; 7128 rule->state = HCLGE_FD_TO_ADD; 7129 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7130 hclge_task_schedule(hdev, 0); 7131 } 7132 spin_unlock_bh(&hdev->fd_rule_lock); 7133 return rule->location; 7134 } 7135 7136 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7137 { 7138 #ifdef CONFIG_RFS_ACCEL 7139 struct hnae3_handle *handle = &hdev->vport[0].nic; 7140 struct hclge_fd_rule *rule; 7141 struct hlist_node *node; 7142 7143 spin_lock_bh(&hdev->fd_rule_lock); 7144 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7145 spin_unlock_bh(&hdev->fd_rule_lock); 7146 return; 7147 } 7148 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7149 if (rule->state != HCLGE_FD_ACTIVE) 7150 continue; 7151 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7152 rule->arfs.flow_id, rule->location)) { 7153 rule->state = HCLGE_FD_TO_DEL; 7154 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7155 } 7156 } 7157 spin_unlock_bh(&hdev->fd_rule_lock); 7158 #endif 7159 } 7160 7161 /* make sure being called after lock up with fd_rule_lock */ 7162 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7163 { 7164 #ifdef CONFIG_RFS_ACCEL 7165 struct hclge_fd_rule *rule; 7166 struct hlist_node *node; 7167 int ret; 7168 7169 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7170 return 0; 7171 7172 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7173 switch (rule->state) { 7174 case HCLGE_FD_TO_DEL: 7175 case HCLGE_FD_ACTIVE: 7176 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7177 rule->location, NULL, false); 7178 if (ret) 7179 return ret; 7180 fallthrough; 7181 case HCLGE_FD_TO_ADD: 7182 hclge_fd_dec_rule_cnt(hdev, rule->location); 7183 hlist_del(&rule->rule_node); 7184 kfree(rule); 7185 break; 7186 default: 7187 break; 7188 } 7189 } 7190 hclge_sync_fd_state(hdev); 7191 7192 #endif 7193 return 0; 7194 } 7195 7196 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7197 struct hclge_fd_rule *rule) 7198 { 7199 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7200 struct flow_match_basic match; 7201 u16 ethtype_key, ethtype_mask; 7202 7203 flow_rule_match_basic(flow, &match); 7204 ethtype_key = ntohs(match.key->n_proto); 7205 ethtype_mask = ntohs(match.mask->n_proto); 7206 7207 if (ethtype_key == ETH_P_ALL) { 7208 ethtype_key = 0; 7209 ethtype_mask = 0; 7210 } 7211 rule->tuples.ether_proto = ethtype_key; 7212 rule->tuples_mask.ether_proto = ethtype_mask; 7213 rule->tuples.ip_proto = match.key->ip_proto; 7214 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7215 } else { 7216 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7217 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7218 } 7219 } 7220 7221 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7222 struct hclge_fd_rule *rule) 7223 { 7224 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7225 struct flow_match_eth_addrs match; 7226 7227 flow_rule_match_eth_addrs(flow, &match); 7228 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7229 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7230 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7231 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7232 } else { 7233 rule->unused_tuple |= BIT(INNER_DST_MAC); 7234 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7235 } 7236 } 7237 7238 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7239 struct hclge_fd_rule *rule) 7240 { 7241 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7242 struct flow_match_vlan match; 7243 7244 flow_rule_match_vlan(flow, &match); 7245 rule->tuples.vlan_tag1 = match.key->vlan_id | 7246 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7247 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7248 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7249 } else { 7250 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7251 } 7252 } 7253 7254 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7255 struct hclge_fd_rule *rule) 7256 { 7257 u16 addr_type = 0; 7258 7259 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7260 struct flow_match_control match; 7261 7262 flow_rule_match_control(flow, &match); 7263 addr_type = match.key->addr_type; 7264 } 7265 7266 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7267 struct flow_match_ipv4_addrs match; 7268 7269 flow_rule_match_ipv4_addrs(flow, &match); 7270 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7271 rule->tuples_mask.src_ip[IPV4_INDEX] = 7272 be32_to_cpu(match.mask->src); 7273 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7274 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7275 be32_to_cpu(match.mask->dst); 7276 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7277 struct flow_match_ipv6_addrs match; 7278 7279 flow_rule_match_ipv6_addrs(flow, &match); 7280 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7281 IPV6_SIZE); 7282 be32_to_cpu_array(rule->tuples_mask.src_ip, 7283 match.mask->src.s6_addr32, IPV6_SIZE); 7284 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7285 IPV6_SIZE); 7286 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7287 match.mask->dst.s6_addr32, IPV6_SIZE); 7288 } else { 7289 rule->unused_tuple |= BIT(INNER_SRC_IP); 7290 rule->unused_tuple |= BIT(INNER_DST_IP); 7291 } 7292 } 7293 7294 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7295 struct hclge_fd_rule *rule) 7296 { 7297 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7298 struct flow_match_ports match; 7299 7300 flow_rule_match_ports(flow, &match); 7301 7302 rule->tuples.src_port = be16_to_cpu(match.key->src); 7303 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7304 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7305 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7306 } else { 7307 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7308 rule->unused_tuple |= BIT(INNER_DST_PORT); 7309 } 7310 } 7311 7312 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7313 struct flow_cls_offload *cls_flower, 7314 struct hclge_fd_rule *rule) 7315 { 7316 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7317 struct flow_dissector *dissector = flow->match.dissector; 7318 7319 if (dissector->used_keys & 7320 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7321 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7322 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7323 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7324 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7325 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7326 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7327 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7328 dissector->used_keys); 7329 return -EOPNOTSUPP; 7330 } 7331 7332 hclge_get_cls_key_basic(flow, rule); 7333 hclge_get_cls_key_mac(flow, rule); 7334 hclge_get_cls_key_vlan(flow, rule); 7335 hclge_get_cls_key_ip(flow, rule); 7336 hclge_get_cls_key_port(flow, rule); 7337 7338 return 0; 7339 } 7340 7341 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7342 struct flow_cls_offload *cls_flower, int tc) 7343 { 7344 u32 prio = cls_flower->common.prio; 7345 7346 if (tc < 0 || tc > hdev->tc_max) { 7347 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7348 return -EINVAL; 7349 } 7350 7351 if (prio == 0 || 7352 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7353 dev_err(&hdev->pdev->dev, 7354 "prio %u should be in range[1, %u]\n", 7355 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7356 return -EINVAL; 7357 } 7358 7359 if (test_bit(prio - 1, hdev->fd_bmap)) { 7360 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7361 return -EINVAL; 7362 } 7363 return 0; 7364 } 7365 7366 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7367 struct flow_cls_offload *cls_flower, 7368 int tc) 7369 { 7370 struct hclge_vport *vport = hclge_get_vport(handle); 7371 struct hclge_dev *hdev = vport->back; 7372 struct hclge_fd_rule *rule; 7373 int ret; 7374 7375 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7376 dev_err(&hdev->pdev->dev, 7377 "cls flower is not supported\n"); 7378 return -EOPNOTSUPP; 7379 } 7380 7381 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7382 if (ret) { 7383 dev_err(&hdev->pdev->dev, 7384 "failed to check cls flower params, ret = %d\n", ret); 7385 return ret; 7386 } 7387 7388 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7389 if (!rule) 7390 return -ENOMEM; 7391 7392 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7393 if (ret) { 7394 kfree(rule); 7395 return ret; 7396 } 7397 7398 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7399 rule->cls_flower.tc = tc; 7400 rule->location = cls_flower->common.prio - 1; 7401 rule->vf_id = 0; 7402 rule->cls_flower.cookie = cls_flower->cookie; 7403 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7404 7405 ret = hclge_add_fd_entry_common(hdev, rule); 7406 if (ret) 7407 kfree(rule); 7408 7409 return ret; 7410 } 7411 7412 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7413 unsigned long cookie) 7414 { 7415 struct hclge_fd_rule *rule; 7416 struct hlist_node *node; 7417 7418 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7419 if (rule->cls_flower.cookie == cookie) 7420 return rule; 7421 } 7422 7423 return NULL; 7424 } 7425 7426 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7427 struct flow_cls_offload *cls_flower) 7428 { 7429 struct hclge_vport *vport = hclge_get_vport(handle); 7430 struct hclge_dev *hdev = vport->back; 7431 struct hclge_fd_rule *rule; 7432 int ret; 7433 7434 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7435 return -EOPNOTSUPP; 7436 7437 spin_lock_bh(&hdev->fd_rule_lock); 7438 7439 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7440 if (!rule) { 7441 spin_unlock_bh(&hdev->fd_rule_lock); 7442 return -EINVAL; 7443 } 7444 7445 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7446 NULL, false); 7447 if (ret) { 7448 spin_unlock_bh(&hdev->fd_rule_lock); 7449 return ret; 7450 } 7451 7452 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7453 spin_unlock_bh(&hdev->fd_rule_lock); 7454 7455 return 0; 7456 } 7457 7458 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7459 { 7460 struct hclge_fd_rule *rule; 7461 struct hlist_node *node; 7462 int ret = 0; 7463 7464 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7465 return; 7466 7467 spin_lock_bh(&hdev->fd_rule_lock); 7468 7469 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7470 switch (rule->state) { 7471 case HCLGE_FD_TO_ADD: 7472 ret = hclge_fd_config_rule(hdev, rule); 7473 if (ret) 7474 goto out; 7475 rule->state = HCLGE_FD_ACTIVE; 7476 break; 7477 case HCLGE_FD_TO_DEL: 7478 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7479 rule->location, NULL, false); 7480 if (ret) 7481 goto out; 7482 hclge_fd_dec_rule_cnt(hdev, rule->location); 7483 hclge_fd_free_node(hdev, rule); 7484 break; 7485 default: 7486 break; 7487 } 7488 } 7489 7490 out: 7491 if (ret) 7492 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7493 7494 spin_unlock_bh(&hdev->fd_rule_lock); 7495 } 7496 7497 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7498 { 7499 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7500 return; 7501 7502 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7503 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7504 7505 hclge_clear_fd_rules_in_list(hdev, clear_list); 7506 } 7507 7508 hclge_sync_fd_user_def_cfg(hdev, false); 7509 7510 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7511 } 7512 7513 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7514 { 7515 struct hclge_vport *vport = hclge_get_vport(handle); 7516 struct hclge_dev *hdev = vport->back; 7517 7518 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7519 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7520 } 7521 7522 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7523 { 7524 struct hclge_vport *vport = hclge_get_vport(handle); 7525 struct hclge_dev *hdev = vport->back; 7526 7527 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7528 } 7529 7530 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7531 { 7532 struct hclge_vport *vport = hclge_get_vport(handle); 7533 struct hclge_dev *hdev = vport->back; 7534 7535 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7536 } 7537 7538 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7539 { 7540 struct hclge_vport *vport = hclge_get_vport(handle); 7541 struct hclge_dev *hdev = vport->back; 7542 7543 return hdev->rst_stats.hw_reset_done_cnt; 7544 } 7545 7546 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7547 { 7548 struct hclge_vport *vport = hclge_get_vport(handle); 7549 struct hclge_dev *hdev = vport->back; 7550 7551 hdev->fd_en = enable; 7552 7553 if (!enable) 7554 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7555 else 7556 hclge_restore_fd_entries(handle); 7557 7558 hclge_task_schedule(hdev, 0); 7559 } 7560 7561 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7562 { 7563 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7564 7565 struct hclge_desc desc; 7566 struct hclge_config_mac_mode_cmd *req = 7567 (struct hclge_config_mac_mode_cmd *)desc.data; 7568 u32 loop_en = 0; 7569 int ret; 7570 7571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7572 7573 if (enable) { 7574 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7575 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7576 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7577 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7578 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7579 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7580 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7581 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7582 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7583 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7584 } 7585 7586 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7587 7588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7589 if (ret) { 7590 dev_err(&hdev->pdev->dev, 7591 "mac enable fail, ret =%d.\n", ret); 7592 return; 7593 } 7594 7595 if (!enable) 7596 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7597 HCLGE_LINK_STATUS_WAIT_CNT); 7598 } 7599 7600 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7601 u8 switch_param, u8 param_mask) 7602 { 7603 struct hclge_mac_vlan_switch_cmd *req; 7604 struct hclge_desc desc; 7605 u32 func_id; 7606 int ret; 7607 7608 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7609 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7610 7611 /* read current config parameter */ 7612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7613 true); 7614 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7615 req->func_id = cpu_to_le32(func_id); 7616 7617 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7618 if (ret) { 7619 dev_err(&hdev->pdev->dev, 7620 "read mac vlan switch parameter fail, ret = %d\n", ret); 7621 return ret; 7622 } 7623 7624 /* modify and write new config parameter */ 7625 hclge_comm_cmd_reuse_desc(&desc, false); 7626 req->switch_param = (req->switch_param & param_mask) | switch_param; 7627 req->param_mask = param_mask; 7628 7629 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7630 if (ret) 7631 dev_err(&hdev->pdev->dev, 7632 "set mac vlan switch parameter fail, ret = %d\n", ret); 7633 return ret; 7634 } 7635 7636 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7637 int link_ret) 7638 { 7639 #define HCLGE_PHY_LINK_STATUS_NUM 200 7640 7641 struct phy_device *phydev = hdev->hw.mac.phydev; 7642 int i = 0; 7643 int ret; 7644 7645 do { 7646 ret = phy_read_status(phydev); 7647 if (ret) { 7648 dev_err(&hdev->pdev->dev, 7649 "phy update link status fail, ret = %d\n", ret); 7650 return; 7651 } 7652 7653 if (phydev->link == link_ret) 7654 break; 7655 7656 msleep(HCLGE_LINK_STATUS_MS); 7657 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7658 } 7659 7660 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7661 int wait_cnt) 7662 { 7663 int link_status; 7664 int i = 0; 7665 int ret; 7666 7667 do { 7668 ret = hclge_get_mac_link_status(hdev, &link_status); 7669 if (ret) 7670 return ret; 7671 if (link_status == link_ret) 7672 return 0; 7673 7674 msleep(HCLGE_LINK_STATUS_MS); 7675 } while (++i < wait_cnt); 7676 return -EBUSY; 7677 } 7678 7679 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7680 bool is_phy) 7681 { 7682 #define HCLGE_MAC_LINK_STATUS_NUM 100 7683 7684 int link_ret; 7685 7686 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7687 7688 if (is_phy) 7689 hclge_phy_link_status_wait(hdev, link_ret); 7690 7691 return hclge_mac_link_status_wait(hdev, link_ret, 7692 HCLGE_MAC_LINK_STATUS_NUM); 7693 } 7694 7695 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7696 { 7697 struct hclge_config_mac_mode_cmd *req; 7698 struct hclge_desc desc; 7699 u32 loop_en; 7700 int ret; 7701 7702 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7703 /* 1 Read out the MAC mode config at first */ 7704 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7705 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7706 if (ret) { 7707 dev_err(&hdev->pdev->dev, 7708 "mac loopback get fail, ret =%d.\n", ret); 7709 return ret; 7710 } 7711 7712 /* 2 Then setup the loopback flag */ 7713 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7714 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7715 7716 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7717 7718 /* 3 Config mac work mode with loopback flag 7719 * and its original configure parameters 7720 */ 7721 hclge_comm_cmd_reuse_desc(&desc, false); 7722 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7723 if (ret) 7724 dev_err(&hdev->pdev->dev, 7725 "mac loopback set fail, ret =%d.\n", ret); 7726 return ret; 7727 } 7728 7729 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7730 enum hnae3_loop loop_mode) 7731 { 7732 struct hclge_common_lb_cmd *req; 7733 struct hclge_desc desc; 7734 u8 loop_mode_b; 7735 int ret; 7736 7737 req = (struct hclge_common_lb_cmd *)desc.data; 7738 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7739 7740 switch (loop_mode) { 7741 case HNAE3_LOOP_SERIAL_SERDES: 7742 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7743 break; 7744 case HNAE3_LOOP_PARALLEL_SERDES: 7745 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7746 break; 7747 case HNAE3_LOOP_PHY: 7748 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7749 break; 7750 default: 7751 dev_err(&hdev->pdev->dev, 7752 "unsupported loopback mode %d\n", loop_mode); 7753 return -ENOTSUPP; 7754 } 7755 7756 req->mask = loop_mode_b; 7757 if (en) 7758 req->enable = loop_mode_b; 7759 7760 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7761 if (ret) 7762 dev_err(&hdev->pdev->dev, 7763 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7764 loop_mode, ret); 7765 7766 return ret; 7767 } 7768 7769 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7770 { 7771 #define HCLGE_COMMON_LB_RETRY_MS 10 7772 #define HCLGE_COMMON_LB_RETRY_NUM 100 7773 7774 struct hclge_common_lb_cmd *req; 7775 struct hclge_desc desc; 7776 u32 i = 0; 7777 int ret; 7778 7779 req = (struct hclge_common_lb_cmd *)desc.data; 7780 7781 do { 7782 msleep(HCLGE_COMMON_LB_RETRY_MS); 7783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7784 true); 7785 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7786 if (ret) { 7787 dev_err(&hdev->pdev->dev, 7788 "failed to get loopback done status, ret = %d\n", 7789 ret); 7790 return ret; 7791 } 7792 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7793 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7794 7795 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7796 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7797 return -EBUSY; 7798 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7799 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7800 return -EIO; 7801 } 7802 7803 return 0; 7804 } 7805 7806 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7807 enum hnae3_loop loop_mode) 7808 { 7809 int ret; 7810 7811 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7812 if (ret) 7813 return ret; 7814 7815 return hclge_cfg_common_loopback_wait(hdev); 7816 } 7817 7818 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7819 enum hnae3_loop loop_mode) 7820 { 7821 int ret; 7822 7823 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7824 if (ret) 7825 return ret; 7826 7827 hclge_cfg_mac_mode(hdev, en); 7828 7829 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7830 if (ret) 7831 dev_err(&hdev->pdev->dev, 7832 "serdes loopback config mac mode timeout\n"); 7833 7834 return ret; 7835 } 7836 7837 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7838 struct phy_device *phydev) 7839 { 7840 int ret; 7841 7842 if (!phydev->suspended) { 7843 ret = phy_suspend(phydev); 7844 if (ret) 7845 return ret; 7846 } 7847 7848 ret = phy_resume(phydev); 7849 if (ret) 7850 return ret; 7851 7852 return phy_loopback(phydev, true); 7853 } 7854 7855 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7856 struct phy_device *phydev) 7857 { 7858 int ret; 7859 7860 ret = phy_loopback(phydev, false); 7861 if (ret) 7862 return ret; 7863 7864 return phy_suspend(phydev); 7865 } 7866 7867 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7868 { 7869 struct phy_device *phydev = hdev->hw.mac.phydev; 7870 int ret; 7871 7872 if (!phydev) { 7873 if (hnae3_dev_phy_imp_supported(hdev)) 7874 return hclge_set_common_loopback(hdev, en, 7875 HNAE3_LOOP_PHY); 7876 return -ENOTSUPP; 7877 } 7878 7879 if (en) 7880 ret = hclge_enable_phy_loopback(hdev, phydev); 7881 else 7882 ret = hclge_disable_phy_loopback(hdev, phydev); 7883 if (ret) { 7884 dev_err(&hdev->pdev->dev, 7885 "set phy loopback fail, ret = %d\n", ret); 7886 return ret; 7887 } 7888 7889 hclge_cfg_mac_mode(hdev, en); 7890 7891 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7892 if (ret) 7893 dev_err(&hdev->pdev->dev, 7894 "phy loopback config mac mode timeout\n"); 7895 7896 return ret; 7897 } 7898 7899 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7900 u16 stream_id, bool enable) 7901 { 7902 struct hclge_desc desc; 7903 struct hclge_cfg_com_tqp_queue_cmd *req = 7904 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7905 7906 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7907 req->tqp_id = cpu_to_le16(tqp_id); 7908 req->stream_id = cpu_to_le16(stream_id); 7909 if (enable) 7910 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7911 7912 return hclge_cmd_send(&hdev->hw, &desc, 1); 7913 } 7914 7915 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7916 { 7917 struct hclge_vport *vport = hclge_get_vport(handle); 7918 struct hclge_dev *hdev = vport->back; 7919 int ret; 7920 u16 i; 7921 7922 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7923 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7924 if (ret) 7925 return ret; 7926 } 7927 return 0; 7928 } 7929 7930 static int hclge_set_loopback(struct hnae3_handle *handle, 7931 enum hnae3_loop loop_mode, bool en) 7932 { 7933 struct hclge_vport *vport = hclge_get_vport(handle); 7934 struct hclge_dev *hdev = vport->back; 7935 int ret = 0; 7936 7937 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7938 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7939 * the same, the packets are looped back in the SSU. If SSU loopback 7940 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7941 */ 7942 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7943 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7944 7945 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7946 HCLGE_SWITCH_ALW_LPBK_MASK); 7947 if (ret) 7948 return ret; 7949 } 7950 7951 switch (loop_mode) { 7952 case HNAE3_LOOP_APP: 7953 ret = hclge_set_app_loopback(hdev, en); 7954 break; 7955 case HNAE3_LOOP_SERIAL_SERDES: 7956 case HNAE3_LOOP_PARALLEL_SERDES: 7957 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7958 break; 7959 case HNAE3_LOOP_PHY: 7960 ret = hclge_set_phy_loopback(hdev, en); 7961 break; 7962 case HNAE3_LOOP_EXTERNAL: 7963 break; 7964 default: 7965 ret = -ENOTSUPP; 7966 dev_err(&hdev->pdev->dev, 7967 "loop_mode %d is not supported\n", loop_mode); 7968 break; 7969 } 7970 7971 if (ret) 7972 return ret; 7973 7974 ret = hclge_tqp_enable(handle, en); 7975 if (ret) 7976 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7977 en ? "enable" : "disable", ret); 7978 7979 return ret; 7980 } 7981 7982 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7983 { 7984 int ret; 7985 7986 ret = hclge_set_app_loopback(hdev, false); 7987 if (ret) 7988 return ret; 7989 7990 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7991 if (ret) 7992 return ret; 7993 7994 return hclge_cfg_common_loopback(hdev, false, 7995 HNAE3_LOOP_PARALLEL_SERDES); 7996 } 7997 7998 static void hclge_flush_link_update(struct hclge_dev *hdev) 7999 { 8000 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 8001 8002 unsigned long last = hdev->serv_processed_cnt; 8003 int i = 0; 8004 8005 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8006 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8007 last == hdev->serv_processed_cnt) 8008 usleep_range(1, 1); 8009 } 8010 8011 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8012 { 8013 struct hclge_vport *vport = hclge_get_vport(handle); 8014 struct hclge_dev *hdev = vport->back; 8015 8016 if (enable) { 8017 hclge_task_schedule(hdev, 0); 8018 } else { 8019 /* Set the DOWN flag here to disable link updating */ 8020 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8021 8022 /* flush memory to make sure DOWN is seen by service task */ 8023 smp_mb__before_atomic(); 8024 hclge_flush_link_update(hdev); 8025 } 8026 } 8027 8028 static int hclge_ae_start(struct hnae3_handle *handle) 8029 { 8030 struct hclge_vport *vport = hclge_get_vport(handle); 8031 struct hclge_dev *hdev = vport->back; 8032 8033 /* mac enable */ 8034 hclge_cfg_mac_mode(hdev, true); 8035 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8036 hdev->hw.mac.link = 0; 8037 8038 /* reset tqp stats */ 8039 hclge_comm_reset_tqp_stats(handle); 8040 8041 hclge_mac_start_phy(hdev); 8042 8043 return 0; 8044 } 8045 8046 static void hclge_ae_stop(struct hnae3_handle *handle) 8047 { 8048 struct hclge_vport *vport = hclge_get_vport(handle); 8049 struct hclge_dev *hdev = vport->back; 8050 8051 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8052 spin_lock_bh(&hdev->fd_rule_lock); 8053 hclge_clear_arfs_rules(hdev); 8054 spin_unlock_bh(&hdev->fd_rule_lock); 8055 8056 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8057 * so it only need to stop phy here. 8058 */ 8059 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8060 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8061 HCLGE_PFC_DISABLE); 8062 if (hdev->reset_type != HNAE3_FUNC_RESET && 8063 hdev->reset_type != HNAE3_FLR_RESET) { 8064 hclge_mac_stop_phy(hdev); 8065 hclge_update_link_status(hdev); 8066 return; 8067 } 8068 } 8069 8070 hclge_reset_tqp(handle); 8071 8072 hclge_config_mac_tnl_int(hdev, false); 8073 8074 /* Mac disable */ 8075 hclge_cfg_mac_mode(hdev, false); 8076 8077 hclge_mac_stop_phy(hdev); 8078 8079 /* reset tqp stats */ 8080 hclge_comm_reset_tqp_stats(handle); 8081 hclge_update_link_status(hdev); 8082 } 8083 8084 int hclge_vport_start(struct hclge_vport *vport) 8085 { 8086 struct hclge_dev *hdev = vport->back; 8087 8088 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8089 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8090 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8091 vport->last_active_jiffies = jiffies; 8092 vport->need_notify = 0; 8093 8094 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8095 if (vport->vport_id) { 8096 hclge_restore_mac_table_common(vport); 8097 hclge_restore_vport_vlan_table(vport); 8098 } else { 8099 hclge_restore_hw_table(hdev); 8100 } 8101 } 8102 8103 clear_bit(vport->vport_id, hdev->vport_config_block); 8104 8105 return 0; 8106 } 8107 8108 void hclge_vport_stop(struct hclge_vport *vport) 8109 { 8110 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8111 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8112 vport->need_notify = 0; 8113 } 8114 8115 static int hclge_client_start(struct hnae3_handle *handle) 8116 { 8117 struct hclge_vport *vport = hclge_get_vport(handle); 8118 8119 return hclge_vport_start(vport); 8120 } 8121 8122 static void hclge_client_stop(struct hnae3_handle *handle) 8123 { 8124 struct hclge_vport *vport = hclge_get_vport(handle); 8125 8126 hclge_vport_stop(vport); 8127 } 8128 8129 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8130 u16 cmdq_resp, u8 resp_code, 8131 enum hclge_mac_vlan_tbl_opcode op) 8132 { 8133 struct hclge_dev *hdev = vport->back; 8134 8135 if (cmdq_resp) { 8136 dev_err(&hdev->pdev->dev, 8137 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8138 cmdq_resp); 8139 return -EIO; 8140 } 8141 8142 if (op == HCLGE_MAC_VLAN_ADD) { 8143 if (!resp_code || resp_code == 1) 8144 return 0; 8145 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8146 resp_code == HCLGE_ADD_MC_OVERFLOW) 8147 return -ENOSPC; 8148 8149 dev_err(&hdev->pdev->dev, 8150 "add mac addr failed for undefined, code=%u.\n", 8151 resp_code); 8152 return -EIO; 8153 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8154 if (!resp_code) { 8155 return 0; 8156 } else if (resp_code == 1) { 8157 dev_dbg(&hdev->pdev->dev, 8158 "remove mac addr failed for miss.\n"); 8159 return -ENOENT; 8160 } 8161 8162 dev_err(&hdev->pdev->dev, 8163 "remove mac addr failed for undefined, code=%u.\n", 8164 resp_code); 8165 return -EIO; 8166 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8167 if (!resp_code) { 8168 return 0; 8169 } else if (resp_code == 1) { 8170 dev_dbg(&hdev->pdev->dev, 8171 "lookup mac addr failed for miss.\n"); 8172 return -ENOENT; 8173 } 8174 8175 dev_err(&hdev->pdev->dev, 8176 "lookup mac addr failed for undefined, code=%u.\n", 8177 resp_code); 8178 return -EIO; 8179 } 8180 8181 dev_err(&hdev->pdev->dev, 8182 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8183 8184 return -EINVAL; 8185 } 8186 8187 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8188 { 8189 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8190 8191 unsigned int word_num; 8192 unsigned int bit_num; 8193 8194 if (vfid > 255 || vfid < 0) 8195 return -EIO; 8196 8197 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8198 word_num = vfid / 32; 8199 bit_num = vfid % 32; 8200 if (clr) 8201 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8202 else 8203 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8204 } else { 8205 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8206 bit_num = vfid % 32; 8207 if (clr) 8208 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8209 else 8210 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8211 } 8212 8213 return 0; 8214 } 8215 8216 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8217 { 8218 #define HCLGE_DESC_NUMBER 3 8219 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8220 int i, j; 8221 8222 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8223 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8224 if (desc[i].data[j]) 8225 return false; 8226 8227 return true; 8228 } 8229 8230 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8231 const u8 *addr, bool is_mc) 8232 { 8233 const unsigned char *mac_addr = addr; 8234 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8235 (mac_addr[0]) | (mac_addr[1] << 8); 8236 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8237 8238 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8239 if (is_mc) { 8240 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8241 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8242 } 8243 8244 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8245 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8246 } 8247 8248 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8249 struct hclge_mac_vlan_tbl_entry_cmd *req) 8250 { 8251 struct hclge_dev *hdev = vport->back; 8252 struct hclge_desc desc; 8253 u8 resp_code; 8254 u16 retval; 8255 int ret; 8256 8257 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8258 8259 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8260 8261 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8262 if (ret) { 8263 dev_err(&hdev->pdev->dev, 8264 "del mac addr failed for cmd_send, ret =%d.\n", 8265 ret); 8266 return ret; 8267 } 8268 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8269 retval = le16_to_cpu(desc.retval); 8270 8271 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8272 HCLGE_MAC_VLAN_REMOVE); 8273 } 8274 8275 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8276 struct hclge_mac_vlan_tbl_entry_cmd *req, 8277 struct hclge_desc *desc, 8278 bool is_mc) 8279 { 8280 struct hclge_dev *hdev = vport->back; 8281 u8 resp_code; 8282 u16 retval; 8283 int ret; 8284 8285 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8286 if (is_mc) { 8287 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8288 memcpy(desc[0].data, 8289 req, 8290 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8291 hclge_cmd_setup_basic_desc(&desc[1], 8292 HCLGE_OPC_MAC_VLAN_ADD, 8293 true); 8294 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8295 hclge_cmd_setup_basic_desc(&desc[2], 8296 HCLGE_OPC_MAC_VLAN_ADD, 8297 true); 8298 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8299 } else { 8300 memcpy(desc[0].data, 8301 req, 8302 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8303 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8304 } 8305 if (ret) { 8306 dev_err(&hdev->pdev->dev, 8307 "lookup mac addr failed for cmd_send, ret =%d.\n", 8308 ret); 8309 return ret; 8310 } 8311 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8312 retval = le16_to_cpu(desc[0].retval); 8313 8314 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8315 HCLGE_MAC_VLAN_LKUP); 8316 } 8317 8318 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8319 struct hclge_mac_vlan_tbl_entry_cmd *req, 8320 struct hclge_desc *mc_desc) 8321 { 8322 struct hclge_dev *hdev = vport->back; 8323 int cfg_status; 8324 u8 resp_code; 8325 u16 retval; 8326 int ret; 8327 8328 if (!mc_desc) { 8329 struct hclge_desc desc; 8330 8331 hclge_cmd_setup_basic_desc(&desc, 8332 HCLGE_OPC_MAC_VLAN_ADD, 8333 false); 8334 memcpy(desc.data, req, 8335 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8336 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8337 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8338 retval = le16_to_cpu(desc.retval); 8339 8340 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8341 resp_code, 8342 HCLGE_MAC_VLAN_ADD); 8343 } else { 8344 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8345 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8346 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8347 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8348 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8349 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8350 memcpy(mc_desc[0].data, req, 8351 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8352 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8353 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8354 retval = le16_to_cpu(mc_desc[0].retval); 8355 8356 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8357 resp_code, 8358 HCLGE_MAC_VLAN_ADD); 8359 } 8360 8361 if (ret) { 8362 dev_err(&hdev->pdev->dev, 8363 "add mac addr failed for cmd_send, ret =%d.\n", 8364 ret); 8365 return ret; 8366 } 8367 8368 return cfg_status; 8369 } 8370 8371 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8372 u16 *allocated_size) 8373 { 8374 struct hclge_umv_spc_alc_cmd *req; 8375 struct hclge_desc desc; 8376 int ret; 8377 8378 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8379 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8380 8381 req->space_size = cpu_to_le32(space_size); 8382 8383 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8384 if (ret) { 8385 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8386 ret); 8387 return ret; 8388 } 8389 8390 *allocated_size = le32_to_cpu(desc.data[1]); 8391 8392 return 0; 8393 } 8394 8395 static int hclge_init_umv_space(struct hclge_dev *hdev) 8396 { 8397 u16 allocated_size = 0; 8398 int ret; 8399 8400 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8401 if (ret) 8402 return ret; 8403 8404 if (allocated_size < hdev->wanted_umv_size) 8405 dev_warn(&hdev->pdev->dev, 8406 "failed to alloc umv space, want %u, get %u\n", 8407 hdev->wanted_umv_size, allocated_size); 8408 8409 hdev->max_umv_size = allocated_size; 8410 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8411 hdev->share_umv_size = hdev->priv_umv_size + 8412 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8413 8414 if (hdev->ae_dev->dev_specs.mc_mac_size) 8415 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8416 8417 return 0; 8418 } 8419 8420 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8421 { 8422 struct hclge_vport *vport; 8423 int i; 8424 8425 for (i = 0; i < hdev->num_alloc_vport; i++) { 8426 vport = &hdev->vport[i]; 8427 vport->used_umv_num = 0; 8428 } 8429 8430 mutex_lock(&hdev->vport_lock); 8431 hdev->share_umv_size = hdev->priv_umv_size + 8432 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8433 mutex_unlock(&hdev->vport_lock); 8434 8435 hdev->used_mc_mac_num = 0; 8436 } 8437 8438 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8439 { 8440 struct hclge_dev *hdev = vport->back; 8441 bool is_full; 8442 8443 if (need_lock) 8444 mutex_lock(&hdev->vport_lock); 8445 8446 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8447 hdev->share_umv_size == 0); 8448 8449 if (need_lock) 8450 mutex_unlock(&hdev->vport_lock); 8451 8452 return is_full; 8453 } 8454 8455 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8456 { 8457 struct hclge_dev *hdev = vport->back; 8458 8459 if (is_free) { 8460 if (vport->used_umv_num > hdev->priv_umv_size) 8461 hdev->share_umv_size++; 8462 8463 if (vport->used_umv_num > 0) 8464 vport->used_umv_num--; 8465 } else { 8466 if (vport->used_umv_num >= hdev->priv_umv_size && 8467 hdev->share_umv_size > 0) 8468 hdev->share_umv_size--; 8469 vport->used_umv_num++; 8470 } 8471 } 8472 8473 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8474 const u8 *mac_addr) 8475 { 8476 struct hclge_mac_node *mac_node, *tmp; 8477 8478 list_for_each_entry_safe(mac_node, tmp, list, node) 8479 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8480 return mac_node; 8481 8482 return NULL; 8483 } 8484 8485 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8486 enum HCLGE_MAC_NODE_STATE state) 8487 { 8488 switch (state) { 8489 /* from set_rx_mode or tmp_add_list */ 8490 case HCLGE_MAC_TO_ADD: 8491 if (mac_node->state == HCLGE_MAC_TO_DEL) 8492 mac_node->state = HCLGE_MAC_ACTIVE; 8493 break; 8494 /* only from set_rx_mode */ 8495 case HCLGE_MAC_TO_DEL: 8496 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8497 list_del(&mac_node->node); 8498 kfree(mac_node); 8499 } else { 8500 mac_node->state = HCLGE_MAC_TO_DEL; 8501 } 8502 break; 8503 /* only from tmp_add_list, the mac_node->state won't be 8504 * ACTIVE. 8505 */ 8506 case HCLGE_MAC_ACTIVE: 8507 if (mac_node->state == HCLGE_MAC_TO_ADD) 8508 mac_node->state = HCLGE_MAC_ACTIVE; 8509 8510 break; 8511 } 8512 } 8513 8514 int hclge_update_mac_list(struct hclge_vport *vport, 8515 enum HCLGE_MAC_NODE_STATE state, 8516 enum HCLGE_MAC_ADDR_TYPE mac_type, 8517 const unsigned char *addr) 8518 { 8519 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8520 struct hclge_dev *hdev = vport->back; 8521 struct hclge_mac_node *mac_node; 8522 struct list_head *list; 8523 8524 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8525 &vport->uc_mac_list : &vport->mc_mac_list; 8526 8527 spin_lock_bh(&vport->mac_list_lock); 8528 8529 /* if the mac addr is already in the mac list, no need to add a new 8530 * one into it, just check the mac addr state, convert it to a new 8531 * state, or just remove it, or do nothing. 8532 */ 8533 mac_node = hclge_find_mac_node(list, addr); 8534 if (mac_node) { 8535 hclge_update_mac_node(mac_node, state); 8536 spin_unlock_bh(&vport->mac_list_lock); 8537 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8538 return 0; 8539 } 8540 8541 /* if this address is never added, unnecessary to delete */ 8542 if (state == HCLGE_MAC_TO_DEL) { 8543 spin_unlock_bh(&vport->mac_list_lock); 8544 hnae3_format_mac_addr(format_mac_addr, addr); 8545 dev_err(&hdev->pdev->dev, 8546 "failed to delete address %s from mac list\n", 8547 format_mac_addr); 8548 return -ENOENT; 8549 } 8550 8551 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8552 if (!mac_node) { 8553 spin_unlock_bh(&vport->mac_list_lock); 8554 return -ENOMEM; 8555 } 8556 8557 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8558 8559 mac_node->state = state; 8560 ether_addr_copy(mac_node->mac_addr, addr); 8561 list_add_tail(&mac_node->node, list); 8562 8563 spin_unlock_bh(&vport->mac_list_lock); 8564 8565 return 0; 8566 } 8567 8568 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8569 const unsigned char *addr) 8570 { 8571 struct hclge_vport *vport = hclge_get_vport(handle); 8572 8573 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8574 addr); 8575 } 8576 8577 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8578 const unsigned char *addr) 8579 { 8580 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8581 struct hclge_dev *hdev = vport->back; 8582 struct hclge_mac_vlan_tbl_entry_cmd req; 8583 struct hclge_desc desc; 8584 u16 egress_port = 0; 8585 int ret; 8586 8587 /* mac addr check */ 8588 if (is_zero_ether_addr(addr) || 8589 is_broadcast_ether_addr(addr) || 8590 is_multicast_ether_addr(addr)) { 8591 hnae3_format_mac_addr(format_mac_addr, addr); 8592 dev_err(&hdev->pdev->dev, 8593 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8594 format_mac_addr, is_zero_ether_addr(addr), 8595 is_broadcast_ether_addr(addr), 8596 is_multicast_ether_addr(addr)); 8597 return -EINVAL; 8598 } 8599 8600 memset(&req, 0, sizeof(req)); 8601 8602 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8603 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8604 8605 req.egress_port = cpu_to_le16(egress_port); 8606 8607 hclge_prepare_mac_addr(&req, addr, false); 8608 8609 /* Lookup the mac address in the mac_vlan table, and add 8610 * it if the entry is inexistent. Repeated unicast entry 8611 * is not allowed in the mac vlan table. 8612 */ 8613 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8614 if (ret == -ENOENT) { 8615 mutex_lock(&hdev->vport_lock); 8616 if (!hclge_is_umv_space_full(vport, false)) { 8617 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8618 if (!ret) 8619 hclge_update_umv_space(vport, false); 8620 mutex_unlock(&hdev->vport_lock); 8621 return ret; 8622 } 8623 mutex_unlock(&hdev->vport_lock); 8624 8625 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8626 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8627 hdev->priv_umv_size); 8628 8629 return -ENOSPC; 8630 } 8631 8632 /* check if we just hit the duplicate */ 8633 if (!ret) 8634 return -EEXIST; 8635 8636 return ret; 8637 } 8638 8639 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8640 const unsigned char *addr) 8641 { 8642 struct hclge_vport *vport = hclge_get_vport(handle); 8643 8644 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8645 addr); 8646 } 8647 8648 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8649 const unsigned char *addr) 8650 { 8651 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8652 struct hclge_dev *hdev = vport->back; 8653 struct hclge_mac_vlan_tbl_entry_cmd req; 8654 int ret; 8655 8656 /* mac addr check */ 8657 if (is_zero_ether_addr(addr) || 8658 is_broadcast_ether_addr(addr) || 8659 is_multicast_ether_addr(addr)) { 8660 hnae3_format_mac_addr(format_mac_addr, addr); 8661 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8662 format_mac_addr); 8663 return -EINVAL; 8664 } 8665 8666 memset(&req, 0, sizeof(req)); 8667 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8668 hclge_prepare_mac_addr(&req, addr, false); 8669 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8670 if (!ret || ret == -ENOENT) { 8671 mutex_lock(&hdev->vport_lock); 8672 hclge_update_umv_space(vport, true); 8673 mutex_unlock(&hdev->vport_lock); 8674 return 0; 8675 } 8676 8677 return ret; 8678 } 8679 8680 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8681 const unsigned char *addr) 8682 { 8683 struct hclge_vport *vport = hclge_get_vport(handle); 8684 8685 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8686 addr); 8687 } 8688 8689 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8690 const unsigned char *addr) 8691 { 8692 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8693 struct hclge_dev *hdev = vport->back; 8694 struct hclge_mac_vlan_tbl_entry_cmd req; 8695 struct hclge_desc desc[3]; 8696 bool is_new_addr = false; 8697 int status; 8698 8699 /* mac addr check */ 8700 if (!is_multicast_ether_addr(addr)) { 8701 hnae3_format_mac_addr(format_mac_addr, addr); 8702 dev_err(&hdev->pdev->dev, 8703 "Add mc mac err! invalid mac:%s.\n", 8704 format_mac_addr); 8705 return -EINVAL; 8706 } 8707 memset(&req, 0, sizeof(req)); 8708 hclge_prepare_mac_addr(&req, addr, true); 8709 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8710 if (status) { 8711 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8712 hdev->used_mc_mac_num >= 8713 hdev->ae_dev->dev_specs.mc_mac_size) 8714 goto err_no_space; 8715 8716 is_new_addr = true; 8717 8718 /* This mac addr do not exist, add new entry for it */ 8719 memset(desc[0].data, 0, sizeof(desc[0].data)); 8720 memset(desc[1].data, 0, sizeof(desc[0].data)); 8721 memset(desc[2].data, 0, sizeof(desc[0].data)); 8722 } 8723 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8724 if (status) 8725 return status; 8726 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8727 if (status == -ENOSPC) 8728 goto err_no_space; 8729 else if (!status && is_new_addr) 8730 hdev->used_mc_mac_num++; 8731 8732 return status; 8733 8734 err_no_space: 8735 /* if already overflow, not to print each time */ 8736 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8737 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8738 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8739 } 8740 8741 return -ENOSPC; 8742 } 8743 8744 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8745 const unsigned char *addr) 8746 { 8747 struct hclge_vport *vport = hclge_get_vport(handle); 8748 8749 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8750 addr); 8751 } 8752 8753 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8754 const unsigned char *addr) 8755 { 8756 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8757 struct hclge_dev *hdev = vport->back; 8758 struct hclge_mac_vlan_tbl_entry_cmd req; 8759 enum hclge_comm_cmd_status status; 8760 struct hclge_desc desc[3]; 8761 8762 /* mac addr check */ 8763 if (!is_multicast_ether_addr(addr)) { 8764 hnae3_format_mac_addr(format_mac_addr, addr); 8765 dev_dbg(&hdev->pdev->dev, 8766 "Remove mc mac err! invalid mac:%s.\n", 8767 format_mac_addr); 8768 return -EINVAL; 8769 } 8770 8771 memset(&req, 0, sizeof(req)); 8772 hclge_prepare_mac_addr(&req, addr, true); 8773 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8774 if (!status) { 8775 /* This mac addr exist, remove this handle's VFID for it */ 8776 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8777 if (status) 8778 return status; 8779 8780 if (hclge_is_all_function_id_zero(desc)) { 8781 /* All the vfid is zero, so need to delete this entry */ 8782 status = hclge_remove_mac_vlan_tbl(vport, &req); 8783 if (!status) 8784 hdev->used_mc_mac_num--; 8785 } else { 8786 /* Not all the vfid is zero, update the vfid */ 8787 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8788 } 8789 } else if (status == -ENOENT) { 8790 status = 0; 8791 } 8792 8793 return status; 8794 } 8795 8796 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8797 struct list_head *list, 8798 enum HCLGE_MAC_ADDR_TYPE mac_type) 8799 { 8800 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8801 struct hclge_mac_node *mac_node, *tmp; 8802 int ret; 8803 8804 if (mac_type == HCLGE_MAC_ADDR_UC) 8805 sync = hclge_add_uc_addr_common; 8806 else 8807 sync = hclge_add_mc_addr_common; 8808 8809 list_for_each_entry_safe(mac_node, tmp, list, node) { 8810 ret = sync(vport, mac_node->mac_addr); 8811 if (!ret) { 8812 mac_node->state = HCLGE_MAC_ACTIVE; 8813 } else { 8814 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8815 &vport->state); 8816 8817 /* If one unicast mac address is existing in hardware, 8818 * we need to try whether other unicast mac addresses 8819 * are new addresses that can be added. 8820 * Multicast mac address can be reusable, even though 8821 * there is no space to add new multicast mac address, 8822 * we should check whether other mac addresses are 8823 * existing in hardware for reuse. 8824 */ 8825 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8826 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8827 break; 8828 } 8829 } 8830 } 8831 8832 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8833 struct list_head *list, 8834 enum HCLGE_MAC_ADDR_TYPE mac_type) 8835 { 8836 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8837 struct hclge_mac_node *mac_node, *tmp; 8838 int ret; 8839 8840 if (mac_type == HCLGE_MAC_ADDR_UC) 8841 unsync = hclge_rm_uc_addr_common; 8842 else 8843 unsync = hclge_rm_mc_addr_common; 8844 8845 list_for_each_entry_safe(mac_node, tmp, list, node) { 8846 ret = unsync(vport, mac_node->mac_addr); 8847 if (!ret || ret == -ENOENT) { 8848 list_del(&mac_node->node); 8849 kfree(mac_node); 8850 } else { 8851 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8852 &vport->state); 8853 break; 8854 } 8855 } 8856 } 8857 8858 static bool hclge_sync_from_add_list(struct list_head *add_list, 8859 struct list_head *mac_list) 8860 { 8861 struct hclge_mac_node *mac_node, *tmp, *new_node; 8862 bool all_added = true; 8863 8864 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8865 if (mac_node->state == HCLGE_MAC_TO_ADD) 8866 all_added = false; 8867 8868 /* if the mac address from tmp_add_list is not in the 8869 * uc/mc_mac_list, it means have received a TO_DEL request 8870 * during the time window of adding the mac address into mac 8871 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8872 * then it will be removed at next time. else it must be TO_ADD, 8873 * this address hasn't been added into mac table, 8874 * so just remove the mac node. 8875 */ 8876 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8877 if (new_node) { 8878 hclge_update_mac_node(new_node, mac_node->state); 8879 list_del(&mac_node->node); 8880 kfree(mac_node); 8881 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8882 mac_node->state = HCLGE_MAC_TO_DEL; 8883 list_move_tail(&mac_node->node, mac_list); 8884 } else { 8885 list_del(&mac_node->node); 8886 kfree(mac_node); 8887 } 8888 } 8889 8890 return all_added; 8891 } 8892 8893 static void hclge_sync_from_del_list(struct list_head *del_list, 8894 struct list_head *mac_list) 8895 { 8896 struct hclge_mac_node *mac_node, *tmp, *new_node; 8897 8898 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8899 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8900 if (new_node) { 8901 /* If the mac addr exists in the mac list, it means 8902 * received a new TO_ADD request during the time window 8903 * of configuring the mac address. For the mac node 8904 * state is TO_ADD, and the address is already in the 8905 * in the hardware(due to delete fail), so we just need 8906 * to change the mac node state to ACTIVE. 8907 */ 8908 new_node->state = HCLGE_MAC_ACTIVE; 8909 list_del(&mac_node->node); 8910 kfree(mac_node); 8911 } else { 8912 list_move_tail(&mac_node->node, mac_list); 8913 } 8914 } 8915 } 8916 8917 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8918 enum HCLGE_MAC_ADDR_TYPE mac_type, 8919 bool is_all_added) 8920 { 8921 if (mac_type == HCLGE_MAC_ADDR_UC) { 8922 if (is_all_added) 8923 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8924 else 8925 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8926 } else { 8927 if (is_all_added) 8928 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8929 else 8930 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8931 } 8932 } 8933 8934 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8935 enum HCLGE_MAC_ADDR_TYPE mac_type) 8936 { 8937 struct hclge_mac_node *mac_node, *tmp, *new_node; 8938 struct list_head tmp_add_list, tmp_del_list; 8939 struct list_head *list; 8940 bool all_added; 8941 8942 INIT_LIST_HEAD(&tmp_add_list); 8943 INIT_LIST_HEAD(&tmp_del_list); 8944 8945 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8946 * we can add/delete these mac addr outside the spin lock 8947 */ 8948 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8949 &vport->uc_mac_list : &vport->mc_mac_list; 8950 8951 spin_lock_bh(&vport->mac_list_lock); 8952 8953 list_for_each_entry_safe(mac_node, tmp, list, node) { 8954 switch (mac_node->state) { 8955 case HCLGE_MAC_TO_DEL: 8956 list_move_tail(&mac_node->node, &tmp_del_list); 8957 break; 8958 case HCLGE_MAC_TO_ADD: 8959 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8960 if (!new_node) 8961 goto stop_traverse; 8962 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8963 new_node->state = mac_node->state; 8964 list_add_tail(&new_node->node, &tmp_add_list); 8965 break; 8966 default: 8967 break; 8968 } 8969 } 8970 8971 stop_traverse: 8972 spin_unlock_bh(&vport->mac_list_lock); 8973 8974 /* delete first, in order to get max mac table space for adding */ 8975 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8976 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8977 8978 /* if some mac addresses were added/deleted fail, move back to the 8979 * mac_list, and retry at next time. 8980 */ 8981 spin_lock_bh(&vport->mac_list_lock); 8982 8983 hclge_sync_from_del_list(&tmp_del_list, list); 8984 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8985 8986 spin_unlock_bh(&vport->mac_list_lock); 8987 8988 hclge_update_overflow_flags(vport, mac_type, all_added); 8989 } 8990 8991 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8992 { 8993 struct hclge_dev *hdev = vport->back; 8994 8995 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8996 return false; 8997 8998 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8999 return true; 9000 9001 return false; 9002 } 9003 9004 static void hclge_sync_mac_table(struct hclge_dev *hdev) 9005 { 9006 int i; 9007 9008 for (i = 0; i < hdev->num_alloc_vport; i++) { 9009 struct hclge_vport *vport = &hdev->vport[i]; 9010 9011 if (!hclge_need_sync_mac_table(vport)) 9012 continue; 9013 9014 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9015 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9016 } 9017 } 9018 9019 static void hclge_build_del_list(struct list_head *list, 9020 bool is_del_list, 9021 struct list_head *tmp_del_list) 9022 { 9023 struct hclge_mac_node *mac_cfg, *tmp; 9024 9025 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9026 switch (mac_cfg->state) { 9027 case HCLGE_MAC_TO_DEL: 9028 case HCLGE_MAC_ACTIVE: 9029 list_move_tail(&mac_cfg->node, tmp_del_list); 9030 break; 9031 case HCLGE_MAC_TO_ADD: 9032 if (is_del_list) { 9033 list_del(&mac_cfg->node); 9034 kfree(mac_cfg); 9035 } 9036 break; 9037 } 9038 } 9039 } 9040 9041 static void hclge_unsync_del_list(struct hclge_vport *vport, 9042 int (*unsync)(struct hclge_vport *vport, 9043 const unsigned char *addr), 9044 bool is_del_list, 9045 struct list_head *tmp_del_list) 9046 { 9047 struct hclge_mac_node *mac_cfg, *tmp; 9048 int ret; 9049 9050 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9051 ret = unsync(vport, mac_cfg->mac_addr); 9052 if (!ret || ret == -ENOENT) { 9053 /* clear all mac addr from hardware, but remain these 9054 * mac addr in the mac list, and restore them after 9055 * vf reset finished. 9056 */ 9057 if (!is_del_list && 9058 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9059 mac_cfg->state = HCLGE_MAC_TO_ADD; 9060 } else { 9061 list_del(&mac_cfg->node); 9062 kfree(mac_cfg); 9063 } 9064 } else if (is_del_list) { 9065 mac_cfg->state = HCLGE_MAC_TO_DEL; 9066 } 9067 } 9068 } 9069 9070 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9071 enum HCLGE_MAC_ADDR_TYPE mac_type) 9072 { 9073 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9074 struct hclge_dev *hdev = vport->back; 9075 struct list_head tmp_del_list, *list; 9076 9077 if (mac_type == HCLGE_MAC_ADDR_UC) { 9078 list = &vport->uc_mac_list; 9079 unsync = hclge_rm_uc_addr_common; 9080 } else { 9081 list = &vport->mc_mac_list; 9082 unsync = hclge_rm_mc_addr_common; 9083 } 9084 9085 INIT_LIST_HEAD(&tmp_del_list); 9086 9087 if (!is_del_list) 9088 set_bit(vport->vport_id, hdev->vport_config_block); 9089 9090 spin_lock_bh(&vport->mac_list_lock); 9091 9092 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9093 9094 spin_unlock_bh(&vport->mac_list_lock); 9095 9096 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9097 9098 spin_lock_bh(&vport->mac_list_lock); 9099 9100 hclge_sync_from_del_list(&tmp_del_list, list); 9101 9102 spin_unlock_bh(&vport->mac_list_lock); 9103 } 9104 9105 /* remove all mac address when uninitailize */ 9106 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9107 enum HCLGE_MAC_ADDR_TYPE mac_type) 9108 { 9109 struct hclge_mac_node *mac_node, *tmp; 9110 struct hclge_dev *hdev = vport->back; 9111 struct list_head tmp_del_list, *list; 9112 9113 INIT_LIST_HEAD(&tmp_del_list); 9114 9115 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9116 &vport->uc_mac_list : &vport->mc_mac_list; 9117 9118 spin_lock_bh(&vport->mac_list_lock); 9119 9120 list_for_each_entry_safe(mac_node, tmp, list, node) { 9121 switch (mac_node->state) { 9122 case HCLGE_MAC_TO_DEL: 9123 case HCLGE_MAC_ACTIVE: 9124 list_move_tail(&mac_node->node, &tmp_del_list); 9125 break; 9126 case HCLGE_MAC_TO_ADD: 9127 list_del(&mac_node->node); 9128 kfree(mac_node); 9129 break; 9130 } 9131 } 9132 9133 spin_unlock_bh(&vport->mac_list_lock); 9134 9135 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9136 9137 if (!list_empty(&tmp_del_list)) 9138 dev_warn(&hdev->pdev->dev, 9139 "uninit %s mac list for vport %u not completely.\n", 9140 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9141 vport->vport_id); 9142 9143 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9144 list_del(&mac_node->node); 9145 kfree(mac_node); 9146 } 9147 } 9148 9149 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9150 { 9151 struct hclge_vport *vport; 9152 int i; 9153 9154 for (i = 0; i < hdev->num_alloc_vport; i++) { 9155 vport = &hdev->vport[i]; 9156 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9157 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9158 } 9159 } 9160 9161 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9162 u16 cmdq_resp, u8 resp_code) 9163 { 9164 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9165 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9166 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9167 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9168 9169 int return_status; 9170 9171 if (cmdq_resp) { 9172 dev_err(&hdev->pdev->dev, 9173 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9174 cmdq_resp); 9175 return -EIO; 9176 } 9177 9178 switch (resp_code) { 9179 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9180 case HCLGE_ETHERTYPE_ALREADY_ADD: 9181 return_status = 0; 9182 break; 9183 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9184 dev_err(&hdev->pdev->dev, 9185 "add mac ethertype failed for manager table overflow.\n"); 9186 return_status = -EIO; 9187 break; 9188 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9189 dev_err(&hdev->pdev->dev, 9190 "add mac ethertype failed for key conflict.\n"); 9191 return_status = -EIO; 9192 break; 9193 default: 9194 dev_err(&hdev->pdev->dev, 9195 "add mac ethertype failed for undefined, code=%u.\n", 9196 resp_code); 9197 return_status = -EIO; 9198 } 9199 9200 return return_status; 9201 } 9202 9203 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9204 u8 *mac_addr) 9205 { 9206 struct hclge_vport *vport = hclge_get_vport(handle); 9207 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9208 struct hclge_dev *hdev = vport->back; 9209 9210 vport = hclge_get_vf_vport(hdev, vf); 9211 if (!vport) 9212 return -EINVAL; 9213 9214 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9215 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9216 dev_info(&hdev->pdev->dev, 9217 "Specified MAC(=%s) is same as before, no change committed!\n", 9218 format_mac_addr); 9219 return 0; 9220 } 9221 9222 ether_addr_copy(vport->vf_info.mac, mac_addr); 9223 9224 /* there is a timewindow for PF to know VF unalive, it may 9225 * cause send mailbox fail, but it doesn't matter, VF will 9226 * query it when reinit. 9227 */ 9228 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9229 dev_info(&hdev->pdev->dev, 9230 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9231 vf, format_mac_addr); 9232 (void)hclge_inform_reset_assert_to_vf(vport); 9233 return 0; 9234 } 9235 9236 dev_info(&hdev->pdev->dev, 9237 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9238 vf, format_mac_addr); 9239 return 0; 9240 } 9241 9242 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9243 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9244 { 9245 struct hclge_desc desc; 9246 u8 resp_code; 9247 u16 retval; 9248 int ret; 9249 9250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9251 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9252 9253 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9254 if (ret) { 9255 dev_err(&hdev->pdev->dev, 9256 "add mac ethertype failed for cmd_send, ret =%d.\n", 9257 ret); 9258 return ret; 9259 } 9260 9261 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9262 retval = le16_to_cpu(desc.retval); 9263 9264 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9265 } 9266 9267 static int init_mgr_tbl(struct hclge_dev *hdev) 9268 { 9269 int ret; 9270 int i; 9271 9272 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9273 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9274 if (ret) { 9275 dev_err(&hdev->pdev->dev, 9276 "add mac ethertype failed, ret =%d.\n", 9277 ret); 9278 return ret; 9279 } 9280 } 9281 9282 return 0; 9283 } 9284 9285 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9286 { 9287 struct hclge_vport *vport = hclge_get_vport(handle); 9288 struct hclge_dev *hdev = vport->back; 9289 9290 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9291 } 9292 9293 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9294 const u8 *old_addr, const u8 *new_addr) 9295 { 9296 struct list_head *list = &vport->uc_mac_list; 9297 struct hclge_mac_node *old_node, *new_node; 9298 9299 new_node = hclge_find_mac_node(list, new_addr); 9300 if (!new_node) { 9301 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9302 if (!new_node) 9303 return -ENOMEM; 9304 9305 new_node->state = HCLGE_MAC_TO_ADD; 9306 ether_addr_copy(new_node->mac_addr, new_addr); 9307 list_add(&new_node->node, list); 9308 } else { 9309 if (new_node->state == HCLGE_MAC_TO_DEL) 9310 new_node->state = HCLGE_MAC_ACTIVE; 9311 9312 /* make sure the new addr is in the list head, avoid dev 9313 * addr may be not re-added into mac table for the umv space 9314 * limitation after global/imp reset which will clear mac 9315 * table by hardware. 9316 */ 9317 list_move(&new_node->node, list); 9318 } 9319 9320 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9321 old_node = hclge_find_mac_node(list, old_addr); 9322 if (old_node) { 9323 if (old_node->state == HCLGE_MAC_TO_ADD) { 9324 list_del(&old_node->node); 9325 kfree(old_node); 9326 } else { 9327 old_node->state = HCLGE_MAC_TO_DEL; 9328 } 9329 } 9330 } 9331 9332 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9333 9334 return 0; 9335 } 9336 9337 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9338 bool is_first) 9339 { 9340 const unsigned char *new_addr = (const unsigned char *)p; 9341 struct hclge_vport *vport = hclge_get_vport(handle); 9342 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9343 struct hclge_dev *hdev = vport->back; 9344 unsigned char *old_addr = NULL; 9345 int ret; 9346 9347 /* mac addr check */ 9348 if (is_zero_ether_addr(new_addr) || 9349 is_broadcast_ether_addr(new_addr) || 9350 is_multicast_ether_addr(new_addr)) { 9351 hnae3_format_mac_addr(format_mac_addr, new_addr); 9352 dev_err(&hdev->pdev->dev, 9353 "change uc mac err! invalid mac: %s.\n", 9354 format_mac_addr); 9355 return -EINVAL; 9356 } 9357 9358 ret = hclge_pause_addr_cfg(hdev, new_addr); 9359 if (ret) { 9360 dev_err(&hdev->pdev->dev, 9361 "failed to configure mac pause address, ret = %d\n", 9362 ret); 9363 return ret; 9364 } 9365 9366 if (!is_first) 9367 old_addr = hdev->hw.mac.mac_addr; 9368 9369 spin_lock_bh(&vport->mac_list_lock); 9370 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9371 if (ret) { 9372 hnae3_format_mac_addr(format_mac_addr, new_addr); 9373 dev_err(&hdev->pdev->dev, 9374 "failed to change the mac addr:%s, ret = %d\n", 9375 format_mac_addr, ret); 9376 spin_unlock_bh(&vport->mac_list_lock); 9377 9378 if (!is_first) 9379 hclge_pause_addr_cfg(hdev, old_addr); 9380 9381 return ret; 9382 } 9383 /* we must update dev addr with spin lock protect, preventing dev addr 9384 * being removed by set_rx_mode path. 9385 */ 9386 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9387 spin_unlock_bh(&vport->mac_list_lock); 9388 9389 hclge_task_schedule(hdev, 0); 9390 9391 return 0; 9392 } 9393 9394 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9395 { 9396 struct mii_ioctl_data *data = if_mii(ifr); 9397 9398 if (!hnae3_dev_phy_imp_supported(hdev)) 9399 return -EOPNOTSUPP; 9400 9401 switch (cmd) { 9402 case SIOCGMIIPHY: 9403 data->phy_id = hdev->hw.mac.phy_addr; 9404 /* this command reads phy id and register at the same time */ 9405 fallthrough; 9406 case SIOCGMIIREG: 9407 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9408 return 0; 9409 9410 case SIOCSMIIREG: 9411 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9412 default: 9413 return -EOPNOTSUPP; 9414 } 9415 } 9416 9417 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9418 int cmd) 9419 { 9420 struct hclge_vport *vport = hclge_get_vport(handle); 9421 struct hclge_dev *hdev = vport->back; 9422 9423 switch (cmd) { 9424 case SIOCGHWTSTAMP: 9425 return hclge_ptp_get_cfg(hdev, ifr); 9426 case SIOCSHWTSTAMP: 9427 return hclge_ptp_set_cfg(hdev, ifr); 9428 default: 9429 if (!hdev->hw.mac.phydev) 9430 return hclge_mii_ioctl(hdev, ifr, cmd); 9431 } 9432 9433 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9434 } 9435 9436 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9437 bool bypass_en) 9438 { 9439 struct hclge_port_vlan_filter_bypass_cmd *req; 9440 struct hclge_desc desc; 9441 int ret; 9442 9443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9444 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9445 req->vf_id = vf_id; 9446 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9447 bypass_en ? 1 : 0); 9448 9449 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9450 if (ret) 9451 dev_err(&hdev->pdev->dev, 9452 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9453 vf_id, ret); 9454 9455 return ret; 9456 } 9457 9458 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9459 u8 fe_type, bool filter_en, u8 vf_id) 9460 { 9461 struct hclge_vlan_filter_ctrl_cmd *req; 9462 struct hclge_desc desc; 9463 int ret; 9464 9465 /* read current vlan filter parameter */ 9466 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9467 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9468 req->vlan_type = vlan_type; 9469 req->vf_id = vf_id; 9470 9471 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9472 if (ret) { 9473 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9474 vf_id, ret); 9475 return ret; 9476 } 9477 9478 /* modify and write new config parameter */ 9479 hclge_comm_cmd_reuse_desc(&desc, false); 9480 req->vlan_fe = filter_en ? 9481 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9482 9483 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9484 if (ret) 9485 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9486 vf_id, ret); 9487 9488 return ret; 9489 } 9490 9491 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9492 { 9493 struct hclge_dev *hdev = vport->back; 9494 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9495 int ret; 9496 9497 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9498 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9499 HCLGE_FILTER_FE_EGRESS_V1_B, 9500 enable, vport->vport_id); 9501 9502 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9503 HCLGE_FILTER_FE_EGRESS, enable, 9504 vport->vport_id); 9505 if (ret) 9506 return ret; 9507 9508 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9509 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9510 !enable); 9511 } else if (!vport->vport_id) { 9512 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9513 enable = false; 9514 9515 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9516 HCLGE_FILTER_FE_INGRESS, 9517 enable, 0); 9518 } 9519 9520 return ret; 9521 } 9522 9523 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9524 { 9525 struct hnae3_handle *handle = &vport->nic; 9526 struct hclge_vport_vlan_cfg *vlan, *tmp; 9527 struct hclge_dev *hdev = vport->back; 9528 9529 if (vport->vport_id) { 9530 if (vport->port_base_vlan_cfg.state != 9531 HNAE3_PORT_BASE_VLAN_DISABLE) 9532 return true; 9533 9534 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9535 return false; 9536 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9537 return false; 9538 } 9539 9540 if (!vport->req_vlan_fltr_en) 9541 return false; 9542 9543 /* compatible with former device, always enable vlan filter */ 9544 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9545 return true; 9546 9547 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9548 if (vlan->vlan_id != 0) 9549 return true; 9550 9551 return false; 9552 } 9553 9554 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9555 { 9556 struct hclge_dev *hdev = vport->back; 9557 bool need_en; 9558 int ret; 9559 9560 mutex_lock(&hdev->vport_lock); 9561 9562 vport->req_vlan_fltr_en = request_en; 9563 9564 need_en = hclge_need_enable_vport_vlan_filter(vport); 9565 if (need_en == vport->cur_vlan_fltr_en) { 9566 mutex_unlock(&hdev->vport_lock); 9567 return 0; 9568 } 9569 9570 ret = hclge_set_vport_vlan_filter(vport, need_en); 9571 if (ret) { 9572 mutex_unlock(&hdev->vport_lock); 9573 return ret; 9574 } 9575 9576 vport->cur_vlan_fltr_en = need_en; 9577 9578 mutex_unlock(&hdev->vport_lock); 9579 9580 return 0; 9581 } 9582 9583 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9584 { 9585 struct hclge_vport *vport = hclge_get_vport(handle); 9586 9587 return hclge_enable_vport_vlan_filter(vport, enable); 9588 } 9589 9590 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9591 bool is_kill, u16 vlan, 9592 struct hclge_desc *desc) 9593 { 9594 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9595 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9596 u8 vf_byte_val; 9597 u8 vf_byte_off; 9598 int ret; 9599 9600 hclge_cmd_setup_basic_desc(&desc[0], 9601 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9602 hclge_cmd_setup_basic_desc(&desc[1], 9603 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9604 9605 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9606 9607 vf_byte_off = vfid / 8; 9608 vf_byte_val = 1 << (vfid % 8); 9609 9610 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9611 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9612 9613 req0->vlan_id = cpu_to_le16(vlan); 9614 req0->vlan_cfg = is_kill; 9615 9616 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9617 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9618 else 9619 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9620 9621 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9622 if (ret) { 9623 dev_err(&hdev->pdev->dev, 9624 "Send vf vlan command fail, ret =%d.\n", 9625 ret); 9626 return ret; 9627 } 9628 9629 return 0; 9630 } 9631 9632 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9633 bool is_kill, struct hclge_desc *desc) 9634 { 9635 struct hclge_vlan_filter_vf_cfg_cmd *req; 9636 9637 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9638 9639 if (!is_kill) { 9640 #define HCLGE_VF_VLAN_NO_ENTRY 2 9641 if (!req->resp_code || req->resp_code == 1) 9642 return 0; 9643 9644 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9645 set_bit(vfid, hdev->vf_vlan_full); 9646 dev_warn(&hdev->pdev->dev, 9647 "vf vlan table is full, vf vlan filter is disabled\n"); 9648 return 0; 9649 } 9650 9651 dev_err(&hdev->pdev->dev, 9652 "Add vf vlan filter fail, ret =%u.\n", 9653 req->resp_code); 9654 } else { 9655 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9656 if (!req->resp_code) 9657 return 0; 9658 9659 /* vf vlan filter is disabled when vf vlan table is full, 9660 * then new vlan id will not be added into vf vlan table. 9661 * Just return 0 without warning, avoid massive verbose 9662 * print logs when unload. 9663 */ 9664 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9665 return 0; 9666 9667 dev_err(&hdev->pdev->dev, 9668 "Kill vf vlan filter fail, ret =%u.\n", 9669 req->resp_code); 9670 } 9671 9672 return -EIO; 9673 } 9674 9675 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9676 bool is_kill, u16 vlan) 9677 { 9678 struct hclge_vport *vport = &hdev->vport[vfid]; 9679 struct hclge_desc desc[2]; 9680 int ret; 9681 9682 /* if vf vlan table is full, firmware will close vf vlan filter, it 9683 * is unable and unnecessary to add new vlan id to vf vlan filter. 9684 * If spoof check is enable, and vf vlan is full, it shouldn't add 9685 * new vlan, because tx packets with these vlan id will be dropped. 9686 */ 9687 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9688 if (vport->vf_info.spoofchk && vlan) { 9689 dev_err(&hdev->pdev->dev, 9690 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9691 return -EPERM; 9692 } 9693 return 0; 9694 } 9695 9696 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9697 if (ret) 9698 return ret; 9699 9700 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9701 } 9702 9703 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9704 u16 vlan_id, bool is_kill) 9705 { 9706 struct hclge_vlan_filter_pf_cfg_cmd *req; 9707 struct hclge_desc desc; 9708 u8 vlan_offset_byte_val; 9709 u8 vlan_offset_byte; 9710 u8 vlan_offset_160; 9711 int ret; 9712 9713 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9714 9715 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9716 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9717 HCLGE_VLAN_BYTE_SIZE; 9718 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9719 9720 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9721 req->vlan_offset = vlan_offset_160; 9722 req->vlan_cfg = is_kill; 9723 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9724 9725 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9726 if (ret) 9727 dev_err(&hdev->pdev->dev, 9728 "port vlan command, send fail, ret =%d.\n", ret); 9729 return ret; 9730 } 9731 9732 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9733 u16 vlan_id, bool is_kill) 9734 { 9735 /* vlan 0 may be added twice when 8021q module is enabled */ 9736 if (!is_kill && !vlan_id && 9737 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9738 return false; 9739 9740 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9741 dev_warn(&hdev->pdev->dev, 9742 "Add port vlan failed, vport %u is already in vlan %u\n", 9743 vport_id, vlan_id); 9744 return false; 9745 } 9746 9747 if (is_kill && 9748 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9749 dev_warn(&hdev->pdev->dev, 9750 "Delete port vlan failed, vport %u is not in vlan %u\n", 9751 vport_id, vlan_id); 9752 return false; 9753 } 9754 9755 return true; 9756 } 9757 9758 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9759 u16 vport_id, u16 vlan_id, 9760 bool is_kill) 9761 { 9762 u16 vport_idx, vport_num = 0; 9763 int ret; 9764 9765 if (is_kill && !vlan_id) 9766 return 0; 9767 9768 if (vlan_id >= VLAN_N_VID) 9769 return -EINVAL; 9770 9771 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9772 if (ret) { 9773 dev_err(&hdev->pdev->dev, 9774 "Set %u vport vlan filter config fail, ret =%d.\n", 9775 vport_id, ret); 9776 return ret; 9777 } 9778 9779 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9780 return 0; 9781 9782 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9783 vport_num++; 9784 9785 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9786 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9787 is_kill); 9788 9789 return ret; 9790 } 9791 9792 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9793 { 9794 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9795 struct hclge_vport_vtag_tx_cfg_cmd *req; 9796 struct hclge_dev *hdev = vport->back; 9797 struct hclge_desc desc; 9798 u16 bmap_index; 9799 int status; 9800 9801 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9802 9803 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9804 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9805 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9806 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9807 vcfg->accept_tag1 ? 1 : 0); 9808 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9809 vcfg->accept_untag1 ? 1 : 0); 9810 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9811 vcfg->accept_tag2 ? 1 : 0); 9812 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9813 vcfg->accept_untag2 ? 1 : 0); 9814 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9815 vcfg->insert_tag1_en ? 1 : 0); 9816 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9817 vcfg->insert_tag2_en ? 1 : 0); 9818 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9819 vcfg->tag_shift_mode_en ? 1 : 0); 9820 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9821 9822 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9823 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9824 HCLGE_VF_NUM_PER_BYTE; 9825 req->vf_bitmap[bmap_index] = 9826 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9827 9828 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9829 if (status) 9830 dev_err(&hdev->pdev->dev, 9831 "Send port txvlan cfg command fail, ret =%d\n", 9832 status); 9833 9834 return status; 9835 } 9836 9837 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9838 { 9839 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9840 struct hclge_vport_vtag_rx_cfg_cmd *req; 9841 struct hclge_dev *hdev = vport->back; 9842 struct hclge_desc desc; 9843 u16 bmap_index; 9844 int status; 9845 9846 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9847 9848 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9849 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9850 vcfg->strip_tag1_en ? 1 : 0); 9851 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9852 vcfg->strip_tag2_en ? 1 : 0); 9853 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9854 vcfg->vlan1_vlan_prionly ? 1 : 0); 9855 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9856 vcfg->vlan2_vlan_prionly ? 1 : 0); 9857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9858 vcfg->strip_tag1_discard_en ? 1 : 0); 9859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9860 vcfg->strip_tag2_discard_en ? 1 : 0); 9861 9862 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9863 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9864 HCLGE_VF_NUM_PER_BYTE; 9865 req->vf_bitmap[bmap_index] = 9866 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9867 9868 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9869 if (status) 9870 dev_err(&hdev->pdev->dev, 9871 "Send port rxvlan cfg command fail, ret =%d\n", 9872 status); 9873 9874 return status; 9875 } 9876 9877 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9878 u16 port_base_vlan_state, 9879 u16 vlan_tag, u8 qos) 9880 { 9881 int ret; 9882 9883 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9884 vport->txvlan_cfg.accept_tag1 = true; 9885 vport->txvlan_cfg.insert_tag1_en = false; 9886 vport->txvlan_cfg.default_tag1 = 0; 9887 } else { 9888 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9889 9890 vport->txvlan_cfg.accept_tag1 = 9891 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9892 vport->txvlan_cfg.insert_tag1_en = true; 9893 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9894 vlan_tag; 9895 } 9896 9897 vport->txvlan_cfg.accept_untag1 = true; 9898 9899 /* accept_tag2 and accept_untag2 are not supported on 9900 * pdev revision(0x20), new revision support them, 9901 * this two fields can not be configured by user. 9902 */ 9903 vport->txvlan_cfg.accept_tag2 = true; 9904 vport->txvlan_cfg.accept_untag2 = true; 9905 vport->txvlan_cfg.insert_tag2_en = false; 9906 vport->txvlan_cfg.default_tag2 = 0; 9907 vport->txvlan_cfg.tag_shift_mode_en = true; 9908 9909 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9910 vport->rxvlan_cfg.strip_tag1_en = false; 9911 vport->rxvlan_cfg.strip_tag2_en = 9912 vport->rxvlan_cfg.rx_vlan_offload_en; 9913 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9914 } else { 9915 vport->rxvlan_cfg.strip_tag1_en = 9916 vport->rxvlan_cfg.rx_vlan_offload_en; 9917 vport->rxvlan_cfg.strip_tag2_en = true; 9918 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9919 } 9920 9921 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9922 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9923 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9924 9925 ret = hclge_set_vlan_tx_offload_cfg(vport); 9926 if (ret) 9927 return ret; 9928 9929 return hclge_set_vlan_rx_offload_cfg(vport); 9930 } 9931 9932 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9933 { 9934 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9935 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9936 struct hclge_desc desc; 9937 int status; 9938 9939 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9940 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9941 rx_req->ot_fst_vlan_type = 9942 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9943 rx_req->ot_sec_vlan_type = 9944 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9945 rx_req->in_fst_vlan_type = 9946 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9947 rx_req->in_sec_vlan_type = 9948 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9949 9950 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9951 if (status) { 9952 dev_err(&hdev->pdev->dev, 9953 "Send rxvlan protocol type command fail, ret =%d\n", 9954 status); 9955 return status; 9956 } 9957 9958 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9959 9960 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9961 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9962 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9963 9964 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9965 if (status) 9966 dev_err(&hdev->pdev->dev, 9967 "Send txvlan protocol type command fail, ret =%d\n", 9968 status); 9969 9970 return status; 9971 } 9972 9973 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9974 { 9975 struct hclge_vport *vport; 9976 int ret; 9977 int i; 9978 9979 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9980 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9981 HCLGE_FILTER_FE_EGRESS_V1_B, 9982 true, 0); 9983 9984 /* for revision 0x21, vf vlan filter is per function */ 9985 for (i = 0; i < hdev->num_alloc_vport; i++) { 9986 vport = &hdev->vport[i]; 9987 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9988 HCLGE_FILTER_FE_EGRESS, true, 9989 vport->vport_id); 9990 if (ret) 9991 return ret; 9992 vport->cur_vlan_fltr_en = true; 9993 } 9994 9995 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9996 HCLGE_FILTER_FE_INGRESS, true, 0); 9997 } 9998 9999 static int hclge_init_vlan_type(struct hclge_dev *hdev) 10000 { 10001 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 10002 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 10003 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 10004 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 10005 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10006 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10007 10008 return hclge_set_vlan_protocol_type(hdev); 10009 } 10010 10011 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10012 { 10013 struct hclge_port_base_vlan_config *cfg; 10014 struct hclge_vport *vport; 10015 int ret; 10016 int i; 10017 10018 for (i = 0; i < hdev->num_alloc_vport; i++) { 10019 vport = &hdev->vport[i]; 10020 cfg = &vport->port_base_vlan_cfg; 10021 10022 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10023 cfg->vlan_info.vlan_tag, 10024 cfg->vlan_info.qos); 10025 if (ret) 10026 return ret; 10027 } 10028 return 0; 10029 } 10030 10031 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10032 { 10033 struct hnae3_handle *handle = &hdev->vport[0].nic; 10034 int ret; 10035 10036 ret = hclge_init_vlan_filter(hdev); 10037 if (ret) 10038 return ret; 10039 10040 ret = hclge_init_vlan_type(hdev); 10041 if (ret) 10042 return ret; 10043 10044 ret = hclge_init_vport_vlan_offload(hdev); 10045 if (ret) 10046 return ret; 10047 10048 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10049 } 10050 10051 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10052 bool writen_to_tbl) 10053 { 10054 struct hclge_vport_vlan_cfg *vlan, *tmp; 10055 struct hclge_dev *hdev = vport->back; 10056 10057 mutex_lock(&hdev->vport_lock); 10058 10059 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10060 if (vlan->vlan_id == vlan_id) { 10061 mutex_unlock(&hdev->vport_lock); 10062 return; 10063 } 10064 } 10065 10066 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10067 if (!vlan) { 10068 mutex_unlock(&hdev->vport_lock); 10069 return; 10070 } 10071 10072 vlan->hd_tbl_status = writen_to_tbl; 10073 vlan->vlan_id = vlan_id; 10074 10075 list_add_tail(&vlan->node, &vport->vlan_list); 10076 mutex_unlock(&hdev->vport_lock); 10077 } 10078 10079 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10080 { 10081 struct hclge_vport_vlan_cfg *vlan, *tmp; 10082 struct hclge_dev *hdev = vport->back; 10083 int ret; 10084 10085 mutex_lock(&hdev->vport_lock); 10086 10087 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10088 if (!vlan->hd_tbl_status) { 10089 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10090 vport->vport_id, 10091 vlan->vlan_id, false); 10092 if (ret) { 10093 dev_err(&hdev->pdev->dev, 10094 "restore vport vlan list failed, ret=%d\n", 10095 ret); 10096 10097 mutex_unlock(&hdev->vport_lock); 10098 return ret; 10099 } 10100 } 10101 vlan->hd_tbl_status = true; 10102 } 10103 10104 mutex_unlock(&hdev->vport_lock); 10105 10106 return 0; 10107 } 10108 10109 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10110 bool is_write_tbl) 10111 { 10112 struct hclge_vport_vlan_cfg *vlan, *tmp; 10113 struct hclge_dev *hdev = vport->back; 10114 10115 mutex_lock(&hdev->vport_lock); 10116 10117 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10118 if (vlan->vlan_id == vlan_id) { 10119 if (is_write_tbl && vlan->hd_tbl_status) 10120 hclge_set_vlan_filter_hw(hdev, 10121 htons(ETH_P_8021Q), 10122 vport->vport_id, 10123 vlan_id, 10124 true); 10125 10126 list_del(&vlan->node); 10127 kfree(vlan); 10128 break; 10129 } 10130 } 10131 10132 mutex_unlock(&hdev->vport_lock); 10133 } 10134 10135 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10136 { 10137 struct hclge_vport_vlan_cfg *vlan, *tmp; 10138 struct hclge_dev *hdev = vport->back; 10139 10140 mutex_lock(&hdev->vport_lock); 10141 10142 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10143 if (vlan->hd_tbl_status) 10144 hclge_set_vlan_filter_hw(hdev, 10145 htons(ETH_P_8021Q), 10146 vport->vport_id, 10147 vlan->vlan_id, 10148 true); 10149 10150 vlan->hd_tbl_status = false; 10151 if (is_del_list) { 10152 list_del(&vlan->node); 10153 kfree(vlan); 10154 } 10155 } 10156 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10157 mutex_unlock(&hdev->vport_lock); 10158 } 10159 10160 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10161 { 10162 struct hclge_vport_vlan_cfg *vlan, *tmp; 10163 struct hclge_vport *vport; 10164 int i; 10165 10166 mutex_lock(&hdev->vport_lock); 10167 10168 for (i = 0; i < hdev->num_alloc_vport; i++) { 10169 vport = &hdev->vport[i]; 10170 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10171 list_del(&vlan->node); 10172 kfree(vlan); 10173 } 10174 } 10175 10176 mutex_unlock(&hdev->vport_lock); 10177 } 10178 10179 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10180 { 10181 struct hclge_vlan_info *vlan_info; 10182 struct hclge_vport *vport; 10183 u16 vlan_proto; 10184 u16 vlan_id; 10185 u16 state; 10186 int vf_id; 10187 int ret; 10188 10189 /* PF should restore all vfs port base vlan */ 10190 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10191 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10192 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10193 &vport->port_base_vlan_cfg.vlan_info : 10194 &vport->port_base_vlan_cfg.old_vlan_info; 10195 10196 vlan_id = vlan_info->vlan_tag; 10197 vlan_proto = vlan_info->vlan_proto; 10198 state = vport->port_base_vlan_cfg.state; 10199 10200 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10201 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10202 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10203 vport->vport_id, 10204 vlan_id, false); 10205 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10206 } 10207 } 10208 } 10209 10210 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10211 { 10212 struct hclge_vport_vlan_cfg *vlan, *tmp; 10213 struct hclge_dev *hdev = vport->back; 10214 int ret; 10215 10216 mutex_lock(&hdev->vport_lock); 10217 10218 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10219 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10220 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10221 vport->vport_id, 10222 vlan->vlan_id, false); 10223 if (ret) 10224 break; 10225 vlan->hd_tbl_status = true; 10226 } 10227 } 10228 10229 mutex_unlock(&hdev->vport_lock); 10230 } 10231 10232 /* For global reset and imp reset, hardware will clear the mac table, 10233 * so we change the mac address state from ACTIVE to TO_ADD, then they 10234 * can be restored in the service task after reset complete. Furtherly, 10235 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10236 * be restored after reset, so just remove these mac nodes from mac_list. 10237 */ 10238 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10239 { 10240 struct hclge_mac_node *mac_node, *tmp; 10241 10242 list_for_each_entry_safe(mac_node, tmp, list, node) { 10243 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10244 mac_node->state = HCLGE_MAC_TO_ADD; 10245 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10246 list_del(&mac_node->node); 10247 kfree(mac_node); 10248 } 10249 } 10250 } 10251 10252 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10253 { 10254 spin_lock_bh(&vport->mac_list_lock); 10255 10256 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10257 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10258 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10259 10260 spin_unlock_bh(&vport->mac_list_lock); 10261 } 10262 10263 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10264 { 10265 struct hclge_vport *vport = &hdev->vport[0]; 10266 struct hnae3_handle *handle = &vport->nic; 10267 10268 hclge_restore_mac_table_common(vport); 10269 hclge_restore_vport_port_base_vlan_config(hdev); 10270 hclge_restore_vport_vlan_table(vport); 10271 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10272 hclge_restore_fd_entries(handle); 10273 } 10274 10275 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10276 { 10277 struct hclge_vport *vport = hclge_get_vport(handle); 10278 10279 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10280 vport->rxvlan_cfg.strip_tag1_en = false; 10281 vport->rxvlan_cfg.strip_tag2_en = enable; 10282 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10283 } else { 10284 vport->rxvlan_cfg.strip_tag1_en = enable; 10285 vport->rxvlan_cfg.strip_tag2_en = true; 10286 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10287 } 10288 10289 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10290 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10291 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10292 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10293 10294 return hclge_set_vlan_rx_offload_cfg(vport); 10295 } 10296 10297 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10298 { 10299 struct hclge_dev *hdev = vport->back; 10300 10301 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10302 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10303 } 10304 10305 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10306 u16 port_base_vlan_state, 10307 struct hclge_vlan_info *new_info, 10308 struct hclge_vlan_info *old_info) 10309 { 10310 struct hclge_dev *hdev = vport->back; 10311 int ret; 10312 10313 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10314 hclge_rm_vport_all_vlan_table(vport, false); 10315 /* force clear VLAN 0 */ 10316 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10317 if (ret) 10318 return ret; 10319 return hclge_set_vlan_filter_hw(hdev, 10320 htons(new_info->vlan_proto), 10321 vport->vport_id, 10322 new_info->vlan_tag, 10323 false); 10324 } 10325 10326 vport->port_base_vlan_cfg.tbl_sta = false; 10327 10328 /* force add VLAN 0 */ 10329 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10330 if (ret) 10331 return ret; 10332 10333 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10334 vport->vport_id, old_info->vlan_tag, 10335 true); 10336 if (ret) 10337 return ret; 10338 10339 return hclge_add_vport_all_vlan_table(vport); 10340 } 10341 10342 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10343 const struct hclge_vlan_info *old_cfg) 10344 { 10345 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10346 return true; 10347 10348 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10349 return true; 10350 10351 return false; 10352 } 10353 10354 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10355 struct hclge_vlan_info *new_info, 10356 struct hclge_vlan_info *old_info) 10357 { 10358 struct hclge_dev *hdev = vport->back; 10359 int ret; 10360 10361 /* add new VLAN tag */ 10362 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10363 vport->vport_id, new_info->vlan_tag, 10364 false); 10365 if (ret) 10366 return ret; 10367 10368 vport->port_base_vlan_cfg.tbl_sta = false; 10369 /* remove old VLAN tag */ 10370 if (old_info->vlan_tag == 0) 10371 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10372 true, 0); 10373 else 10374 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10375 vport->vport_id, 10376 old_info->vlan_tag, true); 10377 if (ret) 10378 dev_err(&hdev->pdev->dev, 10379 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10380 vport->vport_id, old_info->vlan_tag, ret); 10381 10382 return ret; 10383 } 10384 10385 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10386 struct hclge_vlan_info *vlan_info) 10387 { 10388 struct hnae3_handle *nic = &vport->nic; 10389 struct hclge_vlan_info *old_vlan_info; 10390 int ret; 10391 10392 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10393 10394 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10395 vlan_info->qos); 10396 if (ret) 10397 return ret; 10398 10399 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10400 goto out; 10401 10402 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10403 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10404 old_vlan_info); 10405 else 10406 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10407 old_vlan_info); 10408 if (ret) 10409 return ret; 10410 10411 out: 10412 vport->port_base_vlan_cfg.state = state; 10413 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10414 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10415 else 10416 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10417 10418 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10419 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10420 vport->port_base_vlan_cfg.tbl_sta = true; 10421 hclge_set_vport_vlan_fltr_change(vport); 10422 10423 return 0; 10424 } 10425 10426 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10427 enum hnae3_port_base_vlan_state state, 10428 u16 vlan, u8 qos) 10429 { 10430 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10431 if (!vlan && !qos) 10432 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10433 10434 return HNAE3_PORT_BASE_VLAN_ENABLE; 10435 } 10436 10437 if (!vlan && !qos) 10438 return HNAE3_PORT_BASE_VLAN_DISABLE; 10439 10440 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10441 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10442 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10443 10444 return HNAE3_PORT_BASE_VLAN_MODIFY; 10445 } 10446 10447 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10448 u16 vlan, u8 qos, __be16 proto) 10449 { 10450 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10451 struct hclge_vport *vport = hclge_get_vport(handle); 10452 struct hclge_dev *hdev = vport->back; 10453 struct hclge_vlan_info vlan_info; 10454 u16 state; 10455 int ret; 10456 10457 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10458 return -EOPNOTSUPP; 10459 10460 vport = hclge_get_vf_vport(hdev, vfid); 10461 if (!vport) 10462 return -EINVAL; 10463 10464 /* qos is a 3 bits value, so can not be bigger than 7 */ 10465 if (vlan > VLAN_N_VID - 1 || qos > 7) 10466 return -EINVAL; 10467 if (proto != htons(ETH_P_8021Q)) 10468 return -EPROTONOSUPPORT; 10469 10470 state = hclge_get_port_base_vlan_state(vport, 10471 vport->port_base_vlan_cfg.state, 10472 vlan, qos); 10473 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10474 return 0; 10475 10476 vlan_info.vlan_tag = vlan; 10477 vlan_info.qos = qos; 10478 vlan_info.vlan_proto = ntohs(proto); 10479 10480 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10481 if (ret) { 10482 dev_err(&hdev->pdev->dev, 10483 "failed to update port base vlan for vf %d, ret = %d\n", 10484 vfid, ret); 10485 return ret; 10486 } 10487 10488 /* there is a timewindow for PF to know VF unalive, it may 10489 * cause send mailbox fail, but it doesn't matter, VF will 10490 * query it when reinit. 10491 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10492 * VLAN state. 10493 */ 10494 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10495 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10496 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10497 vport->vport_id, 10498 state, 10499 &vlan_info); 10500 else 10501 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10502 &vport->need_notify); 10503 } 10504 return 0; 10505 } 10506 10507 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10508 { 10509 struct hclge_vlan_info *vlan_info; 10510 struct hclge_vport *vport; 10511 int ret; 10512 int vf; 10513 10514 /* clear port base vlan for all vf */ 10515 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10516 vport = &hdev->vport[vf]; 10517 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10518 10519 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10520 vport->vport_id, 10521 vlan_info->vlan_tag, true); 10522 if (ret) 10523 dev_err(&hdev->pdev->dev, 10524 "failed to clear vf vlan for vf%d, ret = %d\n", 10525 vf - HCLGE_VF_VPORT_START_NUM, ret); 10526 } 10527 } 10528 10529 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10530 u16 vlan_id, bool is_kill) 10531 { 10532 struct hclge_vport *vport = hclge_get_vport(handle); 10533 struct hclge_dev *hdev = vport->back; 10534 bool writen_to_tbl = false; 10535 int ret = 0; 10536 10537 /* When device is resetting or reset failed, firmware is unable to 10538 * handle mailbox. Just record the vlan id, and remove it after 10539 * reset finished. 10540 */ 10541 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10542 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10543 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10544 return -EBUSY; 10545 } 10546 10547 /* when port base vlan enabled, we use port base vlan as the vlan 10548 * filter entry. In this case, we don't update vlan filter table 10549 * when user add new vlan or remove exist vlan, just update the vport 10550 * vlan list. The vlan id in vlan list will be writen in vlan filter 10551 * table until port base vlan disabled 10552 */ 10553 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10554 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10555 vlan_id, is_kill); 10556 writen_to_tbl = true; 10557 } 10558 10559 if (!ret) { 10560 if (!is_kill) 10561 hclge_add_vport_vlan_table(vport, vlan_id, 10562 writen_to_tbl); 10563 else if (is_kill && vlan_id != 0) 10564 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10565 } else if (is_kill) { 10566 /* when remove hw vlan filter failed, record the vlan id, 10567 * and try to remove it from hw later, to be consistence 10568 * with stack 10569 */ 10570 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10571 } 10572 10573 hclge_set_vport_vlan_fltr_change(vport); 10574 10575 return ret; 10576 } 10577 10578 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10579 { 10580 struct hclge_vport *vport; 10581 int ret; 10582 u16 i; 10583 10584 for (i = 0; i < hdev->num_alloc_vport; i++) { 10585 vport = &hdev->vport[i]; 10586 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10587 &vport->state)) 10588 continue; 10589 10590 ret = hclge_enable_vport_vlan_filter(vport, 10591 vport->req_vlan_fltr_en); 10592 if (ret) { 10593 dev_err(&hdev->pdev->dev, 10594 "failed to sync vlan filter state for vport%u, ret = %d\n", 10595 vport->vport_id, ret); 10596 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10597 &vport->state); 10598 return; 10599 } 10600 } 10601 } 10602 10603 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10604 { 10605 #define HCLGE_MAX_SYNC_COUNT 60 10606 10607 int i, ret, sync_cnt = 0; 10608 u16 vlan_id; 10609 10610 /* start from vport 1 for PF is always alive */ 10611 for (i = 0; i < hdev->num_alloc_vport; i++) { 10612 struct hclge_vport *vport = &hdev->vport[i]; 10613 10614 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10615 VLAN_N_VID); 10616 while (vlan_id != VLAN_N_VID) { 10617 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10618 vport->vport_id, vlan_id, 10619 true); 10620 if (ret && ret != -EINVAL) 10621 return; 10622 10623 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10624 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10625 hclge_set_vport_vlan_fltr_change(vport); 10626 10627 sync_cnt++; 10628 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10629 return; 10630 10631 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10632 VLAN_N_VID); 10633 } 10634 } 10635 10636 hclge_sync_vlan_fltr_state(hdev); 10637 } 10638 10639 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10640 { 10641 struct hclge_config_max_frm_size_cmd *req; 10642 struct hclge_desc desc; 10643 10644 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10645 10646 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10647 req->max_frm_size = cpu_to_le16(new_mps); 10648 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10649 10650 return hclge_cmd_send(&hdev->hw, &desc, 1); 10651 } 10652 10653 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10654 { 10655 struct hclge_vport *vport = hclge_get_vport(handle); 10656 10657 return hclge_set_vport_mtu(vport, new_mtu); 10658 } 10659 10660 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10661 { 10662 struct hclge_dev *hdev = vport->back; 10663 int i, max_frm_size, ret; 10664 10665 /* HW supprt 2 layer vlan */ 10666 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10667 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10668 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10669 return -EINVAL; 10670 10671 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10672 mutex_lock(&hdev->vport_lock); 10673 /* VF's mps must fit within hdev->mps */ 10674 if (vport->vport_id && max_frm_size > hdev->mps) { 10675 mutex_unlock(&hdev->vport_lock); 10676 return -EINVAL; 10677 } else if (vport->vport_id) { 10678 vport->mps = max_frm_size; 10679 mutex_unlock(&hdev->vport_lock); 10680 return 0; 10681 } 10682 10683 /* PF's mps must be greater then VF's mps */ 10684 for (i = 1; i < hdev->num_alloc_vport; i++) 10685 if (max_frm_size < hdev->vport[i].mps) { 10686 dev_err(&hdev->pdev->dev, 10687 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10688 i, hdev->vport[i].mps); 10689 mutex_unlock(&hdev->vport_lock); 10690 return -EINVAL; 10691 } 10692 10693 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10694 10695 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10696 if (ret) { 10697 dev_err(&hdev->pdev->dev, 10698 "Change mtu fail, ret =%d\n", ret); 10699 goto out; 10700 } 10701 10702 hdev->mps = max_frm_size; 10703 vport->mps = max_frm_size; 10704 10705 ret = hclge_buffer_alloc(hdev); 10706 if (ret) 10707 dev_err(&hdev->pdev->dev, 10708 "Allocate buffer fail, ret =%d\n", ret); 10709 10710 out: 10711 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10712 mutex_unlock(&hdev->vport_lock); 10713 return ret; 10714 } 10715 10716 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10717 bool enable) 10718 { 10719 struct hclge_reset_tqp_queue_cmd *req; 10720 struct hclge_desc desc; 10721 int ret; 10722 10723 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10724 10725 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10726 req->tqp_id = cpu_to_le16(queue_id); 10727 if (enable) 10728 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10729 10730 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10731 if (ret) { 10732 dev_err(&hdev->pdev->dev, 10733 "Send tqp reset cmd error, status =%d\n", ret); 10734 return ret; 10735 } 10736 10737 return 0; 10738 } 10739 10740 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10741 u8 *reset_status) 10742 { 10743 struct hclge_reset_tqp_queue_cmd *req; 10744 struct hclge_desc desc; 10745 int ret; 10746 10747 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10748 10749 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10750 req->tqp_id = cpu_to_le16(queue_id); 10751 10752 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10753 if (ret) { 10754 dev_err(&hdev->pdev->dev, 10755 "Get reset status error, status =%d\n", ret); 10756 return ret; 10757 } 10758 10759 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10760 10761 return 0; 10762 } 10763 10764 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10765 { 10766 struct hclge_comm_tqp *tqp; 10767 struct hnae3_queue *queue; 10768 10769 queue = handle->kinfo.tqp[queue_id]; 10770 tqp = container_of(queue, struct hclge_comm_tqp, q); 10771 10772 return tqp->index; 10773 } 10774 10775 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10776 { 10777 struct hclge_vport *vport = hclge_get_vport(handle); 10778 struct hclge_dev *hdev = vport->back; 10779 u16 reset_try_times = 0; 10780 u8 reset_status; 10781 u16 queue_gid; 10782 int ret; 10783 u16 i; 10784 10785 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10786 queue_gid = hclge_covert_handle_qid_global(handle, i); 10787 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10788 if (ret) { 10789 dev_err(&hdev->pdev->dev, 10790 "failed to send reset tqp cmd, ret = %d\n", 10791 ret); 10792 return ret; 10793 } 10794 10795 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10796 ret = hclge_get_reset_status(hdev, queue_gid, 10797 &reset_status); 10798 if (ret) 10799 return ret; 10800 10801 if (reset_status) 10802 break; 10803 10804 /* Wait for tqp hw reset */ 10805 usleep_range(1000, 1200); 10806 } 10807 10808 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10809 dev_err(&hdev->pdev->dev, 10810 "wait for tqp hw reset timeout\n"); 10811 return -ETIME; 10812 } 10813 10814 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10815 if (ret) { 10816 dev_err(&hdev->pdev->dev, 10817 "failed to deassert soft reset, ret = %d\n", 10818 ret); 10819 return ret; 10820 } 10821 reset_try_times = 0; 10822 } 10823 return 0; 10824 } 10825 10826 static int hclge_reset_rcb(struct hnae3_handle *handle) 10827 { 10828 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10829 #define HCLGE_RESET_RCB_SUCCESS 1U 10830 10831 struct hclge_vport *vport = hclge_get_vport(handle); 10832 struct hclge_dev *hdev = vport->back; 10833 struct hclge_reset_cmd *req; 10834 struct hclge_desc desc; 10835 u8 return_status; 10836 u16 queue_gid; 10837 int ret; 10838 10839 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10840 10841 req = (struct hclge_reset_cmd *)desc.data; 10842 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10843 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10844 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10845 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10846 10847 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10848 if (ret) { 10849 dev_err(&hdev->pdev->dev, 10850 "failed to send rcb reset cmd, ret = %d\n", ret); 10851 return ret; 10852 } 10853 10854 return_status = req->fun_reset_rcb_return_status; 10855 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10856 return 0; 10857 10858 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10859 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10860 return_status); 10861 return -EIO; 10862 } 10863 10864 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10865 * again to reset all tqps 10866 */ 10867 return hclge_reset_tqp_cmd(handle); 10868 } 10869 10870 int hclge_reset_tqp(struct hnae3_handle *handle) 10871 { 10872 struct hclge_vport *vport = hclge_get_vport(handle); 10873 struct hclge_dev *hdev = vport->back; 10874 int ret; 10875 10876 /* only need to disable PF's tqp */ 10877 if (!vport->vport_id) { 10878 ret = hclge_tqp_enable(handle, false); 10879 if (ret) { 10880 dev_err(&hdev->pdev->dev, 10881 "failed to disable tqp, ret = %d\n", ret); 10882 return ret; 10883 } 10884 } 10885 10886 return hclge_reset_rcb(handle); 10887 } 10888 10889 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10890 { 10891 struct hclge_vport *vport = hclge_get_vport(handle); 10892 struct hclge_dev *hdev = vport->back; 10893 10894 return hdev->fw_version; 10895 } 10896 10897 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10898 { 10899 struct phy_device *phydev = hdev->hw.mac.phydev; 10900 10901 if (!phydev) 10902 return; 10903 10904 phy_set_asym_pause(phydev, rx_en, tx_en); 10905 } 10906 10907 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10908 { 10909 int ret; 10910 10911 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10912 return 0; 10913 10914 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10915 if (ret) 10916 dev_err(&hdev->pdev->dev, 10917 "configure pauseparam error, ret = %d.\n", ret); 10918 10919 return ret; 10920 } 10921 10922 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10923 { 10924 struct phy_device *phydev = hdev->hw.mac.phydev; 10925 u16 remote_advertising = 0; 10926 u16 local_advertising; 10927 u32 rx_pause, tx_pause; 10928 u8 flowctl; 10929 10930 if (!phydev->link) 10931 return 0; 10932 10933 if (!phydev->autoneg) 10934 return hclge_mac_pause_setup_hw(hdev); 10935 10936 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10937 10938 if (phydev->pause) 10939 remote_advertising = LPA_PAUSE_CAP; 10940 10941 if (phydev->asym_pause) 10942 remote_advertising |= LPA_PAUSE_ASYM; 10943 10944 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10945 remote_advertising); 10946 tx_pause = flowctl & FLOW_CTRL_TX; 10947 rx_pause = flowctl & FLOW_CTRL_RX; 10948 10949 if (phydev->duplex == HCLGE_MAC_HALF) { 10950 tx_pause = 0; 10951 rx_pause = 0; 10952 } 10953 10954 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10955 } 10956 10957 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10958 u32 *rx_en, u32 *tx_en) 10959 { 10960 struct hclge_vport *vport = hclge_get_vport(handle); 10961 struct hclge_dev *hdev = vport->back; 10962 u8 media_type = hdev->hw.mac.media_type; 10963 10964 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10965 hclge_get_autoneg(handle) : 0; 10966 10967 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10968 *rx_en = 0; 10969 *tx_en = 0; 10970 return; 10971 } 10972 10973 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10974 *rx_en = 1; 10975 *tx_en = 0; 10976 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10977 *tx_en = 1; 10978 *rx_en = 0; 10979 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10980 *rx_en = 1; 10981 *tx_en = 1; 10982 } else { 10983 *rx_en = 0; 10984 *tx_en = 0; 10985 } 10986 } 10987 10988 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10989 u32 rx_en, u32 tx_en) 10990 { 10991 if (rx_en && tx_en) 10992 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10993 else if (rx_en && !tx_en) 10994 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10995 else if (!rx_en && tx_en) 10996 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10997 else 10998 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10999 11000 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 11001 } 11002 11003 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 11004 u32 rx_en, u32 tx_en) 11005 { 11006 struct hclge_vport *vport = hclge_get_vport(handle); 11007 struct hclge_dev *hdev = vport->back; 11008 struct phy_device *phydev = hdev->hw.mac.phydev; 11009 u32 fc_autoneg; 11010 11011 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11012 fc_autoneg = hclge_get_autoneg(handle); 11013 if (auto_neg != fc_autoneg) { 11014 dev_info(&hdev->pdev->dev, 11015 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11016 return -EOPNOTSUPP; 11017 } 11018 } 11019 11020 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11021 dev_info(&hdev->pdev->dev, 11022 "Priority flow control enabled. Cannot set link flow control.\n"); 11023 return -EOPNOTSUPP; 11024 } 11025 11026 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11027 11028 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11029 11030 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11031 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11032 11033 if (phydev) 11034 return phy_start_aneg(phydev); 11035 11036 return -EOPNOTSUPP; 11037 } 11038 11039 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11040 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11041 { 11042 struct hclge_vport *vport = hclge_get_vport(handle); 11043 struct hclge_dev *hdev = vport->back; 11044 11045 if (speed) 11046 *speed = hdev->hw.mac.speed; 11047 if (duplex) 11048 *duplex = hdev->hw.mac.duplex; 11049 if (auto_neg) 11050 *auto_neg = hdev->hw.mac.autoneg; 11051 if (lane_num) 11052 *lane_num = hdev->hw.mac.lane_num; 11053 } 11054 11055 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11056 u8 *module_type) 11057 { 11058 struct hclge_vport *vport = hclge_get_vport(handle); 11059 struct hclge_dev *hdev = vport->back; 11060 11061 /* When nic is down, the service task is not running, doesn't update 11062 * the port information per second. Query the port information before 11063 * return the media type, ensure getting the correct media information. 11064 */ 11065 hclge_update_port_info(hdev); 11066 11067 if (media_type) 11068 *media_type = hdev->hw.mac.media_type; 11069 11070 if (module_type) 11071 *module_type = hdev->hw.mac.module_type; 11072 } 11073 11074 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11075 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11076 { 11077 struct hclge_vport *vport = hclge_get_vport(handle); 11078 struct hclge_dev *hdev = vport->back; 11079 struct phy_device *phydev = hdev->hw.mac.phydev; 11080 int mdix_ctrl, mdix, is_resolved; 11081 unsigned int retval; 11082 11083 if (!phydev) { 11084 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11085 *tp_mdix = ETH_TP_MDI_INVALID; 11086 return; 11087 } 11088 11089 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11090 11091 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11092 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11093 HCLGE_PHY_MDIX_CTRL_S); 11094 11095 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11096 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11097 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11098 11099 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11100 11101 switch (mdix_ctrl) { 11102 case 0x0: 11103 *tp_mdix_ctrl = ETH_TP_MDI; 11104 break; 11105 case 0x1: 11106 *tp_mdix_ctrl = ETH_TP_MDI_X; 11107 break; 11108 case 0x3: 11109 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11110 break; 11111 default: 11112 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11113 break; 11114 } 11115 11116 if (!is_resolved) 11117 *tp_mdix = ETH_TP_MDI_INVALID; 11118 else if (mdix) 11119 *tp_mdix = ETH_TP_MDI_X; 11120 else 11121 *tp_mdix = ETH_TP_MDI; 11122 } 11123 11124 static void hclge_info_show(struct hclge_dev *hdev) 11125 { 11126 struct device *dev = &hdev->pdev->dev; 11127 11128 dev_info(dev, "PF info begin:\n"); 11129 11130 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11131 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11132 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11133 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11134 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11135 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11136 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11137 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11138 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11139 dev_info(dev, "This is %s PF\n", 11140 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11141 dev_info(dev, "DCB %s\n", 11142 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 11143 dev_info(dev, "MQPRIO %s\n", 11144 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 11145 dev_info(dev, "Default tx spare buffer size: %u\n", 11146 hdev->tx_spare_buf_size); 11147 11148 dev_info(dev, "PF info end.\n"); 11149 } 11150 11151 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11152 struct hclge_vport *vport) 11153 { 11154 struct hnae3_client *client = vport->nic.client; 11155 struct hclge_dev *hdev = ae_dev->priv; 11156 int rst_cnt = hdev->rst_stats.reset_cnt; 11157 int ret; 11158 11159 ret = client->ops->init_instance(&vport->nic); 11160 if (ret) 11161 return ret; 11162 11163 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11164 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11165 rst_cnt != hdev->rst_stats.reset_cnt) { 11166 ret = -EBUSY; 11167 goto init_nic_err; 11168 } 11169 11170 /* Enable nic hw error interrupts */ 11171 ret = hclge_config_nic_hw_error(hdev, true); 11172 if (ret) { 11173 dev_err(&ae_dev->pdev->dev, 11174 "fail(%d) to enable hw error interrupts\n", ret); 11175 goto init_nic_err; 11176 } 11177 11178 hnae3_set_client_init_flag(client, ae_dev, 1); 11179 11180 if (netif_msg_drv(&hdev->vport->nic)) 11181 hclge_info_show(hdev); 11182 11183 return ret; 11184 11185 init_nic_err: 11186 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11187 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11188 msleep(HCLGE_WAIT_RESET_DONE); 11189 11190 client->ops->uninit_instance(&vport->nic, 0); 11191 11192 return ret; 11193 } 11194 11195 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11196 struct hclge_vport *vport) 11197 { 11198 struct hclge_dev *hdev = ae_dev->priv; 11199 struct hnae3_client *client; 11200 int rst_cnt; 11201 int ret; 11202 11203 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11204 !hdev->nic_client) 11205 return 0; 11206 11207 client = hdev->roce_client; 11208 ret = hclge_init_roce_base_info(vport); 11209 if (ret) 11210 return ret; 11211 11212 rst_cnt = hdev->rst_stats.reset_cnt; 11213 ret = client->ops->init_instance(&vport->roce); 11214 if (ret) 11215 return ret; 11216 11217 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11218 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11219 rst_cnt != hdev->rst_stats.reset_cnt) { 11220 ret = -EBUSY; 11221 goto init_roce_err; 11222 } 11223 11224 /* Enable roce ras interrupts */ 11225 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11226 if (ret) { 11227 dev_err(&ae_dev->pdev->dev, 11228 "fail(%d) to enable roce ras interrupts\n", ret); 11229 goto init_roce_err; 11230 } 11231 11232 hnae3_set_client_init_flag(client, ae_dev, 1); 11233 11234 return 0; 11235 11236 init_roce_err: 11237 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11238 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11239 msleep(HCLGE_WAIT_RESET_DONE); 11240 11241 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11242 11243 return ret; 11244 } 11245 11246 static int hclge_init_client_instance(struct hnae3_client *client, 11247 struct hnae3_ae_dev *ae_dev) 11248 { 11249 struct hclge_dev *hdev = ae_dev->priv; 11250 struct hclge_vport *vport = &hdev->vport[0]; 11251 int ret; 11252 11253 switch (client->type) { 11254 case HNAE3_CLIENT_KNIC: 11255 hdev->nic_client = client; 11256 vport->nic.client = client; 11257 ret = hclge_init_nic_client_instance(ae_dev, vport); 11258 if (ret) 11259 goto clear_nic; 11260 11261 ret = hclge_init_roce_client_instance(ae_dev, vport); 11262 if (ret) 11263 goto clear_roce; 11264 11265 break; 11266 case HNAE3_CLIENT_ROCE: 11267 if (hnae3_dev_roce_supported(hdev)) { 11268 hdev->roce_client = client; 11269 vport->roce.client = client; 11270 } 11271 11272 ret = hclge_init_roce_client_instance(ae_dev, vport); 11273 if (ret) 11274 goto clear_roce; 11275 11276 break; 11277 default: 11278 return -EINVAL; 11279 } 11280 11281 return 0; 11282 11283 clear_nic: 11284 hdev->nic_client = NULL; 11285 vport->nic.client = NULL; 11286 return ret; 11287 clear_roce: 11288 hdev->roce_client = NULL; 11289 vport->roce.client = NULL; 11290 return ret; 11291 } 11292 11293 static void hclge_uninit_client_instance(struct hnae3_client *client, 11294 struct hnae3_ae_dev *ae_dev) 11295 { 11296 struct hclge_dev *hdev = ae_dev->priv; 11297 struct hclge_vport *vport = &hdev->vport[0]; 11298 11299 if (hdev->roce_client) { 11300 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11301 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11302 msleep(HCLGE_WAIT_RESET_DONE); 11303 11304 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11305 hdev->roce_client = NULL; 11306 vport->roce.client = NULL; 11307 } 11308 if (client->type == HNAE3_CLIENT_ROCE) 11309 return; 11310 if (hdev->nic_client && client->ops->uninit_instance) { 11311 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11312 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11313 msleep(HCLGE_WAIT_RESET_DONE); 11314 11315 client->ops->uninit_instance(&vport->nic, 0); 11316 hdev->nic_client = NULL; 11317 vport->nic.client = NULL; 11318 } 11319 } 11320 11321 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11322 { 11323 struct pci_dev *pdev = hdev->pdev; 11324 struct hclge_hw *hw = &hdev->hw; 11325 11326 /* for device does not have device memory, return directly */ 11327 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11328 return 0; 11329 11330 hw->hw.mem_base = 11331 devm_ioremap_wc(&pdev->dev, 11332 pci_resource_start(pdev, HCLGE_MEM_BAR), 11333 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11334 if (!hw->hw.mem_base) { 11335 dev_err(&pdev->dev, "failed to map device memory\n"); 11336 return -EFAULT; 11337 } 11338 11339 return 0; 11340 } 11341 11342 static int hclge_pci_init(struct hclge_dev *hdev) 11343 { 11344 struct pci_dev *pdev = hdev->pdev; 11345 struct hclge_hw *hw; 11346 int ret; 11347 11348 ret = pci_enable_device(pdev); 11349 if (ret) { 11350 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11351 return ret; 11352 } 11353 11354 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11355 if (ret) { 11356 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11357 if (ret) { 11358 dev_err(&pdev->dev, 11359 "can't set consistent PCI DMA"); 11360 goto err_disable_device; 11361 } 11362 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11363 } 11364 11365 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11366 if (ret) { 11367 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11368 goto err_disable_device; 11369 } 11370 11371 pci_set_master(pdev); 11372 hw = &hdev->hw; 11373 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11374 if (!hw->hw.io_base) { 11375 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11376 ret = -ENOMEM; 11377 goto err_release_regions; 11378 } 11379 11380 ret = hclge_dev_mem_map(hdev); 11381 if (ret) 11382 goto err_unmap_io_base; 11383 11384 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11385 11386 return 0; 11387 11388 err_unmap_io_base: 11389 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11390 err_release_regions: 11391 pci_release_regions(pdev); 11392 err_disable_device: 11393 pci_disable_device(pdev); 11394 11395 return ret; 11396 } 11397 11398 static void hclge_pci_uninit(struct hclge_dev *hdev) 11399 { 11400 struct pci_dev *pdev = hdev->pdev; 11401 11402 if (hdev->hw.hw.mem_base) 11403 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11404 11405 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11406 pci_free_irq_vectors(pdev); 11407 pci_release_mem_regions(pdev); 11408 pci_disable_device(pdev); 11409 } 11410 11411 static void hclge_state_init(struct hclge_dev *hdev) 11412 { 11413 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11414 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11415 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11416 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11417 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11418 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11419 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11420 } 11421 11422 static void hclge_state_uninit(struct hclge_dev *hdev) 11423 { 11424 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11425 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11426 11427 if (hdev->reset_timer.function) 11428 del_timer_sync(&hdev->reset_timer); 11429 if (hdev->service_task.work.func) 11430 cancel_delayed_work_sync(&hdev->service_task); 11431 } 11432 11433 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11434 enum hnae3_reset_type rst_type) 11435 { 11436 #define HCLGE_RESET_RETRY_WAIT_MS 500 11437 #define HCLGE_RESET_RETRY_CNT 5 11438 11439 struct hclge_dev *hdev = ae_dev->priv; 11440 int retry_cnt = 0; 11441 int ret; 11442 11443 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11444 down(&hdev->reset_sem); 11445 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11446 hdev->reset_type = rst_type; 11447 ret = hclge_reset_prepare(hdev); 11448 if (!ret && !hdev->reset_pending) 11449 break; 11450 11451 dev_err(&hdev->pdev->dev, 11452 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11453 ret, hdev->reset_pending, retry_cnt); 11454 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11455 up(&hdev->reset_sem); 11456 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11457 } 11458 11459 /* disable misc vector before reset done */ 11460 hclge_enable_vector(&hdev->misc_vector, false); 11461 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11462 11463 if (hdev->reset_type == HNAE3_FLR_RESET) 11464 hdev->rst_stats.flr_rst_cnt++; 11465 } 11466 11467 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11468 { 11469 struct hclge_dev *hdev = ae_dev->priv; 11470 int ret; 11471 11472 hclge_enable_vector(&hdev->misc_vector, true); 11473 11474 ret = hclge_reset_rebuild(hdev); 11475 if (ret) 11476 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11477 11478 hdev->reset_type = HNAE3_NONE_RESET; 11479 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11480 up(&hdev->reset_sem); 11481 } 11482 11483 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11484 { 11485 u16 i; 11486 11487 for (i = 0; i < hdev->num_alloc_vport; i++) { 11488 struct hclge_vport *vport = &hdev->vport[i]; 11489 int ret; 11490 11491 /* Send cmd to clear vport's FUNC_RST_ING */ 11492 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11493 if (ret) 11494 dev_warn(&hdev->pdev->dev, 11495 "clear vport(%u) rst failed %d!\n", 11496 vport->vport_id, ret); 11497 } 11498 } 11499 11500 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11501 { 11502 struct hclge_desc desc; 11503 int ret; 11504 11505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11506 11507 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11508 /* This new command is only supported by new firmware, it will 11509 * fail with older firmware. Error value -EOPNOSUPP can only be 11510 * returned by older firmware running this command, to keep code 11511 * backward compatible we will override this value and return 11512 * success. 11513 */ 11514 if (ret && ret != -EOPNOTSUPP) { 11515 dev_err(&hdev->pdev->dev, 11516 "failed to clear hw resource, ret = %d\n", ret); 11517 return ret; 11518 } 11519 return 0; 11520 } 11521 11522 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11523 { 11524 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11525 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11526 } 11527 11528 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11529 { 11530 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11531 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11532 } 11533 11534 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11535 { 11536 struct hclge_vport *vport = hclge_get_vport(handle); 11537 11538 return &vport->back->hw.mac.wol; 11539 } 11540 11541 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11542 u32 *wol_supported) 11543 { 11544 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11545 struct hclge_desc desc; 11546 int ret; 11547 11548 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11549 true); 11550 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11551 11552 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11553 if (ret) { 11554 dev_err(&hdev->pdev->dev, 11555 "failed to query wol supported, ret = %d\n", ret); 11556 return ret; 11557 } 11558 11559 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11560 11561 return 0; 11562 } 11563 11564 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11565 struct hclge_wol_info *wol_info) 11566 { 11567 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11568 struct hclge_desc desc; 11569 int ret; 11570 11571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11572 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11573 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11574 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11575 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11576 11577 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11578 if (ret) 11579 dev_err(&hdev->pdev->dev, 11580 "failed to set wol config, ret = %d\n", ret); 11581 11582 return ret; 11583 } 11584 11585 static int hclge_update_wol(struct hclge_dev *hdev) 11586 { 11587 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11588 11589 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11590 return 0; 11591 11592 return hclge_set_wol_cfg(hdev, wol_info); 11593 } 11594 11595 static int hclge_init_wol(struct hclge_dev *hdev) 11596 { 11597 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11598 int ret; 11599 11600 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11601 return 0; 11602 11603 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11604 ret = hclge_get_wol_supported_mode(hdev, 11605 &wol_info->wol_support_mode); 11606 if (ret) { 11607 wol_info->wol_support_mode = 0; 11608 return ret; 11609 } 11610 11611 return hclge_update_wol(hdev); 11612 } 11613 11614 static void hclge_get_wol(struct hnae3_handle *handle, 11615 struct ethtool_wolinfo *wol) 11616 { 11617 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11618 11619 wol->supported = wol_info->wol_support_mode; 11620 wol->wolopts = wol_info->wol_current_mode; 11621 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11622 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11623 } 11624 11625 static int hclge_set_wol(struct hnae3_handle *handle, 11626 struct ethtool_wolinfo *wol) 11627 { 11628 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11629 struct hclge_vport *vport = hclge_get_vport(handle); 11630 u32 wol_mode; 11631 int ret; 11632 11633 wol_mode = wol->wolopts; 11634 if (wol_mode & ~wol_info->wol_support_mode) 11635 return -EINVAL; 11636 11637 wol_info->wol_current_mode = wol_mode; 11638 if (wol_mode & WAKE_MAGICSECURE) { 11639 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11640 wol_info->wol_sopass_size = SOPASS_MAX; 11641 } else { 11642 wol_info->wol_sopass_size = 0; 11643 } 11644 11645 ret = hclge_set_wol_cfg(vport->back, wol_info); 11646 if (ret) 11647 wol_info->wol_current_mode = 0; 11648 11649 return ret; 11650 } 11651 11652 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11653 { 11654 struct pci_dev *pdev = ae_dev->pdev; 11655 struct hclge_dev *hdev; 11656 int ret; 11657 11658 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11659 if (!hdev) 11660 return -ENOMEM; 11661 11662 hdev->pdev = pdev; 11663 hdev->ae_dev = ae_dev; 11664 hdev->reset_type = HNAE3_NONE_RESET; 11665 hdev->reset_level = HNAE3_FUNC_RESET; 11666 ae_dev->priv = hdev; 11667 11668 /* HW supprt 2 layer vlan */ 11669 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11670 11671 mutex_init(&hdev->vport_lock); 11672 spin_lock_init(&hdev->fd_rule_lock); 11673 sema_init(&hdev->reset_sem, 1); 11674 11675 ret = hclge_pci_init(hdev); 11676 if (ret) 11677 goto out; 11678 11679 ret = hclge_devlink_init(hdev); 11680 if (ret) 11681 goto err_pci_uninit; 11682 11683 /* Firmware command queue initialize */ 11684 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11685 if (ret) 11686 goto err_devlink_uninit; 11687 11688 /* Firmware command initialize */ 11689 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11690 true, hdev->reset_pending); 11691 if (ret) 11692 goto err_cmd_uninit; 11693 11694 ret = hclge_clear_hw_resource(hdev); 11695 if (ret) 11696 goto err_cmd_uninit; 11697 11698 ret = hclge_get_cap(hdev); 11699 if (ret) 11700 goto err_cmd_uninit; 11701 11702 ret = hclge_query_dev_specs(hdev); 11703 if (ret) { 11704 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11705 ret); 11706 goto err_cmd_uninit; 11707 } 11708 11709 ret = hclge_configure(hdev); 11710 if (ret) { 11711 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11712 goto err_cmd_uninit; 11713 } 11714 11715 ret = hclge_init_msi(hdev); 11716 if (ret) { 11717 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11718 goto err_cmd_uninit; 11719 } 11720 11721 ret = hclge_misc_irq_init(hdev); 11722 if (ret) 11723 goto err_msi_uninit; 11724 11725 ret = hclge_alloc_tqps(hdev); 11726 if (ret) { 11727 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11728 goto err_msi_irq_uninit; 11729 } 11730 11731 ret = hclge_alloc_vport(hdev); 11732 if (ret) 11733 goto err_msi_irq_uninit; 11734 11735 ret = hclge_map_tqp(hdev); 11736 if (ret) 11737 goto err_msi_irq_uninit; 11738 11739 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11740 if (hnae3_dev_phy_imp_supported(hdev)) 11741 ret = hclge_update_tp_port_info(hdev); 11742 else 11743 ret = hclge_mac_mdio_config(hdev); 11744 11745 if (ret) 11746 goto err_msi_irq_uninit; 11747 } 11748 11749 ret = hclge_init_umv_space(hdev); 11750 if (ret) 11751 goto err_mdiobus_unreg; 11752 11753 ret = hclge_mac_init(hdev); 11754 if (ret) { 11755 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11756 goto err_mdiobus_unreg; 11757 } 11758 11759 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11760 if (ret) { 11761 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11762 goto err_mdiobus_unreg; 11763 } 11764 11765 ret = hclge_config_gro(hdev); 11766 if (ret) 11767 goto err_mdiobus_unreg; 11768 11769 ret = hclge_init_vlan_config(hdev); 11770 if (ret) { 11771 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11772 goto err_mdiobus_unreg; 11773 } 11774 11775 ret = hclge_tm_schd_init(hdev); 11776 if (ret) { 11777 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11778 goto err_mdiobus_unreg; 11779 } 11780 11781 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11782 &hdev->rss_cfg); 11783 if (ret) { 11784 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11785 goto err_mdiobus_unreg; 11786 } 11787 11788 ret = hclge_rss_init_hw(hdev); 11789 if (ret) { 11790 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11791 goto err_mdiobus_unreg; 11792 } 11793 11794 ret = init_mgr_tbl(hdev); 11795 if (ret) { 11796 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11797 goto err_mdiobus_unreg; 11798 } 11799 11800 ret = hclge_init_fd_config(hdev); 11801 if (ret) { 11802 dev_err(&pdev->dev, 11803 "fd table init fail, ret=%d\n", ret); 11804 goto err_mdiobus_unreg; 11805 } 11806 11807 ret = hclge_ptp_init(hdev); 11808 if (ret) 11809 goto err_mdiobus_unreg; 11810 11811 ret = hclge_update_port_info(hdev); 11812 if (ret) 11813 goto err_mdiobus_unreg; 11814 11815 INIT_KFIFO(hdev->mac_tnl_log); 11816 11817 hclge_dcb_ops_set(hdev); 11818 11819 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11820 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11821 11822 hclge_clear_all_event_cause(hdev); 11823 hclge_clear_resetting_state(hdev); 11824 11825 /* Log and clear the hw errors those already occurred */ 11826 if (hnae3_dev_ras_imp_supported(hdev)) 11827 hclge_handle_occurred_error(hdev); 11828 else 11829 hclge_handle_all_hns_hw_errors(ae_dev); 11830 11831 /* request delayed reset for the error recovery because an immediate 11832 * global reset on a PF affecting pending initialization of other PFs 11833 */ 11834 if (ae_dev->hw_err_reset_req) { 11835 enum hnae3_reset_type reset_level; 11836 11837 reset_level = hclge_get_reset_level(ae_dev, 11838 &ae_dev->hw_err_reset_req); 11839 hclge_set_def_reset_request(ae_dev, reset_level); 11840 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11841 } 11842 11843 hclge_init_rxd_adv_layout(hdev); 11844 11845 /* Enable MISC vector(vector0) */ 11846 hclge_enable_vector(&hdev->misc_vector, true); 11847 11848 ret = hclge_init_wol(hdev); 11849 if (ret) 11850 dev_warn(&pdev->dev, 11851 "failed to wake on lan init, ret = %d\n", ret); 11852 11853 hclge_state_init(hdev); 11854 hdev->last_reset_time = jiffies; 11855 11856 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11857 HCLGE_DRIVER_NAME); 11858 11859 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11860 11861 return 0; 11862 11863 err_mdiobus_unreg: 11864 if (hdev->hw.mac.phydev) 11865 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11866 err_msi_irq_uninit: 11867 hclge_misc_irq_uninit(hdev); 11868 err_msi_uninit: 11869 pci_free_irq_vectors(pdev); 11870 err_cmd_uninit: 11871 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11872 err_devlink_uninit: 11873 hclge_devlink_uninit(hdev); 11874 err_pci_uninit: 11875 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11876 pci_release_regions(pdev); 11877 pci_disable_device(pdev); 11878 out: 11879 mutex_destroy(&hdev->vport_lock); 11880 return ret; 11881 } 11882 11883 static void hclge_stats_clear(struct hclge_dev *hdev) 11884 { 11885 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11886 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11887 } 11888 11889 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11890 { 11891 return hclge_config_switch_param(hdev, vf, enable, 11892 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11893 } 11894 11895 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11896 { 11897 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11898 HCLGE_FILTER_FE_NIC_INGRESS_B, 11899 enable, vf); 11900 } 11901 11902 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11903 { 11904 int ret; 11905 11906 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11907 if (ret) { 11908 dev_err(&hdev->pdev->dev, 11909 "Set vf %d mac spoof check %s failed, ret=%d\n", 11910 vf, enable ? "on" : "off", ret); 11911 return ret; 11912 } 11913 11914 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11915 if (ret) 11916 dev_err(&hdev->pdev->dev, 11917 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11918 vf, enable ? "on" : "off", ret); 11919 11920 return ret; 11921 } 11922 11923 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11924 bool enable) 11925 { 11926 struct hclge_vport *vport = hclge_get_vport(handle); 11927 struct hclge_dev *hdev = vport->back; 11928 u32 new_spoofchk = enable ? 1 : 0; 11929 int ret; 11930 11931 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11932 return -EOPNOTSUPP; 11933 11934 vport = hclge_get_vf_vport(hdev, vf); 11935 if (!vport) 11936 return -EINVAL; 11937 11938 if (vport->vf_info.spoofchk == new_spoofchk) 11939 return 0; 11940 11941 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11942 dev_warn(&hdev->pdev->dev, 11943 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11944 vf); 11945 else if (enable && hclge_is_umv_space_full(vport, true)) 11946 dev_warn(&hdev->pdev->dev, 11947 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11948 vf); 11949 11950 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11951 if (ret) 11952 return ret; 11953 11954 vport->vf_info.spoofchk = new_spoofchk; 11955 return 0; 11956 } 11957 11958 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11959 { 11960 struct hclge_vport *vport = hdev->vport; 11961 int ret; 11962 int i; 11963 11964 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11965 return 0; 11966 11967 /* resume the vf spoof check state after reset */ 11968 for (i = 0; i < hdev->num_alloc_vport; i++) { 11969 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11970 vport->vf_info.spoofchk); 11971 if (ret) 11972 return ret; 11973 11974 vport++; 11975 } 11976 11977 return 0; 11978 } 11979 11980 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11981 { 11982 struct hclge_vport *vport = hclge_get_vport(handle); 11983 struct hclge_dev *hdev = vport->back; 11984 u32 new_trusted = enable ? 1 : 0; 11985 11986 vport = hclge_get_vf_vport(hdev, vf); 11987 if (!vport) 11988 return -EINVAL; 11989 11990 if (vport->vf_info.trusted == new_trusted) 11991 return 0; 11992 11993 vport->vf_info.trusted = new_trusted; 11994 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11995 hclge_task_schedule(hdev, 0); 11996 11997 return 0; 11998 } 11999 12000 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 12001 { 12002 int ret; 12003 int vf; 12004 12005 /* reset vf rate to default value */ 12006 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 12007 struct hclge_vport *vport = &hdev->vport[vf]; 12008 12009 vport->vf_info.max_tx_rate = 0; 12010 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 12011 if (ret) 12012 dev_err(&hdev->pdev->dev, 12013 "vf%d failed to reset to default, ret=%d\n", 12014 vf - HCLGE_VF_VPORT_START_NUM, ret); 12015 } 12016 } 12017 12018 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12019 int min_tx_rate, int max_tx_rate) 12020 { 12021 if (min_tx_rate != 0 || 12022 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 12023 dev_err(&hdev->pdev->dev, 12024 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12025 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12026 return -EINVAL; 12027 } 12028 12029 return 0; 12030 } 12031 12032 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12033 int min_tx_rate, int max_tx_rate, bool force) 12034 { 12035 struct hclge_vport *vport = hclge_get_vport(handle); 12036 struct hclge_dev *hdev = vport->back; 12037 int ret; 12038 12039 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12040 if (ret) 12041 return ret; 12042 12043 vport = hclge_get_vf_vport(hdev, vf); 12044 if (!vport) 12045 return -EINVAL; 12046 12047 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12048 return 0; 12049 12050 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12051 if (ret) 12052 return ret; 12053 12054 vport->vf_info.max_tx_rate = max_tx_rate; 12055 12056 return 0; 12057 } 12058 12059 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12060 { 12061 struct hnae3_handle *handle = &hdev->vport->nic; 12062 struct hclge_vport *vport; 12063 int ret; 12064 int vf; 12065 12066 /* resume the vf max_tx_rate after reset */ 12067 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12068 vport = hclge_get_vf_vport(hdev, vf); 12069 if (!vport) 12070 return -EINVAL; 12071 12072 /* zero means max rate, after reset, firmware already set it to 12073 * max rate, so just continue. 12074 */ 12075 if (!vport->vf_info.max_tx_rate) 12076 continue; 12077 12078 ret = hclge_set_vf_rate(handle, vf, 0, 12079 vport->vf_info.max_tx_rate, true); 12080 if (ret) { 12081 dev_err(&hdev->pdev->dev, 12082 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12083 vf, vport->vf_info.max_tx_rate, ret); 12084 return ret; 12085 } 12086 } 12087 12088 return 0; 12089 } 12090 12091 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12092 { 12093 struct hclge_vport *vport = hdev->vport; 12094 int i; 12095 12096 for (i = 0; i < hdev->num_alloc_vport; i++) { 12097 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12098 vport++; 12099 } 12100 } 12101 12102 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12103 { 12104 struct hclge_dev *hdev = ae_dev->priv; 12105 struct pci_dev *pdev = ae_dev->pdev; 12106 int ret; 12107 12108 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12109 12110 hclge_stats_clear(hdev); 12111 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12112 * so here should not clean table in memory. 12113 */ 12114 if (hdev->reset_type == HNAE3_IMP_RESET || 12115 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12116 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12117 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12118 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12119 hclge_reset_umv_space(hdev); 12120 } 12121 12122 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12123 true, hdev->reset_pending); 12124 if (ret) { 12125 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12126 return ret; 12127 } 12128 12129 ret = hclge_map_tqp(hdev); 12130 if (ret) { 12131 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12132 return ret; 12133 } 12134 12135 ret = hclge_mac_init(hdev); 12136 if (ret) { 12137 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12138 return ret; 12139 } 12140 12141 ret = hclge_tp_port_init(hdev); 12142 if (ret) { 12143 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12144 ret); 12145 return ret; 12146 } 12147 12148 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12149 if (ret) { 12150 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12151 return ret; 12152 } 12153 12154 ret = hclge_config_gro(hdev); 12155 if (ret) 12156 return ret; 12157 12158 ret = hclge_init_vlan_config(hdev); 12159 if (ret) { 12160 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12161 return ret; 12162 } 12163 12164 ret = hclge_tm_init_hw(hdev, true); 12165 if (ret) { 12166 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12167 return ret; 12168 } 12169 12170 ret = hclge_rss_init_hw(hdev); 12171 if (ret) { 12172 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12173 return ret; 12174 } 12175 12176 ret = init_mgr_tbl(hdev); 12177 if (ret) { 12178 dev_err(&pdev->dev, 12179 "failed to reinit manager table, ret = %d\n", ret); 12180 return ret; 12181 } 12182 12183 ret = hclge_init_fd_config(hdev); 12184 if (ret) { 12185 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12186 return ret; 12187 } 12188 12189 ret = hclge_ptp_init(hdev); 12190 if (ret) 12191 return ret; 12192 12193 /* Log and clear the hw errors those already occurred */ 12194 if (hnae3_dev_ras_imp_supported(hdev)) 12195 hclge_handle_occurred_error(hdev); 12196 else 12197 hclge_handle_all_hns_hw_errors(ae_dev); 12198 12199 /* Re-enable the hw error interrupts because 12200 * the interrupts get disabled on global reset. 12201 */ 12202 ret = hclge_config_nic_hw_error(hdev, true); 12203 if (ret) { 12204 dev_err(&pdev->dev, 12205 "fail(%d) to re-enable NIC hw error interrupts\n", 12206 ret); 12207 return ret; 12208 } 12209 12210 if (hdev->roce_client) { 12211 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12212 if (ret) { 12213 dev_err(&pdev->dev, 12214 "fail(%d) to re-enable roce ras interrupts\n", 12215 ret); 12216 return ret; 12217 } 12218 } 12219 12220 hclge_reset_vport_state(hdev); 12221 ret = hclge_reset_vport_spoofchk(hdev); 12222 if (ret) 12223 return ret; 12224 12225 ret = hclge_resume_vf_rate(hdev); 12226 if (ret) 12227 return ret; 12228 12229 hclge_init_rxd_adv_layout(hdev); 12230 12231 ret = hclge_update_wol(hdev); 12232 if (ret) 12233 dev_warn(&pdev->dev, 12234 "failed to update wol config, ret = %d\n", ret); 12235 12236 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12237 HCLGE_DRIVER_NAME); 12238 12239 return 0; 12240 } 12241 12242 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12243 { 12244 struct hclge_dev *hdev = ae_dev->priv; 12245 struct hclge_mac *mac = &hdev->hw.mac; 12246 12247 hclge_reset_vf_rate(hdev); 12248 hclge_clear_vf_vlan(hdev); 12249 hclge_state_uninit(hdev); 12250 hclge_ptp_uninit(hdev); 12251 hclge_uninit_rxd_adv_layout(hdev); 12252 hclge_uninit_mac_table(hdev); 12253 hclge_del_all_fd_entries(hdev); 12254 12255 if (mac->phydev) 12256 mdiobus_unregister(mac->mdio_bus); 12257 12258 /* Disable MISC vector(vector0) */ 12259 hclge_enable_vector(&hdev->misc_vector, false); 12260 synchronize_irq(hdev->misc_vector.vector_irq); 12261 12262 /* Disable all hw interrupts */ 12263 hclge_config_mac_tnl_int(hdev, false); 12264 hclge_config_nic_hw_error(hdev, false); 12265 hclge_config_rocee_ras_interrupt(hdev, false); 12266 12267 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12268 hclge_misc_irq_uninit(hdev); 12269 hclge_devlink_uninit(hdev); 12270 hclge_pci_uninit(hdev); 12271 hclge_uninit_vport_vlan_table(hdev); 12272 mutex_destroy(&hdev->vport_lock); 12273 ae_dev->priv = NULL; 12274 } 12275 12276 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12277 { 12278 struct hclge_vport *vport = hclge_get_vport(handle); 12279 struct hclge_dev *hdev = vport->back; 12280 12281 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12282 } 12283 12284 static void hclge_get_channels(struct hnae3_handle *handle, 12285 struct ethtool_channels *ch) 12286 { 12287 ch->max_combined = hclge_get_max_channels(handle); 12288 ch->other_count = 1; 12289 ch->max_other = 1; 12290 ch->combined_count = handle->kinfo.rss_size; 12291 } 12292 12293 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12294 u16 *alloc_tqps, u16 *max_rss_size) 12295 { 12296 struct hclge_vport *vport = hclge_get_vport(handle); 12297 struct hclge_dev *hdev = vport->back; 12298 12299 *alloc_tqps = vport->alloc_tqps; 12300 *max_rss_size = hdev->pf_rss_size_max; 12301 } 12302 12303 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12304 { 12305 struct hclge_vport *vport = hclge_get_vport(handle); 12306 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12307 struct hclge_dev *hdev = vport->back; 12308 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12309 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12310 u16 roundup_size; 12311 unsigned int i; 12312 12313 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12314 roundup_size = ilog2(roundup_size); 12315 /* Set the RSS TC mode according to the new RSS size */ 12316 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12317 tc_valid[i] = 0; 12318 12319 if (!(hdev->hw_tc_map & BIT(i))) 12320 continue; 12321 12322 tc_valid[i] = 1; 12323 tc_size[i] = roundup_size; 12324 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12325 } 12326 12327 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12328 tc_size); 12329 } 12330 12331 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12332 bool rxfh_configured) 12333 { 12334 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12335 struct hclge_vport *vport = hclge_get_vport(handle); 12336 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12337 struct hclge_dev *hdev = vport->back; 12338 u16 cur_rss_size = kinfo->rss_size; 12339 u16 cur_tqps = kinfo->num_tqps; 12340 u32 *rss_indir; 12341 unsigned int i; 12342 int ret; 12343 12344 kinfo->req_rss_size = new_tqps_num; 12345 12346 ret = hclge_tm_vport_map_update(hdev); 12347 if (ret) { 12348 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12349 return ret; 12350 } 12351 12352 ret = hclge_set_rss_tc_mode_cfg(handle); 12353 if (ret) 12354 return ret; 12355 12356 /* RSS indirection table has been configured by user */ 12357 if (rxfh_configured) 12358 goto out; 12359 12360 /* Reinitializes the rss indirect table according to the new RSS size */ 12361 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12362 GFP_KERNEL); 12363 if (!rss_indir) 12364 return -ENOMEM; 12365 12366 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12367 rss_indir[i] = i % kinfo->rss_size; 12368 12369 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12370 if (ret) 12371 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12372 ret); 12373 12374 kfree(rss_indir); 12375 12376 out: 12377 if (!ret) 12378 dev_info(&hdev->pdev->dev, 12379 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12380 cur_rss_size, kinfo->rss_size, 12381 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12382 12383 return ret; 12384 } 12385 12386 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 12387 u32 *regs_num_64_bit) 12388 { 12389 struct hclge_desc desc; 12390 u32 total_num; 12391 int ret; 12392 12393 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 12394 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12395 if (ret) { 12396 dev_err(&hdev->pdev->dev, 12397 "Query register number cmd failed, ret = %d.\n", ret); 12398 return ret; 12399 } 12400 12401 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 12402 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 12403 12404 total_num = *regs_num_32_bit + *regs_num_64_bit; 12405 if (!total_num) 12406 return -EINVAL; 12407 12408 return 0; 12409 } 12410 12411 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12412 void *data) 12413 { 12414 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 12415 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 12416 12417 struct hclge_desc *desc; 12418 u32 *reg_val = data; 12419 __le32 *desc_data; 12420 int nodata_num; 12421 int cmd_num; 12422 int i, k, n; 12423 int ret; 12424 12425 if (regs_num == 0) 12426 return 0; 12427 12428 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 12429 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 12430 HCLGE_32_BIT_REG_RTN_DATANUM); 12431 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12432 if (!desc) 12433 return -ENOMEM; 12434 12435 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 12436 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12437 if (ret) { 12438 dev_err(&hdev->pdev->dev, 12439 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12440 kfree(desc); 12441 return ret; 12442 } 12443 12444 for (i = 0; i < cmd_num; i++) { 12445 if (i == 0) { 12446 desc_data = (__le32 *)(&desc[i].data[0]); 12447 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12448 } else { 12449 desc_data = (__le32 *)(&desc[i]); 12450 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12451 } 12452 for (k = 0; k < n; k++) { 12453 *reg_val++ = le32_to_cpu(*desc_data++); 12454 12455 regs_num--; 12456 if (!regs_num) 12457 break; 12458 } 12459 } 12460 12461 kfree(desc); 12462 return 0; 12463 } 12464 12465 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12466 void *data) 12467 { 12468 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12469 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12470 12471 struct hclge_desc *desc; 12472 u64 *reg_val = data; 12473 __le64 *desc_data; 12474 int nodata_len; 12475 int cmd_num; 12476 int i, k, n; 12477 int ret; 12478 12479 if (regs_num == 0) 12480 return 0; 12481 12482 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12483 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12484 HCLGE_64_BIT_REG_RTN_DATANUM); 12485 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12486 if (!desc) 12487 return -ENOMEM; 12488 12489 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12490 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12491 if (ret) { 12492 dev_err(&hdev->pdev->dev, 12493 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12494 kfree(desc); 12495 return ret; 12496 } 12497 12498 for (i = 0; i < cmd_num; i++) { 12499 if (i == 0) { 12500 desc_data = (__le64 *)(&desc[i].data[0]); 12501 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12502 } else { 12503 desc_data = (__le64 *)(&desc[i]); 12504 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12505 } 12506 for (k = 0; k < n; k++) { 12507 *reg_val++ = le64_to_cpu(*desc_data++); 12508 12509 regs_num--; 12510 if (!regs_num) 12511 break; 12512 } 12513 } 12514 12515 kfree(desc); 12516 return 0; 12517 } 12518 12519 #define MAX_SEPARATE_NUM 4 12520 #define SEPARATOR_VALUE 0xFDFCFBFA 12521 #define REG_NUM_PER_LINE 4 12522 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12523 #define REG_SEPARATOR_LINE 1 12524 #define REG_NUM_REMAIN_MASK 3 12525 12526 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12527 { 12528 int i; 12529 12530 /* initialize command BD except the last one */ 12531 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12532 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12533 true); 12534 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12535 } 12536 12537 /* initialize the last command BD */ 12538 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12539 12540 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12541 } 12542 12543 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12544 int *bd_num_list, 12545 u32 type_num) 12546 { 12547 u32 entries_per_desc, desc_index, index, offset, i; 12548 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12549 int ret; 12550 12551 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12552 if (ret) { 12553 dev_err(&hdev->pdev->dev, 12554 "Get dfx bd num fail, status is %d.\n", ret); 12555 return ret; 12556 } 12557 12558 entries_per_desc = ARRAY_SIZE(desc[0].data); 12559 for (i = 0; i < type_num; i++) { 12560 offset = hclge_dfx_bd_offset_list[i]; 12561 index = offset % entries_per_desc; 12562 desc_index = offset / entries_per_desc; 12563 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12564 } 12565 12566 return ret; 12567 } 12568 12569 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12570 struct hclge_desc *desc_src, int bd_num, 12571 enum hclge_opcode_type cmd) 12572 { 12573 struct hclge_desc *desc = desc_src; 12574 int i, ret; 12575 12576 hclge_cmd_setup_basic_desc(desc, cmd, true); 12577 for (i = 0; i < bd_num - 1; i++) { 12578 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12579 desc++; 12580 hclge_cmd_setup_basic_desc(desc, cmd, true); 12581 } 12582 12583 desc = desc_src; 12584 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12585 if (ret) 12586 dev_err(&hdev->pdev->dev, 12587 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12588 cmd, ret); 12589 12590 return ret; 12591 } 12592 12593 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12594 void *data) 12595 { 12596 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12597 struct hclge_desc *desc = desc_src; 12598 u32 *reg = data; 12599 12600 entries_per_desc = ARRAY_SIZE(desc->data); 12601 reg_num = entries_per_desc * bd_num; 12602 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12603 for (i = 0; i < reg_num; i++) { 12604 index = i % entries_per_desc; 12605 desc_index = i / entries_per_desc; 12606 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12607 } 12608 for (i = 0; i < separator_num; i++) 12609 *reg++ = SEPARATOR_VALUE; 12610 12611 return reg_num + separator_num; 12612 } 12613 12614 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12615 { 12616 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12617 int data_len_per_desc, bd_num, i; 12618 int *bd_num_list; 12619 u32 data_len; 12620 int ret; 12621 12622 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12623 if (!bd_num_list) 12624 return -ENOMEM; 12625 12626 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12627 if (ret) { 12628 dev_err(&hdev->pdev->dev, 12629 "Get dfx reg bd num fail, status is %d.\n", ret); 12630 goto out; 12631 } 12632 12633 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12634 *len = 0; 12635 for (i = 0; i < dfx_reg_type_num; i++) { 12636 bd_num = bd_num_list[i]; 12637 data_len = data_len_per_desc * bd_num; 12638 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12639 } 12640 12641 out: 12642 kfree(bd_num_list); 12643 return ret; 12644 } 12645 12646 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12647 { 12648 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12649 int bd_num, bd_num_max, buf_len, i; 12650 struct hclge_desc *desc_src; 12651 int *bd_num_list; 12652 u32 *reg = data; 12653 int ret; 12654 12655 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12656 if (!bd_num_list) 12657 return -ENOMEM; 12658 12659 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12660 if (ret) { 12661 dev_err(&hdev->pdev->dev, 12662 "Get dfx reg bd num fail, status is %d.\n", ret); 12663 goto out; 12664 } 12665 12666 bd_num_max = bd_num_list[0]; 12667 for (i = 1; i < dfx_reg_type_num; i++) 12668 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12669 12670 buf_len = sizeof(*desc_src) * bd_num_max; 12671 desc_src = kzalloc(buf_len, GFP_KERNEL); 12672 if (!desc_src) { 12673 ret = -ENOMEM; 12674 goto out; 12675 } 12676 12677 for (i = 0; i < dfx_reg_type_num; i++) { 12678 bd_num = bd_num_list[i]; 12679 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12680 hclge_dfx_reg_opcode_list[i]); 12681 if (ret) { 12682 dev_err(&hdev->pdev->dev, 12683 "Get dfx reg fail, status is %d.\n", ret); 12684 break; 12685 } 12686 12687 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12688 } 12689 12690 kfree(desc_src); 12691 out: 12692 kfree(bd_num_list); 12693 return ret; 12694 } 12695 12696 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12697 struct hnae3_knic_private_info *kinfo) 12698 { 12699 #define HCLGE_RING_REG_OFFSET 0x200 12700 #define HCLGE_RING_INT_REG_OFFSET 0x4 12701 12702 int i, j, reg_num, separator_num; 12703 int data_num_sum; 12704 u32 *reg = data; 12705 12706 /* fetching per-PF registers valus from PF PCIe register space */ 12707 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12708 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12709 for (i = 0; i < reg_num; i++) 12710 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12711 for (i = 0; i < separator_num; i++) 12712 *reg++ = SEPARATOR_VALUE; 12713 data_num_sum = reg_num + separator_num; 12714 12715 reg_num = ARRAY_SIZE(common_reg_addr_list); 12716 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12717 for (i = 0; i < reg_num; i++) 12718 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12719 for (i = 0; i < separator_num; i++) 12720 *reg++ = SEPARATOR_VALUE; 12721 data_num_sum += reg_num + separator_num; 12722 12723 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12724 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12725 for (j = 0; j < kinfo->num_tqps; j++) { 12726 for (i = 0; i < reg_num; i++) 12727 *reg++ = hclge_read_dev(&hdev->hw, 12728 ring_reg_addr_list[i] + 12729 HCLGE_RING_REG_OFFSET * j); 12730 for (i = 0; i < separator_num; i++) 12731 *reg++ = SEPARATOR_VALUE; 12732 } 12733 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12734 12735 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12736 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12737 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12738 for (i = 0; i < reg_num; i++) 12739 *reg++ = hclge_read_dev(&hdev->hw, 12740 tqp_intr_reg_addr_list[i] + 12741 HCLGE_RING_INT_REG_OFFSET * j); 12742 for (i = 0; i < separator_num; i++) 12743 *reg++ = SEPARATOR_VALUE; 12744 } 12745 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12746 12747 return data_num_sum; 12748 } 12749 12750 static int hclge_get_regs_len(struct hnae3_handle *handle) 12751 { 12752 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12753 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12754 struct hclge_vport *vport = hclge_get_vport(handle); 12755 struct hclge_dev *hdev = vport->back; 12756 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12757 int regs_lines_32_bit, regs_lines_64_bit; 12758 int ret; 12759 12760 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12761 if (ret) { 12762 dev_err(&hdev->pdev->dev, 12763 "Get register number failed, ret = %d.\n", ret); 12764 return ret; 12765 } 12766 12767 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12768 if (ret) { 12769 dev_err(&hdev->pdev->dev, 12770 "Get dfx reg len failed, ret = %d.\n", ret); 12771 return ret; 12772 } 12773 12774 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12775 REG_SEPARATOR_LINE; 12776 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12777 REG_SEPARATOR_LINE; 12778 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12779 REG_SEPARATOR_LINE; 12780 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12781 REG_SEPARATOR_LINE; 12782 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12783 REG_SEPARATOR_LINE; 12784 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12785 REG_SEPARATOR_LINE; 12786 12787 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12788 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12789 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12790 } 12791 12792 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12793 void *data) 12794 { 12795 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12796 struct hclge_vport *vport = hclge_get_vport(handle); 12797 struct hclge_dev *hdev = vport->back; 12798 u32 regs_num_32_bit, regs_num_64_bit; 12799 int i, reg_num, separator_num, ret; 12800 u32 *reg = data; 12801 12802 *version = hdev->fw_version; 12803 12804 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12805 if (ret) { 12806 dev_err(&hdev->pdev->dev, 12807 "Get register number failed, ret = %d.\n", ret); 12808 return; 12809 } 12810 12811 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12812 12813 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12814 if (ret) { 12815 dev_err(&hdev->pdev->dev, 12816 "Get 32 bit register failed, ret = %d.\n", ret); 12817 return; 12818 } 12819 reg_num = regs_num_32_bit; 12820 reg += reg_num; 12821 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12822 for (i = 0; i < separator_num; i++) 12823 *reg++ = SEPARATOR_VALUE; 12824 12825 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12826 if (ret) { 12827 dev_err(&hdev->pdev->dev, 12828 "Get 64 bit register failed, ret = %d.\n", ret); 12829 return; 12830 } 12831 reg_num = regs_num_64_bit * 2; 12832 reg += reg_num; 12833 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12834 for (i = 0; i < separator_num; i++) 12835 *reg++ = SEPARATOR_VALUE; 12836 12837 ret = hclge_get_dfx_reg(hdev, reg); 12838 if (ret) 12839 dev_err(&hdev->pdev->dev, 12840 "Get dfx register failed, ret = %d.\n", ret); 12841 } 12842 12843 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12844 { 12845 struct hclge_set_led_state_cmd *req; 12846 struct hclge_desc desc; 12847 int ret; 12848 12849 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12850 12851 req = (struct hclge_set_led_state_cmd *)desc.data; 12852 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12853 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12854 12855 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12856 if (ret) 12857 dev_err(&hdev->pdev->dev, 12858 "Send set led state cmd error, ret =%d\n", ret); 12859 12860 return ret; 12861 } 12862 12863 enum hclge_led_status { 12864 HCLGE_LED_OFF, 12865 HCLGE_LED_ON, 12866 HCLGE_LED_NO_CHANGE = 0xFF, 12867 }; 12868 12869 static int hclge_set_led_id(struct hnae3_handle *handle, 12870 enum ethtool_phys_id_state status) 12871 { 12872 struct hclge_vport *vport = hclge_get_vport(handle); 12873 struct hclge_dev *hdev = vport->back; 12874 12875 switch (status) { 12876 case ETHTOOL_ID_ACTIVE: 12877 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12878 case ETHTOOL_ID_INACTIVE: 12879 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12880 default: 12881 return -EINVAL; 12882 } 12883 } 12884 12885 static void hclge_get_link_mode(struct hnae3_handle *handle, 12886 unsigned long *supported, 12887 unsigned long *advertising) 12888 { 12889 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12890 struct hclge_vport *vport = hclge_get_vport(handle); 12891 struct hclge_dev *hdev = vport->back; 12892 unsigned int idx = 0; 12893 12894 for (; idx < size; idx++) { 12895 supported[idx] = hdev->hw.mac.supported[idx]; 12896 advertising[idx] = hdev->hw.mac.advertising[idx]; 12897 } 12898 } 12899 12900 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12901 { 12902 struct hclge_vport *vport = hclge_get_vport(handle); 12903 struct hclge_dev *hdev = vport->back; 12904 bool gro_en_old = hdev->gro_en; 12905 int ret; 12906 12907 hdev->gro_en = enable; 12908 ret = hclge_config_gro(hdev); 12909 if (ret) 12910 hdev->gro_en = gro_en_old; 12911 12912 return ret; 12913 } 12914 12915 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12916 { 12917 struct hnae3_handle *handle = &vport->nic; 12918 struct hclge_dev *hdev = vport->back; 12919 bool uc_en = false; 12920 bool mc_en = false; 12921 u8 tmp_flags; 12922 bool bc_en; 12923 int ret; 12924 12925 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12926 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12927 vport->last_promisc_flags = vport->overflow_promisc_flags; 12928 } 12929 12930 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12931 &vport->state)) 12932 return 0; 12933 12934 /* for PF */ 12935 if (!vport->vport_id) { 12936 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12937 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12938 tmp_flags & HNAE3_MPE); 12939 if (!ret) 12940 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12941 &vport->state); 12942 else 12943 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12944 &vport->state); 12945 return ret; 12946 } 12947 12948 /* for VF */ 12949 if (vport->vf_info.trusted) { 12950 uc_en = vport->vf_info.request_uc_en > 0 || 12951 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12952 mc_en = vport->vf_info.request_mc_en > 0 || 12953 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12954 } 12955 bc_en = vport->vf_info.request_bc_en > 0; 12956 12957 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12958 mc_en, bc_en); 12959 if (ret) { 12960 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12961 return ret; 12962 } 12963 hclge_set_vport_vlan_fltr_change(vport); 12964 12965 return 0; 12966 } 12967 12968 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12969 { 12970 struct hclge_vport *vport; 12971 int ret; 12972 u16 i; 12973 12974 for (i = 0; i < hdev->num_alloc_vport; i++) { 12975 vport = &hdev->vport[i]; 12976 12977 ret = hclge_sync_vport_promisc_mode(vport); 12978 if (ret) 12979 return; 12980 } 12981 } 12982 12983 static bool hclge_module_existed(struct hclge_dev *hdev) 12984 { 12985 struct hclge_desc desc; 12986 u32 existed; 12987 int ret; 12988 12989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12990 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12991 if (ret) { 12992 dev_err(&hdev->pdev->dev, 12993 "failed to get SFP exist state, ret = %d\n", ret); 12994 return false; 12995 } 12996 12997 existed = le32_to_cpu(desc.data[0]); 12998 12999 return existed != 0; 13000 } 13001 13002 /* need 6 bds(total 140 bytes) in one reading 13003 * return the number of bytes actually read, 0 means read failed. 13004 */ 13005 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 13006 u32 len, u8 *data) 13007 { 13008 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 13009 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 13010 u16 read_len; 13011 u16 copy_len; 13012 int ret; 13013 int i; 13014 13015 /* setup all 6 bds to read module eeprom info. */ 13016 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 13017 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 13018 true); 13019 13020 /* bd0~bd4 need next flag */ 13021 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 13022 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 13023 } 13024 13025 /* setup bd0, this bd contains offset and read length. */ 13026 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 13027 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 13028 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 13029 sfp_info_bd0->read_len = cpu_to_le16(read_len); 13030 13031 ret = hclge_cmd_send(&hdev->hw, desc, i); 13032 if (ret) { 13033 dev_err(&hdev->pdev->dev, 13034 "failed to get SFP eeprom info, ret = %d\n", ret); 13035 return 0; 13036 } 13037 13038 /* copy sfp info from bd0 to out buffer. */ 13039 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 13040 memcpy(data, sfp_info_bd0->data, copy_len); 13041 read_len = copy_len; 13042 13043 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 13044 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 13045 if (read_len >= len) 13046 return read_len; 13047 13048 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 13049 memcpy(data + read_len, desc[i].data, copy_len); 13050 read_len += copy_len; 13051 } 13052 13053 return read_len; 13054 } 13055 13056 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 13057 u32 len, u8 *data) 13058 { 13059 struct hclge_vport *vport = hclge_get_vport(handle); 13060 struct hclge_dev *hdev = vport->back; 13061 u32 read_len = 0; 13062 u16 data_len; 13063 13064 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 13065 return -EOPNOTSUPP; 13066 13067 if (!hclge_module_existed(hdev)) 13068 return -ENXIO; 13069 13070 while (read_len < len) { 13071 data_len = hclge_get_sfp_eeprom_info(hdev, 13072 offset + read_len, 13073 len - read_len, 13074 data + read_len); 13075 if (!data_len) 13076 return -EIO; 13077 13078 read_len += data_len; 13079 } 13080 13081 return 0; 13082 } 13083 13084 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 13085 u32 *status_code) 13086 { 13087 struct hclge_vport *vport = hclge_get_vport(handle); 13088 struct hclge_dev *hdev = vport->back; 13089 struct hclge_desc desc; 13090 int ret; 13091 13092 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 13093 return -EOPNOTSUPP; 13094 13095 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 13096 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 13097 if (ret) { 13098 dev_err(&hdev->pdev->dev, 13099 "failed to query link diagnosis info, ret = %d\n", ret); 13100 return ret; 13101 } 13102 13103 *status_code = le32_to_cpu(desc.data[0]); 13104 return 0; 13105 } 13106 13107 /* After disable sriov, VF still has some config and info need clean, 13108 * which configed by PF. 13109 */ 13110 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 13111 { 13112 struct hclge_dev *hdev = vport->back; 13113 struct hclge_vlan_info vlan_info; 13114 int ret; 13115 13116 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 13117 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 13118 vport->need_notify = 0; 13119 vport->mps = 0; 13120 13121 /* after disable sriov, clean VF rate configured by PF */ 13122 ret = hclge_tm_qs_shaper_cfg(vport, 0); 13123 if (ret) 13124 dev_err(&hdev->pdev->dev, 13125 "failed to clean vf%d rate config, ret = %d\n", 13126 vfid, ret); 13127 13128 vlan_info.vlan_tag = 0; 13129 vlan_info.qos = 0; 13130 vlan_info.vlan_proto = ETH_P_8021Q; 13131 ret = hclge_update_port_base_vlan_cfg(vport, 13132 HNAE3_PORT_BASE_VLAN_DISABLE, 13133 &vlan_info); 13134 if (ret) 13135 dev_err(&hdev->pdev->dev, 13136 "failed to clean vf%d port base vlan, ret = %d\n", 13137 vfid, ret); 13138 13139 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 13140 if (ret) 13141 dev_err(&hdev->pdev->dev, 13142 "failed to clean vf%d spoof config, ret = %d\n", 13143 vfid, ret); 13144 13145 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 13146 } 13147 13148 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 13149 { 13150 struct hclge_dev *hdev = ae_dev->priv; 13151 struct hclge_vport *vport; 13152 int i; 13153 13154 for (i = 0; i < num_vfs; i++) { 13155 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 13156 13157 hclge_clear_vport_vf_info(vport, i); 13158 } 13159 } 13160 13161 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 13162 u8 *priority) 13163 { 13164 struct hclge_vport *vport = hclge_get_vport(h); 13165 13166 if (dscp >= HNAE3_MAX_DSCP) 13167 return -EINVAL; 13168 13169 if (tc_mode) 13170 *tc_mode = vport->nic.kinfo.tc_map_mode; 13171 if (priority) 13172 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 13173 vport->nic.kinfo.dscp_prio[dscp]; 13174 13175 return 0; 13176 } 13177 13178 static const struct hnae3_ae_ops hclge_ops = { 13179 .init_ae_dev = hclge_init_ae_dev, 13180 .uninit_ae_dev = hclge_uninit_ae_dev, 13181 .reset_prepare = hclge_reset_prepare_general, 13182 .reset_done = hclge_reset_done, 13183 .init_client_instance = hclge_init_client_instance, 13184 .uninit_client_instance = hclge_uninit_client_instance, 13185 .map_ring_to_vector = hclge_map_ring_to_vector, 13186 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 13187 .get_vector = hclge_get_vector, 13188 .put_vector = hclge_put_vector, 13189 .set_promisc_mode = hclge_set_promisc_mode, 13190 .request_update_promisc_mode = hclge_request_update_promisc_mode, 13191 .set_loopback = hclge_set_loopback, 13192 .start = hclge_ae_start, 13193 .stop = hclge_ae_stop, 13194 .client_start = hclge_client_start, 13195 .client_stop = hclge_client_stop, 13196 .get_status = hclge_get_status, 13197 .get_ksettings_an_result = hclge_get_ksettings_an_result, 13198 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 13199 .get_media_type = hclge_get_media_type, 13200 .check_port_speed = hclge_check_port_speed, 13201 .get_fec_stats = hclge_get_fec_stats, 13202 .get_fec = hclge_get_fec, 13203 .set_fec = hclge_set_fec, 13204 .get_rss_key_size = hclge_comm_get_rss_key_size, 13205 .get_rss = hclge_get_rss, 13206 .set_rss = hclge_set_rss, 13207 .set_rss_tuple = hclge_set_rss_tuple, 13208 .get_rss_tuple = hclge_get_rss_tuple, 13209 .get_tc_size = hclge_get_tc_size, 13210 .get_mac_addr = hclge_get_mac_addr, 13211 .set_mac_addr = hclge_set_mac_addr, 13212 .do_ioctl = hclge_do_ioctl, 13213 .add_uc_addr = hclge_add_uc_addr, 13214 .rm_uc_addr = hclge_rm_uc_addr, 13215 .add_mc_addr = hclge_add_mc_addr, 13216 .rm_mc_addr = hclge_rm_mc_addr, 13217 .set_autoneg = hclge_set_autoneg, 13218 .get_autoneg = hclge_get_autoneg, 13219 .restart_autoneg = hclge_restart_autoneg, 13220 .halt_autoneg = hclge_halt_autoneg, 13221 .get_pauseparam = hclge_get_pauseparam, 13222 .set_pauseparam = hclge_set_pauseparam, 13223 .set_mtu = hclge_set_mtu, 13224 .reset_queue = hclge_reset_tqp, 13225 .get_stats = hclge_get_stats, 13226 .get_mac_stats = hclge_get_mac_stat, 13227 .update_stats = hclge_update_stats, 13228 .get_strings = hclge_get_strings, 13229 .get_sset_count = hclge_get_sset_count, 13230 .get_fw_version = hclge_get_fw_version, 13231 .get_mdix_mode = hclge_get_mdix_mode, 13232 .enable_vlan_filter = hclge_enable_vlan_filter, 13233 .set_vlan_filter = hclge_set_vlan_filter, 13234 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 13235 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 13236 .reset_event = hclge_reset_event, 13237 .get_reset_level = hclge_get_reset_level, 13238 .set_default_reset_request = hclge_set_def_reset_request, 13239 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 13240 .set_channels = hclge_set_channels, 13241 .get_channels = hclge_get_channels, 13242 .get_regs_len = hclge_get_regs_len, 13243 .get_regs = hclge_get_regs, 13244 .set_led_id = hclge_set_led_id, 13245 .get_link_mode = hclge_get_link_mode, 13246 .add_fd_entry = hclge_add_fd_entry, 13247 .del_fd_entry = hclge_del_fd_entry, 13248 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 13249 .get_fd_rule_info = hclge_get_fd_rule_info, 13250 .get_fd_all_rules = hclge_get_all_rules, 13251 .enable_fd = hclge_enable_fd, 13252 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 13253 .dbg_read_cmd = hclge_dbg_read_cmd, 13254 .handle_hw_ras_error = hclge_handle_hw_ras_error, 13255 .get_hw_reset_stat = hclge_get_hw_reset_stat, 13256 .ae_dev_resetting = hclge_ae_dev_resetting, 13257 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 13258 .set_gro_en = hclge_gro_en, 13259 .get_global_queue_id = hclge_covert_handle_qid_global, 13260 .set_timer_task = hclge_set_timer_task, 13261 .mac_connect_phy = hclge_mac_connect_phy, 13262 .mac_disconnect_phy = hclge_mac_disconnect_phy, 13263 .get_vf_config = hclge_get_vf_config, 13264 .set_vf_link_state = hclge_set_vf_link_state, 13265 .set_vf_spoofchk = hclge_set_vf_spoofchk, 13266 .set_vf_trust = hclge_set_vf_trust, 13267 .set_vf_rate = hclge_set_vf_rate, 13268 .set_vf_mac = hclge_set_vf_mac, 13269 .get_module_eeprom = hclge_get_module_eeprom, 13270 .get_cmdq_stat = hclge_get_cmdq_stat, 13271 .add_cls_flower = hclge_add_cls_flower, 13272 .del_cls_flower = hclge_del_cls_flower, 13273 .cls_flower_active = hclge_is_cls_flower_active, 13274 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 13275 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 13276 .set_tx_hwts_info = hclge_ptp_set_tx_info, 13277 .get_rx_hwts = hclge_ptp_get_rx_hwts, 13278 .get_ts_info = hclge_ptp_get_ts_info, 13279 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 13280 .clean_vf_config = hclge_clean_vport_config, 13281 .get_dscp_prio = hclge_get_dscp_prio, 13282 .get_wol = hclge_get_wol, 13283 .set_wol = hclge_set_wol, 13284 }; 13285 13286 static struct hnae3_ae_algo ae_algo = { 13287 .ops = &hclge_ops, 13288 .pdev_id_table = ae_algo_pci_tbl, 13289 }; 13290 13291 static int __init hclge_init(void) 13292 { 13293 pr_info("%s is initializing\n", HCLGE_NAME); 13294 13295 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 13296 if (!hclge_wq) { 13297 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 13298 return -ENOMEM; 13299 } 13300 13301 hnae3_register_ae_algo(&ae_algo); 13302 13303 return 0; 13304 } 13305 13306 static void __exit hclge_exit(void) 13307 { 13308 hnae3_unregister_ae_algo_prepare(&ae_algo); 13309 hnae3_unregister_ae_algo(&ae_algo); 13310 destroy_workqueue(hclge_wq); 13311 } 13312 module_init(hclge_init); 13313 module_exit(hclge_exit); 13314 13315 MODULE_LICENSE("GPL"); 13316 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 13317 MODULE_DESCRIPTION("HCLGE Driver"); 13318 MODULE_VERSION(HCLGE_MOD_VERSION); 13319