1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * DPAA2 Ethernet Switch declarations 4 * 5 * Copyright 2014-2016 Freescale Semiconductor Inc. 6 * Copyright 2017-2021 NXP 7 * 8 */ 9 10 #ifndef __ETHSW_H 11 #define __ETHSW_H 12 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/rtnetlink.h> 16 #include <linux/if_vlan.h> 17 #include <uapi/linux/if_bridge.h> 18 #include <net/switchdev.h> 19 #include <linux/if_bridge.h> 20 #include <linux/fsl/mc.h> 21 #include <soc/fsl/dpaa2-io.h> 22 23 #include "dpsw.h" 24 25 /* Number of IRQs supported */ 26 #define DPSW_IRQ_NUM 2 27 28 /* Port is member of VLAN */ 29 #define ETHSW_VLAN_MEMBER 1 30 /* VLAN to be treated as untagged on egress */ 31 #define ETHSW_VLAN_UNTAGGED 2 32 /* Untagged frames will be assigned to this VLAN */ 33 #define ETHSW_VLAN_PVID 4 34 /* VLAN configured on the switch */ 35 #define ETHSW_VLAN_GLOBAL 8 36 37 /* Maximum Frame Length supported by HW (currently 10k) */ 38 #define DPAA2_MFL (10 * 1024) 39 #define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN) 40 #define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN) 41 42 #define ETHSW_FEATURE_MAC_ADDR BIT(0) 43 44 /* Number of receive queues (one RX and one TX_CONF) */ 45 #define DPAA2_SWITCH_RX_NUM_FQS 2 46 47 /* Hardware requires alignment for ingress/egress buffer addresses */ 48 #define DPAA2_SWITCH_RX_BUF_RAW_SIZE PAGE_SIZE 49 #define DPAA2_SWITCH_RX_BUF_TAILROOM \ 50 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 51 #define DPAA2_SWITCH_RX_BUF_SIZE \ 52 (DPAA2_SWITCH_RX_BUF_RAW_SIZE - DPAA2_SWITCH_RX_BUF_TAILROOM) 53 54 #define DPAA2_SWITCH_STORE_SIZE 16 55 56 /* Buffer management */ 57 #define BUFS_PER_CMD 7 58 #define DPAA2_ETHSW_NUM_BUFS (1024 * BUFS_PER_CMD) 59 #define DPAA2_ETHSW_REFILL_THRESH (DPAA2_ETHSW_NUM_BUFS * 5 / 6) 60 61 /* Number of times to retry DPIO portal operations while waiting 62 * for portal to finish executing current command and become 63 * available. We want to avoid being stuck in a while loop in case 64 * hardware becomes unresponsive, but not give up too easily if 65 * the portal really is busy for valid reasons 66 */ 67 #define DPAA2_SWITCH_SWP_BUSY_RETRIES 1000 68 69 /* Hardware annotation buffer size */ 70 #define DPAA2_SWITCH_HWA_SIZE 64 71 /* Software annotation buffer size */ 72 #define DPAA2_SWITCH_SWA_SIZE 64 73 74 #define DPAA2_SWITCH_TX_BUF_ALIGN 64 75 76 #define DPAA2_SWITCH_TX_DATA_OFFSET \ 77 (DPAA2_SWITCH_HWA_SIZE + DPAA2_SWITCH_SWA_SIZE) 78 79 #define DPAA2_SWITCH_NEEDED_HEADROOM \ 80 (DPAA2_SWITCH_TX_DATA_OFFSET + DPAA2_SWITCH_TX_BUF_ALIGN) 81 82 #define DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES 16 83 #define DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE 256 84 85 extern const struct ethtool_ops dpaa2_switch_port_ethtool_ops; 86 87 struct ethsw_core; 88 89 struct dpaa2_switch_fq { 90 struct ethsw_core *ethsw; 91 enum dpsw_queue_type type; 92 struct dpaa2_io_store *store; 93 struct dpaa2_io_notification_ctx nctx; 94 struct napi_struct napi; 95 u32 fqid; 96 }; 97 98 struct dpaa2_switch_fdb { 99 struct net_device *bridge_dev; 100 u16 fdb_id; 101 bool in_use; 102 }; 103 104 /* Per port private data */ 105 struct ethsw_port_priv { 106 struct net_device *netdev; 107 u16 idx; 108 struct ethsw_core *ethsw_data; 109 u8 link_state; 110 u8 stp_state; 111 112 u8 vlans[VLAN_VID_MASK + 1]; 113 u16 pvid; 114 u16 tx_qdid; 115 116 struct dpaa2_switch_fdb *fdb; 117 bool bcast_flood; 118 bool ucast_flood; 119 bool learn_ena; 120 121 u16 acl_tbl; 122 u8 acl_num_rules; 123 }; 124 125 /* Switch data */ 126 struct ethsw_core { 127 struct device *dev; 128 struct fsl_mc_io *mc_io; 129 u16 dpsw_handle; 130 struct dpsw_attr sw_attr; 131 u16 major, minor; 132 unsigned long features; 133 int dev_id; 134 struct ethsw_port_priv **ports; 135 struct iommu_domain *iommu_domain; 136 137 u8 vlans[VLAN_VID_MASK + 1]; 138 139 struct workqueue_struct *workqueue; 140 141 struct dpaa2_switch_fq fq[DPAA2_SWITCH_RX_NUM_FQS]; 142 struct fsl_mc_device *dpbp_dev; 143 int buf_count; 144 u16 bpid; 145 int napi_users; 146 147 struct dpaa2_switch_fdb *fdbs; 148 }; 149 150 static inline bool dpaa2_switch_supports_cpu_traffic(struct ethsw_core *ethsw) 151 { 152 if (ethsw->sw_attr.options & DPSW_OPT_CTRL_IF_DIS) { 153 dev_err(ethsw->dev, "Control Interface is disabled, cannot probe\n"); 154 return false; 155 } 156 157 if (ethsw->sw_attr.flooding_cfg != DPSW_FLOODING_PER_FDB) { 158 dev_err(ethsw->dev, "Flooding domain is not per FDB, cannot probe\n"); 159 return false; 160 } 161 162 if (ethsw->sw_attr.broadcast_cfg != DPSW_BROADCAST_PER_FDB) { 163 dev_err(ethsw->dev, "Broadcast domain is not per FDB, cannot probe\n"); 164 return false; 165 } 166 167 if (ethsw->sw_attr.max_fdbs < ethsw->sw_attr.num_ifs) { 168 dev_err(ethsw->dev, "The number of FDBs is lower than the number of ports, cannot probe\n"); 169 return false; 170 } 171 172 return true; 173 } 174 175 bool dpaa2_switch_port_dev_check(const struct net_device *netdev); 176 177 int dpaa2_switch_port_vlans_add(struct net_device *netdev, 178 const struct switchdev_obj_port_vlan *vlan); 179 180 int dpaa2_switch_port_vlans_del(struct net_device *netdev, 181 const struct switchdev_obj_port_vlan *vlan); 182 183 typedef int dpaa2_switch_fdb_cb_t(struct ethsw_port_priv *port_priv, 184 struct fdb_dump_entry *fdb_entry, 185 void *data); 186 #endif /* __ETHSW_H */ 187