1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/clk.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/interrupt.h> 29 #include <linux/io.h> 30 #include <linux/module.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/phy.h> 34 #include <linux/platform_device.h> 35 #include <linux/property.h> 36 #include <linux/crc32.h> 37 #include <linux/if_vlan.h> 38 #include <linux/of_net.h> 39 #include <net/ip.h> 40 #include <net/ncsi.h> 41 42 #include "ftgmac100.h" 43 44 #define DRV_NAME "ftgmac100" 45 #define DRV_VERSION "0.7" 46 47 /* Arbitrary values, I am not sure the HW has limits */ 48 #define MAX_RX_QUEUE_ENTRIES 1024 49 #define MAX_TX_QUEUE_ENTRIES 1024 50 #define MIN_RX_QUEUE_ENTRIES 32 51 #define MIN_TX_QUEUE_ENTRIES 32 52 53 /* Defaults */ 54 #define DEF_RX_QUEUE_ENTRIES 128 55 #define DEF_TX_QUEUE_ENTRIES 128 56 57 #define MAX_PKT_SIZE 1536 58 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 59 60 /* Min number of tx ring entries before stopping queue */ 61 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 62 63 #define FTGMAC_100MHZ 100000000 64 #define FTGMAC_25MHZ 25000000 65 66 struct ftgmac100 { 67 /* Registers */ 68 struct resource *res; 69 void __iomem *base; 70 71 /* Rx ring */ 72 unsigned int rx_q_entries; 73 struct ftgmac100_rxdes *rxdes; 74 dma_addr_t rxdes_dma; 75 struct sk_buff **rx_skbs; 76 unsigned int rx_pointer; 77 u32 rxdes0_edorr_mask; 78 79 /* Tx ring */ 80 unsigned int tx_q_entries; 81 struct ftgmac100_txdes *txdes; 82 dma_addr_t txdes_dma; 83 struct sk_buff **tx_skbs; 84 unsigned int tx_clean_pointer; 85 unsigned int tx_pointer; 86 u32 txdes0_edotr_mask; 87 88 /* Used to signal the reset task of ring change request */ 89 unsigned int new_rx_q_entries; 90 unsigned int new_tx_q_entries; 91 92 /* Scratch page to use when rx skb alloc fails */ 93 void *rx_scratch; 94 dma_addr_t rx_scratch_dma; 95 96 /* Component structures */ 97 struct net_device *netdev; 98 struct device *dev; 99 struct ncsi_dev *ndev; 100 struct napi_struct napi; 101 struct work_struct reset_task; 102 struct mii_bus *mii_bus; 103 struct clk *clk; 104 105 /* Link management */ 106 int cur_speed; 107 int cur_duplex; 108 bool use_ncsi; 109 110 /* Multicast filter settings */ 111 u32 maht0; 112 u32 maht1; 113 114 /* Flow control settings */ 115 bool tx_pause; 116 bool rx_pause; 117 bool aneg_pause; 118 119 /* Misc */ 120 bool need_mac_restart; 121 bool is_aspeed; 122 }; 123 124 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 125 { 126 struct net_device *netdev = priv->netdev; 127 int i; 128 129 /* NOTE: reset clears all registers */ 130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 131 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 132 priv->base + FTGMAC100_OFFSET_MACCR); 133 for (i = 0; i < 200; i++) { 134 unsigned int maccr; 135 136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 137 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 138 return 0; 139 140 udelay(1); 141 } 142 143 netdev_err(netdev, "Hardware reset failed\n"); 144 return -EIO; 145 } 146 147 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 148 { 149 u32 maccr = 0; 150 151 switch (priv->cur_speed) { 152 case SPEED_10: 153 case 0: /* no link */ 154 break; 155 156 case SPEED_100: 157 maccr |= FTGMAC100_MACCR_FAST_MODE; 158 break; 159 160 case SPEED_1000: 161 maccr |= FTGMAC100_MACCR_GIGA_MODE; 162 break; 163 default: 164 netdev_err(priv->netdev, "Unknown speed %d !\n", 165 priv->cur_speed); 166 break; 167 } 168 169 /* (Re)initialize the queue pointers */ 170 priv->rx_pointer = 0; 171 priv->tx_clean_pointer = 0; 172 priv->tx_pointer = 0; 173 174 /* The doc says reset twice with 10us interval */ 175 if (ftgmac100_reset_mac(priv, maccr)) 176 return -EIO; 177 usleep_range(10, 1000); 178 return ftgmac100_reset_mac(priv, maccr); 179 } 180 181 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 182 { 183 unsigned int maddr = mac[0] << 8 | mac[1]; 184 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 185 186 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 187 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 188 } 189 190 static void ftgmac100_initial_mac(struct ftgmac100 *priv) 191 { 192 u8 mac[ETH_ALEN]; 193 unsigned int m; 194 unsigned int l; 195 void *addr; 196 197 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 198 if (addr) { 199 ether_addr_copy(priv->netdev->dev_addr, mac); 200 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 201 mac); 202 return; 203 } 204 205 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 206 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 207 208 mac[0] = (m >> 8) & 0xff; 209 mac[1] = m & 0xff; 210 mac[2] = (l >> 24) & 0xff; 211 mac[3] = (l >> 16) & 0xff; 212 mac[4] = (l >> 8) & 0xff; 213 mac[5] = l & 0xff; 214 215 if (is_valid_ether_addr(mac)) { 216 ether_addr_copy(priv->netdev->dev_addr, mac); 217 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 218 } else { 219 eth_hw_addr_random(priv->netdev); 220 dev_info(priv->dev, "Generated random MAC address %pM\n", 221 priv->netdev->dev_addr); 222 } 223 } 224 225 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 226 { 227 int ret; 228 229 ret = eth_prepare_mac_addr_change(dev, p); 230 if (ret < 0) 231 return ret; 232 233 eth_commit_mac_addr_change(dev, p); 234 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 235 236 return 0; 237 } 238 239 static void ftgmac100_config_pause(struct ftgmac100 *priv) 240 { 241 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); 242 243 /* Throttle tx queue when receiving pause frames */ 244 if (priv->rx_pause) 245 fcr |= FTGMAC100_FCR_FC_EN; 246 247 /* Enables sending pause frames when the RX queue is past a 248 * certain threshold. 249 */ 250 if (priv->tx_pause) 251 fcr |= FTGMAC100_FCR_FCTHR_EN; 252 253 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); 254 } 255 256 static void ftgmac100_init_hw(struct ftgmac100 *priv) 257 { 258 u32 reg, rfifo_sz, tfifo_sz; 259 260 /* Clear stale interrupts */ 261 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 262 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 263 264 /* Setup RX ring buffer base */ 265 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); 266 267 /* Setup TX ring buffer base */ 268 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 269 270 /* Configure RX buffer size */ 271 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 272 priv->base + FTGMAC100_OFFSET_RBSR); 273 274 /* Set RX descriptor autopoll */ 275 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 276 priv->base + FTGMAC100_OFFSET_APTC); 277 278 /* Write MAC address */ 279 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 280 281 /* Write multicast filter */ 282 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 283 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 284 285 /* Configure descriptor sizes and increase burst sizes according 286 * to values in Aspeed SDK. The FIFO arbitration is enabled and 287 * the thresholds set based on the recommended values in the 288 * AST2400 specification. 289 */ 290 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 291 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 292 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 293 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 294 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 295 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 296 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 297 priv->base + FTGMAC100_OFFSET_DBLAC); 298 299 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 300 * mitigation doesn't seem to provide any benefit with NAPI so leave 301 * it at that. 302 */ 303 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 304 FTGMAC100_ITC_TXINT_THR(1), 305 priv->base + FTGMAC100_OFFSET_ITC); 306 307 /* Configure FIFO sizes in the TPAFCR register */ 308 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 309 rfifo_sz = reg & 0x00000007; 310 tfifo_sz = (reg >> 3) & 0x00000007; 311 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 312 reg &= ~0x3f000000; 313 reg |= (tfifo_sz << 27); 314 reg |= (rfifo_sz << 24); 315 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 316 } 317 318 static void ftgmac100_start_hw(struct ftgmac100 *priv) 319 { 320 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 321 322 /* Keep the original GMAC and FAST bits */ 323 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 324 325 /* Add all the main enable bits */ 326 maccr |= FTGMAC100_MACCR_TXDMA_EN | 327 FTGMAC100_MACCR_RXDMA_EN | 328 FTGMAC100_MACCR_TXMAC_EN | 329 FTGMAC100_MACCR_RXMAC_EN | 330 FTGMAC100_MACCR_CRC_APD | 331 FTGMAC100_MACCR_PHY_LINK_LEVEL | 332 FTGMAC100_MACCR_RX_RUNT | 333 FTGMAC100_MACCR_RX_BROADPKT; 334 335 /* Add other bits as needed */ 336 if (priv->cur_duplex == DUPLEX_FULL) 337 maccr |= FTGMAC100_MACCR_FULLDUP; 338 if (priv->netdev->flags & IFF_PROMISC) 339 maccr |= FTGMAC100_MACCR_RX_ALL; 340 if (priv->netdev->flags & IFF_ALLMULTI) 341 maccr |= FTGMAC100_MACCR_RX_MULTIPKT; 342 else if (netdev_mc_count(priv->netdev)) 343 maccr |= FTGMAC100_MACCR_HT_MULTI_EN; 344 345 /* Vlan filtering enabled */ 346 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 347 maccr |= FTGMAC100_MACCR_RM_VLAN; 348 349 /* Hit the HW */ 350 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 351 } 352 353 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 354 { 355 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 356 } 357 358 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) 359 { 360 struct netdev_hw_addr *ha; 361 362 priv->maht1 = 0; 363 priv->maht0 = 0; 364 netdev_for_each_mc_addr(ha, priv->netdev) { 365 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); 366 367 crc_val = (~(crc_val >> 2)) & 0x3f; 368 if (crc_val >= 32) 369 priv->maht1 |= 1ul << (crc_val - 32); 370 else 371 priv->maht0 |= 1ul << (crc_val); 372 } 373 } 374 375 static void ftgmac100_set_rx_mode(struct net_device *netdev) 376 { 377 struct ftgmac100 *priv = netdev_priv(netdev); 378 379 /* Setup the hash filter */ 380 ftgmac100_calc_mc_hash(priv); 381 382 /* Interface down ? that's all there is to do */ 383 if (!netif_running(netdev)) 384 return; 385 386 /* Update the HW */ 387 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 388 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 389 390 /* Reconfigure MACCR */ 391 ftgmac100_start_hw(priv); 392 } 393 394 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 395 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 396 { 397 struct net_device *netdev = priv->netdev; 398 struct sk_buff *skb; 399 dma_addr_t map; 400 int err = 0; 401 402 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 403 if (unlikely(!skb)) { 404 if (net_ratelimit()) 405 netdev_warn(netdev, "failed to allocate rx skb\n"); 406 err = -ENOMEM; 407 map = priv->rx_scratch_dma; 408 } else { 409 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 410 DMA_FROM_DEVICE); 411 if (unlikely(dma_mapping_error(priv->dev, map))) { 412 if (net_ratelimit()) 413 netdev_err(netdev, "failed to map rx page\n"); 414 dev_kfree_skb_any(skb); 415 map = priv->rx_scratch_dma; 416 skb = NULL; 417 err = -ENOMEM; 418 } 419 } 420 421 /* Store skb */ 422 priv->rx_skbs[entry] = skb; 423 424 /* Store DMA address into RX desc */ 425 rxdes->rxdes3 = cpu_to_le32(map); 426 427 /* Ensure the above is ordered vs clearing the OWN bit */ 428 dma_wmb(); 429 430 /* Clean status (which resets own bit) */ 431 if (entry == (priv->rx_q_entries - 1)) 432 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 433 else 434 rxdes->rxdes0 = 0; 435 436 return err; 437 } 438 439 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, 440 unsigned int pointer) 441 { 442 return (pointer + 1) & (priv->rx_q_entries - 1); 443 } 444 445 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 446 { 447 struct net_device *netdev = priv->netdev; 448 449 if (status & FTGMAC100_RXDES0_RX_ERR) 450 netdev->stats.rx_errors++; 451 452 if (status & FTGMAC100_RXDES0_CRC_ERR) 453 netdev->stats.rx_crc_errors++; 454 455 if (status & (FTGMAC100_RXDES0_FTL | 456 FTGMAC100_RXDES0_RUNT | 457 FTGMAC100_RXDES0_RX_ODD_NB)) 458 netdev->stats.rx_length_errors++; 459 } 460 461 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 462 { 463 struct net_device *netdev = priv->netdev; 464 struct ftgmac100_rxdes *rxdes; 465 struct sk_buff *skb; 466 unsigned int pointer, size; 467 u32 status, csum_vlan; 468 dma_addr_t map; 469 470 /* Grab next RX descriptor */ 471 pointer = priv->rx_pointer; 472 rxdes = &priv->rxdes[pointer]; 473 474 /* Grab descriptor status */ 475 status = le32_to_cpu(rxdes->rxdes0); 476 477 /* Do we have a packet ? */ 478 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 479 return false; 480 481 /* Order subsequent reads with the test for the ready bit */ 482 dma_rmb(); 483 484 /* We don't cope with fragmented RX packets */ 485 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 486 !(status & FTGMAC100_RXDES0_LRS))) 487 goto drop; 488 489 /* Grab received size and csum vlan field in the descriptor */ 490 size = status & FTGMAC100_RXDES0_VDBC; 491 csum_vlan = le32_to_cpu(rxdes->rxdes1); 492 493 /* Any error (other than csum offload) flagged ? */ 494 if (unlikely(status & RXDES0_ANY_ERROR)) { 495 /* Correct for incorrect flagging of runt packets 496 * with vlan tags... Just accept a runt packet that 497 * has been flagged as vlan and whose size is at 498 * least 60 bytes. 499 */ 500 if ((status & FTGMAC100_RXDES0_RUNT) && 501 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 502 (size >= 60)) 503 status &= ~FTGMAC100_RXDES0_RUNT; 504 505 /* Any error still in there ? */ 506 if (status & RXDES0_ANY_ERROR) { 507 ftgmac100_rx_packet_error(priv, status); 508 goto drop; 509 } 510 } 511 512 /* If the packet had no skb (failed to allocate earlier) 513 * then try to allocate one and skip 514 */ 515 skb = priv->rx_skbs[pointer]; 516 if (!unlikely(skb)) { 517 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 518 goto drop; 519 } 520 521 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 522 netdev->stats.multicast++; 523 524 /* If the HW found checksum errors, bounce it to software. 525 * 526 * If we didn't, we need to see if the packet was recognized 527 * by HW as one of the supported checksummed protocols before 528 * we accept the HW test results. 529 */ 530 if (netdev->features & NETIF_F_RXCSUM) { 531 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 532 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 533 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 534 if ((csum_vlan & err_bits) || 535 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 536 skb->ip_summed = CHECKSUM_NONE; 537 else 538 skb->ip_summed = CHECKSUM_UNNECESSARY; 539 } 540 541 /* Transfer received size to skb */ 542 skb_put(skb, size); 543 544 /* Extract vlan tag */ 545 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 546 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) 547 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 548 csum_vlan & 0xffff); 549 550 /* Tear down DMA mapping, do necessary cache management */ 551 map = le32_to_cpu(rxdes->rxdes3); 552 553 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 554 /* When we don't have an iommu, we can save cycles by not 555 * invalidating the cache for the part of the packet that 556 * wasn't received. 557 */ 558 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 559 #else 560 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 561 #endif 562 563 564 /* Resplenish rx ring */ 565 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 566 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 567 568 skb->protocol = eth_type_trans(skb, netdev); 569 570 netdev->stats.rx_packets++; 571 netdev->stats.rx_bytes += size; 572 573 /* push packet to protocol stack */ 574 if (skb->ip_summed == CHECKSUM_NONE) 575 netif_receive_skb(skb); 576 else 577 napi_gro_receive(&priv->napi, skb); 578 579 (*processed)++; 580 return true; 581 582 drop: 583 /* Clean rxdes0 (which resets own bit) */ 584 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 585 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 586 netdev->stats.rx_dropped++; 587 return true; 588 } 589 590 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 591 unsigned int index) 592 { 593 if (index == (priv->tx_q_entries - 1)) 594 return priv->txdes0_edotr_mask; 595 else 596 return 0; 597 } 598 599 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, 600 unsigned int pointer) 601 { 602 return (pointer + 1) & (priv->tx_q_entries - 1); 603 } 604 605 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 606 { 607 /* Returns the number of available slots in the TX queue 608 * 609 * This always leaves one free slot so we don't have to 610 * worry about empty vs. full, and this simplifies the 611 * test for ftgmac100_tx_buf_cleanable() below 612 */ 613 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 614 (priv->tx_q_entries - 1); 615 } 616 617 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 618 { 619 return priv->tx_pointer != priv->tx_clean_pointer; 620 } 621 622 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 623 unsigned int pointer, 624 struct sk_buff *skb, 625 struct ftgmac100_txdes *txdes, 626 u32 ctl_stat) 627 { 628 dma_addr_t map = le32_to_cpu(txdes->txdes3); 629 size_t len; 630 631 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 632 len = skb_headlen(skb); 633 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 634 } else { 635 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 636 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 637 } 638 639 /* Free SKB on last segment */ 640 if (ctl_stat & FTGMAC100_TXDES0_LTS) 641 dev_kfree_skb(skb); 642 priv->tx_skbs[pointer] = NULL; 643 } 644 645 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 646 { 647 struct net_device *netdev = priv->netdev; 648 struct ftgmac100_txdes *txdes; 649 struct sk_buff *skb; 650 unsigned int pointer; 651 u32 ctl_stat; 652 653 pointer = priv->tx_clean_pointer; 654 txdes = &priv->txdes[pointer]; 655 656 ctl_stat = le32_to_cpu(txdes->txdes0); 657 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 658 return false; 659 660 skb = priv->tx_skbs[pointer]; 661 netdev->stats.tx_packets++; 662 netdev->stats.tx_bytes += skb->len; 663 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 664 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 665 666 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); 667 668 return true; 669 } 670 671 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 672 { 673 struct net_device *netdev = priv->netdev; 674 675 /* Process all completed packets */ 676 while (ftgmac100_tx_buf_cleanable(priv) && 677 ftgmac100_tx_complete_packet(priv)) 678 ; 679 680 /* Restart queue if needed */ 681 smp_mb(); 682 if (unlikely(netif_queue_stopped(netdev) && 683 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 684 struct netdev_queue *txq; 685 686 txq = netdev_get_tx_queue(netdev, 0); 687 __netif_tx_lock(txq, smp_processor_id()); 688 if (netif_queue_stopped(netdev) && 689 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 690 netif_wake_queue(netdev); 691 __netif_tx_unlock(txq); 692 } 693 } 694 695 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 696 { 697 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 698 u8 ip_proto = ip_hdr(skb)->protocol; 699 700 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 701 switch(ip_proto) { 702 case IPPROTO_TCP: 703 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 704 return true; 705 case IPPROTO_UDP: 706 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 707 return true; 708 case IPPROTO_IP: 709 return true; 710 } 711 } 712 return skb_checksum_help(skb) == 0; 713 } 714 715 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 716 struct net_device *netdev) 717 { 718 struct ftgmac100 *priv = netdev_priv(netdev); 719 struct ftgmac100_txdes *txdes, *first; 720 unsigned int pointer, nfrags, len, i, j; 721 u32 f_ctl_stat, ctl_stat, csum_vlan; 722 dma_addr_t map; 723 724 /* The HW doesn't pad small frames */ 725 if (eth_skb_pad(skb)) { 726 netdev->stats.tx_dropped++; 727 return NETDEV_TX_OK; 728 } 729 730 /* Reject oversize packets */ 731 if (unlikely(skb->len > MAX_PKT_SIZE)) { 732 if (net_ratelimit()) 733 netdev_dbg(netdev, "tx packet too big\n"); 734 goto drop; 735 } 736 737 /* Do we have a limit on #fragments ? I yet have to get a reply 738 * from Aspeed. If there's one I haven't hit it. 739 */ 740 nfrags = skb_shinfo(skb)->nr_frags; 741 742 /* Get header len */ 743 len = skb_headlen(skb); 744 745 /* Map the packet head */ 746 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 747 if (dma_mapping_error(priv->dev, map)) { 748 if (net_ratelimit()) 749 netdev_err(netdev, "map tx packet head failed\n"); 750 goto drop; 751 } 752 753 /* Grab the next free tx descriptor */ 754 pointer = priv->tx_pointer; 755 txdes = first = &priv->txdes[pointer]; 756 757 /* Setup it up with the packet head. Don't write the head to the 758 * ring just yet 759 */ 760 priv->tx_skbs[pointer] = skb; 761 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 762 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 763 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 764 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 765 if (nfrags == 0) 766 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 767 txdes->txdes3 = cpu_to_le32(map); 768 769 /* Setup HW checksumming */ 770 csum_vlan = 0; 771 if (skb->ip_summed == CHECKSUM_PARTIAL && 772 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 773 goto drop; 774 775 /* Add VLAN tag */ 776 if (skb_vlan_tag_present(skb)) { 777 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; 778 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; 779 } 780 781 txdes->txdes1 = cpu_to_le32(csum_vlan); 782 783 /* Next descriptor */ 784 pointer = ftgmac100_next_tx_pointer(priv, pointer); 785 786 /* Add the fragments */ 787 for (i = 0; i < nfrags; i++) { 788 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 789 790 len = frag->size; 791 792 /* Map it */ 793 map = skb_frag_dma_map(priv->dev, frag, 0, len, 794 DMA_TO_DEVICE); 795 if (dma_mapping_error(priv->dev, map)) 796 goto dma_err; 797 798 /* Setup descriptor */ 799 priv->tx_skbs[pointer] = skb; 800 txdes = &priv->txdes[pointer]; 801 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 802 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 803 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 804 if (i == (nfrags - 1)) 805 ctl_stat |= FTGMAC100_TXDES0_LTS; 806 txdes->txdes0 = cpu_to_le32(ctl_stat); 807 txdes->txdes1 = 0; 808 txdes->txdes3 = cpu_to_le32(map); 809 810 /* Next one */ 811 pointer = ftgmac100_next_tx_pointer(priv, pointer); 812 } 813 814 /* Order the previous packet and descriptor udpates 815 * before setting the OWN bit on the first descriptor. 816 */ 817 dma_wmb(); 818 first->txdes0 = cpu_to_le32(f_ctl_stat); 819 820 /* Update next TX pointer */ 821 priv->tx_pointer = pointer; 822 823 /* If there isn't enough room for all the fragments of a new packet 824 * in the TX ring, stop the queue. The sequence below is race free 825 * vs. a concurrent restart in ftgmac100_poll() 826 */ 827 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 828 netif_stop_queue(netdev); 829 /* Order the queue stop with the test below */ 830 smp_mb(); 831 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 832 netif_wake_queue(netdev); 833 } 834 835 /* Poke transmitter to read the updated TX descriptors */ 836 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 837 838 return NETDEV_TX_OK; 839 840 dma_err: 841 if (net_ratelimit()) 842 netdev_err(netdev, "map tx fragment failed\n"); 843 844 /* Free head */ 845 pointer = priv->tx_pointer; 846 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 847 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 848 849 /* Then all fragments */ 850 for (j = 0; j < i; j++) { 851 pointer = ftgmac100_next_tx_pointer(priv, pointer); 852 txdes = &priv->txdes[pointer]; 853 ctl_stat = le32_to_cpu(txdes->txdes0); 854 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 855 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 856 } 857 858 /* This cannot be reached if we successfully mapped the 859 * last fragment, so we know ftgmac100_free_tx_packet() 860 * hasn't freed the skb yet. 861 */ 862 drop: 863 /* Drop the packet */ 864 dev_kfree_skb_any(skb); 865 netdev->stats.tx_dropped++; 866 867 return NETDEV_TX_OK; 868 } 869 870 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 871 { 872 int i; 873 874 /* Free all RX buffers */ 875 for (i = 0; i < priv->rx_q_entries; i++) { 876 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 877 struct sk_buff *skb = priv->rx_skbs[i]; 878 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 879 880 if (!skb) 881 continue; 882 883 priv->rx_skbs[i] = NULL; 884 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 885 dev_kfree_skb_any(skb); 886 } 887 888 /* Free all TX buffers */ 889 for (i = 0; i < priv->tx_q_entries; i++) { 890 struct ftgmac100_txdes *txdes = &priv->txdes[i]; 891 struct sk_buff *skb = priv->tx_skbs[i]; 892 893 if (!skb) 894 continue; 895 ftgmac100_free_tx_packet(priv, i, skb, txdes, 896 le32_to_cpu(txdes->txdes0)); 897 } 898 } 899 900 static void ftgmac100_free_rings(struct ftgmac100 *priv) 901 { 902 /* Free skb arrays */ 903 kfree(priv->rx_skbs); 904 kfree(priv->tx_skbs); 905 906 /* Free descriptors */ 907 if (priv->rxdes) 908 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * 909 sizeof(struct ftgmac100_rxdes), 910 priv->rxdes, priv->rxdes_dma); 911 priv->rxdes = NULL; 912 913 if (priv->txdes) 914 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * 915 sizeof(struct ftgmac100_txdes), 916 priv->txdes, priv->txdes_dma); 917 priv->txdes = NULL; 918 919 /* Free scratch packet buffer */ 920 if (priv->rx_scratch) 921 dma_free_coherent(priv->dev, RX_BUF_SIZE, 922 priv->rx_scratch, priv->rx_scratch_dma); 923 } 924 925 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 926 { 927 /* Allocate skb arrays */ 928 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), 929 GFP_KERNEL); 930 if (!priv->rx_skbs) 931 return -ENOMEM; 932 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), 933 GFP_KERNEL); 934 if (!priv->tx_skbs) 935 return -ENOMEM; 936 937 /* Allocate descriptors */ 938 priv->rxdes = dma_zalloc_coherent(priv->dev, 939 MAX_RX_QUEUE_ENTRIES * 940 sizeof(struct ftgmac100_rxdes), 941 &priv->rxdes_dma, GFP_KERNEL); 942 if (!priv->rxdes) 943 return -ENOMEM; 944 priv->txdes = dma_zalloc_coherent(priv->dev, 945 MAX_TX_QUEUE_ENTRIES * 946 sizeof(struct ftgmac100_txdes), 947 &priv->txdes_dma, GFP_KERNEL); 948 if (!priv->txdes) 949 return -ENOMEM; 950 951 /* Allocate scratch packet buffer */ 952 priv->rx_scratch = dma_alloc_coherent(priv->dev, 953 RX_BUF_SIZE, 954 &priv->rx_scratch_dma, 955 GFP_KERNEL); 956 if (!priv->rx_scratch) 957 return -ENOMEM; 958 959 return 0; 960 } 961 962 static void ftgmac100_init_rings(struct ftgmac100 *priv) 963 { 964 struct ftgmac100_rxdes *rxdes = NULL; 965 struct ftgmac100_txdes *txdes = NULL; 966 int i; 967 968 /* Update entries counts */ 969 priv->rx_q_entries = priv->new_rx_q_entries; 970 priv->tx_q_entries = priv->new_tx_q_entries; 971 972 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) 973 return; 974 975 /* Initialize RX ring */ 976 for (i = 0; i < priv->rx_q_entries; i++) { 977 rxdes = &priv->rxdes[i]; 978 rxdes->rxdes0 = 0; 979 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 980 } 981 /* Mark the end of the ring */ 982 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 983 984 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) 985 return; 986 987 /* Initialize TX ring */ 988 for (i = 0; i < priv->tx_q_entries; i++) { 989 txdes = &priv->txdes[i]; 990 txdes->txdes0 = 0; 991 } 992 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 993 } 994 995 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 996 { 997 int i; 998 999 for (i = 0; i < priv->rx_q_entries; i++) { 1000 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 1001 1002 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 1003 return -ENOMEM; 1004 } 1005 return 0; 1006 } 1007 1008 static void ftgmac100_adjust_link(struct net_device *netdev) 1009 { 1010 struct ftgmac100 *priv = netdev_priv(netdev); 1011 struct phy_device *phydev = netdev->phydev; 1012 bool tx_pause, rx_pause; 1013 int new_speed; 1014 1015 /* We store "no link" as speed 0 */ 1016 if (!phydev->link) 1017 new_speed = 0; 1018 else 1019 new_speed = phydev->speed; 1020 1021 /* Grab pause settings from PHY if configured to do so */ 1022 if (priv->aneg_pause) { 1023 rx_pause = tx_pause = phydev->pause; 1024 if (phydev->asym_pause) 1025 tx_pause = !rx_pause; 1026 } else { 1027 rx_pause = priv->rx_pause; 1028 tx_pause = priv->tx_pause; 1029 } 1030 1031 /* Link hasn't changed, do nothing */ 1032 if (phydev->speed == priv->cur_speed && 1033 phydev->duplex == priv->cur_duplex && 1034 rx_pause == priv->rx_pause && 1035 tx_pause == priv->tx_pause) 1036 return; 1037 1038 /* Print status if we have a link or we had one and just lost it, 1039 * don't print otherwise. 1040 */ 1041 if (new_speed || priv->cur_speed) 1042 phy_print_status(phydev); 1043 1044 priv->cur_speed = new_speed; 1045 priv->cur_duplex = phydev->duplex; 1046 priv->rx_pause = rx_pause; 1047 priv->tx_pause = tx_pause; 1048 1049 /* Link is down, do nothing else */ 1050 if (!new_speed) 1051 return; 1052 1053 /* Disable all interrupts */ 1054 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1055 1056 /* Reset the adapter asynchronously */ 1057 schedule_work(&priv->reset_task); 1058 } 1059 1060 static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf) 1061 { 1062 struct net_device *netdev = priv->netdev; 1063 struct phy_device *phydev; 1064 1065 phydev = phy_find_first(priv->mii_bus); 1066 if (!phydev) { 1067 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 1068 return -ENODEV; 1069 } 1070 1071 phydev = phy_connect(netdev, phydev_name(phydev), 1072 &ftgmac100_adjust_link, intf); 1073 1074 if (IS_ERR(phydev)) { 1075 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 1076 return PTR_ERR(phydev); 1077 } 1078 1079 /* Indicate that we support PAUSE frames (see comment in 1080 * Documentation/networking/phy.txt) 1081 */ 1082 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 1083 phydev->advertising = phydev->supported; 1084 1085 /* Display what we found */ 1086 phy_attached_info(phydev); 1087 1088 return 0; 1089 } 1090 1091 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 1092 { 1093 struct net_device *netdev = bus->priv; 1094 struct ftgmac100 *priv = netdev_priv(netdev); 1095 unsigned int phycr; 1096 int i; 1097 1098 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1099 1100 /* preserve MDC cycle threshold */ 1101 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1102 1103 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1104 FTGMAC100_PHYCR_REGAD(regnum) | 1105 FTGMAC100_PHYCR_MIIRD; 1106 1107 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1108 1109 for (i = 0; i < 10; i++) { 1110 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1111 1112 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 1113 int data; 1114 1115 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 1116 return FTGMAC100_PHYDATA_MIIRDATA(data); 1117 } 1118 1119 udelay(100); 1120 } 1121 1122 netdev_err(netdev, "mdio read timed out\n"); 1123 return -EIO; 1124 } 1125 1126 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 1127 int regnum, u16 value) 1128 { 1129 struct net_device *netdev = bus->priv; 1130 struct ftgmac100 *priv = netdev_priv(netdev); 1131 unsigned int phycr; 1132 int data; 1133 int i; 1134 1135 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1136 1137 /* preserve MDC cycle threshold */ 1138 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1139 1140 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1141 FTGMAC100_PHYCR_REGAD(regnum) | 1142 FTGMAC100_PHYCR_MIIWR; 1143 1144 data = FTGMAC100_PHYDATA_MIIWDATA(value); 1145 1146 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 1147 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1148 1149 for (i = 0; i < 10; i++) { 1150 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1151 1152 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 1153 return 0; 1154 1155 udelay(100); 1156 } 1157 1158 netdev_err(netdev, "mdio write timed out\n"); 1159 return -EIO; 1160 } 1161 1162 static void ftgmac100_get_drvinfo(struct net_device *netdev, 1163 struct ethtool_drvinfo *info) 1164 { 1165 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1166 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1167 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1168 } 1169 1170 static void ftgmac100_get_ringparam(struct net_device *netdev, 1171 struct ethtool_ringparam *ering) 1172 { 1173 struct ftgmac100 *priv = netdev_priv(netdev); 1174 1175 memset(ering, 0, sizeof(*ering)); 1176 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; 1177 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; 1178 ering->rx_pending = priv->rx_q_entries; 1179 ering->tx_pending = priv->tx_q_entries; 1180 } 1181 1182 static int ftgmac100_set_ringparam(struct net_device *netdev, 1183 struct ethtool_ringparam *ering) 1184 { 1185 struct ftgmac100 *priv = netdev_priv(netdev); 1186 1187 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || 1188 ering->tx_pending > MAX_TX_QUEUE_ENTRIES || 1189 ering->rx_pending < MIN_RX_QUEUE_ENTRIES || 1190 ering->tx_pending < MIN_TX_QUEUE_ENTRIES || 1191 !is_power_of_2(ering->rx_pending) || 1192 !is_power_of_2(ering->tx_pending)) 1193 return -EINVAL; 1194 1195 priv->new_rx_q_entries = ering->rx_pending; 1196 priv->new_tx_q_entries = ering->tx_pending; 1197 if (netif_running(netdev)) 1198 schedule_work(&priv->reset_task); 1199 1200 return 0; 1201 } 1202 1203 static void ftgmac100_get_pauseparam(struct net_device *netdev, 1204 struct ethtool_pauseparam *pause) 1205 { 1206 struct ftgmac100 *priv = netdev_priv(netdev); 1207 1208 pause->autoneg = priv->aneg_pause; 1209 pause->tx_pause = priv->tx_pause; 1210 pause->rx_pause = priv->rx_pause; 1211 } 1212 1213 static int ftgmac100_set_pauseparam(struct net_device *netdev, 1214 struct ethtool_pauseparam *pause) 1215 { 1216 struct ftgmac100 *priv = netdev_priv(netdev); 1217 struct phy_device *phydev = netdev->phydev; 1218 1219 priv->aneg_pause = pause->autoneg; 1220 priv->tx_pause = pause->tx_pause; 1221 priv->rx_pause = pause->rx_pause; 1222 1223 if (phydev) { 1224 phydev->advertising &= ~ADVERTISED_Pause; 1225 phydev->advertising &= ~ADVERTISED_Asym_Pause; 1226 1227 if (pause->rx_pause) { 1228 phydev->advertising |= ADVERTISED_Pause; 1229 phydev->advertising |= ADVERTISED_Asym_Pause; 1230 } 1231 1232 if (pause->tx_pause) 1233 phydev->advertising ^= ADVERTISED_Asym_Pause; 1234 } 1235 if (netif_running(netdev)) { 1236 if (phydev && priv->aneg_pause) 1237 phy_start_aneg(phydev); 1238 else 1239 ftgmac100_config_pause(priv); 1240 } 1241 1242 return 0; 1243 } 1244 1245 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1246 .get_drvinfo = ftgmac100_get_drvinfo, 1247 .get_link = ethtool_op_get_link, 1248 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1249 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1250 .nway_reset = phy_ethtool_nway_reset, 1251 .get_ringparam = ftgmac100_get_ringparam, 1252 .set_ringparam = ftgmac100_set_ringparam, 1253 .get_pauseparam = ftgmac100_get_pauseparam, 1254 .set_pauseparam = ftgmac100_set_pauseparam, 1255 }; 1256 1257 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1258 { 1259 struct net_device *netdev = dev_id; 1260 struct ftgmac100 *priv = netdev_priv(netdev); 1261 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1262 1263 /* Fetch and clear interrupt bits, process abnormal ones */ 1264 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1265 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1266 if (unlikely(status & FTGMAC100_INT_BAD)) { 1267 1268 /* RX buffer unavailable */ 1269 if (status & FTGMAC100_INT_NO_RXBUF) 1270 netdev->stats.rx_over_errors++; 1271 1272 /* received packet lost due to RX FIFO full */ 1273 if (status & FTGMAC100_INT_RPKT_LOST) 1274 netdev->stats.rx_fifo_errors++; 1275 1276 /* sent packet lost due to excessive TX collision */ 1277 if (status & FTGMAC100_INT_XPKT_LOST) 1278 netdev->stats.tx_fifo_errors++; 1279 1280 /* AHB error -> Reset the chip */ 1281 if (status & FTGMAC100_INT_AHB_ERR) { 1282 if (net_ratelimit()) 1283 netdev_warn(netdev, 1284 "AHB bus error ! Resetting chip.\n"); 1285 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1286 schedule_work(&priv->reset_task); 1287 return IRQ_HANDLED; 1288 } 1289 1290 /* We may need to restart the MAC after such errors, delay 1291 * this until after we have freed some Rx buffers though 1292 */ 1293 priv->need_mac_restart = true; 1294 1295 /* Disable those errors until we restart */ 1296 new_mask &= ~status; 1297 } 1298 1299 /* Only enable "bad" interrupts while NAPI is on */ 1300 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1301 1302 /* Schedule NAPI bh */ 1303 napi_schedule_irqoff(&priv->napi); 1304 1305 return IRQ_HANDLED; 1306 } 1307 1308 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1309 { 1310 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; 1311 1312 /* Do we have a packet ? */ 1313 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1314 } 1315 1316 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1317 { 1318 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1319 int work_done = 0; 1320 bool more; 1321 1322 /* Handle TX completions */ 1323 if (ftgmac100_tx_buf_cleanable(priv)) 1324 ftgmac100_tx_complete(priv); 1325 1326 /* Handle RX packets */ 1327 do { 1328 more = ftgmac100_rx_packet(priv, &work_done); 1329 } while (more && work_done < budget); 1330 1331 1332 /* The interrupt is telling us to kick the MAC back to life 1333 * after an RX overflow 1334 */ 1335 if (unlikely(priv->need_mac_restart)) { 1336 ftgmac100_start_hw(priv); 1337 1338 /* Re-enable "bad" interrupts */ 1339 iowrite32(FTGMAC100_INT_BAD, 1340 priv->base + FTGMAC100_OFFSET_IER); 1341 } 1342 1343 /* As long as we are waiting for transmit packets to be 1344 * completed we keep NAPI going 1345 */ 1346 if (ftgmac100_tx_buf_cleanable(priv)) 1347 work_done = budget; 1348 1349 if (work_done < budget) { 1350 /* We are about to re-enable all interrupts. However 1351 * the HW has been latching RX/TX packet interrupts while 1352 * they were masked. So we clear them first, then we need 1353 * to re-check if there's something to process 1354 */ 1355 iowrite32(FTGMAC100_INT_RXTX, 1356 priv->base + FTGMAC100_OFFSET_ISR); 1357 1358 /* Push the above (and provides a barrier vs. subsequent 1359 * reads of the descriptor). 1360 */ 1361 ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1362 1363 /* Check RX and TX descriptors for more work to do */ 1364 if (ftgmac100_check_rx(priv) || 1365 ftgmac100_tx_buf_cleanable(priv)) 1366 return budget; 1367 1368 /* deschedule NAPI */ 1369 napi_complete(napi); 1370 1371 /* enable all interrupts */ 1372 iowrite32(FTGMAC100_INT_ALL, 1373 priv->base + FTGMAC100_OFFSET_IER); 1374 } 1375 1376 return work_done; 1377 } 1378 1379 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1380 { 1381 int err = 0; 1382 1383 /* Re-init descriptors (adjust queue sizes) */ 1384 ftgmac100_init_rings(priv); 1385 1386 /* Realloc rx descriptors */ 1387 err = ftgmac100_alloc_rx_buffers(priv); 1388 if (err && !ignore_alloc_err) 1389 return err; 1390 1391 /* Reinit and restart HW */ 1392 ftgmac100_init_hw(priv); 1393 ftgmac100_config_pause(priv); 1394 ftgmac100_start_hw(priv); 1395 1396 /* Re-enable the device */ 1397 napi_enable(&priv->napi); 1398 netif_start_queue(priv->netdev); 1399 1400 /* Enable all interrupts */ 1401 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1402 1403 return err; 1404 } 1405 1406 static void ftgmac100_reset_task(struct work_struct *work) 1407 { 1408 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1409 reset_task); 1410 struct net_device *netdev = priv->netdev; 1411 int err; 1412 1413 netdev_dbg(netdev, "Resetting NIC...\n"); 1414 1415 /* Lock the world */ 1416 rtnl_lock(); 1417 if (netdev->phydev) 1418 mutex_lock(&netdev->phydev->lock); 1419 if (priv->mii_bus) 1420 mutex_lock(&priv->mii_bus->mdio_lock); 1421 1422 1423 /* Check if the interface is still up */ 1424 if (!netif_running(netdev)) 1425 goto bail; 1426 1427 /* Stop the network stack */ 1428 netif_trans_update(netdev); 1429 napi_disable(&priv->napi); 1430 netif_tx_disable(netdev); 1431 1432 /* Stop and reset the MAC */ 1433 ftgmac100_stop_hw(priv); 1434 err = ftgmac100_reset_and_config_mac(priv); 1435 if (err) { 1436 /* Not much we can do ... it might come back... */ 1437 netdev_err(netdev, "attempting to continue...\n"); 1438 } 1439 1440 /* Free all rx and tx buffers */ 1441 ftgmac100_free_buffers(priv); 1442 1443 /* Setup everything again and restart chip */ 1444 ftgmac100_init_all(priv, true); 1445 1446 netdev_dbg(netdev, "Reset done !\n"); 1447 bail: 1448 if (priv->mii_bus) 1449 mutex_unlock(&priv->mii_bus->mdio_lock); 1450 if (netdev->phydev) 1451 mutex_unlock(&netdev->phydev->lock); 1452 rtnl_unlock(); 1453 } 1454 1455 static int ftgmac100_open(struct net_device *netdev) 1456 { 1457 struct ftgmac100 *priv = netdev_priv(netdev); 1458 int err; 1459 1460 /* Allocate ring buffers */ 1461 err = ftgmac100_alloc_rings(priv); 1462 if (err) { 1463 netdev_err(netdev, "Failed to allocate descriptors\n"); 1464 return err; 1465 } 1466 1467 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1468 * 1469 * Otherwise we leave it set to 0 (no link), the link 1470 * message from the PHY layer will handle setting it up to 1471 * something else if needed. 1472 */ 1473 if (priv->use_ncsi) { 1474 priv->cur_duplex = DUPLEX_FULL; 1475 priv->cur_speed = SPEED_100; 1476 } else { 1477 priv->cur_duplex = 0; 1478 priv->cur_speed = 0; 1479 } 1480 1481 /* Reset the hardware */ 1482 err = ftgmac100_reset_and_config_mac(priv); 1483 if (err) 1484 goto err_hw; 1485 1486 /* Initialize NAPI */ 1487 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1488 1489 /* Grab our interrupt */ 1490 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1491 if (err) { 1492 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1493 goto err_irq; 1494 } 1495 1496 /* Start things up */ 1497 err = ftgmac100_init_all(priv, false); 1498 if (err) { 1499 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1500 goto err_alloc; 1501 } 1502 1503 if (netdev->phydev) { 1504 /* If we have a PHY, start polling */ 1505 phy_start(netdev->phydev); 1506 } else if (priv->use_ncsi) { 1507 /* If using NC-SI, set our carrier on and start the stack */ 1508 netif_carrier_on(netdev); 1509 1510 /* Start the NCSI device */ 1511 err = ncsi_start_dev(priv->ndev); 1512 if (err) 1513 goto err_ncsi; 1514 } 1515 1516 return 0; 1517 1518 err_ncsi: 1519 napi_disable(&priv->napi); 1520 netif_stop_queue(netdev); 1521 err_alloc: 1522 ftgmac100_free_buffers(priv); 1523 free_irq(netdev->irq, netdev); 1524 err_irq: 1525 netif_napi_del(&priv->napi); 1526 err_hw: 1527 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1528 ftgmac100_free_rings(priv); 1529 return err; 1530 } 1531 1532 static int ftgmac100_stop(struct net_device *netdev) 1533 { 1534 struct ftgmac100 *priv = netdev_priv(netdev); 1535 1536 /* Note about the reset task: We are called with the rtnl lock 1537 * held, so we are synchronized against the core of the reset 1538 * task. We must not try to synchronously cancel it otherwise 1539 * we can deadlock. But since it will test for netif_running() 1540 * which has already been cleared by the net core, we don't 1541 * anything special to do. 1542 */ 1543 1544 /* disable all interrupts */ 1545 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1546 1547 netif_stop_queue(netdev); 1548 napi_disable(&priv->napi); 1549 netif_napi_del(&priv->napi); 1550 if (netdev->phydev) 1551 phy_stop(netdev->phydev); 1552 else if (priv->use_ncsi) 1553 ncsi_stop_dev(priv->ndev); 1554 1555 ftgmac100_stop_hw(priv); 1556 free_irq(netdev->irq, netdev); 1557 ftgmac100_free_buffers(priv); 1558 ftgmac100_free_rings(priv); 1559 1560 return 0; 1561 } 1562 1563 /* optional */ 1564 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1565 { 1566 if (!netdev->phydev) 1567 return -ENXIO; 1568 1569 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 1570 } 1571 1572 static void ftgmac100_tx_timeout(struct net_device *netdev) 1573 { 1574 struct ftgmac100 *priv = netdev_priv(netdev); 1575 1576 /* Disable all interrupts */ 1577 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1578 1579 /* Do the reset outside of interrupt context */ 1580 schedule_work(&priv->reset_task); 1581 } 1582 1583 static int ftgmac100_set_features(struct net_device *netdev, 1584 netdev_features_t features) 1585 { 1586 struct ftgmac100 *priv = netdev_priv(netdev); 1587 netdev_features_t changed = netdev->features ^ features; 1588 1589 if (!netif_running(netdev)) 1590 return 0; 1591 1592 /* Update the vlan filtering bit */ 1593 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 1594 u32 maccr; 1595 1596 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 1597 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1598 maccr |= FTGMAC100_MACCR_RM_VLAN; 1599 else 1600 maccr &= ~FTGMAC100_MACCR_RM_VLAN; 1601 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 1602 } 1603 1604 return 0; 1605 } 1606 1607 #ifdef CONFIG_NET_POLL_CONTROLLER 1608 static void ftgmac100_poll_controller(struct net_device *netdev) 1609 { 1610 unsigned long flags; 1611 1612 local_irq_save(flags); 1613 ftgmac100_interrupt(netdev->irq, netdev); 1614 local_irq_restore(flags); 1615 } 1616 #endif 1617 1618 static const struct net_device_ops ftgmac100_netdev_ops = { 1619 .ndo_open = ftgmac100_open, 1620 .ndo_stop = ftgmac100_stop, 1621 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1622 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1623 .ndo_validate_addr = eth_validate_addr, 1624 .ndo_do_ioctl = ftgmac100_do_ioctl, 1625 .ndo_tx_timeout = ftgmac100_tx_timeout, 1626 .ndo_set_rx_mode = ftgmac100_set_rx_mode, 1627 .ndo_set_features = ftgmac100_set_features, 1628 #ifdef CONFIG_NET_POLL_CONTROLLER 1629 .ndo_poll_controller = ftgmac100_poll_controller, 1630 #endif 1631 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid, 1632 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid, 1633 }; 1634 1635 static int ftgmac100_setup_mdio(struct net_device *netdev) 1636 { 1637 struct ftgmac100 *priv = netdev_priv(netdev); 1638 struct platform_device *pdev = to_platform_device(priv->dev); 1639 int phy_intf = PHY_INTERFACE_MODE_RGMII; 1640 struct device_node *np = pdev->dev.of_node; 1641 int i, err = 0; 1642 u32 reg; 1643 1644 /* initialize mdio bus */ 1645 priv->mii_bus = mdiobus_alloc(); 1646 if (!priv->mii_bus) 1647 return -EIO; 1648 1649 if (priv->is_aspeed) { 1650 /* This driver supports the old MDIO interface */ 1651 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1652 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1653 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1654 }; 1655 1656 /* Get PHY mode from device-tree */ 1657 if (np) { 1658 /* Default to RGMII. It's a gigabit part after all */ 1659 phy_intf = of_get_phy_mode(np); 1660 if (phy_intf < 0) 1661 phy_intf = PHY_INTERFACE_MODE_RGMII; 1662 1663 /* Aspeed only supports these. I don't know about other IP 1664 * block vendors so I'm going to just let them through for 1665 * now. Note that this is only a warning if for some obscure 1666 * reason the DT really means to lie about it or it's a newer 1667 * part we don't know about. 1668 * 1669 * On the Aspeed SoC there are additionally straps and SCU 1670 * control bits that could tell us what the interface is 1671 * (or allow us to configure it while the IP block is held 1672 * in reset). For now I chose to keep this driver away from 1673 * those SoC specific bits and assume the device-tree is 1674 * right and the SCU has been configured properly by pinmux 1675 * or the firmware. 1676 */ 1677 if (priv->is_aspeed && 1678 phy_intf != PHY_INTERFACE_MODE_RMII && 1679 phy_intf != PHY_INTERFACE_MODE_RGMII && 1680 phy_intf != PHY_INTERFACE_MODE_RGMII_ID && 1681 phy_intf != PHY_INTERFACE_MODE_RGMII_RXID && 1682 phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) { 1683 netdev_warn(netdev, 1684 "Unsupported PHY mode %s !\n", 1685 phy_modes(phy_intf)); 1686 } 1687 } 1688 1689 priv->mii_bus->name = "ftgmac100_mdio"; 1690 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1691 pdev->name, pdev->id); 1692 priv->mii_bus->parent = priv->dev; 1693 priv->mii_bus->priv = priv->netdev; 1694 priv->mii_bus->read = ftgmac100_mdiobus_read; 1695 priv->mii_bus->write = ftgmac100_mdiobus_write; 1696 1697 for (i = 0; i < PHY_MAX_ADDR; i++) 1698 priv->mii_bus->irq[i] = PHY_POLL; 1699 1700 err = mdiobus_register(priv->mii_bus); 1701 if (err) { 1702 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1703 goto err_register_mdiobus; 1704 } 1705 1706 err = ftgmac100_mii_probe(priv, phy_intf); 1707 if (err) { 1708 dev_err(priv->dev, "MII Probe failed!\n"); 1709 goto err_mii_probe; 1710 } 1711 1712 return 0; 1713 1714 err_mii_probe: 1715 mdiobus_unregister(priv->mii_bus); 1716 err_register_mdiobus: 1717 mdiobus_free(priv->mii_bus); 1718 return err; 1719 } 1720 1721 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1722 { 1723 struct ftgmac100 *priv = netdev_priv(netdev); 1724 1725 if (!netdev->phydev) 1726 return; 1727 1728 phy_disconnect(netdev->phydev); 1729 mdiobus_unregister(priv->mii_bus); 1730 mdiobus_free(priv->mii_bus); 1731 } 1732 1733 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1734 { 1735 if (unlikely(nd->state != ncsi_dev_state_functional)) 1736 return; 1737 1738 netdev_info(nd->dev, "NCSI interface %s\n", 1739 nd->link_up ? "up" : "down"); 1740 } 1741 1742 static void ftgmac100_setup_clk(struct ftgmac100 *priv) 1743 { 1744 priv->clk = devm_clk_get(priv->dev, NULL); 1745 if (IS_ERR(priv->clk)) 1746 return; 1747 1748 clk_prepare_enable(priv->clk); 1749 1750 /* Aspeed specifies a 100MHz clock is required for up to 1751 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz 1752 * is sufficient 1753 */ 1754 clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : 1755 FTGMAC_100MHZ); 1756 } 1757 1758 static int ftgmac100_probe(struct platform_device *pdev) 1759 { 1760 struct resource *res; 1761 int irq; 1762 struct net_device *netdev; 1763 struct ftgmac100 *priv; 1764 struct device_node *np; 1765 int err = 0; 1766 1767 if (!pdev) 1768 return -ENODEV; 1769 1770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1771 if (!res) 1772 return -ENXIO; 1773 1774 irq = platform_get_irq(pdev, 0); 1775 if (irq < 0) 1776 return irq; 1777 1778 /* setup net_device */ 1779 netdev = alloc_etherdev(sizeof(*priv)); 1780 if (!netdev) { 1781 err = -ENOMEM; 1782 goto err_alloc_etherdev; 1783 } 1784 1785 SET_NETDEV_DEV(netdev, &pdev->dev); 1786 1787 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1788 netdev->netdev_ops = &ftgmac100_netdev_ops; 1789 netdev->watchdog_timeo = 5 * HZ; 1790 1791 platform_set_drvdata(pdev, netdev); 1792 1793 /* setup private data */ 1794 priv = netdev_priv(netdev); 1795 priv->netdev = netdev; 1796 priv->dev = &pdev->dev; 1797 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1798 1799 /* map io memory */ 1800 priv->res = request_mem_region(res->start, resource_size(res), 1801 dev_name(&pdev->dev)); 1802 if (!priv->res) { 1803 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1804 err = -ENOMEM; 1805 goto err_req_mem; 1806 } 1807 1808 priv->base = ioremap(res->start, resource_size(res)); 1809 if (!priv->base) { 1810 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1811 err = -EIO; 1812 goto err_ioremap; 1813 } 1814 1815 netdev->irq = irq; 1816 1817 /* Enable pause */ 1818 priv->tx_pause = true; 1819 priv->rx_pause = true; 1820 priv->aneg_pause = true; 1821 1822 /* MAC address from chip or random one */ 1823 ftgmac100_initial_mac(priv); 1824 1825 np = pdev->dev.of_node; 1826 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1827 of_device_is_compatible(np, "aspeed,ast2500-mac"))) { 1828 priv->rxdes0_edorr_mask = BIT(30); 1829 priv->txdes0_edotr_mask = BIT(30); 1830 priv->is_aspeed = true; 1831 } else { 1832 priv->rxdes0_edorr_mask = BIT(15); 1833 priv->txdes0_edotr_mask = BIT(15); 1834 } 1835 1836 if (np && of_get_property(np, "use-ncsi", NULL)) { 1837 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1838 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1839 goto err_ncsi_dev; 1840 } 1841 1842 dev_info(&pdev->dev, "Using NCSI interface\n"); 1843 priv->use_ncsi = true; 1844 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1845 if (!priv->ndev) 1846 goto err_ncsi_dev; 1847 } else { 1848 priv->use_ncsi = false; 1849 err = ftgmac100_setup_mdio(netdev); 1850 if (err) 1851 goto err_setup_mdio; 1852 } 1853 1854 if (priv->is_aspeed) 1855 ftgmac100_setup_clk(priv); 1856 1857 /* Default ring sizes */ 1858 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; 1859 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; 1860 1861 /* Base feature set */ 1862 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1863 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | 1864 NETIF_F_HW_VLAN_CTAG_TX; 1865 1866 if (priv->use_ncsi) 1867 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1868 1869 /* AST2400 doesn't have working HW checksum generation */ 1870 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1871 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1872 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1873 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1874 netdev->features |= netdev->hw_features; 1875 1876 /* register network device */ 1877 err = register_netdev(netdev); 1878 if (err) { 1879 dev_err(&pdev->dev, "Failed to register netdev\n"); 1880 goto err_register_netdev; 1881 } 1882 1883 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 1884 1885 return 0; 1886 1887 err_ncsi_dev: 1888 err_register_netdev: 1889 ftgmac100_destroy_mdio(netdev); 1890 err_setup_mdio: 1891 iounmap(priv->base); 1892 err_ioremap: 1893 release_resource(priv->res); 1894 err_req_mem: 1895 free_netdev(netdev); 1896 err_alloc_etherdev: 1897 return err; 1898 } 1899 1900 static int ftgmac100_remove(struct platform_device *pdev) 1901 { 1902 struct net_device *netdev; 1903 struct ftgmac100 *priv; 1904 1905 netdev = platform_get_drvdata(pdev); 1906 priv = netdev_priv(netdev); 1907 1908 unregister_netdev(netdev); 1909 1910 clk_disable_unprepare(priv->clk); 1911 1912 /* There's a small chance the reset task will have been re-queued, 1913 * during stop, make sure it's gone before we free the structure. 1914 */ 1915 cancel_work_sync(&priv->reset_task); 1916 1917 ftgmac100_destroy_mdio(netdev); 1918 1919 iounmap(priv->base); 1920 release_resource(priv->res); 1921 1922 netif_napi_del(&priv->napi); 1923 free_netdev(netdev); 1924 return 0; 1925 } 1926 1927 static const struct of_device_id ftgmac100_of_match[] = { 1928 { .compatible = "faraday,ftgmac100" }, 1929 { } 1930 }; 1931 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1932 1933 static struct platform_driver ftgmac100_driver = { 1934 .probe = ftgmac100_probe, 1935 .remove = ftgmac100_remove, 1936 .driver = { 1937 .name = DRV_NAME, 1938 .of_match_table = ftgmac100_of_match, 1939 }, 1940 }; 1941 module_platform_driver(ftgmac100_driver); 1942 1943 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1944 MODULE_DESCRIPTION("FTGMAC100 driver"); 1945 MODULE_LICENSE("GPL"); 1946