1 /* 2 * Dave DNET Ethernet Controller driver 3 * 4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> 5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/kernel.h> 15 #include <linux/types.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/netdevice.h> 21 #include <linux/etherdevice.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/platform_device.h> 24 #include <linux/phy.h> 25 26 #include "dnet.h" 27 28 #undef DEBUG 29 30 /* function for reading internal MAC register */ 31 static u16 dnet_readw_mac(struct dnet *bp, u16 reg) 32 { 33 u16 data_read; 34 35 /* issue a read */ 36 dnet_writel(bp, reg, MACREG_ADDR); 37 38 /* since a read/write op to the MAC is very slow, 39 * we must wait before reading the data */ 40 ndelay(500); 41 42 /* read data read from the MAC register */ 43 data_read = dnet_readl(bp, MACREG_DATA); 44 45 /* all done */ 46 return data_read; 47 } 48 49 /* function for writing internal MAC register */ 50 static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) 51 { 52 /* load data to write */ 53 dnet_writel(bp, val, MACREG_DATA); 54 55 /* issue a write */ 56 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); 57 58 /* since a read/write op to the MAC is very slow, 59 * we must wait before exiting */ 60 ndelay(500); 61 } 62 63 static void __dnet_set_hwaddr(struct dnet *bp) 64 { 65 u16 tmp; 66 67 tmp = be16_to_cpup((__be16 *)bp->dev->dev_addr); 68 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); 69 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 2)); 70 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); 71 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 4)); 72 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); 73 } 74 75 static void dnet_get_hwaddr(struct dnet *bp) 76 { 77 u16 tmp; 78 u8 addr[6]; 79 80 /* 81 * from MAC docs: 82 * "Note that the MAC address is stored in the registers in Hexadecimal 83 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80 84 * would require writing 0xAC (octet 0) to address 0x0B (high byte of 85 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of 86 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of 87 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of 88 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of 89 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of 90 * Mac_addr[15:0]). 91 */ 92 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG); 93 *((__be16 *)addr) = cpu_to_be16(tmp); 94 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG); 95 *((__be16 *)(addr + 2)) = cpu_to_be16(tmp); 96 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG); 97 *((__be16 *)(addr + 4)) = cpu_to_be16(tmp); 98 99 if (is_valid_ether_addr(addr)) 100 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 101 } 102 103 static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 104 { 105 struct dnet *bp = bus->priv; 106 u16 value; 107 108 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 109 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 110 cpu_relax(); 111 112 /* only 5 bits allowed for phy-addr and reg_offset */ 113 mii_id &= 0x1f; 114 regnum &= 0x1f; 115 116 /* prepare reg_value for a read */ 117 value = (mii_id << 8); 118 value |= regnum; 119 120 /* write control word */ 121 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value); 122 123 /* wait for end of transfer */ 124 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 125 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 126 cpu_relax(); 127 128 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG); 129 130 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value); 131 132 return value; 133 } 134 135 static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 136 u16 value) 137 { 138 struct dnet *bp = bus->priv; 139 u16 tmp; 140 141 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value); 142 143 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 144 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 145 cpu_relax(); 146 147 /* prepare for a write operation */ 148 tmp = (1 << 13); 149 150 /* only 5 bits allowed for phy-addr and reg_offset */ 151 mii_id &= 0x1f; 152 regnum &= 0x1f; 153 154 /* only 16 bits on data */ 155 value &= 0xffff; 156 157 /* prepare reg_value for a write */ 158 tmp |= (mii_id << 8); 159 tmp |= regnum; 160 161 /* write data to write first */ 162 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value); 163 164 /* write control word */ 165 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); 166 167 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 168 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 169 cpu_relax(); 170 171 return 0; 172 } 173 174 static int dnet_mdio_reset(struct mii_bus *bus) 175 { 176 return 0; 177 } 178 179 static void dnet_handle_link_change(struct net_device *dev) 180 { 181 struct dnet *bp = netdev_priv(dev); 182 struct phy_device *phydev = bp->phy_dev; 183 unsigned long flags; 184 u32 mode_reg, ctl_reg; 185 186 int status_change = 0; 187 188 spin_lock_irqsave(&bp->lock, flags); 189 190 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); 191 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 192 193 if (phydev->link) { 194 if (bp->duplex != phydev->duplex) { 195 if (phydev->duplex) 196 ctl_reg &= 197 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); 198 else 199 ctl_reg |= 200 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; 201 202 bp->duplex = phydev->duplex; 203 status_change = 1; 204 } 205 206 if (bp->speed != phydev->speed) { 207 status_change = 1; 208 switch (phydev->speed) { 209 case 1000: 210 mode_reg |= DNET_INTERNAL_MODE_GBITEN; 211 break; 212 case 100: 213 case 10: 214 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; 215 break; 216 default: 217 printk(KERN_WARNING 218 "%s: Ack! Speed (%d) is not " 219 "10/100/1000!\n", dev->name, 220 phydev->speed); 221 break; 222 } 223 bp->speed = phydev->speed; 224 } 225 } 226 227 if (phydev->link != bp->link) { 228 if (phydev->link) { 229 mode_reg |= 230 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); 231 } else { 232 mode_reg &= 233 ~(DNET_INTERNAL_MODE_RXEN | 234 DNET_INTERNAL_MODE_TXEN); 235 bp->speed = 0; 236 bp->duplex = -1; 237 } 238 bp->link = phydev->link; 239 240 status_change = 1; 241 } 242 243 if (status_change) { 244 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); 245 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); 246 } 247 248 spin_unlock_irqrestore(&bp->lock, flags); 249 250 if (status_change) { 251 if (phydev->link) 252 printk(KERN_INFO "%s: link up (%d/%s)\n", 253 dev->name, phydev->speed, 254 DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); 255 else 256 printk(KERN_INFO "%s: link down\n", dev->name); 257 } 258 } 259 260 static int dnet_mii_probe(struct net_device *dev) 261 { 262 struct dnet *bp = netdev_priv(dev); 263 struct phy_device *phydev = NULL; 264 int phy_addr; 265 266 /* find the first phy */ 267 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 268 if (bp->mii_bus->phy_map[phy_addr]) { 269 phydev = bp->mii_bus->phy_map[phy_addr]; 270 break; 271 } 272 } 273 274 if (!phydev) { 275 printk(KERN_ERR "%s: no PHY found\n", dev->name); 276 return -ENODEV; 277 } 278 279 /* TODO : add pin_irq */ 280 281 /* attach the mac to the phy */ 282 if (bp->capabilities & DNET_HAS_RMII) { 283 phydev = phy_connect(dev, dev_name(&phydev->dev), 284 &dnet_handle_link_change, 285 PHY_INTERFACE_MODE_RMII); 286 } else { 287 phydev = phy_connect(dev, dev_name(&phydev->dev), 288 &dnet_handle_link_change, 289 PHY_INTERFACE_MODE_MII); 290 } 291 292 if (IS_ERR(phydev)) { 293 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 294 return PTR_ERR(phydev); 295 } 296 297 /* mask with MAC supported features */ 298 if (bp->capabilities & DNET_HAS_GIGABIT) 299 phydev->supported &= PHY_GBIT_FEATURES; 300 else 301 phydev->supported &= PHY_BASIC_FEATURES; 302 303 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; 304 305 phydev->advertising = phydev->supported; 306 307 bp->link = 0; 308 bp->speed = 0; 309 bp->duplex = -1; 310 bp->phy_dev = phydev; 311 312 return 0; 313 } 314 315 static int dnet_mii_init(struct dnet *bp) 316 { 317 int err, i; 318 319 bp->mii_bus = mdiobus_alloc(); 320 if (bp->mii_bus == NULL) 321 return -ENOMEM; 322 323 bp->mii_bus->name = "dnet_mii_bus"; 324 bp->mii_bus->read = &dnet_mdio_read; 325 bp->mii_bus->write = &dnet_mdio_write; 326 bp->mii_bus->reset = &dnet_mdio_reset; 327 328 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 329 bp->pdev->name, bp->pdev->id); 330 331 bp->mii_bus->priv = bp; 332 333 bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 334 if (!bp->mii_bus->irq) { 335 err = -ENOMEM; 336 goto err_out; 337 } 338 339 for (i = 0; i < PHY_MAX_ADDR; i++) 340 bp->mii_bus->irq[i] = PHY_POLL; 341 342 if (mdiobus_register(bp->mii_bus)) { 343 err = -ENXIO; 344 goto err_out_free_mdio_irq; 345 } 346 347 if (dnet_mii_probe(bp->dev) != 0) { 348 err = -ENXIO; 349 goto err_out_unregister_bus; 350 } 351 352 return 0; 353 354 err_out_unregister_bus: 355 mdiobus_unregister(bp->mii_bus); 356 err_out_free_mdio_irq: 357 kfree(bp->mii_bus->irq); 358 err_out: 359 mdiobus_free(bp->mii_bus); 360 return err; 361 } 362 363 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */ 364 static int dnet_phy_marvell_fixup(struct phy_device *phydev) 365 { 366 return phy_write(phydev, 0x18, 0x4148); 367 } 368 369 static void dnet_update_stats(struct dnet *bp) 370 { 371 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; 372 u32 *p = &bp->hw_stats.rx_pkt_ignr; 373 u32 *end = &bp->hw_stats.rx_byte + 1; 374 375 WARN_ON((unsigned long)(end - p - 1) != 376 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4); 377 378 for (; p < end; p++, reg++) 379 *p += readl(reg); 380 381 reg = bp->regs + DNET_TX_UNICAST_CNT; 382 p = &bp->hw_stats.tx_unicast; 383 end = &bp->hw_stats.tx_byte + 1; 384 385 WARN_ON((unsigned long)(end - p - 1) != 386 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4); 387 388 for (; p < end; p++, reg++) 389 *p += readl(reg); 390 } 391 392 static int dnet_poll(struct napi_struct *napi, int budget) 393 { 394 struct dnet *bp = container_of(napi, struct dnet, napi); 395 struct net_device *dev = bp->dev; 396 int npackets = 0; 397 unsigned int pkt_len; 398 struct sk_buff *skb; 399 unsigned int *data_ptr; 400 u32 int_enable; 401 u32 cmd_word; 402 int i; 403 404 while (npackets < budget) { 405 /* 406 * break out of while loop if there are no more 407 * packets waiting 408 */ 409 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) { 410 napi_complete(napi); 411 int_enable = dnet_readl(bp, INTR_ENB); 412 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; 413 dnet_writel(bp, int_enable, INTR_ENB); 414 return 0; 415 } 416 417 cmd_word = dnet_readl(bp, RX_LEN_FIFO); 418 pkt_len = cmd_word & 0xFFFF; 419 420 if (cmd_word & 0xDF180000) 421 printk(KERN_ERR "%s packet receive error %x\n", 422 __func__, cmd_word); 423 424 skb = netdev_alloc_skb(dev, pkt_len + 5); 425 if (skb != NULL) { 426 /* Align IP on 16 byte boundaries */ 427 skb_reserve(skb, 2); 428 /* 429 * 'skb_put()' points to the start of sk_buff 430 * data area. 431 */ 432 data_ptr = (unsigned int *)skb_put(skb, pkt_len); 433 for (i = 0; i < (pkt_len + 3) >> 2; i++) 434 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO); 435 skb->protocol = eth_type_trans(skb, dev); 436 netif_receive_skb(skb); 437 npackets++; 438 } else 439 printk(KERN_NOTICE 440 "%s: No memory to allocate a sk_buff of " 441 "size %u.\n", dev->name, pkt_len); 442 } 443 444 budget -= npackets; 445 446 if (npackets < budget) { 447 /* We processed all packets available. Tell NAPI it can 448 * stop polling then re-enable rx interrupts */ 449 napi_complete(napi); 450 int_enable = dnet_readl(bp, INTR_ENB); 451 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; 452 dnet_writel(bp, int_enable, INTR_ENB); 453 return 0; 454 } 455 456 /* There are still packets waiting */ 457 return 1; 458 } 459 460 static irqreturn_t dnet_interrupt(int irq, void *dev_id) 461 { 462 struct net_device *dev = dev_id; 463 struct dnet *bp = netdev_priv(dev); 464 u32 int_src, int_enable, int_current; 465 unsigned long flags; 466 unsigned int handled = 0; 467 468 spin_lock_irqsave(&bp->lock, flags); 469 470 /* read and clear the DNET irq (clear on read) */ 471 int_src = dnet_readl(bp, INTR_SRC); 472 int_enable = dnet_readl(bp, INTR_ENB); 473 int_current = int_src & int_enable; 474 475 /* restart the queue if we had stopped it for TX fifo almost full */ 476 if (int_current & DNET_INTR_SRC_TX_FIFOAE) { 477 int_enable = dnet_readl(bp, INTR_ENB); 478 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE; 479 dnet_writel(bp, int_enable, INTR_ENB); 480 netif_wake_queue(dev); 481 handled = 1; 482 } 483 484 /* RX FIFO error checking */ 485 if (int_current & 486 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) { 487 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__, 488 dnet_readl(bp, RX_STATUS), int_current); 489 /* we can only flush the RX FIFOs */ 490 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL); 491 ndelay(500); 492 dnet_writel(bp, 0, SYS_CTL); 493 handled = 1; 494 } 495 496 /* TX FIFO error checking */ 497 if (int_current & 498 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) { 499 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__, 500 dnet_readl(bp, TX_STATUS), int_current); 501 /* we can only flush the TX FIFOs */ 502 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL); 503 ndelay(500); 504 dnet_writel(bp, 0, SYS_CTL); 505 handled = 1; 506 } 507 508 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) { 509 if (napi_schedule_prep(&bp->napi)) { 510 /* 511 * There's no point taking any more interrupts 512 * until we have processed the buffers 513 */ 514 /* Disable Rx interrupts and schedule NAPI poll */ 515 int_enable = dnet_readl(bp, INTR_ENB); 516 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF; 517 dnet_writel(bp, int_enable, INTR_ENB); 518 __napi_schedule(&bp->napi); 519 } 520 handled = 1; 521 } 522 523 if (!handled) 524 pr_debug("%s: irq %x remains\n", __func__, int_current); 525 526 spin_unlock_irqrestore(&bp->lock, flags); 527 528 return IRQ_RETVAL(handled); 529 } 530 531 #ifdef DEBUG 532 static inline void dnet_print_skb(struct sk_buff *skb) 533 { 534 int k; 535 printk(KERN_DEBUG PFX "data:"); 536 for (k = 0; k < skb->len; k++) 537 printk(" %02x", (unsigned int)skb->data[k]); 538 printk("\n"); 539 } 540 #else 541 #define dnet_print_skb(skb) do {} while (0) 542 #endif 543 544 static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev) 545 { 546 547 struct dnet *bp = netdev_priv(dev); 548 u32 tx_status, irq_enable; 549 unsigned int len, i, tx_cmd, wrsz; 550 unsigned long flags; 551 unsigned int *bufp; 552 553 tx_status = dnet_readl(bp, TX_STATUS); 554 555 pr_debug("start_xmit: len %u head %p data %p\n", 556 skb->len, skb->head, skb->data); 557 dnet_print_skb(skb); 558 559 /* frame size (words) */ 560 len = (skb->len + 3) >> 2; 561 562 spin_lock_irqsave(&bp->lock, flags); 563 564 tx_status = dnet_readl(bp, TX_STATUS); 565 566 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL); 567 wrsz = (u32) skb->len + 3; 568 wrsz += ((unsigned long) skb->data) & 0x3; 569 wrsz >>= 2; 570 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len; 571 572 /* check if there is enough room for the current frame */ 573 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) { 574 for (i = 0; i < wrsz; i++) 575 dnet_writel(bp, *bufp++, TX_DATA_FIFO); 576 577 /* 578 * inform MAC that a packet's written and ready to be 579 * shipped out 580 */ 581 dnet_writel(bp, tx_cmd, TX_LEN_FIFO); 582 } 583 584 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) { 585 netif_stop_queue(dev); 586 tx_status = dnet_readl(bp, INTR_SRC); 587 irq_enable = dnet_readl(bp, INTR_ENB); 588 irq_enable |= DNET_INTR_ENB_TX_FIFOAE; 589 dnet_writel(bp, irq_enable, INTR_ENB); 590 } 591 592 skb_tx_timestamp(skb); 593 594 /* free the buffer */ 595 dev_kfree_skb(skb); 596 597 spin_unlock_irqrestore(&bp->lock, flags); 598 599 return NETDEV_TX_OK; 600 } 601 602 static void dnet_reset_hw(struct dnet *bp) 603 { 604 /* put ts_mac in IDLE state i.e. disable rx/tx */ 605 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN); 606 607 /* 608 * RX FIFO almost full threshold: only cmd FIFO almost full is 609 * implemented for RX side 610 */ 611 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH); 612 /* 613 * TX FIFO almost empty threshold: only data FIFO almost empty 614 * is implemented for TX side 615 */ 616 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH); 617 618 /* flush rx/tx fifos */ 619 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, 620 SYS_CTL); 621 msleep(1); 622 dnet_writel(bp, 0, SYS_CTL); 623 } 624 625 static void dnet_init_hw(struct dnet *bp) 626 { 627 u32 config; 628 629 dnet_reset_hw(bp); 630 __dnet_set_hwaddr(bp); 631 632 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 633 634 if (bp->dev->flags & IFF_PROMISC) 635 /* Copy All Frames */ 636 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC; 637 if (!(bp->dev->flags & IFF_BROADCAST)) 638 /* No BroadCast */ 639 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST; 640 641 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | 642 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | 643 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | 644 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; 645 646 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config); 647 648 /* clear irq before enabling them */ 649 config = dnet_readl(bp, INTR_SRC); 650 651 /* enable RX/TX interrupt, recv packet ready interrupt */ 652 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY | 653 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR | 654 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL | 655 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM | 656 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB); 657 } 658 659 static int dnet_open(struct net_device *dev) 660 { 661 struct dnet *bp = netdev_priv(dev); 662 663 /* if the phy is not yet register, retry later */ 664 if (!bp->phy_dev) 665 return -EAGAIN; 666 667 napi_enable(&bp->napi); 668 dnet_init_hw(bp); 669 670 phy_start_aneg(bp->phy_dev); 671 672 /* schedule a link state check */ 673 phy_start(bp->phy_dev); 674 675 netif_start_queue(dev); 676 677 return 0; 678 } 679 680 static int dnet_close(struct net_device *dev) 681 { 682 struct dnet *bp = netdev_priv(dev); 683 684 netif_stop_queue(dev); 685 napi_disable(&bp->napi); 686 687 if (bp->phy_dev) 688 phy_stop(bp->phy_dev); 689 690 dnet_reset_hw(bp); 691 netif_carrier_off(dev); 692 693 return 0; 694 } 695 696 static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat) 697 { 698 pr_debug("%s\n", __func__); 699 pr_debug("----------------------------- RX statistics " 700 "-------------------------------\n"); 701 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr); 702 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err); 703 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm); 704 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm); 705 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol); 706 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err); 707 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt); 708 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm); 709 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm); 710 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast); 711 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast); 712 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag); 713 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink); 714 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib); 715 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd); 716 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte); 717 pr_debug("----------------------------- TX statistics " 718 "-------------------------------\n"); 719 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast); 720 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm); 721 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast); 722 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast); 723 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag); 724 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs); 725 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo); 726 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte); 727 } 728 729 static struct net_device_stats *dnet_get_stats(struct net_device *dev) 730 { 731 732 struct dnet *bp = netdev_priv(dev); 733 struct net_device_stats *nstat = &dev->stats; 734 struct dnet_stats *hwstat = &bp->hw_stats; 735 736 /* read stats from hardware */ 737 dnet_update_stats(bp); 738 739 /* Convert HW stats into netdevice stats */ 740 nstat->rx_errors = (hwstat->rx_len_chk_err + 741 hwstat->rx_lng_frm + hwstat->rx_shrt_frm + 742 /* ignore IGP violation error 743 hwstat->rx_ipg_viol + */ 744 hwstat->rx_crc_err + 745 hwstat->rx_pre_shrink + 746 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd); 747 nstat->tx_errors = hwstat->tx_bad_fcs; 748 nstat->rx_length_errors = (hwstat->rx_len_chk_err + 749 hwstat->rx_lng_frm + 750 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink); 751 nstat->rx_crc_errors = hwstat->rx_crc_err; 752 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib; 753 nstat->rx_packets = hwstat->rx_ok_pkt; 754 nstat->tx_packets = (hwstat->tx_unicast + 755 hwstat->tx_multicast + hwstat->tx_brdcast); 756 nstat->rx_bytes = hwstat->rx_byte; 757 nstat->tx_bytes = hwstat->tx_byte; 758 nstat->multicast = hwstat->rx_multicast; 759 nstat->rx_missed_errors = hwstat->rx_pkt_ignr; 760 761 dnet_print_pretty_hwstats(hwstat); 762 763 return nstat; 764 } 765 766 static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 767 { 768 struct dnet *bp = netdev_priv(dev); 769 struct phy_device *phydev = bp->phy_dev; 770 771 if (!phydev) 772 return -ENODEV; 773 774 return phy_ethtool_gset(phydev, cmd); 775 } 776 777 static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 778 { 779 struct dnet *bp = netdev_priv(dev); 780 struct phy_device *phydev = bp->phy_dev; 781 782 if (!phydev) 783 return -ENODEV; 784 785 return phy_ethtool_sset(phydev, cmd); 786 } 787 788 static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 789 { 790 struct dnet *bp = netdev_priv(dev); 791 struct phy_device *phydev = bp->phy_dev; 792 793 if (!netif_running(dev)) 794 return -EINVAL; 795 796 if (!phydev) 797 return -ENODEV; 798 799 return phy_mii_ioctl(phydev, rq, cmd); 800 } 801 802 static void dnet_get_drvinfo(struct net_device *dev, 803 struct ethtool_drvinfo *info) 804 { 805 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 806 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 807 strlcpy(info->bus_info, "0", sizeof(info->bus_info)); 808 } 809 810 static const struct ethtool_ops dnet_ethtool_ops = { 811 .get_settings = dnet_get_settings, 812 .set_settings = dnet_set_settings, 813 .get_drvinfo = dnet_get_drvinfo, 814 .get_link = ethtool_op_get_link, 815 .get_ts_info = ethtool_op_get_ts_info, 816 }; 817 818 static const struct net_device_ops dnet_netdev_ops = { 819 .ndo_open = dnet_open, 820 .ndo_stop = dnet_close, 821 .ndo_get_stats = dnet_get_stats, 822 .ndo_start_xmit = dnet_start_xmit, 823 .ndo_do_ioctl = dnet_ioctl, 824 .ndo_set_mac_address = eth_mac_addr, 825 .ndo_validate_addr = eth_validate_addr, 826 .ndo_change_mtu = eth_change_mtu, 827 }; 828 829 static int dnet_probe(struct platform_device *pdev) 830 { 831 struct resource *res; 832 struct net_device *dev; 833 struct dnet *bp; 834 struct phy_device *phydev; 835 int err = -ENXIO; 836 unsigned int mem_base, mem_size, irq; 837 838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 if (!res) { 840 dev_err(&pdev->dev, "no mmio resource defined\n"); 841 goto err_out; 842 } 843 mem_base = res->start; 844 mem_size = resource_size(res); 845 irq = platform_get_irq(pdev, 0); 846 847 if (!request_mem_region(mem_base, mem_size, DRV_NAME)) { 848 dev_err(&pdev->dev, "no memory region available\n"); 849 err = -EBUSY; 850 goto err_out; 851 } 852 853 err = -ENOMEM; 854 dev = alloc_etherdev(sizeof(*bp)); 855 if (!dev) 856 goto err_out_release_mem; 857 858 /* TODO: Actually, we have some interesting features... */ 859 dev->features |= 0; 860 861 bp = netdev_priv(dev); 862 bp->dev = dev; 863 864 platform_set_drvdata(pdev, dev); 865 SET_NETDEV_DEV(dev, &pdev->dev); 866 867 spin_lock_init(&bp->lock); 868 869 bp->regs = ioremap(mem_base, mem_size); 870 if (!bp->regs) { 871 dev_err(&pdev->dev, "failed to map registers, aborting.\n"); 872 err = -ENOMEM; 873 goto err_out_free_dev; 874 } 875 876 dev->irq = irq; 877 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev); 878 if (err) { 879 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", 880 irq, err); 881 goto err_out_iounmap; 882 } 883 884 dev->netdev_ops = &dnet_netdev_ops; 885 netif_napi_add(dev, &bp->napi, dnet_poll, 64); 886 dev->ethtool_ops = &dnet_ethtool_ops; 887 888 dev->base_addr = (unsigned long)bp->regs; 889 890 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK; 891 892 dnet_get_hwaddr(bp); 893 894 if (!is_valid_ether_addr(dev->dev_addr)) { 895 /* choose a random ethernet address */ 896 eth_hw_addr_random(dev); 897 __dnet_set_hwaddr(bp); 898 } 899 900 err = register_netdev(dev); 901 if (err) { 902 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 903 goto err_out_free_irq; 904 } 905 906 /* register the PHY board fixup (for Marvell 88E1111) */ 907 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0, 908 dnet_phy_marvell_fixup); 909 /* we can live without it, so just issue a warning */ 910 if (err) 911 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n"); 912 913 err = dnet_mii_init(bp); 914 if (err) 915 goto err_out_unregister_netdev; 916 917 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n", 918 bp->regs, mem_base, dev->irq, dev->dev_addr); 919 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n", 920 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ", 921 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ", 922 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", 923 (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); 924 phydev = bp->phy_dev; 925 dev_info(&pdev->dev, "attached PHY driver [%s] " 926 "(mii_bus:phy_addr=%s, irq=%d)\n", 927 phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 928 929 return 0; 930 931 err_out_unregister_netdev: 932 unregister_netdev(dev); 933 err_out_free_irq: 934 free_irq(dev->irq, dev); 935 err_out_iounmap: 936 iounmap(bp->regs); 937 err_out_free_dev: 938 free_netdev(dev); 939 err_out_release_mem: 940 release_mem_region(mem_base, mem_size); 941 err_out: 942 return err; 943 } 944 945 static int dnet_remove(struct platform_device *pdev) 946 { 947 948 struct net_device *dev; 949 struct dnet *bp; 950 951 dev = platform_get_drvdata(pdev); 952 953 if (dev) { 954 bp = netdev_priv(dev); 955 if (bp->phy_dev) 956 phy_disconnect(bp->phy_dev); 957 mdiobus_unregister(bp->mii_bus); 958 kfree(bp->mii_bus->irq); 959 mdiobus_free(bp->mii_bus); 960 unregister_netdev(dev); 961 free_irq(dev->irq, dev); 962 iounmap(bp->regs); 963 free_netdev(dev); 964 } 965 966 return 0; 967 } 968 969 static struct platform_driver dnet_driver = { 970 .probe = dnet_probe, 971 .remove = dnet_remove, 972 .driver = { 973 .name = "dnet", 974 }, 975 }; 976 977 module_platform_driver(dnet_driver); 978 979 MODULE_LICENSE("GPL"); 980 MODULE_DESCRIPTION("Dave DNET Ethernet driver"); 981 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, " 982 "Matteo Vit <matteo.vit@dave.eu>"); 983