1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Keyur Chudgar <kchudgar@apm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "xgene_enet_main.h" 22 #include "xgene_enet_hw.h" 23 #include "xgene_enet_sgmac.h" 24 #include "xgene_enet_xgmac.h" 25 26 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) 27 { 28 iowrite32(val, p->eth_csr_addr + offset); 29 } 30 31 static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset, 32 u32 val) 33 { 34 iowrite32(val, p->base_addr + offset); 35 } 36 37 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p, 38 u32 offset, u32 val) 39 { 40 iowrite32(val, p->eth_ring_if_addr + offset); 41 } 42 43 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p, 44 u32 offset, u32 val) 45 { 46 iowrite32(val, p->eth_diag_csr_addr + offset); 47 } 48 49 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, 50 u32 offset, u32 val) 51 { 52 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; 53 54 iowrite32(val, addr); 55 } 56 57 static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl, 58 u32 wr_addr, u32 wr_data) 59 { 60 int i; 61 62 iowrite32(wr_addr, ctl->addr); 63 iowrite32(wr_data, ctl->ctl); 64 iowrite32(XGENE_ENET_WR_CMD, ctl->cmd); 65 66 /* wait for write command to complete */ 67 for (i = 0; i < 10; i++) { 68 if (ioread32(ctl->cmd_done)) { 69 iowrite32(0, ctl->cmd); 70 return true; 71 } 72 udelay(1); 73 } 74 75 return false; 76 } 77 78 static void xgene_enet_wr_mac(struct xgene_enet_pdata *p, 79 u32 wr_addr, u32 wr_data) 80 { 81 struct xgene_indirect_ctl ctl = { 82 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, 83 .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, 84 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, 85 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET 86 }; 87 88 if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data)) 89 netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr); 90 } 91 92 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) 93 { 94 return ioread32(p->eth_csr_addr + offset); 95 } 96 97 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) 98 { 99 return ioread32(p->eth_diag_csr_addr + offset); 100 } 101 102 static u32 xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *p, u32 offset) 103 { 104 return ioread32(p->mcx_mac_csr_addr + offset); 105 } 106 107 static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr) 108 { 109 u32 rd_data; 110 int i; 111 112 iowrite32(rd_addr, ctl->addr); 113 iowrite32(XGENE_ENET_RD_CMD, ctl->cmd); 114 115 /* wait for read command to complete */ 116 for (i = 0; i < 10; i++) { 117 if (ioread32(ctl->cmd_done)) { 118 rd_data = ioread32(ctl->ctl); 119 iowrite32(0, ctl->cmd); 120 121 return rd_data; 122 } 123 udelay(1); 124 } 125 126 pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr); 127 128 return 0; 129 } 130 131 static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr) 132 { 133 struct xgene_indirect_ctl ctl = { 134 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, 135 .ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET, 136 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, 137 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET 138 }; 139 140 return xgene_enet_rd_indirect(&ctl, rd_addr); 141 } 142 143 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) 144 { 145 struct net_device *ndev = p->ndev; 146 u32 data, shutdown; 147 int i = 0; 148 149 shutdown = xgene_enet_rd_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR); 150 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); 151 152 if (!shutdown && data == ~0U) { 153 netdev_dbg(ndev, "+ ecc_init done, skipping\n"); 154 return 0; 155 } 156 157 xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); 158 do { 159 usleep_range(100, 110); 160 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); 161 if (data == ~0U) 162 return 0; 163 } while (++i < 10); 164 165 netdev_err(ndev, "Failed to release memory from shutdown\n"); 166 return -ENODEV; 167 } 168 169 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) 170 { 171 u32 val; 172 173 val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0; 174 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); 175 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); 176 } 177 178 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, 179 u32 reg, u16 data) 180 { 181 u32 addr, wr_data, done; 182 int i; 183 184 addr = PHY_ADDR(phy_id) | REG_ADDR(reg); 185 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); 186 187 wr_data = PHY_CONTROL(data); 188 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); 189 190 for (i = 0; i < 10; i++) { 191 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); 192 if (!(done & BUSY_MASK)) 193 return; 194 usleep_range(10, 20); 195 } 196 197 netdev_err(p->ndev, "MII_MGMT write failed\n"); 198 } 199 200 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) 201 { 202 u32 addr, data, done; 203 int i; 204 205 addr = PHY_ADDR(phy_id) | REG_ADDR(reg); 206 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); 207 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); 208 209 for (i = 0; i < 10; i++) { 210 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); 211 if (!(done & BUSY_MASK)) { 212 data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); 213 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); 214 215 return data; 216 } 217 usleep_range(10, 20); 218 } 219 220 netdev_err(p->ndev, "MII_MGMT read failed\n"); 221 222 return 0; 223 } 224 225 static void xgene_sgmac_reset(struct xgene_enet_pdata *p) 226 { 227 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); 228 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); 229 } 230 231 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) 232 { 233 u32 addr0, addr1; 234 u8 *dev_addr = p->ndev->dev_addr; 235 236 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 237 (dev_addr[1] << 8) | dev_addr[0]; 238 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); 239 240 addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); 241 addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16); 242 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); 243 } 244 245 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p) 246 { 247 u32 data; 248 249 data = xgene_mii_phy_read(p, INT_PHY_ADDR, 250 SGMII_BASE_PAGE_ABILITY_ADDR >> 2); 251 252 if (LINK_SPEED(data) == PHY_SPEED_1000) 253 p->phy_speed = SPEED_1000; 254 else if (LINK_SPEED(data) == PHY_SPEED_100) 255 p->phy_speed = SPEED_100; 256 else 257 p->phy_speed = SPEED_10; 258 259 return data & LINK_UP; 260 } 261 262 static void xgene_sgmii_configure(struct xgene_enet_pdata *p) 263 { 264 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 265 0x8000); 266 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x9000); 267 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); 268 } 269 270 static void xgene_sgmii_tbi_control_reset(struct xgene_enet_pdata *p) 271 { 272 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 273 0x8000); 274 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); 275 } 276 277 static void xgene_sgmii_reset(struct xgene_enet_pdata *p) 278 { 279 u32 value; 280 281 if (p->phy_speed == SPEED_UNKNOWN) 282 return; 283 284 value = xgene_mii_phy_read(p, INT_PHY_ADDR, 285 SGMII_BASE_PAGE_ABILITY_ADDR >> 2); 286 if (!(value & LINK_UP)) 287 xgene_sgmii_tbi_control_reset(p); 288 } 289 290 static void xgene_sgmac_set_speed(struct xgene_enet_pdata *p) 291 { 292 u32 icm0_addr, icm2_addr, debug_addr; 293 u32 icm0, icm2, intf_ctl; 294 u32 mc2, value; 295 296 xgene_sgmii_reset(p); 297 298 if (p->enet_id == XGENE_ENET1) { 299 icm0_addr = ICM_CONFIG0_REG_0_ADDR + p->port_id * OFFSET_8; 300 icm2_addr = ICM_CONFIG2_REG_0_ADDR + p->port_id * OFFSET_4; 301 debug_addr = DEBUG_REG_ADDR; 302 } else { 303 icm0_addr = XG_MCX_ICM_CONFIG0_REG_0_ADDR; 304 icm2_addr = XG_MCX_ICM_CONFIG2_REG_0_ADDR; 305 debug_addr = XG_DEBUG_REG_ADDR; 306 } 307 308 icm0 = xgene_enet_rd_mcx_csr(p, icm0_addr); 309 icm2 = xgene_enet_rd_mcx_csr(p, icm2_addr); 310 mc2 = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); 311 intf_ctl = xgene_enet_rd_mac(p, INTERFACE_CONTROL_ADDR); 312 313 switch (p->phy_speed) { 314 case SPEED_10: 315 ENET_INTERFACE_MODE2_SET(&mc2, 1); 316 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE); 317 CFG_MACMODE_SET(&icm0, 0); 318 CFG_WAITASYNCRD_SET(&icm2, 500); 319 break; 320 case SPEED_100: 321 ENET_INTERFACE_MODE2_SET(&mc2, 1); 322 intf_ctl &= ~ENET_GHD_MODE; 323 intf_ctl |= ENET_LHD_MODE; 324 CFG_MACMODE_SET(&icm0, 1); 325 CFG_WAITASYNCRD_SET(&icm2, 80); 326 break; 327 default: 328 ENET_INTERFACE_MODE2_SET(&mc2, 2); 329 intf_ctl &= ~ENET_LHD_MODE; 330 intf_ctl |= ENET_GHD_MODE; 331 CFG_MACMODE_SET(&icm0, 2); 332 CFG_WAITASYNCRD_SET(&icm2, 16); 333 value = xgene_enet_rd_csr(p, debug_addr); 334 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX; 335 xgene_enet_wr_csr(p, debug_addr, value); 336 break; 337 } 338 339 mc2 |= FULL_DUPLEX2 | PAD_CRC; 340 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2); 341 xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, intf_ctl); 342 xgene_enet_wr_mcx_csr(p, icm0_addr, icm0); 343 xgene_enet_wr_mcx_csr(p, icm2_addr, icm2); 344 } 345 346 static void xgene_sgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size) 347 { 348 xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size); 349 } 350 351 static void xgene_sgmii_enable_autoneg(struct xgene_enet_pdata *p) 352 { 353 u32 data, loop = 10; 354 355 xgene_sgmii_configure(p); 356 357 while (loop--) { 358 data = xgene_mii_phy_read(p, INT_PHY_ADDR, 359 SGMII_STATUS_ADDR >> 2); 360 if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS)) 361 break; 362 usleep_range(1000, 2000); 363 } 364 if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS)) 365 netdev_err(p->ndev, "Auto-negotiation failed\n"); 366 } 367 368 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) 369 { 370 u32 data; 371 372 data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); 373 374 if (set) 375 data |= bits; 376 else 377 data &= ~bits; 378 379 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); 380 } 381 382 static void xgene_sgmac_flowctl_tx(struct xgene_enet_pdata *p, bool enable) 383 { 384 xgene_sgmac_rxtx(p, TX_FLOW_EN, enable); 385 386 p->mac_ops->enable_tx_pause(p, enable); 387 } 388 389 static void xgene_sgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable) 390 { 391 xgene_sgmac_rxtx(pdata, RX_FLOW_EN, enable); 392 } 393 394 static void xgene_sgmac_init(struct xgene_enet_pdata *p) 395 { 396 u32 pause_thres_reg, pause_off_thres_reg; 397 u32 enet_spare_cfg_reg, rsif_config_reg; 398 u32 cfg_bypass_reg, rx_dv_gate_reg; 399 u32 data, data1, data2, offset; 400 u32 multi_dpf_reg; 401 402 if (!(p->enet_id == XGENE_ENET2 && p->mdio_driver)) 403 xgene_sgmac_reset(p); 404 405 xgene_sgmii_enable_autoneg(p); 406 xgene_sgmac_set_speed(p); 407 xgene_sgmac_set_mac_addr(p); 408 409 if (p->enet_id == XGENE_ENET1) { 410 enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR; 411 rsif_config_reg = RSIF_CONFIG_REG_ADDR; 412 cfg_bypass_reg = CFG_BYPASS_ADDR; 413 offset = p->port_id * OFFSET_4; 414 rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR + offset; 415 } else { 416 enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR; 417 rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR; 418 cfg_bypass_reg = XG_CFG_BYPASS_ADDR; 419 rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR; 420 } 421 422 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); 423 data |= MPA_IDLE_WITH_QMI_EMPTY; 424 xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); 425 426 /* Adjust MDC clock frequency */ 427 data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); 428 MGMT_CLOCK_SEL_SET(&data, 7); 429 xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); 430 431 /* Enable drop if bufpool not available */ 432 data = xgene_enet_rd_csr(p, rsif_config_reg); 433 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; 434 xgene_enet_wr_csr(p, rsif_config_reg, data); 435 436 /* Configure HW pause frame generation */ 437 multi_dpf_reg = (p->enet_id == XGENE_ENET1) ? CSR_MULTI_DPF0_ADDR : 438 XG_MCX_MULTI_DPF0_ADDR; 439 data = xgene_enet_rd_mcx_csr(p, multi_dpf_reg); 440 data = (DEF_QUANTA << 16) | (data & 0xffff); 441 xgene_enet_wr_mcx_csr(p, multi_dpf_reg, data); 442 443 if (p->enet_id != XGENE_ENET1) { 444 data = xgene_enet_rd_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR); 445 data = (NORM_PAUSE_OPCODE << 16) | (data & 0xFFFF); 446 xgene_enet_wr_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR, data); 447 } 448 449 pause_thres_reg = (p->enet_id == XGENE_ENET1) ? RXBUF_PAUSE_THRESH : 450 XG_RXBUF_PAUSE_THRESH; 451 pause_off_thres_reg = (p->enet_id == XGENE_ENET1) ? 452 RXBUF_PAUSE_OFF_THRESH : 0; 453 454 if (p->enet_id == XGENE_ENET1) { 455 data1 = xgene_enet_rd_csr(p, pause_thres_reg); 456 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); 457 458 if (!(p->port_id % 2)) { 459 data1 = (data1 & 0xffff0000) | DEF_PAUSE_THRES; 460 data2 = (data2 & 0xffff0000) | DEF_PAUSE_OFF_THRES; 461 } else { 462 data1 = (data1 & 0xffff) | (DEF_PAUSE_THRES << 16); 463 data2 = (data2 & 0xffff) | (DEF_PAUSE_OFF_THRES << 16); 464 } 465 466 xgene_enet_wr_csr(p, pause_thres_reg, data1); 467 xgene_enet_wr_csr(p, pause_off_thres_reg, data2); 468 } else { 469 data = (DEF_PAUSE_OFF_THRES << 16) | DEF_PAUSE_THRES; 470 xgene_enet_wr_csr(p, pause_thres_reg, data); 471 } 472 473 xgene_sgmac_flowctl_tx(p, p->tx_pause); 474 xgene_sgmac_flowctl_rx(p, p->rx_pause); 475 476 /* Bypass traffic gating */ 477 xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); 478 xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); 479 xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg, RESUME_RX0); 480 } 481 482 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p) 483 { 484 xgene_sgmac_rxtx(p, RX_EN, true); 485 } 486 487 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p) 488 { 489 xgene_sgmac_rxtx(p, TX_EN, true); 490 } 491 492 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p) 493 { 494 xgene_sgmac_rxtx(p, RX_EN, false); 495 } 496 497 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p) 498 { 499 xgene_sgmac_rxtx(p, TX_EN, false); 500 } 501 502 static int xgene_enet_reset(struct xgene_enet_pdata *p) 503 { 504 struct device *dev = &p->pdev->dev; 505 506 if (!xgene_ring_mgr_init(p)) 507 return -ENODEV; 508 509 if (p->mdio_driver && p->enet_id == XGENE_ENET2) { 510 xgene_enet_config_ring_if_assoc(p); 511 return 0; 512 } 513 514 if (p->enet_id == XGENE_ENET2) 515 xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN); 516 517 if (dev->of_node) { 518 if (!IS_ERR(p->clk)) { 519 clk_prepare_enable(p->clk); 520 udelay(5); 521 clk_disable_unprepare(p->clk); 522 udelay(5); 523 clk_prepare_enable(p->clk); 524 udelay(5); 525 } 526 } else { 527 #ifdef CONFIG_ACPI 528 if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_RST")) 529 acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev), 530 "_RST", NULL, NULL); 531 else if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_INI")) 532 acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev), 533 "_INI", NULL, NULL); 534 #endif 535 } 536 537 if (!p->port_id) { 538 xgene_enet_ecc_init(p); 539 xgene_enet_config_ring_if_assoc(p); 540 } 541 542 return 0; 543 } 544 545 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, 546 u32 dst_ring_num, u16 bufpool_id, 547 u16 nxtbufpool_id) 548 { 549 u32 cle_bypass_reg0, cle_bypass_reg1; 550 u32 offset = p->port_id * MAC_OFFSET; 551 u32 data, fpsel, nxtfpsel; 552 553 if (p->enet_id == XGENE_ENET1) { 554 cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR; 555 cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR; 556 } else { 557 cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR; 558 cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR; 559 } 560 561 data = CFG_CLE_BYPASS_EN0; 562 xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); 563 564 fpsel = xgene_enet_get_fpsel(bufpool_id); 565 nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id); 566 data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel) | 567 CFG_CLE_NXTFPSEL0(nxtfpsel); 568 xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data); 569 } 570 571 static void xgene_enet_clear(struct xgene_enet_pdata *pdata, 572 struct xgene_enet_desc_ring *ring) 573 { 574 u32 addr, data; 575 576 if (xgene_enet_is_bufpool(ring->id)) { 577 addr = ENET_CFGSSQMIFPRESET_ADDR; 578 data = BIT(xgene_enet_get_fpsel(ring->id)); 579 } else { 580 addr = ENET_CFGSSQMIWQRESET_ADDR; 581 data = BIT(xgene_enet_ring_bufnum(ring->id)); 582 } 583 584 xgene_enet_wr_ring_if(pdata, addr, data); 585 } 586 587 static void xgene_enet_shutdown(struct xgene_enet_pdata *p) 588 { 589 struct device *dev = &p->pdev->dev; 590 struct xgene_enet_desc_ring *ring; 591 u32 pb; 592 int i; 593 594 pb = 0; 595 for (i = 0; i < p->rxq_cnt; i++) { 596 ring = p->rx_ring[i]->buf_pool; 597 pb |= BIT(xgene_enet_get_fpsel(ring->id)); 598 ring = p->rx_ring[i]->page_pool; 599 if (ring) 600 pb |= BIT(xgene_enet_get_fpsel(ring->id)); 601 } 602 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb); 603 604 pb = 0; 605 for (i = 0; i < p->txq_cnt; i++) { 606 ring = p->tx_ring[i]; 607 pb |= BIT(xgene_enet_ring_bufnum(ring->id)); 608 } 609 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQRESET_ADDR, pb); 610 611 if (dev->of_node) { 612 if (!IS_ERR(p->clk)) 613 clk_disable_unprepare(p->clk); 614 } 615 } 616 617 static void xgene_enet_link_state(struct work_struct *work) 618 { 619 struct xgene_enet_pdata *p = container_of(to_delayed_work(work), 620 struct xgene_enet_pdata, link_work); 621 struct net_device *ndev = p->ndev; 622 u32 link, poll_interval; 623 624 link = xgene_enet_link_status(p); 625 if (link) { 626 if (!netif_carrier_ok(ndev)) { 627 netif_carrier_on(ndev); 628 xgene_sgmac_set_speed(p); 629 xgene_sgmac_rx_enable(p); 630 xgene_sgmac_tx_enable(p); 631 netdev_info(ndev, "Link is Up - %dMbps\n", 632 p->phy_speed); 633 } 634 poll_interval = PHY_POLL_LINK_ON; 635 } else { 636 if (netif_carrier_ok(ndev)) { 637 xgene_sgmac_rx_disable(p); 638 xgene_sgmac_tx_disable(p); 639 netif_carrier_off(ndev); 640 netdev_info(ndev, "Link is Down\n"); 641 } 642 poll_interval = PHY_POLL_LINK_OFF; 643 } 644 645 schedule_delayed_work(&p->link_work, poll_interval); 646 } 647 648 static void xgene_sgmac_enable_tx_pause(struct xgene_enet_pdata *p, bool enable) 649 { 650 u32 data, ecm_cfg_addr; 651 652 if (p->enet_id == XGENE_ENET1) { 653 ecm_cfg_addr = (!(p->port_id % 2)) ? CSR_ECM_CFG_0_ADDR : 654 CSR_ECM_CFG_1_ADDR; 655 } else { 656 ecm_cfg_addr = XG_MCX_ECM_CFG_0_ADDR; 657 } 658 659 data = xgene_enet_rd_mcx_csr(p, ecm_cfg_addr); 660 if (enable) 661 data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN; 662 else 663 data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN); 664 xgene_enet_wr_mcx_csr(p, ecm_cfg_addr, data); 665 } 666 667 const struct xgene_mac_ops xgene_sgmac_ops = { 668 .init = xgene_sgmac_init, 669 .reset = xgene_sgmac_reset, 670 .rx_enable = xgene_sgmac_rx_enable, 671 .tx_enable = xgene_sgmac_tx_enable, 672 .rx_disable = xgene_sgmac_rx_disable, 673 .tx_disable = xgene_sgmac_tx_disable, 674 .set_speed = xgene_sgmac_set_speed, 675 .set_mac_addr = xgene_sgmac_set_mac_addr, 676 .set_framesize = xgene_sgmac_set_frame_size, 677 .link_state = xgene_enet_link_state, 678 .enable_tx_pause = xgene_sgmac_enable_tx_pause, 679 .flowctl_tx = xgene_sgmac_flowctl_tx, 680 .flowctl_rx = xgene_sgmac_flowctl_rx 681 }; 682 683 const struct xgene_port_ops xgene_sgport_ops = { 684 .reset = xgene_enet_reset, 685 .clear = xgene_enet_clear, 686 .cle_bypass = xgene_enet_cle_bypass, 687 .shutdown = xgene_enet_shutdown 688 }; 689