1 /* Altera TSE SGDMA and MSGDMA Linux driver 2 * Copyright (C) 2014 Altera Corporation. All rights reserved 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ALTERA_SGDMAHW_H__ 18 #define __ALTERA_SGDMAHW_H__ 19 20 /* SGDMA descriptor structure */ 21 struct sgdma_descrip { 22 u32 raddr; /* address of data to be read */ 23 u32 pad1; 24 u32 waddr; 25 u32 pad2; 26 u32 next; 27 u32 pad3; 28 u16 bytes; 29 u8 rburst; 30 u8 wburst; 31 u16 bytes_xferred; /* 16 bits, bytes xferred */ 32 33 /* bit 0: error 34 * bit 1: length error 35 * bit 2: crc error 36 * bit 3: truncated error 37 * bit 4: phy error 38 * bit 5: collision error 39 * bit 6: reserved 40 * bit 7: status eop for recv case 41 */ 42 u8 status; 43 44 /* bit 0: eop 45 * bit 1: read_fixed 46 * bit 2: write fixed 47 * bits 3,4,5,6: Channel (always 0) 48 * bit 7: hardware owned 49 */ 50 u8 control; 51 } __packed; 52 53 #define SGDMA_DESC_LEN sizeof(struct sgdma_descrip) 54 55 #define SGDMA_STATUS_ERR BIT(0) 56 #define SGDMA_STATUS_LENGTH_ERR BIT(1) 57 #define SGDMA_STATUS_CRC_ERR BIT(2) 58 #define SGDMA_STATUS_TRUNC_ERR BIT(3) 59 #define SGDMA_STATUS_PHY_ERR BIT(4) 60 #define SGDMA_STATUS_COLL_ERR BIT(5) 61 #define SGDMA_STATUS_EOP BIT(7) 62 63 #define SGDMA_CONTROL_EOP BIT(0) 64 #define SGDMA_CONTROL_RD_FIXED BIT(1) 65 #define SGDMA_CONTROL_WR_FIXED BIT(2) 66 67 /* Channel is always 0, so just zero initialize it */ 68 69 #define SGDMA_CONTROL_HW_OWNED BIT(7) 70 71 /* SGDMA register space */ 72 struct sgdma_csr { 73 /* bit 0: error 74 * bit 1: eop 75 * bit 2: descriptor completed 76 * bit 3: chain completed 77 * bit 4: busy 78 * remainder reserved 79 */ 80 u32 status; 81 u32 pad1[3]; 82 83 /* bit 0: interrupt on error 84 * bit 1: interrupt on eop 85 * bit 2: interrupt after every descriptor 86 * bit 3: interrupt after last descrip in a chain 87 * bit 4: global interrupt enable 88 * bit 5: starts descriptor processing 89 * bit 6: stop core on dma error 90 * bit 7: interrupt on max descriptors 91 * bits 8-15: max descriptors to generate interrupt 92 * bit 16: Software reset 93 * bit 17: clears owned by hardware if 0, does not clear otherwise 94 * bit 18: enables descriptor polling mode 95 * bit 19-26: clocks before polling again 96 * bit 27-30: reserved 97 * bit 31: clear interrupt 98 */ 99 u32 control; 100 u32 pad2[3]; 101 u32 next_descrip; 102 u32 pad3[3]; 103 }; 104 105 #define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a)) 106 #define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a)) 107 108 #define SGDMA_STSREG_ERR BIT(0) /* Error */ 109 #define SGDMA_STSREG_EOP BIT(1) /* EOP */ 110 #define SGDMA_STSREG_DESCRIP BIT(2) /* Descriptor completed */ 111 #define SGDMA_STSREG_CHAIN BIT(3) /* Chain completed */ 112 #define SGDMA_STSREG_BUSY BIT(4) /* Controller busy */ 113 114 #define SGDMA_CTRLREG_IOE BIT(0) /* Interrupt on error */ 115 #define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */ 116 #define SGDMA_CTRLREG_IDESCRIP BIT(2) /* Interrupt after every descriptor */ 117 #define SGDMA_CTRLREG_ILASTD BIT(3) /* Interrupt after last descriptor */ 118 #define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */ 119 #define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */ 120 #define SGDMA_CTRLREG_STOPERR BIT(6) /* stop on dma error */ 121 #define SGDMA_CTRLREG_INTMAX BIT(7) /* Interrupt on max descriptors */ 122 #define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */ 123 #define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */ 124 #define SGDMA_CTRLREG_POLL BIT(18)/* enables descriptor polling mode */ 125 #define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */ 126 127 #endif /* __ALTERA_SGDMAHW_H__ */ 128