1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phylink.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/gpio/driver.h> 22 #include <net/dsa.h> 23 24 #include "mt7530.h" 25 26 /* String, offset, and register size in bytes if different from 4 bytes */ 27 static const struct mt7530_mib_desc mt7530_mib[] = { 28 MIB_DESC(1, 0x00, "TxDrop"), 29 MIB_DESC(1, 0x04, "TxCrcErr"), 30 MIB_DESC(1, 0x08, "TxUnicast"), 31 MIB_DESC(1, 0x0c, "TxMulticast"), 32 MIB_DESC(1, 0x10, "TxBroadcast"), 33 MIB_DESC(1, 0x14, "TxCollision"), 34 MIB_DESC(1, 0x18, "TxSingleCollision"), 35 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 36 MIB_DESC(1, 0x20, "TxDeferred"), 37 MIB_DESC(1, 0x24, "TxLateCollision"), 38 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 39 MIB_DESC(1, 0x2c, "TxPause"), 40 MIB_DESC(1, 0x30, "TxPktSz64"), 41 MIB_DESC(1, 0x34, "TxPktSz65To127"), 42 MIB_DESC(1, 0x38, "TxPktSz128To255"), 43 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 44 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 45 MIB_DESC(1, 0x44, "Tx1024ToMax"), 46 MIB_DESC(2, 0x48, "TxBytes"), 47 MIB_DESC(1, 0x60, "RxDrop"), 48 MIB_DESC(1, 0x64, "RxFiltering"), 49 MIB_DESC(1, 0x6c, "RxMulticast"), 50 MIB_DESC(1, 0x70, "RxBroadcast"), 51 MIB_DESC(1, 0x74, "RxAlignErr"), 52 MIB_DESC(1, 0x78, "RxCrcErr"), 53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 54 MIB_DESC(1, 0x80, "RxFragErr"), 55 MIB_DESC(1, 0x84, "RxOverSzErr"), 56 MIB_DESC(1, 0x88, "RxJabberErr"), 57 MIB_DESC(1, 0x8c, "RxPause"), 58 MIB_DESC(1, 0x90, "RxPktSz64"), 59 MIB_DESC(1, 0x94, "RxPktSz65To127"), 60 MIB_DESC(1, 0x98, "RxPktSz128To255"), 61 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 64 MIB_DESC(2, 0xa8, "RxBytes"), 65 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 66 MIB_DESC(1, 0xb4, "RxIngressDrop"), 67 MIB_DESC(1, 0xb8, "RxArlDrop"), 68 }; 69 70 /* Since phy_device has not yet been created and 71 * phy_{read,write}_mmd_indirect is not available, we provide our own 72 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 73 * to complete this function. 74 */ 75 static int 76 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 77 { 78 struct mii_bus *bus = priv->bus; 79 int value, ret; 80 81 /* Write the desired MMD Devad */ 82 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 83 if (ret < 0) 84 goto err; 85 86 /* Write the desired MMD register address */ 87 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 88 if (ret < 0) 89 goto err; 90 91 /* Select the Function : DATA with no post increment */ 92 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 93 if (ret < 0) 94 goto err; 95 96 /* Read the content of the MMD's selected register */ 97 value = bus->read(bus, 0, MII_MMD_DATA); 98 99 return value; 100 err: 101 dev_err(&bus->dev, "failed to read mmd register\n"); 102 103 return ret; 104 } 105 106 static int 107 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 108 int devad, u32 data) 109 { 110 struct mii_bus *bus = priv->bus; 111 int ret; 112 113 /* Write the desired MMD Devad */ 114 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 115 if (ret < 0) 116 goto err; 117 118 /* Write the desired MMD register address */ 119 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 120 if (ret < 0) 121 goto err; 122 123 /* Select the Function : DATA with no post increment */ 124 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 125 if (ret < 0) 126 goto err; 127 128 /* Write the data into MMD's selected register */ 129 ret = bus->write(bus, 0, MII_MMD_DATA, data); 130 err: 131 if (ret < 0) 132 dev_err(&bus->dev, 133 "failed to write mmd register\n"); 134 return ret; 135 } 136 137 static void 138 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 139 { 140 struct mii_bus *bus = priv->bus; 141 142 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 143 144 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 145 146 mutex_unlock(&bus->mdio_lock); 147 } 148 149 static void 150 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 151 { 152 struct mii_bus *bus = priv->bus; 153 u32 val; 154 155 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 156 157 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 158 val &= ~mask; 159 val |= set; 160 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 161 162 mutex_unlock(&bus->mdio_lock); 163 } 164 165 static void 166 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 167 { 168 core_rmw(priv, reg, 0, val); 169 } 170 171 static void 172 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 173 { 174 core_rmw(priv, reg, val, 0); 175 } 176 177 static int 178 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 179 { 180 struct mii_bus *bus = priv->bus; 181 u16 page, r, lo, hi; 182 int ret; 183 184 page = (reg >> 6) & 0x3ff; 185 r = (reg >> 2) & 0xf; 186 lo = val & 0xffff; 187 hi = val >> 16; 188 189 /* MT7530 uses 31 as the pseudo port */ 190 ret = bus->write(bus, 0x1f, 0x1f, page); 191 if (ret < 0) 192 goto err; 193 194 ret = bus->write(bus, 0x1f, r, lo); 195 if (ret < 0) 196 goto err; 197 198 ret = bus->write(bus, 0x1f, 0x10, hi); 199 err: 200 if (ret < 0) 201 dev_err(&bus->dev, 202 "failed to write mt7530 register\n"); 203 return ret; 204 } 205 206 static u32 207 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 208 { 209 struct mii_bus *bus = priv->bus; 210 u16 page, r, lo, hi; 211 int ret; 212 213 page = (reg >> 6) & 0x3ff; 214 r = (reg >> 2) & 0xf; 215 216 /* MT7530 uses 31 as the pseudo port */ 217 ret = bus->write(bus, 0x1f, 0x1f, page); 218 if (ret < 0) { 219 dev_err(&bus->dev, 220 "failed to read mt7530 register\n"); 221 return ret; 222 } 223 224 lo = bus->read(bus, 0x1f, r); 225 hi = bus->read(bus, 0x1f, 0x10); 226 227 return (hi << 16) | (lo & 0xffff); 228 } 229 230 static void 231 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 232 { 233 struct mii_bus *bus = priv->bus; 234 235 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 236 237 mt7530_mii_write(priv, reg, val); 238 239 mutex_unlock(&bus->mdio_lock); 240 } 241 242 static u32 243 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 244 { 245 return mt7530_mii_read(p->priv, p->reg); 246 } 247 248 static u32 249 _mt7530_read(struct mt7530_dummy_poll *p) 250 { 251 struct mii_bus *bus = p->priv->bus; 252 u32 val; 253 254 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 255 256 val = mt7530_mii_read(p->priv, p->reg); 257 258 mutex_unlock(&bus->mdio_lock); 259 260 return val; 261 } 262 263 static u32 264 mt7530_read(struct mt7530_priv *priv, u32 reg) 265 { 266 struct mt7530_dummy_poll p; 267 268 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 269 return _mt7530_read(&p); 270 } 271 272 static void 273 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 274 u32 mask, u32 set) 275 { 276 struct mii_bus *bus = priv->bus; 277 u32 val; 278 279 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 280 281 val = mt7530_mii_read(priv, reg); 282 val &= ~mask; 283 val |= set; 284 mt7530_mii_write(priv, reg, val); 285 286 mutex_unlock(&bus->mdio_lock); 287 } 288 289 static void 290 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 291 { 292 mt7530_rmw(priv, reg, 0, val); 293 } 294 295 static void 296 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 297 { 298 mt7530_rmw(priv, reg, val, 0); 299 } 300 301 static int 302 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 303 { 304 u32 val; 305 int ret; 306 struct mt7530_dummy_poll p; 307 308 /* Set the command operating upon the MAC address entries */ 309 val = ATC_BUSY | ATC_MAT(0) | cmd; 310 mt7530_write(priv, MT7530_ATC, val); 311 312 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 313 ret = readx_poll_timeout(_mt7530_read, &p, val, 314 !(val & ATC_BUSY), 20, 20000); 315 if (ret < 0) { 316 dev_err(priv->dev, "reset timeout\n"); 317 return ret; 318 } 319 320 /* Additional sanity for read command if the specified 321 * entry is invalid 322 */ 323 val = mt7530_read(priv, MT7530_ATC); 324 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 325 return -EINVAL; 326 327 if (rsp) 328 *rsp = val; 329 330 return 0; 331 } 332 333 static void 334 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 335 { 336 u32 reg[3]; 337 int i; 338 339 /* Read from ARL table into an array */ 340 for (i = 0; i < 3; i++) { 341 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 342 343 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 344 __func__, __LINE__, i, reg[i]); 345 } 346 347 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 348 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 349 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 350 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 351 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 352 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 353 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 354 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 355 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 356 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 357 } 358 359 static void 360 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 361 u8 port_mask, const u8 *mac, 362 u8 aging, u8 type) 363 { 364 u32 reg[3] = { 0 }; 365 int i; 366 367 reg[1] |= vid & CVID_MASK; 368 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 369 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 370 /* STATIC_ENT indicate that entry is static wouldn't 371 * be aged out and STATIC_EMP specified as erasing an 372 * entry 373 */ 374 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 375 reg[1] |= mac[5] << MAC_BYTE_5; 376 reg[1] |= mac[4] << MAC_BYTE_4; 377 reg[0] |= mac[3] << MAC_BYTE_3; 378 reg[0] |= mac[2] << MAC_BYTE_2; 379 reg[0] |= mac[1] << MAC_BYTE_1; 380 reg[0] |= mac[0] << MAC_BYTE_0; 381 382 /* Write array into the ARL table */ 383 for (i = 0; i < 3; i++) 384 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 385 } 386 387 /* Setup TX circuit including relevant PAD and driving */ 388 static int 389 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 390 { 391 struct mt7530_priv *priv = ds->priv; 392 u32 ncpo1, ssc_delta, trgint, i, xtal; 393 394 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 395 396 if (xtal == HWTRAP_XTAL_20MHZ) { 397 dev_err(priv->dev, 398 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 399 __func__); 400 return -EINVAL; 401 } 402 403 switch (interface) { 404 case PHY_INTERFACE_MODE_RGMII: 405 trgint = 0; 406 /* PLL frequency: 125MHz */ 407 ncpo1 = 0x0c80; 408 break; 409 case PHY_INTERFACE_MODE_TRGMII: 410 trgint = 1; 411 if (priv->id == ID_MT7621) { 412 /* PLL frequency: 150MHz: 1.2GBit */ 413 if (xtal == HWTRAP_XTAL_40MHZ) 414 ncpo1 = 0x0780; 415 if (xtal == HWTRAP_XTAL_25MHZ) 416 ncpo1 = 0x0a00; 417 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 418 if (xtal == HWTRAP_XTAL_40MHZ) 419 ncpo1 = 0x0c80; 420 if (xtal == HWTRAP_XTAL_25MHZ) 421 ncpo1 = 0x1400; 422 } 423 break; 424 default: 425 dev_err(priv->dev, "xMII interface %d not supported\n", 426 interface); 427 return -EINVAL; 428 } 429 430 if (xtal == HWTRAP_XTAL_25MHZ) 431 ssc_delta = 0x57; 432 else 433 ssc_delta = 0x87; 434 435 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 436 P6_INTF_MODE(trgint)); 437 438 /* Lower Tx Driving for TRGMII path */ 439 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 440 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 441 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 442 443 /* Disable MT7530 core and TRGMII Tx clocks */ 444 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 445 REG_GSWCK_EN | REG_TRGMIICK_EN); 446 447 /* Setup core clock for MT7530 */ 448 /* Disable PLL */ 449 core_write(priv, CORE_GSWPLL_GRP1, 0); 450 451 /* Set core clock into 500Mhz */ 452 core_write(priv, CORE_GSWPLL_GRP2, 453 RG_GSWPLL_POSDIV_500M(1) | 454 RG_GSWPLL_FBKDIV_500M(25)); 455 456 /* Enable PLL */ 457 core_write(priv, CORE_GSWPLL_GRP1, 458 RG_GSWPLL_EN_PRE | 459 RG_GSWPLL_POSDIV_200M(2) | 460 RG_GSWPLL_FBKDIV_200M(32)); 461 462 /* Setup the MT7530 TRGMII Tx Clock */ 463 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 464 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 465 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 466 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 467 core_write(priv, CORE_PLL_GROUP4, 468 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 469 RG_SYSPLL_BIAS_LPF_EN); 470 core_write(priv, CORE_PLL_GROUP2, 471 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 472 RG_SYSPLL_POSDIV(1)); 473 core_write(priv, CORE_PLL_GROUP7, 474 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 475 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 476 477 /* Enable MT7530 core and TRGMII Tx clocks */ 478 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 479 REG_GSWCK_EN | REG_TRGMIICK_EN); 480 481 if (!trgint) 482 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 483 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 484 RD_TAP_MASK, RD_TAP(16)); 485 return 0; 486 } 487 488 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 489 { 490 u32 val; 491 492 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 493 494 return (val & PAD_DUAL_SGMII_EN) != 0; 495 } 496 497 static int 498 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 499 { 500 struct mt7530_priv *priv = ds->priv; 501 u32 top_sig; 502 u32 hwstrap; 503 u32 xtal; 504 u32 val; 505 506 if (mt7531_dual_sgmii_supported(priv)) 507 return 0; 508 509 val = mt7530_read(priv, MT7531_CREV); 510 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 511 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 512 if ((val & CHIP_REV_M) > 0) 513 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 514 HWTRAP_XTAL_FSEL_25MHZ; 515 else 516 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 517 518 /* Step 1 : Disable MT7531 COREPLL */ 519 val = mt7530_read(priv, MT7531_PLLGP_EN); 520 val &= ~EN_COREPLL; 521 mt7530_write(priv, MT7531_PLLGP_EN, val); 522 523 /* Step 2: switch to XTAL output */ 524 val = mt7530_read(priv, MT7531_PLLGP_EN); 525 val |= SW_CLKSW; 526 mt7530_write(priv, MT7531_PLLGP_EN, val); 527 528 val = mt7530_read(priv, MT7531_PLLGP_CR0); 529 val &= ~RG_COREPLL_EN; 530 mt7530_write(priv, MT7531_PLLGP_CR0, val); 531 532 /* Step 3: disable PLLGP and enable program PLLGP */ 533 val = mt7530_read(priv, MT7531_PLLGP_EN); 534 val |= SW_PLLGP; 535 mt7530_write(priv, MT7531_PLLGP_EN, val); 536 537 /* Step 4: program COREPLL output frequency to 500MHz */ 538 val = mt7530_read(priv, MT7531_PLLGP_CR0); 539 val &= ~RG_COREPLL_POSDIV_M; 540 val |= 2 << RG_COREPLL_POSDIV_S; 541 mt7530_write(priv, MT7531_PLLGP_CR0, val); 542 usleep_range(25, 35); 543 544 switch (xtal) { 545 case HWTRAP_XTAL_FSEL_25MHZ: 546 val = mt7530_read(priv, MT7531_PLLGP_CR0); 547 val &= ~RG_COREPLL_SDM_PCW_M; 548 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 549 mt7530_write(priv, MT7531_PLLGP_CR0, val); 550 break; 551 case HWTRAP_XTAL_FSEL_40MHZ: 552 val = mt7530_read(priv, MT7531_PLLGP_CR0); 553 val &= ~RG_COREPLL_SDM_PCW_M; 554 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 555 mt7530_write(priv, MT7531_PLLGP_CR0, val); 556 break; 557 } 558 559 /* Set feedback divide ratio update signal to high */ 560 val = mt7530_read(priv, MT7531_PLLGP_CR0); 561 val |= RG_COREPLL_SDM_PCW_CHG; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 /* Wait for at least 16 XTAL clocks */ 564 usleep_range(10, 20); 565 566 /* Step 5: set feedback divide ratio update signal to low */ 567 val = mt7530_read(priv, MT7531_PLLGP_CR0); 568 val &= ~RG_COREPLL_SDM_PCW_CHG; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 571 /* Enable 325M clock for SGMII */ 572 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 573 574 /* Enable 250SSC clock for RGMII */ 575 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 576 577 /* Step 6: Enable MT7531 PLL */ 578 val = mt7530_read(priv, MT7531_PLLGP_CR0); 579 val |= RG_COREPLL_EN; 580 mt7530_write(priv, MT7531_PLLGP_CR0, val); 581 582 val = mt7530_read(priv, MT7531_PLLGP_EN); 583 val |= EN_COREPLL; 584 mt7530_write(priv, MT7531_PLLGP_EN, val); 585 usleep_range(25, 35); 586 587 return 0; 588 } 589 590 static void 591 mt7530_mib_reset(struct dsa_switch *ds) 592 { 593 struct mt7530_priv *priv = ds->priv; 594 595 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 596 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 597 } 598 599 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 600 { 601 struct mt7530_priv *priv = ds->priv; 602 603 return mdiobus_read_nested(priv->bus, port, regnum); 604 } 605 606 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 607 u16 val) 608 { 609 struct mt7530_priv *priv = ds->priv; 610 611 return mdiobus_write_nested(priv->bus, port, regnum, val); 612 } 613 614 static int 615 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 616 int regnum) 617 { 618 struct mii_bus *bus = priv->bus; 619 struct mt7530_dummy_poll p; 620 u32 reg, val; 621 int ret; 622 623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 624 625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | regnum; 636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 639 !(val & MT7531_PHY_ACS_ST), 20, 100000); 640 if (ret < 0) { 641 dev_err(priv->dev, "poll timeout\n"); 642 goto out; 643 } 644 645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 646 MT7531_MDIO_DEV_ADDR(devad); 647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 ret = val & MT7531_MDIO_RW_DATA_MASK; 657 out: 658 mutex_unlock(&bus->mdio_lock); 659 660 return ret; 661 } 662 663 static int 664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 665 int regnum, u32 data) 666 { 667 struct mii_bus *bus = priv->bus; 668 struct mt7530_dummy_poll p; 669 u32 val, reg; 670 int ret; 671 672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 673 674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 675 676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 677 !(val & MT7531_PHY_ACS_ST), 20, 100000); 678 if (ret < 0) { 679 dev_err(priv->dev, "poll timeout\n"); 680 goto out; 681 } 682 683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 684 MT7531_MDIO_DEV_ADDR(devad) | regnum; 685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | data; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 out: 706 mutex_unlock(&bus->mdio_lock); 707 708 return ret; 709 } 710 711 static int 712 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 713 { 714 struct mii_bus *bus = priv->bus; 715 struct mt7530_dummy_poll p; 716 int ret; 717 u32 val; 718 719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 720 721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 722 723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 724 !(val & MT7531_PHY_ACS_ST), 20, 100000); 725 if (ret < 0) { 726 dev_err(priv->dev, "poll timeout\n"); 727 goto out; 728 } 729 730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 731 MT7531_MDIO_REG_ADDR(regnum); 732 733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 734 735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 736 !(val & MT7531_PHY_ACS_ST), 20, 100000); 737 if (ret < 0) { 738 dev_err(priv->dev, "poll timeout\n"); 739 goto out; 740 } 741 742 ret = val & MT7531_MDIO_RW_DATA_MASK; 743 out: 744 mutex_unlock(&bus->mdio_lock); 745 746 return ret; 747 } 748 749 static int 750 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 751 u16 data) 752 { 753 struct mii_bus *bus = priv->bus; 754 struct mt7530_dummy_poll p; 755 int ret; 756 u32 reg; 757 758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 759 760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 761 762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 763 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 764 if (ret < 0) { 765 dev_err(priv->dev, "poll timeout\n"); 766 goto out; 767 } 768 769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 770 MT7531_MDIO_REG_ADDR(regnum) | data; 771 772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 773 774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 775 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 776 if (ret < 0) { 777 dev_err(priv->dev, "poll timeout\n"); 778 goto out; 779 } 780 781 out: 782 mutex_unlock(&bus->mdio_lock); 783 784 return ret; 785 } 786 787 static int 788 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) 789 { 790 struct mt7530_priv *priv = ds->priv; 791 int devad; 792 int ret; 793 794 if (regnum & MII_ADDR_C45) { 795 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 796 ret = mt7531_ind_c45_phy_read(priv, port, devad, 797 regnum & MII_REGADDR_C45_MASK); 798 } else { 799 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 800 } 801 802 return ret; 803 } 804 805 static int 806 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, 807 u16 data) 808 { 809 struct mt7530_priv *priv = ds->priv; 810 int devad; 811 int ret; 812 813 if (regnum & MII_ADDR_C45) { 814 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 815 ret = mt7531_ind_c45_phy_write(priv, port, devad, 816 regnum & MII_REGADDR_C45_MASK, 817 data); 818 } else { 819 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 820 } 821 822 return ret; 823 } 824 825 static void 826 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 827 uint8_t *data) 828 { 829 int i; 830 831 if (stringset != ETH_SS_STATS) 832 return; 833 834 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 835 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 836 ETH_GSTRING_LEN); 837 } 838 839 static void 840 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 841 uint64_t *data) 842 { 843 struct mt7530_priv *priv = ds->priv; 844 const struct mt7530_mib_desc *mib; 845 u32 reg, i; 846 u64 hi; 847 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 849 mib = &mt7530_mib[i]; 850 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 851 852 data[i] = mt7530_read(priv, reg); 853 if (mib->size == 2) { 854 hi = mt7530_read(priv, reg + 4); 855 data[i] |= hi << 32; 856 } 857 } 858 } 859 860 static int 861 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 862 { 863 if (sset != ETH_SS_STATS) 864 return 0; 865 866 return ARRAY_SIZE(mt7530_mib); 867 } 868 869 static int 870 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 871 { 872 struct mt7530_priv *priv = ds->priv; 873 unsigned int secs = msecs / 1000; 874 unsigned int tmp_age_count; 875 unsigned int error = -1; 876 unsigned int age_count; 877 unsigned int age_unit; 878 879 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 880 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 881 return -ERANGE; 882 883 /* iterate through all possible age_count to find the closest pair */ 884 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 885 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 886 887 if (tmp_age_unit <= AGE_UNIT_MAX) { 888 unsigned int tmp_error = secs - 889 (tmp_age_count + 1) * (tmp_age_unit + 1); 890 891 /* found a closer pair */ 892 if (error > tmp_error) { 893 error = tmp_error; 894 age_count = tmp_age_count; 895 age_unit = tmp_age_unit; 896 } 897 898 /* found the exact match, so break the loop */ 899 if (!error) 900 break; 901 } 902 } 903 904 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 905 906 return 0; 907 } 908 909 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 910 { 911 struct mt7530_priv *priv = ds->priv; 912 u8 tx_delay = 0; 913 int val; 914 915 mutex_lock(&priv->reg_mutex); 916 917 val = mt7530_read(priv, MT7530_MHWTRAP); 918 919 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 920 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 921 922 switch (priv->p5_intf_sel) { 923 case P5_INTF_SEL_PHY_P0: 924 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 925 val |= MHWTRAP_PHY0_SEL; 926 fallthrough; 927 case P5_INTF_SEL_PHY_P4: 928 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 929 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 930 931 /* Setup the MAC by default for the cpu port */ 932 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 933 break; 934 case P5_INTF_SEL_GMAC5: 935 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 936 val &= ~MHWTRAP_P5_DIS; 937 break; 938 case P5_DISABLED: 939 interface = PHY_INTERFACE_MODE_NA; 940 break; 941 default: 942 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 943 priv->p5_intf_sel); 944 goto unlock_exit; 945 } 946 947 /* Setup RGMII settings */ 948 if (phy_interface_mode_is_rgmii(interface)) { 949 val |= MHWTRAP_P5_RGMII_MODE; 950 951 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 952 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 953 954 /* Don't set delay in DSA mode */ 955 if (!dsa_is_dsa_port(priv->ds, 5) && 956 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 957 interface == PHY_INTERFACE_MODE_RGMII_ID)) 958 tx_delay = 4; /* n * 0.5 ns */ 959 960 /* P5 RGMII TX Clock Control: delay x */ 961 mt7530_write(priv, MT7530_P5RGMIITXCR, 962 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 963 964 /* reduce P5 RGMII Tx driving, 8mA */ 965 mt7530_write(priv, MT7530_IO_DRV_CR, 966 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 967 } 968 969 mt7530_write(priv, MT7530_MHWTRAP, val); 970 971 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 972 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 973 974 priv->p5_interface = interface; 975 976 unlock_exit: 977 mutex_unlock(&priv->reg_mutex); 978 } 979 980 static int 981 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 982 { 983 struct mt7530_priv *priv = ds->priv; 984 int ret; 985 986 /* Setup max capability of CPU port at first */ 987 if (priv->info->cpu_port_config) { 988 ret = priv->info->cpu_port_config(ds, port); 989 if (ret) 990 return ret; 991 } 992 993 /* Enable Mediatek header mode on the cpu port */ 994 mt7530_write(priv, MT7530_PVC_P(port), 995 PORT_SPEC_TAG); 996 997 /* Disable flooding by default */ 998 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 999 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1000 1001 /* Set CPU port number */ 1002 if (priv->id == ID_MT7621) 1003 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1004 1005 /* CPU port gets connected to all user ports of 1006 * the switch. 1007 */ 1008 mt7530_write(priv, MT7530_PCR_P(port), 1009 PCR_MATRIX(dsa_user_ports(priv->ds))); 1010 1011 return 0; 1012 } 1013 1014 static int 1015 mt7530_port_enable(struct dsa_switch *ds, int port, 1016 struct phy_device *phy) 1017 { 1018 struct mt7530_priv *priv = ds->priv; 1019 1020 if (!dsa_is_user_port(ds, port)) 1021 return 0; 1022 1023 mutex_lock(&priv->reg_mutex); 1024 1025 /* Allow the user port gets connected to the cpu port and also 1026 * restore the port matrix if the port is the member of a certain 1027 * bridge. 1028 */ 1029 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1030 priv->ports[port].enable = true; 1031 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1032 priv->ports[port].pm); 1033 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1034 1035 mutex_unlock(&priv->reg_mutex); 1036 1037 return 0; 1038 } 1039 1040 static void 1041 mt7530_port_disable(struct dsa_switch *ds, int port) 1042 { 1043 struct mt7530_priv *priv = ds->priv; 1044 1045 if (!dsa_is_user_port(ds, port)) 1046 return; 1047 1048 mutex_lock(&priv->reg_mutex); 1049 1050 /* Clear up all port matrix which could be restored in the next 1051 * enablement for the port. 1052 */ 1053 priv->ports[port].enable = false; 1054 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1055 PCR_MATRIX_CLR); 1056 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1057 1058 mutex_unlock(&priv->reg_mutex); 1059 } 1060 1061 static int 1062 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1063 { 1064 struct mt7530_priv *priv = ds->priv; 1065 struct mii_bus *bus = priv->bus; 1066 int length; 1067 u32 val; 1068 1069 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1070 * largest MTU of the slave ports. Because the switch only has a global 1071 * RX length register, only allowing CPU port here is enough. 1072 */ 1073 if (!dsa_is_cpu_port(ds, port)) 1074 return 0; 1075 1076 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1077 1078 val = mt7530_mii_read(priv, MT7530_GMACCR); 1079 val &= ~MAX_RX_PKT_LEN_MASK; 1080 1081 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1082 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1083 if (length <= 1522) { 1084 val |= MAX_RX_PKT_LEN_1522; 1085 } else if (length <= 1536) { 1086 val |= MAX_RX_PKT_LEN_1536; 1087 } else if (length <= 1552) { 1088 val |= MAX_RX_PKT_LEN_1552; 1089 } else { 1090 val &= ~MAX_RX_JUMBO_MASK; 1091 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1092 val |= MAX_RX_PKT_LEN_JUMBO; 1093 } 1094 1095 mt7530_mii_write(priv, MT7530_GMACCR, val); 1096 1097 mutex_unlock(&bus->mdio_lock); 1098 1099 return 0; 1100 } 1101 1102 static int 1103 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1104 { 1105 return MT7530_MAX_MTU; 1106 } 1107 1108 static void 1109 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1110 { 1111 struct mt7530_priv *priv = ds->priv; 1112 u32 stp_state; 1113 1114 switch (state) { 1115 case BR_STATE_DISABLED: 1116 stp_state = MT7530_STP_DISABLED; 1117 break; 1118 case BR_STATE_BLOCKING: 1119 stp_state = MT7530_STP_BLOCKING; 1120 break; 1121 case BR_STATE_LISTENING: 1122 stp_state = MT7530_STP_LISTENING; 1123 break; 1124 case BR_STATE_LEARNING: 1125 stp_state = MT7530_STP_LEARNING; 1126 break; 1127 case BR_STATE_FORWARDING: 1128 default: 1129 stp_state = MT7530_STP_FORWARDING; 1130 break; 1131 } 1132 1133 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1134 } 1135 1136 static int 1137 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1138 struct switchdev_brport_flags flags, 1139 struct netlink_ext_ack *extack) 1140 { 1141 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1142 BR_BCAST_FLOOD)) 1143 return -EINVAL; 1144 1145 return 0; 1146 } 1147 1148 static int 1149 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1150 struct switchdev_brport_flags flags, 1151 struct netlink_ext_ack *extack) 1152 { 1153 struct mt7530_priv *priv = ds->priv; 1154 1155 if (flags.mask & BR_LEARNING) 1156 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1157 flags.val & BR_LEARNING ? 0 : SA_DIS); 1158 1159 if (flags.mask & BR_FLOOD) 1160 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1161 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1162 1163 if (flags.mask & BR_MCAST_FLOOD) 1164 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1165 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1166 1167 if (flags.mask & BR_BCAST_FLOOD) 1168 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1169 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1170 1171 return 0; 1172 } 1173 1174 static int 1175 mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1176 struct netlink_ext_ack *extack) 1177 { 1178 struct mt7530_priv *priv = ds->priv; 1179 1180 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1181 mrouter ? UNM_FFP(BIT(port)) : 0); 1182 1183 return 0; 1184 } 1185 1186 static int 1187 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1188 struct net_device *bridge) 1189 { 1190 struct mt7530_priv *priv = ds->priv; 1191 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1192 int i; 1193 1194 mutex_lock(&priv->reg_mutex); 1195 1196 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1197 /* Add this port to the port matrix of the other ports in the 1198 * same bridge. If the port is disabled, port matrix is kept 1199 * and not being setup until the port becomes enabled. 1200 */ 1201 if (dsa_is_user_port(ds, i) && i != port) { 1202 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1203 continue; 1204 if (priv->ports[i].enable) 1205 mt7530_set(priv, MT7530_PCR_P(i), 1206 PCR_MATRIX(BIT(port))); 1207 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1208 1209 port_bitmap |= BIT(i); 1210 } 1211 } 1212 1213 /* Add the all other ports to this port matrix. */ 1214 if (priv->ports[port].enable) 1215 mt7530_rmw(priv, MT7530_PCR_P(port), 1216 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1217 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1218 1219 mutex_unlock(&priv->reg_mutex); 1220 1221 return 0; 1222 } 1223 1224 static void 1225 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1226 { 1227 struct mt7530_priv *priv = ds->priv; 1228 bool all_user_ports_removed = true; 1229 int i; 1230 1231 /* When a port is removed from the bridge, the port would be set up 1232 * back to the default as is at initial boot which is a VLAN-unaware 1233 * port. 1234 */ 1235 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1236 MT7530_PORT_MATRIX_MODE); 1237 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1238 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1239 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1240 1241 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1242 if (dsa_is_user_port(ds, i) && 1243 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1244 all_user_ports_removed = false; 1245 break; 1246 } 1247 } 1248 1249 /* CPU port also does the same thing until all user ports belonging to 1250 * the CPU port get out of VLAN filtering mode. 1251 */ 1252 if (all_user_ports_removed) { 1253 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1254 PCR_MATRIX(dsa_user_ports(priv->ds))); 1255 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1256 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1257 } 1258 } 1259 1260 static void 1261 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1262 { 1263 struct mt7530_priv *priv = ds->priv; 1264 1265 /* The real fabric path would be decided on the membership in the 1266 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 1267 * means potential VLAN can be consisting of certain subset of all 1268 * ports. 1269 */ 1270 mt7530_rmw(priv, MT7530_PCR_P(port), 1271 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 1272 1273 /* Trapped into security mode allows packet forwarding through VLAN 1274 * table lookup. CPU port is set to fallback mode to let untagged 1275 * frames pass through. 1276 */ 1277 if (dsa_is_cpu_port(ds, port)) 1278 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1279 MT7530_PORT_FALLBACK_MODE); 1280 else 1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1282 MT7530_PORT_SECURITY_MODE); 1283 1284 /* Set the port as a user port which is to be able to recognize VID 1285 * from incoming packets before fetching entry within the VLAN table. 1286 */ 1287 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1288 VLAN_ATTR(MT7530_VLAN_USER) | 1289 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1290 } 1291 1292 static void 1293 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1294 struct net_device *bridge) 1295 { 1296 struct mt7530_priv *priv = ds->priv; 1297 int i; 1298 1299 mutex_lock(&priv->reg_mutex); 1300 1301 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1302 /* Remove this port from the port matrix of the other ports 1303 * in the same bridge. If the port is disabled, port matrix 1304 * is kept and not being setup until the port becomes enabled. 1305 * And the other port's port matrix cannot be broken when the 1306 * other port is still a VLAN-aware port. 1307 */ 1308 if (dsa_is_user_port(ds, i) && i != port && 1309 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1310 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1311 continue; 1312 if (priv->ports[i].enable) 1313 mt7530_clear(priv, MT7530_PCR_P(i), 1314 PCR_MATRIX(BIT(port))); 1315 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1316 } 1317 } 1318 1319 /* Set the cpu port to be the only one in the port matrix of 1320 * this port. 1321 */ 1322 if (priv->ports[port].enable) 1323 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1324 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1325 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1326 1327 mutex_unlock(&priv->reg_mutex); 1328 } 1329 1330 static int 1331 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1332 const unsigned char *addr, u16 vid) 1333 { 1334 struct mt7530_priv *priv = ds->priv; 1335 int ret; 1336 u8 port_mask = BIT(port); 1337 1338 mutex_lock(&priv->reg_mutex); 1339 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1340 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1341 mutex_unlock(&priv->reg_mutex); 1342 1343 return ret; 1344 } 1345 1346 static int 1347 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1348 const unsigned char *addr, u16 vid) 1349 { 1350 struct mt7530_priv *priv = ds->priv; 1351 int ret; 1352 u8 port_mask = BIT(port); 1353 1354 mutex_lock(&priv->reg_mutex); 1355 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1356 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1357 mutex_unlock(&priv->reg_mutex); 1358 1359 return ret; 1360 } 1361 1362 static int 1363 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1364 dsa_fdb_dump_cb_t *cb, void *data) 1365 { 1366 struct mt7530_priv *priv = ds->priv; 1367 struct mt7530_fdb _fdb = { 0 }; 1368 int cnt = MT7530_NUM_FDB_RECORDS; 1369 int ret = 0; 1370 u32 rsp = 0; 1371 1372 mutex_lock(&priv->reg_mutex); 1373 1374 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1375 if (ret < 0) 1376 goto err; 1377 1378 do { 1379 if (rsp & ATC_SRCH_HIT) { 1380 mt7530_fdb_read(priv, &_fdb); 1381 if (_fdb.port_mask & BIT(port)) { 1382 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1383 data); 1384 if (ret < 0) 1385 break; 1386 } 1387 } 1388 } while (--cnt && 1389 !(rsp & ATC_SRCH_END) && 1390 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1391 err: 1392 mutex_unlock(&priv->reg_mutex); 1393 1394 return 0; 1395 } 1396 1397 static int 1398 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1399 const struct switchdev_obj_port_mdb *mdb) 1400 { 1401 struct mt7530_priv *priv = ds->priv; 1402 const u8 *addr = mdb->addr; 1403 u16 vid = mdb->vid; 1404 u8 port_mask = 0; 1405 int ret; 1406 1407 mutex_lock(&priv->reg_mutex); 1408 1409 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1410 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1411 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1412 & PORT_MAP_MASK; 1413 1414 port_mask |= BIT(port); 1415 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1416 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1417 1418 mutex_unlock(&priv->reg_mutex); 1419 1420 return ret; 1421 } 1422 1423 static int 1424 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1425 const struct switchdev_obj_port_mdb *mdb) 1426 { 1427 struct mt7530_priv *priv = ds->priv; 1428 const u8 *addr = mdb->addr; 1429 u16 vid = mdb->vid; 1430 u8 port_mask = 0; 1431 int ret; 1432 1433 mutex_lock(&priv->reg_mutex); 1434 1435 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1436 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1437 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1438 & PORT_MAP_MASK; 1439 1440 port_mask &= ~BIT(port); 1441 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1442 port_mask ? STATIC_ENT : STATIC_EMP); 1443 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1444 1445 mutex_unlock(&priv->reg_mutex); 1446 1447 return ret; 1448 } 1449 1450 static int 1451 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1452 { 1453 struct mt7530_dummy_poll p; 1454 u32 val; 1455 int ret; 1456 1457 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1458 mt7530_write(priv, MT7530_VTCR, val); 1459 1460 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1461 ret = readx_poll_timeout(_mt7530_read, &p, val, 1462 !(val & VTCR_BUSY), 20, 20000); 1463 if (ret < 0) { 1464 dev_err(priv->dev, "poll timeout\n"); 1465 return ret; 1466 } 1467 1468 val = mt7530_read(priv, MT7530_VTCR); 1469 if (val & VTCR_INVALID) { 1470 dev_err(priv->dev, "read VTCR invalid\n"); 1471 return -EINVAL; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int 1478 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1479 struct netlink_ext_ack *extack) 1480 { 1481 if (vlan_filtering) { 1482 /* The port is being kept as VLAN-unaware port when bridge is 1483 * set up with vlan_filtering not being set, Otherwise, the 1484 * port and the corresponding CPU port is required the setup 1485 * for becoming a VLAN-aware port. 1486 */ 1487 mt7530_port_set_vlan_aware(ds, port); 1488 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1489 } else { 1490 mt7530_port_set_vlan_unaware(ds, port); 1491 } 1492 1493 return 0; 1494 } 1495 1496 static void 1497 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1498 struct mt7530_hw_vlan_entry *entry) 1499 { 1500 u8 new_members; 1501 u32 val; 1502 1503 new_members = entry->old_members | BIT(entry->port) | 1504 BIT(MT7530_CPU_PORT); 1505 1506 /* Validate the entry with independent learning, create egress tag per 1507 * VLAN and joining the port as one of the port members. 1508 */ 1509 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1510 mt7530_write(priv, MT7530_VAWD1, val); 1511 1512 /* Decide whether adding tag or not for those outgoing packets from the 1513 * port inside the VLAN. 1514 */ 1515 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1516 MT7530_VLAN_EGRESS_TAG; 1517 mt7530_rmw(priv, MT7530_VAWD2, 1518 ETAG_CTRL_P_MASK(entry->port), 1519 ETAG_CTRL_P(entry->port, val)); 1520 1521 /* CPU port is always taken as a tagged port for serving more than one 1522 * VLANs across and also being applied with egress type stack mode for 1523 * that VLAN tags would be appended after hardware special tag used as 1524 * DSA tag. 1525 */ 1526 mt7530_rmw(priv, MT7530_VAWD2, 1527 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1528 ETAG_CTRL_P(MT7530_CPU_PORT, 1529 MT7530_VLAN_EGRESS_STACK)); 1530 } 1531 1532 static void 1533 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1534 struct mt7530_hw_vlan_entry *entry) 1535 { 1536 u8 new_members; 1537 u32 val; 1538 1539 new_members = entry->old_members & ~BIT(entry->port); 1540 1541 val = mt7530_read(priv, MT7530_VAWD1); 1542 if (!(val & VLAN_VALID)) { 1543 dev_err(priv->dev, 1544 "Cannot be deleted due to invalid entry\n"); 1545 return; 1546 } 1547 1548 /* If certain member apart from CPU port is still alive in the VLAN, 1549 * the entry would be kept valid. Otherwise, the entry is got to be 1550 * disabled. 1551 */ 1552 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1553 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1554 VLAN_VALID; 1555 mt7530_write(priv, MT7530_VAWD1, val); 1556 } else { 1557 mt7530_write(priv, MT7530_VAWD1, 0); 1558 mt7530_write(priv, MT7530_VAWD2, 0); 1559 } 1560 } 1561 1562 static void 1563 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1564 struct mt7530_hw_vlan_entry *entry, 1565 mt7530_vlan_op vlan_op) 1566 { 1567 u32 val; 1568 1569 /* Fetch entry */ 1570 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1571 1572 val = mt7530_read(priv, MT7530_VAWD1); 1573 1574 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1575 1576 /* Manipulate entry */ 1577 vlan_op(priv, entry); 1578 1579 /* Flush result to hardware */ 1580 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1581 } 1582 1583 static int 1584 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1585 const struct switchdev_obj_port_vlan *vlan, 1586 struct netlink_ext_ack *extack) 1587 { 1588 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1589 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1590 struct mt7530_hw_vlan_entry new_entry; 1591 struct mt7530_priv *priv = ds->priv; 1592 1593 mutex_lock(&priv->reg_mutex); 1594 1595 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1596 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1597 1598 if (pvid) { 1599 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1600 G0_PORT_VID(vlan->vid)); 1601 priv->ports[port].pvid = vlan->vid; 1602 } 1603 1604 mutex_unlock(&priv->reg_mutex); 1605 1606 return 0; 1607 } 1608 1609 static int 1610 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1611 const struct switchdev_obj_port_vlan *vlan) 1612 { 1613 struct mt7530_hw_vlan_entry target_entry; 1614 struct mt7530_priv *priv = ds->priv; 1615 u16 pvid; 1616 1617 mutex_lock(&priv->reg_mutex); 1618 1619 pvid = priv->ports[port].pvid; 1620 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1621 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1622 mt7530_hw_vlan_del); 1623 1624 /* PVID is being restored to the default whenever the PVID port 1625 * is being removed from the VLAN. 1626 */ 1627 if (pvid == vlan->vid) 1628 pvid = G0_PORT_VID_DEF; 1629 1630 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1631 priv->ports[port].pvid = pvid; 1632 1633 mutex_unlock(&priv->reg_mutex); 1634 1635 return 0; 1636 } 1637 1638 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1639 { 1640 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1641 MIRROR_PORT(val); 1642 } 1643 1644 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1645 { 1646 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1647 MIRROR_PORT(val); 1648 } 1649 1650 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1651 struct dsa_mall_mirror_tc_entry *mirror, 1652 bool ingress) 1653 { 1654 struct mt7530_priv *priv = ds->priv; 1655 int monitor_port; 1656 u32 val; 1657 1658 /* Check for existent entry */ 1659 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1660 return -EEXIST; 1661 1662 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1663 1664 /* MT7530 only supports one monitor port */ 1665 monitor_port = mt753x_mirror_port_get(priv->id, val); 1666 if (val & MT753X_MIRROR_EN(priv->id) && 1667 monitor_port != mirror->to_local_port) 1668 return -EEXIST; 1669 1670 val |= MT753X_MIRROR_EN(priv->id); 1671 val &= ~MT753X_MIRROR_MASK(priv->id); 1672 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1673 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1674 1675 val = mt7530_read(priv, MT7530_PCR_P(port)); 1676 if (ingress) { 1677 val |= PORT_RX_MIR; 1678 priv->mirror_rx |= BIT(port); 1679 } else { 1680 val |= PORT_TX_MIR; 1681 priv->mirror_tx |= BIT(port); 1682 } 1683 mt7530_write(priv, MT7530_PCR_P(port), val); 1684 1685 return 0; 1686 } 1687 1688 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1689 struct dsa_mall_mirror_tc_entry *mirror) 1690 { 1691 struct mt7530_priv *priv = ds->priv; 1692 u32 val; 1693 1694 val = mt7530_read(priv, MT7530_PCR_P(port)); 1695 if (mirror->ingress) { 1696 val &= ~PORT_RX_MIR; 1697 priv->mirror_rx &= ~BIT(port); 1698 } else { 1699 val &= ~PORT_TX_MIR; 1700 priv->mirror_tx &= ~BIT(port); 1701 } 1702 mt7530_write(priv, MT7530_PCR_P(port), val); 1703 1704 if (!priv->mirror_rx && !priv->mirror_tx) { 1705 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1706 val &= ~MT753X_MIRROR_EN(priv->id); 1707 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1708 } 1709 } 1710 1711 static enum dsa_tag_protocol 1712 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1713 enum dsa_tag_protocol mp) 1714 { 1715 struct mt7530_priv *priv = ds->priv; 1716 1717 if (port != MT7530_CPU_PORT) { 1718 dev_warn(priv->dev, 1719 "port not matched with tagging CPU port\n"); 1720 return DSA_TAG_PROTO_NONE; 1721 } else { 1722 return DSA_TAG_PROTO_MTK; 1723 } 1724 } 1725 1726 #ifdef CONFIG_GPIOLIB 1727 static inline u32 1728 mt7530_gpio_to_bit(unsigned int offset) 1729 { 1730 /* Map GPIO offset to register bit 1731 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1732 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1733 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1734 * [14:12] port 3 LED 0..2 as GPIO 9..11 1735 * [18:16] port 4 LED 0..2 as GPIO 12..14 1736 */ 1737 return BIT(offset + offset / 3); 1738 } 1739 1740 static int 1741 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1742 { 1743 struct mt7530_priv *priv = gpiochip_get_data(gc); 1744 u32 bit = mt7530_gpio_to_bit(offset); 1745 1746 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1747 } 1748 1749 static void 1750 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1751 { 1752 struct mt7530_priv *priv = gpiochip_get_data(gc); 1753 u32 bit = mt7530_gpio_to_bit(offset); 1754 1755 if (value) 1756 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1757 else 1758 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1759 } 1760 1761 static int 1762 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1763 { 1764 struct mt7530_priv *priv = gpiochip_get_data(gc); 1765 u32 bit = mt7530_gpio_to_bit(offset); 1766 1767 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1768 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1769 } 1770 1771 static int 1772 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1773 { 1774 struct mt7530_priv *priv = gpiochip_get_data(gc); 1775 u32 bit = mt7530_gpio_to_bit(offset); 1776 1777 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1778 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1779 1780 return 0; 1781 } 1782 1783 static int 1784 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1785 { 1786 struct mt7530_priv *priv = gpiochip_get_data(gc); 1787 u32 bit = mt7530_gpio_to_bit(offset); 1788 1789 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1790 1791 if (value) 1792 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1793 else 1794 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1795 1796 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1797 1798 return 0; 1799 } 1800 1801 static int 1802 mt7530_setup_gpio(struct mt7530_priv *priv) 1803 { 1804 struct device *dev = priv->dev; 1805 struct gpio_chip *gc; 1806 1807 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1808 if (!gc) 1809 return -ENOMEM; 1810 1811 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1812 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1813 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1814 1815 gc->label = "mt7530"; 1816 gc->parent = dev; 1817 gc->owner = THIS_MODULE; 1818 gc->get_direction = mt7530_gpio_get_direction; 1819 gc->direction_input = mt7530_gpio_direction_input; 1820 gc->direction_output = mt7530_gpio_direction_output; 1821 gc->get = mt7530_gpio_get; 1822 gc->set = mt7530_gpio_set; 1823 gc->base = -1; 1824 gc->ngpio = 15; 1825 gc->can_sleep = true; 1826 1827 return devm_gpiochip_add_data(dev, gc, priv); 1828 } 1829 #endif /* CONFIG_GPIOLIB */ 1830 1831 static int 1832 mt7530_setup(struct dsa_switch *ds) 1833 { 1834 struct mt7530_priv *priv = ds->priv; 1835 struct device_node *phy_node; 1836 struct device_node *mac_np; 1837 struct mt7530_dummy_poll p; 1838 phy_interface_t interface; 1839 struct device_node *dn; 1840 u32 id, val; 1841 int ret, i; 1842 1843 /* The parent node of master netdev which holds the common system 1844 * controller also is the container for two GMACs nodes representing 1845 * as two netdev instances. 1846 */ 1847 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 1848 ds->mtu_enforcement_ingress = true; 1849 1850 if (priv->id == ID_MT7530) { 1851 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1852 ret = regulator_enable(priv->core_pwr); 1853 if (ret < 0) { 1854 dev_err(priv->dev, 1855 "Failed to enable core power: %d\n", ret); 1856 return ret; 1857 } 1858 1859 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1860 ret = regulator_enable(priv->io_pwr); 1861 if (ret < 0) { 1862 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1863 ret); 1864 return ret; 1865 } 1866 } 1867 1868 /* Reset whole chip through gpio pin or memory-mapped registers for 1869 * different type of hardware 1870 */ 1871 if (priv->mcm) { 1872 reset_control_assert(priv->rstc); 1873 usleep_range(1000, 1100); 1874 reset_control_deassert(priv->rstc); 1875 } else { 1876 gpiod_set_value_cansleep(priv->reset, 0); 1877 usleep_range(1000, 1100); 1878 gpiod_set_value_cansleep(priv->reset, 1); 1879 } 1880 1881 /* Waiting for MT7530 got to stable */ 1882 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1883 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1884 20, 1000000); 1885 if (ret < 0) { 1886 dev_err(priv->dev, "reset timeout\n"); 1887 return ret; 1888 } 1889 1890 id = mt7530_read(priv, MT7530_CREV); 1891 id >>= CHIP_NAME_SHIFT; 1892 if (id != MT7530_ID) { 1893 dev_err(priv->dev, "chip %x can't be supported\n", id); 1894 return -ENODEV; 1895 } 1896 1897 /* Reset the switch through internal reset */ 1898 mt7530_write(priv, MT7530_SYS_CTRL, 1899 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1900 SYS_CTRL_REG_RST); 1901 1902 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1903 val = mt7530_read(priv, MT7530_MHWTRAP); 1904 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1905 val |= MHWTRAP_MANUAL; 1906 mt7530_write(priv, MT7530_MHWTRAP, val); 1907 1908 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1909 1910 /* Enable and reset MIB counters */ 1911 mt7530_mib_reset(ds); 1912 1913 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1914 /* Disable forwarding by default on all ports */ 1915 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1916 PCR_MATRIX_CLR); 1917 1918 if (dsa_is_cpu_port(ds, i)) { 1919 ret = mt753x_cpu_port_enable(ds, i); 1920 if (ret) 1921 return ret; 1922 } else { 1923 mt7530_port_disable(ds, i); 1924 1925 /* Disable learning by default on all user ports */ 1926 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 1927 } 1928 /* Enable consistent egress tag */ 1929 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1930 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1931 } 1932 1933 /* Setup port 5 */ 1934 priv->p5_intf_sel = P5_DISABLED; 1935 interface = PHY_INTERFACE_MODE_NA; 1936 1937 if (!dsa_is_unused_port(ds, 5)) { 1938 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1939 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 1940 if (ret && ret != -ENODEV) 1941 return ret; 1942 } else { 1943 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 1944 for_each_child_of_node(dn, mac_np) { 1945 if (!of_device_is_compatible(mac_np, 1946 "mediatek,eth-mac")) 1947 continue; 1948 1949 ret = of_property_read_u32(mac_np, "reg", &id); 1950 if (ret < 0 || id != 1) 1951 continue; 1952 1953 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 1954 if (!phy_node) 1955 continue; 1956 1957 if (phy_node->parent == priv->dev->of_node->parent) { 1958 ret = of_get_phy_mode(mac_np, &interface); 1959 if (ret && ret != -ENODEV) { 1960 of_node_put(mac_np); 1961 return ret; 1962 } 1963 id = of_mdio_parse_addr(ds->dev, phy_node); 1964 if (id == 0) 1965 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 1966 if (id == 4) 1967 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 1968 } 1969 of_node_put(mac_np); 1970 of_node_put(phy_node); 1971 break; 1972 } 1973 } 1974 1975 #ifdef CONFIG_GPIOLIB 1976 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 1977 ret = mt7530_setup_gpio(priv); 1978 if (ret) 1979 return ret; 1980 } 1981 #endif /* CONFIG_GPIOLIB */ 1982 1983 mt7530_setup_port5(ds, interface); 1984 1985 /* Flush the FDB table */ 1986 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1987 if (ret < 0) 1988 return ret; 1989 1990 return 0; 1991 } 1992 1993 static int 1994 mt7531_setup(struct dsa_switch *ds) 1995 { 1996 struct mt7530_priv *priv = ds->priv; 1997 struct mt7530_dummy_poll p; 1998 u32 val, id; 1999 int ret, i; 2000 2001 /* Reset whole chip through gpio pin or memory-mapped registers for 2002 * different type of hardware 2003 */ 2004 if (priv->mcm) { 2005 reset_control_assert(priv->rstc); 2006 usleep_range(1000, 1100); 2007 reset_control_deassert(priv->rstc); 2008 } else { 2009 gpiod_set_value_cansleep(priv->reset, 0); 2010 usleep_range(1000, 1100); 2011 gpiod_set_value_cansleep(priv->reset, 1); 2012 } 2013 2014 /* Waiting for MT7530 got to stable */ 2015 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2016 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2017 20, 1000000); 2018 if (ret < 0) { 2019 dev_err(priv->dev, "reset timeout\n"); 2020 return ret; 2021 } 2022 2023 id = mt7530_read(priv, MT7531_CREV); 2024 id >>= CHIP_NAME_SHIFT; 2025 2026 if (id != MT7531_ID) { 2027 dev_err(priv->dev, "chip %x can't be supported\n", id); 2028 return -ENODEV; 2029 } 2030 2031 /* Reset the switch through internal reset */ 2032 mt7530_write(priv, MT7530_SYS_CTRL, 2033 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2034 SYS_CTRL_REG_RST); 2035 2036 if (mt7531_dual_sgmii_supported(priv)) { 2037 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2038 2039 /* Let ds->slave_mii_bus be able to access external phy. */ 2040 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2041 MT7531_EXT_P_MDC_11); 2042 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2043 MT7531_EXT_P_MDIO_12); 2044 } else { 2045 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2046 } 2047 dev_dbg(ds->dev, "P5 support %s interface\n", 2048 p5_intf_modes(priv->p5_intf_sel)); 2049 2050 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2051 MT7531_GPIO0_INTERRUPT); 2052 2053 /* Let phylink decide the interface later. */ 2054 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2055 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2056 2057 /* Enable PHY core PLL, since phy_device has not yet been created 2058 * provided for phy_[read,write]_mmd_indirect is called, we provide 2059 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2060 * function. 2061 */ 2062 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2063 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2064 val |= MT7531_PHY_PLL_BYPASS_MODE; 2065 val &= ~MT7531_PHY_PLL_OFF; 2066 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2067 CORE_PLL_GROUP4, val); 2068 2069 /* BPDU to CPU port */ 2070 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2071 BIT(MT7530_CPU_PORT)); 2072 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2073 MT753X_BPDU_CPU_ONLY); 2074 2075 /* Enable and reset MIB counters */ 2076 mt7530_mib_reset(ds); 2077 2078 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2079 /* Disable forwarding by default on all ports */ 2080 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2081 PCR_MATRIX_CLR); 2082 2083 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2084 2085 if (dsa_is_cpu_port(ds, i)) { 2086 ret = mt753x_cpu_port_enable(ds, i); 2087 if (ret) 2088 return ret; 2089 } else { 2090 mt7530_port_disable(ds, i); 2091 2092 /* Disable learning by default on all user ports */ 2093 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2094 } 2095 2096 /* Enable consistent egress tag */ 2097 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2098 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2099 } 2100 2101 ds->mtu_enforcement_ingress = true; 2102 2103 /* Flush the FDB table */ 2104 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2105 if (ret < 0) 2106 return ret; 2107 2108 return 0; 2109 } 2110 2111 static bool 2112 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2113 const struct phylink_link_state *state) 2114 { 2115 struct mt7530_priv *priv = ds->priv; 2116 2117 switch (port) { 2118 case 0 ... 4: /* Internal phy */ 2119 if (state->interface != PHY_INTERFACE_MODE_GMII) 2120 return false; 2121 break; 2122 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2123 if (!phy_interface_mode_is_rgmii(state->interface) && 2124 state->interface != PHY_INTERFACE_MODE_MII && 2125 state->interface != PHY_INTERFACE_MODE_GMII) 2126 return false; 2127 break; 2128 case 6: /* 1st cpu port */ 2129 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2130 state->interface != PHY_INTERFACE_MODE_TRGMII) 2131 return false; 2132 break; 2133 default: 2134 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2135 port); 2136 return false; 2137 } 2138 2139 return true; 2140 } 2141 2142 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2143 { 2144 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2145 } 2146 2147 static bool 2148 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2149 const struct phylink_link_state *state) 2150 { 2151 struct mt7530_priv *priv = ds->priv; 2152 2153 switch (port) { 2154 case 0 ... 4: /* Internal phy */ 2155 if (state->interface != PHY_INTERFACE_MODE_GMII) 2156 return false; 2157 break; 2158 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2159 if (mt7531_is_rgmii_port(priv, port)) 2160 return phy_interface_mode_is_rgmii(state->interface); 2161 fallthrough; 2162 case 6: /* 1st cpu port supports sgmii/8023z only */ 2163 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2164 !phy_interface_mode_is_8023z(state->interface)) 2165 return false; 2166 break; 2167 default: 2168 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2169 port); 2170 return false; 2171 } 2172 2173 return true; 2174 } 2175 2176 static bool 2177 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2178 const struct phylink_link_state *state) 2179 { 2180 struct mt7530_priv *priv = ds->priv; 2181 2182 return priv->info->phy_mode_supported(ds, port, state); 2183 } 2184 2185 static int 2186 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2187 { 2188 struct mt7530_priv *priv = ds->priv; 2189 2190 return priv->info->pad_setup(ds, state->interface); 2191 } 2192 2193 static int 2194 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2195 phy_interface_t interface) 2196 { 2197 struct mt7530_priv *priv = ds->priv; 2198 2199 /* Only need to setup port5. */ 2200 if (port != 5) 2201 return 0; 2202 2203 mt7530_setup_port5(priv->ds, interface); 2204 2205 return 0; 2206 } 2207 2208 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2209 phy_interface_t interface, 2210 struct phy_device *phydev) 2211 { 2212 u32 val; 2213 2214 if (!mt7531_is_rgmii_port(priv, port)) { 2215 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2216 port); 2217 return -EINVAL; 2218 } 2219 2220 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2221 val |= GP_CLK_EN; 2222 val &= ~GP_MODE_MASK; 2223 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2224 val &= ~CLK_SKEW_IN_MASK; 2225 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2226 val &= ~CLK_SKEW_OUT_MASK; 2227 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2228 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2229 2230 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2231 if (!phydev || phy_driver_is_genphy(phydev)) { 2232 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2233 switch (interface) { 2234 case PHY_INTERFACE_MODE_RGMII: 2235 val |= TXCLK_NO_REVERSE; 2236 val |= RXCLK_NO_DELAY; 2237 break; 2238 case PHY_INTERFACE_MODE_RGMII_RXID: 2239 val |= TXCLK_NO_REVERSE; 2240 break; 2241 case PHY_INTERFACE_MODE_RGMII_TXID: 2242 val |= RXCLK_NO_DELAY; 2243 break; 2244 case PHY_INTERFACE_MODE_RGMII_ID: 2245 break; 2246 default: 2247 return -EINVAL; 2248 } 2249 } 2250 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2251 2252 return 0; 2253 } 2254 2255 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2256 unsigned long *supported) 2257 { 2258 /* Port5 supports ethier RGMII or SGMII. 2259 * Port6 supports SGMII only. 2260 */ 2261 switch (port) { 2262 case 5: 2263 if (mt7531_is_rgmii_port(priv, port)) 2264 break; 2265 fallthrough; 2266 case 6: 2267 phylink_set(supported, 1000baseX_Full); 2268 phylink_set(supported, 2500baseX_Full); 2269 phylink_set(supported, 2500baseT_Full); 2270 } 2271 } 2272 2273 static void 2274 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2275 unsigned int mode, phy_interface_t interface, 2276 int speed, int duplex) 2277 { 2278 struct mt7530_priv *priv = ds->priv; 2279 unsigned int val; 2280 2281 /* For adjusting speed and duplex of SGMII force mode. */ 2282 if (interface != PHY_INTERFACE_MODE_SGMII || 2283 phylink_autoneg_inband(mode)) 2284 return; 2285 2286 /* SGMII force mode setting */ 2287 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2288 val &= ~MT7531_SGMII_IF_MODE_MASK; 2289 2290 switch (speed) { 2291 case SPEED_10: 2292 val |= MT7531_SGMII_FORCE_SPEED_10; 2293 break; 2294 case SPEED_100: 2295 val |= MT7531_SGMII_FORCE_SPEED_100; 2296 break; 2297 case SPEED_1000: 2298 val |= MT7531_SGMII_FORCE_SPEED_1000; 2299 break; 2300 } 2301 2302 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2303 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2304 */ 2305 if ((speed == SPEED_10 || speed == SPEED_100) && 2306 duplex != DUPLEX_FULL) 2307 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2308 2309 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2310 } 2311 2312 static bool mt753x_is_mac_port(u32 port) 2313 { 2314 return (port == 5 || port == 6); 2315 } 2316 2317 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2318 phy_interface_t interface) 2319 { 2320 u32 val; 2321 2322 if (!mt753x_is_mac_port(port)) 2323 return -EINVAL; 2324 2325 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2326 MT7531_SGMII_PHYA_PWD); 2327 2328 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2329 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2330 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2331 * encoding. 2332 */ 2333 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2334 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2335 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2336 2337 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2338 2339 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2340 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2341 */ 2342 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2343 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2344 MT7531_SGMII_FORCE_SPEED_1000); 2345 2346 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2347 2348 return 0; 2349 } 2350 2351 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2352 phy_interface_t interface) 2353 { 2354 if (!mt753x_is_mac_port(port)) 2355 return -EINVAL; 2356 2357 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2358 MT7531_SGMII_PHYA_PWD); 2359 2360 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2361 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2362 2363 mt7530_set(priv, MT7531_SGMII_MODE(port), 2364 MT7531_SGMII_REMOTE_FAULT_DIS | 2365 MT7531_SGMII_SPEED_DUPLEX_AN); 2366 2367 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2368 MT7531_SGMII_TX_CONFIG_MASK, 1); 2369 2370 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2371 2372 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2373 2374 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2375 2376 return 0; 2377 } 2378 2379 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2380 { 2381 struct mt7530_priv *priv = ds->priv; 2382 u32 val; 2383 2384 /* Only restart AN when AN is enabled */ 2385 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2386 if (val & MT7531_SGMII_AN_ENABLE) { 2387 val |= MT7531_SGMII_AN_RESTART; 2388 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2389 } 2390 } 2391 2392 static int 2393 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2394 phy_interface_t interface) 2395 { 2396 struct mt7530_priv *priv = ds->priv; 2397 struct phy_device *phydev; 2398 struct dsa_port *dp; 2399 2400 if (!mt753x_is_mac_port(port)) { 2401 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2402 return -EINVAL; 2403 } 2404 2405 switch (interface) { 2406 case PHY_INTERFACE_MODE_RGMII: 2407 case PHY_INTERFACE_MODE_RGMII_ID: 2408 case PHY_INTERFACE_MODE_RGMII_RXID: 2409 case PHY_INTERFACE_MODE_RGMII_TXID: 2410 dp = dsa_to_port(ds, port); 2411 phydev = dp->slave->phydev; 2412 return mt7531_rgmii_setup(priv, port, interface, phydev); 2413 case PHY_INTERFACE_MODE_SGMII: 2414 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2415 case PHY_INTERFACE_MODE_NA: 2416 case PHY_INTERFACE_MODE_1000BASEX: 2417 case PHY_INTERFACE_MODE_2500BASEX: 2418 if (phylink_autoneg_inband(mode)) 2419 return -EINVAL; 2420 2421 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2422 default: 2423 return -EINVAL; 2424 } 2425 2426 return -EINVAL; 2427 } 2428 2429 static int 2430 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2431 const struct phylink_link_state *state) 2432 { 2433 struct mt7530_priv *priv = ds->priv; 2434 2435 return priv->info->mac_port_config(ds, port, mode, state->interface); 2436 } 2437 2438 static void 2439 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2440 const struct phylink_link_state *state) 2441 { 2442 struct mt7530_priv *priv = ds->priv; 2443 u32 mcr_cur, mcr_new; 2444 2445 if (!mt753x_phy_mode_supported(ds, port, state)) 2446 goto unsupported; 2447 2448 switch (port) { 2449 case 0 ... 4: /* Internal phy */ 2450 if (state->interface != PHY_INTERFACE_MODE_GMII) 2451 goto unsupported; 2452 break; 2453 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2454 if (priv->p5_interface == state->interface) 2455 break; 2456 2457 if (mt753x_mac_config(ds, port, mode, state) < 0) 2458 goto unsupported; 2459 2460 if (priv->p5_intf_sel != P5_DISABLED) 2461 priv->p5_interface = state->interface; 2462 break; 2463 case 6: /* 1st cpu port */ 2464 if (priv->p6_interface == state->interface) 2465 break; 2466 2467 mt753x_pad_setup(ds, state); 2468 2469 if (mt753x_mac_config(ds, port, mode, state) < 0) 2470 goto unsupported; 2471 2472 priv->p6_interface = state->interface; 2473 break; 2474 default: 2475 unsupported: 2476 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2477 __func__, phy_modes(state->interface), port); 2478 return; 2479 } 2480 2481 if (phylink_autoneg_inband(mode) && 2482 state->interface != PHY_INTERFACE_MODE_SGMII) { 2483 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2484 __func__); 2485 return; 2486 } 2487 2488 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2489 mcr_new = mcr_cur; 2490 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2491 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2492 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2493 2494 /* Are we connected to external phy */ 2495 if (port == 5 && dsa_is_user_port(ds, 5)) 2496 mcr_new |= PMCR_EXT_PHY; 2497 2498 if (mcr_new != mcr_cur) 2499 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2500 } 2501 2502 static void 2503 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2504 { 2505 struct mt7530_priv *priv = ds->priv; 2506 2507 if (!priv->info->mac_pcs_an_restart) 2508 return; 2509 2510 priv->info->mac_pcs_an_restart(ds, port); 2511 } 2512 2513 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2514 unsigned int mode, 2515 phy_interface_t interface) 2516 { 2517 struct mt7530_priv *priv = ds->priv; 2518 2519 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2520 } 2521 2522 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2523 unsigned int mode, phy_interface_t interface, 2524 int speed, int duplex) 2525 { 2526 struct mt7530_priv *priv = ds->priv; 2527 2528 if (!priv->info->mac_pcs_link_up) 2529 return; 2530 2531 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2532 } 2533 2534 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2535 unsigned int mode, 2536 phy_interface_t interface, 2537 struct phy_device *phydev, 2538 int speed, int duplex, 2539 bool tx_pause, bool rx_pause) 2540 { 2541 struct mt7530_priv *priv = ds->priv; 2542 u32 mcr; 2543 2544 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2545 2546 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2547 2548 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2549 * variants. 2550 */ 2551 if (interface == PHY_INTERFACE_MODE_TRGMII || 2552 (phy_interface_mode_is_8023z(interface))) { 2553 speed = SPEED_1000; 2554 duplex = DUPLEX_FULL; 2555 } 2556 2557 switch (speed) { 2558 case SPEED_1000: 2559 mcr |= PMCR_FORCE_SPEED_1000; 2560 break; 2561 case SPEED_100: 2562 mcr |= PMCR_FORCE_SPEED_100; 2563 break; 2564 } 2565 if (duplex == DUPLEX_FULL) { 2566 mcr |= PMCR_FORCE_FDX; 2567 if (tx_pause) 2568 mcr |= PMCR_TX_FC_EN; 2569 if (rx_pause) 2570 mcr |= PMCR_RX_FC_EN; 2571 } 2572 2573 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2574 } 2575 2576 static int 2577 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2578 { 2579 struct mt7530_priv *priv = ds->priv; 2580 phy_interface_t interface; 2581 int speed; 2582 int ret; 2583 2584 switch (port) { 2585 case 5: 2586 if (mt7531_is_rgmii_port(priv, port)) 2587 interface = PHY_INTERFACE_MODE_RGMII; 2588 else 2589 interface = PHY_INTERFACE_MODE_2500BASEX; 2590 2591 priv->p5_interface = interface; 2592 break; 2593 case 6: 2594 interface = PHY_INTERFACE_MODE_2500BASEX; 2595 2596 mt7531_pad_setup(ds, interface); 2597 2598 priv->p6_interface = interface; 2599 break; 2600 default: 2601 return -EINVAL; 2602 } 2603 2604 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2605 speed = SPEED_2500; 2606 else 2607 speed = SPEED_1000; 2608 2609 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2610 if (ret) 2611 return ret; 2612 mt7530_write(priv, MT7530_PMCR_P(port), 2613 PMCR_CPU_PORT_SETTING(priv->id)); 2614 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2615 speed, DUPLEX_FULL, true, true); 2616 2617 return 0; 2618 } 2619 2620 static void 2621 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2622 unsigned long *supported) 2623 { 2624 if (port == 5) 2625 phylink_set(supported, 1000baseX_Full); 2626 } 2627 2628 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2629 unsigned long *supported) 2630 { 2631 struct mt7530_priv *priv = ds->priv; 2632 2633 mt7531_sgmii_validate(priv, port, supported); 2634 } 2635 2636 static void 2637 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2638 unsigned long *supported, 2639 struct phylink_link_state *state) 2640 { 2641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2642 struct mt7530_priv *priv = ds->priv; 2643 2644 if (state->interface != PHY_INTERFACE_MODE_NA && 2645 !mt753x_phy_mode_supported(ds, port, state)) { 2646 linkmode_zero(supported); 2647 return; 2648 } 2649 2650 phylink_set_port_modes(mask); 2651 2652 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2653 !phy_interface_mode_is_8023z(state->interface)) { 2654 phylink_set(mask, 10baseT_Half); 2655 phylink_set(mask, 10baseT_Full); 2656 phylink_set(mask, 100baseT_Half); 2657 phylink_set(mask, 100baseT_Full); 2658 phylink_set(mask, Autoneg); 2659 } 2660 2661 /* This switch only supports 1G full-duplex. */ 2662 if (state->interface != PHY_INTERFACE_MODE_MII) 2663 phylink_set(mask, 1000baseT_Full); 2664 2665 priv->info->mac_port_validate(ds, port, mask); 2666 2667 phylink_set(mask, Pause); 2668 phylink_set(mask, Asym_Pause); 2669 2670 linkmode_and(supported, supported, mask); 2671 linkmode_and(state->advertising, state->advertising, mask); 2672 2673 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2674 * to advertise both, only report advertising at 2500BaseX. 2675 */ 2676 phylink_helper_basex_speed(state); 2677 } 2678 2679 static int 2680 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2681 struct phylink_link_state *state) 2682 { 2683 struct mt7530_priv *priv = ds->priv; 2684 u32 pmsr; 2685 2686 if (port < 0 || port >= MT7530_NUM_PORTS) 2687 return -EINVAL; 2688 2689 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2690 2691 state->link = (pmsr & PMSR_LINK); 2692 state->an_complete = state->link; 2693 state->duplex = !!(pmsr & PMSR_DPX); 2694 2695 switch (pmsr & PMSR_SPEED_MASK) { 2696 case PMSR_SPEED_10: 2697 state->speed = SPEED_10; 2698 break; 2699 case PMSR_SPEED_100: 2700 state->speed = SPEED_100; 2701 break; 2702 case PMSR_SPEED_1000: 2703 state->speed = SPEED_1000; 2704 break; 2705 default: 2706 state->speed = SPEED_UNKNOWN; 2707 break; 2708 } 2709 2710 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2711 if (pmsr & PMSR_RX_FC) 2712 state->pause |= MLO_PAUSE_RX; 2713 if (pmsr & PMSR_TX_FC) 2714 state->pause |= MLO_PAUSE_TX; 2715 2716 return 1; 2717 } 2718 2719 static int 2720 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2721 struct phylink_link_state *state) 2722 { 2723 u32 status, val; 2724 u16 config_reg; 2725 2726 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2727 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2728 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2729 (status & MT7531_SGMII_AN_ENABLE)) { 2730 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2731 config_reg = val >> 16; 2732 2733 switch (config_reg & LPA_SGMII_SPD_MASK) { 2734 case LPA_SGMII_1000: 2735 state->speed = SPEED_1000; 2736 break; 2737 case LPA_SGMII_100: 2738 state->speed = SPEED_100; 2739 break; 2740 case LPA_SGMII_10: 2741 state->speed = SPEED_10; 2742 break; 2743 default: 2744 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2745 state->link = false; 2746 return -EINVAL; 2747 } 2748 2749 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2750 state->duplex = DUPLEX_FULL; 2751 else 2752 state->duplex = DUPLEX_HALF; 2753 } 2754 2755 return 0; 2756 } 2757 2758 static int 2759 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2760 struct phylink_link_state *state) 2761 { 2762 struct mt7530_priv *priv = ds->priv; 2763 2764 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2765 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2766 2767 return -EOPNOTSUPP; 2768 } 2769 2770 static int 2771 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2772 struct phylink_link_state *state) 2773 { 2774 struct mt7530_priv *priv = ds->priv; 2775 2776 return priv->info->mac_port_get_state(ds, port, state); 2777 } 2778 2779 static int 2780 mt753x_setup(struct dsa_switch *ds) 2781 { 2782 struct mt7530_priv *priv = ds->priv; 2783 2784 return priv->info->sw_setup(ds); 2785 } 2786 2787 static int 2788 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) 2789 { 2790 struct mt7530_priv *priv = ds->priv; 2791 2792 return priv->info->phy_read(ds, port, regnum); 2793 } 2794 2795 static int 2796 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 2797 { 2798 struct mt7530_priv *priv = ds->priv; 2799 2800 return priv->info->phy_write(ds, port, regnum, val); 2801 } 2802 2803 static const struct dsa_switch_ops mt7530_switch_ops = { 2804 .get_tag_protocol = mtk_get_tag_protocol, 2805 .setup = mt753x_setup, 2806 .get_strings = mt7530_get_strings, 2807 .phy_read = mt753x_phy_read, 2808 .phy_write = mt753x_phy_write, 2809 .get_ethtool_stats = mt7530_get_ethtool_stats, 2810 .get_sset_count = mt7530_get_sset_count, 2811 .set_ageing_time = mt7530_set_ageing_time, 2812 .port_enable = mt7530_port_enable, 2813 .port_disable = mt7530_port_disable, 2814 .port_change_mtu = mt7530_port_change_mtu, 2815 .port_max_mtu = mt7530_port_max_mtu, 2816 .port_stp_state_set = mt7530_stp_state_set, 2817 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 2818 .port_bridge_flags = mt7530_port_bridge_flags, 2819 .port_set_mrouter = mt7530_port_set_mrouter, 2820 .port_bridge_join = mt7530_port_bridge_join, 2821 .port_bridge_leave = mt7530_port_bridge_leave, 2822 .port_fdb_add = mt7530_port_fdb_add, 2823 .port_fdb_del = mt7530_port_fdb_del, 2824 .port_fdb_dump = mt7530_port_fdb_dump, 2825 .port_mdb_add = mt7530_port_mdb_add, 2826 .port_mdb_del = mt7530_port_mdb_del, 2827 .port_vlan_filtering = mt7530_port_vlan_filtering, 2828 .port_vlan_add = mt7530_port_vlan_add, 2829 .port_vlan_del = mt7530_port_vlan_del, 2830 .port_mirror_add = mt753x_port_mirror_add, 2831 .port_mirror_del = mt753x_port_mirror_del, 2832 .phylink_validate = mt753x_phylink_validate, 2833 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 2834 .phylink_mac_config = mt753x_phylink_mac_config, 2835 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 2836 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2837 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2838 }; 2839 2840 static const struct mt753x_info mt753x_table[] = { 2841 [ID_MT7621] = { 2842 .id = ID_MT7621, 2843 .sw_setup = mt7530_setup, 2844 .phy_read = mt7530_phy_read, 2845 .phy_write = mt7530_phy_write, 2846 .pad_setup = mt7530_pad_clk_setup, 2847 .phy_mode_supported = mt7530_phy_mode_supported, 2848 .mac_port_validate = mt7530_mac_port_validate, 2849 .mac_port_get_state = mt7530_phylink_mac_link_state, 2850 .mac_port_config = mt7530_mac_config, 2851 }, 2852 [ID_MT7530] = { 2853 .id = ID_MT7530, 2854 .sw_setup = mt7530_setup, 2855 .phy_read = mt7530_phy_read, 2856 .phy_write = mt7530_phy_write, 2857 .pad_setup = mt7530_pad_clk_setup, 2858 .phy_mode_supported = mt7530_phy_mode_supported, 2859 .mac_port_validate = mt7530_mac_port_validate, 2860 .mac_port_get_state = mt7530_phylink_mac_link_state, 2861 .mac_port_config = mt7530_mac_config, 2862 }, 2863 [ID_MT7531] = { 2864 .id = ID_MT7531, 2865 .sw_setup = mt7531_setup, 2866 .phy_read = mt7531_ind_phy_read, 2867 .phy_write = mt7531_ind_phy_write, 2868 .pad_setup = mt7531_pad_setup, 2869 .cpu_port_config = mt7531_cpu_port_config, 2870 .phy_mode_supported = mt7531_phy_mode_supported, 2871 .mac_port_validate = mt7531_mac_port_validate, 2872 .mac_port_get_state = mt7531_phylink_mac_link_state, 2873 .mac_port_config = mt7531_mac_config, 2874 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 2875 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 2876 }, 2877 }; 2878 2879 static const struct of_device_id mt7530_of_match[] = { 2880 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 2881 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 2882 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 2883 { /* sentinel */ }, 2884 }; 2885 MODULE_DEVICE_TABLE(of, mt7530_of_match); 2886 2887 static int 2888 mt7530_probe(struct mdio_device *mdiodev) 2889 { 2890 struct mt7530_priv *priv; 2891 struct device_node *dn; 2892 2893 dn = mdiodev->dev.of_node; 2894 2895 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2896 if (!priv) 2897 return -ENOMEM; 2898 2899 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2900 if (!priv->ds) 2901 return -ENOMEM; 2902 2903 priv->ds->dev = &mdiodev->dev; 2904 priv->ds->num_ports = DSA_MAX_PORTS; 2905 2906 /* Use medatek,mcm property to distinguish hardware type that would 2907 * casues a little bit differences on power-on sequence. 2908 */ 2909 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 2910 if (priv->mcm) { 2911 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 2912 2913 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 2914 if (IS_ERR(priv->rstc)) { 2915 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2916 return PTR_ERR(priv->rstc); 2917 } 2918 } 2919 2920 /* Get the hardware identifier from the devicetree node. 2921 * We will need it for some of the clock and regulator setup. 2922 */ 2923 priv->info = of_device_get_match_data(&mdiodev->dev); 2924 if (!priv->info) 2925 return -EINVAL; 2926 2927 /* Sanity check if these required device operations are filled 2928 * properly. 2929 */ 2930 if (!priv->info->sw_setup || !priv->info->pad_setup || 2931 !priv->info->phy_read || !priv->info->phy_write || 2932 !priv->info->phy_mode_supported || 2933 !priv->info->mac_port_validate || 2934 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 2935 return -EINVAL; 2936 2937 priv->id = priv->info->id; 2938 2939 if (priv->id == ID_MT7530) { 2940 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 2941 if (IS_ERR(priv->core_pwr)) 2942 return PTR_ERR(priv->core_pwr); 2943 2944 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 2945 if (IS_ERR(priv->io_pwr)) 2946 return PTR_ERR(priv->io_pwr); 2947 } 2948 2949 /* Not MCM that indicates switch works as the remote standalone 2950 * integrated circuit so the GPIO pin would be used to complete 2951 * the reset, otherwise memory-mapped register accessing used 2952 * through syscon provides in the case of MCM. 2953 */ 2954 if (!priv->mcm) { 2955 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 2956 GPIOD_OUT_LOW); 2957 if (IS_ERR(priv->reset)) { 2958 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2959 return PTR_ERR(priv->reset); 2960 } 2961 } 2962 2963 priv->bus = mdiodev->bus; 2964 priv->dev = &mdiodev->dev; 2965 priv->ds->priv = priv; 2966 priv->ds->ops = &mt7530_switch_ops; 2967 mutex_init(&priv->reg_mutex); 2968 dev_set_drvdata(&mdiodev->dev, priv); 2969 2970 return dsa_register_switch(priv->ds); 2971 } 2972 2973 static void 2974 mt7530_remove(struct mdio_device *mdiodev) 2975 { 2976 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 2977 int ret = 0; 2978 2979 ret = regulator_disable(priv->core_pwr); 2980 if (ret < 0) 2981 dev_err(priv->dev, 2982 "Failed to disable core power: %d\n", ret); 2983 2984 ret = regulator_disable(priv->io_pwr); 2985 if (ret < 0) 2986 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 2987 ret); 2988 2989 dsa_unregister_switch(priv->ds); 2990 mutex_destroy(&priv->reg_mutex); 2991 } 2992 2993 static struct mdio_driver mt7530_mdio_driver = { 2994 .probe = mt7530_probe, 2995 .remove = mt7530_remove, 2996 .mdiodrv.driver = { 2997 .name = "mt7530", 2998 .of_match_table = mt7530_of_match, 2999 }, 3000 }; 3001 3002 mdio_module_driver(mt7530_mdio_driver); 3003 3004 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3005 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3006 MODULE_LICENSE("GPL"); 3007