1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/debugfs.h> 21 #include <linux/seq_file.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/platform_device.h> 26 #include <linux/workqueue.h> 27 #include <linux/timer.h> 28 #include <linux/clk.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/io.h> 33 #include <linux/semaphore.h> 34 #include <linux/gpio.h> 35 #include <linux/regulator/consumer.h> 36 #include <plat/dma.h> 37 #include <mach/hardware.h> 38 #include <plat/board.h> 39 #include <plat/mmc.h> 40 #include <plat/cpu.h> 41 42 /* OMAP HSMMC Host Controller Registers */ 43 #define OMAP_HSMMC_SYSCONFIG 0x0010 44 #define OMAP_HSMMC_SYSSTATUS 0x0014 45 #define OMAP_HSMMC_CON 0x002C 46 #define OMAP_HSMMC_BLK 0x0104 47 #define OMAP_HSMMC_ARG 0x0108 48 #define OMAP_HSMMC_CMD 0x010C 49 #define OMAP_HSMMC_RSP10 0x0110 50 #define OMAP_HSMMC_RSP32 0x0114 51 #define OMAP_HSMMC_RSP54 0x0118 52 #define OMAP_HSMMC_RSP76 0x011C 53 #define OMAP_HSMMC_DATA 0x0120 54 #define OMAP_HSMMC_HCTL 0x0128 55 #define OMAP_HSMMC_SYSCTL 0x012C 56 #define OMAP_HSMMC_STAT 0x0130 57 #define OMAP_HSMMC_IE 0x0134 58 #define OMAP_HSMMC_ISE 0x0138 59 #define OMAP_HSMMC_CAPA 0x0140 60 61 #define VS18 (1 << 26) 62 #define VS30 (1 << 25) 63 #define SDVS18 (0x5 << 9) 64 #define SDVS30 (0x6 << 9) 65 #define SDVS33 (0x7 << 9) 66 #define SDVS_MASK 0x00000E00 67 #define SDVSCLR 0xFFFFF1FF 68 #define SDVSDET 0x00000400 69 #define AUTOIDLE 0x1 70 #define SDBP (1 << 8) 71 #define DTO 0xe 72 #define ICE 0x1 73 #define ICS 0x2 74 #define CEN (1 << 2) 75 #define CLKD_MASK 0x0000FFC0 76 #define CLKD_SHIFT 6 77 #define DTO_MASK 0x000F0000 78 #define DTO_SHIFT 16 79 #define INT_EN_MASK 0x307F0033 80 #define BWR_ENABLE (1 << 4) 81 #define BRR_ENABLE (1 << 5) 82 #define DTO_ENABLE (1 << 20) 83 #define INIT_STREAM (1 << 1) 84 #define DP_SELECT (1 << 21) 85 #define DDIR (1 << 4) 86 #define DMA_EN 0x1 87 #define MSBS (1 << 5) 88 #define BCE (1 << 1) 89 #define FOUR_BIT (1 << 1) 90 #define DW8 (1 << 5) 91 #define CC 0x1 92 #define TC 0x02 93 #define OD 0x1 94 #define ERR (1 << 15) 95 #define CMD_TIMEOUT (1 << 16) 96 #define DATA_TIMEOUT (1 << 20) 97 #define CMD_CRC (1 << 17) 98 #define DATA_CRC (1 << 21) 99 #define CARD_ERR (1 << 28) 100 #define STAT_CLEAR 0xFFFFFFFF 101 #define INIT_STREAM_CMD 0x00000000 102 #define DUAL_VOLT_OCR_BIT 7 103 #define SRC (1 << 25) 104 #define SRD (1 << 26) 105 #define SOFTRESET (1 << 1) 106 #define RESETDONE (1 << 0) 107 108 /* 109 * FIXME: Most likely all the data using these _DEVID defines should come 110 * from the platform_data, or implemented in controller and slot specific 111 * functions. 112 */ 113 #define OMAP_MMC1_DEVID 0 114 #define OMAP_MMC2_DEVID 1 115 #define OMAP_MMC3_DEVID 2 116 #define OMAP_MMC4_DEVID 3 117 #define OMAP_MMC5_DEVID 4 118 119 #define MMC_TIMEOUT_MS 20 120 #define OMAP_MMC_MASTER_CLOCK 96000000 121 #define DRIVER_NAME "omap_hsmmc" 122 123 /* Timeouts for entering power saving states on inactivity, msec */ 124 #define OMAP_MMC_DISABLED_TIMEOUT 100 125 #define OMAP_MMC_SLEEP_TIMEOUT 1000 126 #define OMAP_MMC_OFF_TIMEOUT 8000 127 128 /* 129 * One controller can have multiple slots, like on some omap boards using 130 * omap.c controller driver. Luckily this is not currently done on any known 131 * omap_hsmmc.c device. 132 */ 133 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 134 135 /* 136 * MMC Host controller read/write API's 137 */ 138 #define OMAP_HSMMC_READ(base, reg) \ 139 __raw_readl((base) + OMAP_HSMMC_##reg) 140 141 #define OMAP_HSMMC_WRITE(base, reg, val) \ 142 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 143 144 struct omap_hsmmc_host { 145 struct device *dev; 146 struct mmc_host *mmc; 147 struct mmc_request *mrq; 148 struct mmc_command *cmd; 149 struct mmc_data *data; 150 struct clk *fclk; 151 struct clk *iclk; 152 struct clk *dbclk; 153 /* 154 * vcc == configured supply 155 * vcc_aux == optional 156 * - MMC1, supply for DAT4..DAT7 157 * - MMC2/MMC2, external level shifter voltage supply, for 158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 159 */ 160 struct regulator *vcc; 161 struct regulator *vcc_aux; 162 struct work_struct mmc_carddetect_work; 163 void __iomem *base; 164 resource_size_t mapbase; 165 spinlock_t irq_lock; /* Prevent races with irq handler */ 166 unsigned int id; 167 unsigned int dma_len; 168 unsigned int dma_sg_idx; 169 unsigned char bus_mode; 170 unsigned char power_mode; 171 u32 *buffer; 172 u32 bytesleft; 173 int suspended; 174 int irq; 175 int use_dma, dma_ch; 176 int dma_line_tx, dma_line_rx; 177 int slot_id; 178 int got_dbclk; 179 int response_busy; 180 int context_loss; 181 int dpm_state; 182 int vdd; 183 int protect_card; 184 int reqs_blocked; 185 int use_reg; 186 int req_in_progress; 187 188 struct omap_mmc_platform_data *pdata; 189 }; 190 191 static int omap_hsmmc_card_detect(struct device *dev, int slot) 192 { 193 struct omap_mmc_platform_data *mmc = dev->platform_data; 194 195 /* NOTE: assumes card detect signal is active-low */ 196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 197 } 198 199 static int omap_hsmmc_get_wp(struct device *dev, int slot) 200 { 201 struct omap_mmc_platform_data *mmc = dev->platform_data; 202 203 /* NOTE: assumes write protect signal is active-high */ 204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 205 } 206 207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 208 { 209 struct omap_mmc_platform_data *mmc = dev->platform_data; 210 211 /* NOTE: assumes card detect signal is active-low */ 212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 213 } 214 215 #ifdef CONFIG_PM 216 217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 218 { 219 struct omap_mmc_platform_data *mmc = dev->platform_data; 220 221 disable_irq(mmc->slots[0].card_detect_irq); 222 return 0; 223 } 224 225 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 226 { 227 struct omap_mmc_platform_data *mmc = dev->platform_data; 228 229 enable_irq(mmc->slots[0].card_detect_irq); 230 return 0; 231 } 232 233 #else 234 235 #define omap_hsmmc_suspend_cdirq NULL 236 #define omap_hsmmc_resume_cdirq NULL 237 238 #endif 239 240 #ifdef CONFIG_REGULATOR 241 242 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 243 int vdd) 244 { 245 struct omap_hsmmc_host *host = 246 platform_get_drvdata(to_platform_device(dev)); 247 int ret; 248 249 if (mmc_slot(host).before_set_reg) 250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 251 252 if (power_on) 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 254 else 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 256 257 if (mmc_slot(host).after_set_reg) 258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 259 260 return ret; 261 } 262 263 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, 264 int vdd) 265 { 266 struct omap_hsmmc_host *host = 267 platform_get_drvdata(to_platform_device(dev)); 268 int ret = 0; 269 270 /* 271 * If we don't see a Vcc regulator, assume it's a fixed 272 * voltage always-on regulator. 273 */ 274 if (!host->vcc) 275 return 0; 276 277 if (mmc_slot(host).before_set_reg) 278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 279 280 /* 281 * Assume Vcc regulator is used only to power the card ... OMAP 282 * VDDS is used to power the pins, optionally with a transceiver to 283 * support cards using voltages other than VDDS (1.8V nominal). When a 284 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 285 * 286 * In some cases this regulator won't support enable/disable; 287 * e.g. it's a fixed rail for a WLAN chip. 288 * 289 * In other cases vcc_aux switches interface power. Example, for 290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 291 * chips/cards need an interface voltage rail too. 292 */ 293 if (power_on) { 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 295 /* Enable interface voltage rail, if needed */ 296 if (ret == 0 && host->vcc_aux) { 297 ret = regulator_enable(host->vcc_aux); 298 if (ret < 0) 299 ret = mmc_regulator_set_ocr(host->mmc, 300 host->vcc, 0); 301 } 302 } else { 303 /* Shut down the rail */ 304 if (host->vcc_aux) 305 ret = regulator_disable(host->vcc_aux); 306 if (!ret) { 307 /* Then proceed to shut down the local regulator */ 308 ret = mmc_regulator_set_ocr(host->mmc, 309 host->vcc, 0); 310 } 311 } 312 313 if (mmc_slot(host).after_set_reg) 314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 315 316 return ret; 317 } 318 319 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, 320 int vdd) 321 { 322 return 0; 323 } 324 325 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 326 int vdd, int cardsleep) 327 { 328 struct omap_hsmmc_host *host = 329 platform_get_drvdata(to_platform_device(dev)); 330 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 331 332 return regulator_set_mode(host->vcc, mode); 333 } 334 335 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, 336 int vdd, int cardsleep) 337 { 338 struct omap_hsmmc_host *host = 339 platform_get_drvdata(to_platform_device(dev)); 340 int err, mode; 341 342 /* 343 * If we don't see a Vcc regulator, assume it's a fixed 344 * voltage always-on regulator. 345 */ 346 if (!host->vcc) 347 return 0; 348 349 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 350 351 if (!host->vcc_aux) 352 return regulator_set_mode(host->vcc, mode); 353 354 if (cardsleep) { 355 /* VCC can be turned off if card is asleep */ 356 if (sleep) 357 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 358 else 359 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 360 } else 361 err = regulator_set_mode(host->vcc, mode); 362 if (err) 363 return err; 364 365 if (!mmc_slot(host).vcc_aux_disable_is_sleep) 366 return regulator_set_mode(host->vcc_aux, mode); 367 368 if (sleep) 369 return regulator_disable(host->vcc_aux); 370 else 371 return regulator_enable(host->vcc_aux); 372 } 373 374 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, 375 int vdd, int cardsleep) 376 { 377 return 0; 378 } 379 380 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 381 { 382 struct regulator *reg; 383 int ret = 0; 384 int ocr_value = 0; 385 386 switch (host->id) { 387 case OMAP_MMC1_DEVID: 388 /* On-chip level shifting via PBIAS0/PBIAS1 */ 389 mmc_slot(host).set_power = omap_hsmmc_1_set_power; 390 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 391 break; 392 case OMAP_MMC2_DEVID: 393 case OMAP_MMC3_DEVID: 394 case OMAP_MMC5_DEVID: 395 /* Off-chip level shifting, or none */ 396 mmc_slot(host).set_power = omap_hsmmc_235_set_power; 397 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; 398 break; 399 case OMAP_MMC4_DEVID: 400 mmc_slot(host).set_power = omap_hsmmc_4_set_power; 401 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; 402 default: 403 pr_err("MMC%d configuration not supported!\n", host->id); 404 return -EINVAL; 405 } 406 407 reg = regulator_get(host->dev, "vmmc"); 408 if (IS_ERR(reg)) { 409 dev_dbg(host->dev, "vmmc regulator missing\n"); 410 /* 411 * HACK: until fixed.c regulator is usable, 412 * we don't require a main regulator 413 * for MMC2 or MMC3 414 */ 415 if (host->id == OMAP_MMC1_DEVID) { 416 ret = PTR_ERR(reg); 417 goto err; 418 } 419 } else { 420 host->vcc = reg; 421 ocr_value = mmc_regulator_get_ocrmask(reg); 422 if (!mmc_slot(host).ocr_mask) { 423 mmc_slot(host).ocr_mask = ocr_value; 424 } else { 425 if (!(mmc_slot(host).ocr_mask & ocr_value)) { 426 pr_err("MMC%d ocrmask %x is not supported\n", 427 host->id, mmc_slot(host).ocr_mask); 428 mmc_slot(host).ocr_mask = 0; 429 return -EINVAL; 430 } 431 } 432 433 /* Allow an aux regulator */ 434 reg = regulator_get(host->dev, "vmmc_aux"); 435 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 436 437 /* For eMMC do not power off when not in sleep state */ 438 if (mmc_slot(host).no_regulator_off_init) 439 return 0; 440 /* 441 * UGLY HACK: workaround regulator framework bugs. 442 * When the bootloader leaves a supply active, it's 443 * initialized with zero usecount ... and we can't 444 * disable it without first enabling it. Until the 445 * framework is fixed, we need a workaround like this 446 * (which is safe for MMC, but not in general). 447 */ 448 if (regulator_is_enabled(host->vcc) > 0) { 449 regulator_enable(host->vcc); 450 regulator_disable(host->vcc); 451 } 452 if (host->vcc_aux) { 453 if (regulator_is_enabled(reg) > 0) { 454 regulator_enable(reg); 455 regulator_disable(reg); 456 } 457 } 458 } 459 460 return 0; 461 462 err: 463 mmc_slot(host).set_power = NULL; 464 mmc_slot(host).set_sleep = NULL; 465 return ret; 466 } 467 468 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 469 { 470 regulator_put(host->vcc); 471 regulator_put(host->vcc_aux); 472 mmc_slot(host).set_power = NULL; 473 mmc_slot(host).set_sleep = NULL; 474 } 475 476 static inline int omap_hsmmc_have_reg(void) 477 { 478 return 1; 479 } 480 481 #else 482 483 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 484 { 485 return -EINVAL; 486 } 487 488 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 489 { 490 } 491 492 static inline int omap_hsmmc_have_reg(void) 493 { 494 return 0; 495 } 496 497 #endif 498 499 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 500 { 501 int ret; 502 503 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 504 if (pdata->slots[0].cover) 505 pdata->slots[0].get_cover_state = 506 omap_hsmmc_get_cover_state; 507 else 508 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 509 pdata->slots[0].card_detect_irq = 510 gpio_to_irq(pdata->slots[0].switch_pin); 511 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 512 if (ret) 513 return ret; 514 ret = gpio_direction_input(pdata->slots[0].switch_pin); 515 if (ret) 516 goto err_free_sp; 517 } else 518 pdata->slots[0].switch_pin = -EINVAL; 519 520 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 521 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 522 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 523 if (ret) 524 goto err_free_cd; 525 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 526 if (ret) 527 goto err_free_wp; 528 } else 529 pdata->slots[0].gpio_wp = -EINVAL; 530 531 return 0; 532 533 err_free_wp: 534 gpio_free(pdata->slots[0].gpio_wp); 535 err_free_cd: 536 if (gpio_is_valid(pdata->slots[0].switch_pin)) 537 err_free_sp: 538 gpio_free(pdata->slots[0].switch_pin); 539 return ret; 540 } 541 542 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 543 { 544 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 545 gpio_free(pdata->slots[0].gpio_wp); 546 if (gpio_is_valid(pdata->slots[0].switch_pin)) 547 gpio_free(pdata->slots[0].switch_pin); 548 } 549 550 /* 551 * Stop clock to the card 552 */ 553 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 554 { 555 OMAP_HSMMC_WRITE(host->base, SYSCTL, 556 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 557 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 558 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 559 } 560 561 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 562 struct mmc_command *cmd) 563 { 564 unsigned int irq_mask; 565 566 if (host->use_dma) 567 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 568 else 569 irq_mask = INT_EN_MASK; 570 571 /* Disable timeout for erases */ 572 if (cmd->opcode == MMC_ERASE) 573 irq_mask &= ~DTO_ENABLE; 574 575 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 576 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 577 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 578 } 579 580 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 581 { 582 OMAP_HSMMC_WRITE(host->base, ISE, 0); 583 OMAP_HSMMC_WRITE(host->base, IE, 0); 584 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 585 } 586 587 #ifdef CONFIG_PM 588 589 /* 590 * Restore the MMC host context, if it was lost as result of a 591 * power state change. 592 */ 593 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 594 { 595 struct mmc_ios *ios = &host->mmc->ios; 596 struct omap_mmc_platform_data *pdata = host->pdata; 597 int context_loss = 0; 598 u32 hctl, capa, con; 599 u16 dsor = 0; 600 unsigned long timeout; 601 602 if (pdata->get_context_loss_count) { 603 context_loss = pdata->get_context_loss_count(host->dev); 604 if (context_loss < 0) 605 return 1; 606 } 607 608 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 609 context_loss == host->context_loss ? "not " : ""); 610 if (host->context_loss == context_loss) 611 return 1; 612 613 /* Wait for hardware reset */ 614 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 615 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 616 && time_before(jiffies, timeout)) 617 ; 618 619 /* Do software reset */ 620 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 621 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 622 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 623 && time_before(jiffies, timeout)) 624 ; 625 626 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 627 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 628 629 if (host->id == OMAP_MMC1_DEVID) { 630 if (host->power_mode != MMC_POWER_OFF && 631 (1 << ios->vdd) <= MMC_VDD_23_24) 632 hctl = SDVS18; 633 else 634 hctl = SDVS30; 635 capa = VS30 | VS18; 636 } else { 637 hctl = SDVS18; 638 capa = VS18; 639 } 640 641 OMAP_HSMMC_WRITE(host->base, HCTL, 642 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 643 644 OMAP_HSMMC_WRITE(host->base, CAPA, 645 OMAP_HSMMC_READ(host->base, CAPA) | capa); 646 647 OMAP_HSMMC_WRITE(host->base, HCTL, 648 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 649 650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 651 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 652 && time_before(jiffies, timeout)) 653 ; 654 655 omap_hsmmc_disable_irq(host); 656 657 /* Do not initialize card-specific things if the power is off */ 658 if (host->power_mode == MMC_POWER_OFF) 659 goto out; 660 661 con = OMAP_HSMMC_READ(host->base, CON); 662 switch (ios->bus_width) { 663 case MMC_BUS_WIDTH_8: 664 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 665 break; 666 case MMC_BUS_WIDTH_4: 667 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 668 OMAP_HSMMC_WRITE(host->base, HCTL, 669 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 670 break; 671 case MMC_BUS_WIDTH_1: 672 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 673 OMAP_HSMMC_WRITE(host->base, HCTL, 674 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 675 break; 676 } 677 678 if (ios->clock) { 679 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 680 if (dsor < 1) 681 dsor = 1; 682 683 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 684 dsor++; 685 686 if (dsor > 250) 687 dsor = 250; 688 } 689 690 OMAP_HSMMC_WRITE(host->base, SYSCTL, 691 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 692 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 693 OMAP_HSMMC_WRITE(host->base, SYSCTL, 694 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 695 696 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 697 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 698 && time_before(jiffies, timeout)) 699 ; 700 701 OMAP_HSMMC_WRITE(host->base, SYSCTL, 702 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 703 704 con = OMAP_HSMMC_READ(host->base, CON); 705 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 706 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 707 else 708 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 709 out: 710 host->context_loss = context_loss; 711 712 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 713 return 0; 714 } 715 716 /* 717 * Save the MMC host context (store the number of power state changes so far). 718 */ 719 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 720 { 721 struct omap_mmc_platform_data *pdata = host->pdata; 722 int context_loss; 723 724 if (pdata->get_context_loss_count) { 725 context_loss = pdata->get_context_loss_count(host->dev); 726 if (context_loss < 0) 727 return; 728 host->context_loss = context_loss; 729 } 730 } 731 732 #else 733 734 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 735 { 736 return 0; 737 } 738 739 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 740 { 741 } 742 743 #endif 744 745 /* 746 * Send init stream sequence to card 747 * before sending IDLE command 748 */ 749 static void send_init_stream(struct omap_hsmmc_host *host) 750 { 751 int reg = 0; 752 unsigned long timeout; 753 754 if (host->protect_card) 755 return; 756 757 disable_irq(host->irq); 758 759 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 760 OMAP_HSMMC_WRITE(host->base, CON, 761 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 762 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 763 764 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 765 while ((reg != CC) && time_before(jiffies, timeout)) 766 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 767 768 OMAP_HSMMC_WRITE(host->base, CON, 769 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 770 771 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 772 OMAP_HSMMC_READ(host->base, STAT); 773 774 enable_irq(host->irq); 775 } 776 777 static inline 778 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 779 { 780 int r = 1; 781 782 if (mmc_slot(host).get_cover_state) 783 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 784 return r; 785 } 786 787 static ssize_t 788 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 789 char *buf) 790 { 791 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 792 struct omap_hsmmc_host *host = mmc_priv(mmc); 793 794 return sprintf(buf, "%s\n", 795 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 796 } 797 798 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 799 800 static ssize_t 801 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 802 char *buf) 803 { 804 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 805 struct omap_hsmmc_host *host = mmc_priv(mmc); 806 807 return sprintf(buf, "%s\n", mmc_slot(host).name); 808 } 809 810 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 811 812 /* 813 * Configure the response type and send the cmd. 814 */ 815 static void 816 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 817 struct mmc_data *data) 818 { 819 int cmdreg = 0, resptype = 0, cmdtype = 0; 820 821 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 822 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 823 host->cmd = cmd; 824 825 omap_hsmmc_enable_irq(host, cmd); 826 827 host->response_busy = 0; 828 if (cmd->flags & MMC_RSP_PRESENT) { 829 if (cmd->flags & MMC_RSP_136) 830 resptype = 1; 831 else if (cmd->flags & MMC_RSP_BUSY) { 832 resptype = 3; 833 host->response_busy = 1; 834 } else 835 resptype = 2; 836 } 837 838 /* 839 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 840 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 841 * a val of 0x3, rest 0x0. 842 */ 843 if (cmd == host->mrq->stop) 844 cmdtype = 0x3; 845 846 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 847 848 if (data) { 849 cmdreg |= DP_SELECT | MSBS | BCE; 850 if (data->flags & MMC_DATA_READ) 851 cmdreg |= DDIR; 852 else 853 cmdreg &= ~(DDIR); 854 } 855 856 if (host->use_dma) 857 cmdreg |= DMA_EN; 858 859 host->req_in_progress = 1; 860 861 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 862 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 863 } 864 865 static int 866 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 867 { 868 if (data->flags & MMC_DATA_WRITE) 869 return DMA_TO_DEVICE; 870 else 871 return DMA_FROM_DEVICE; 872 } 873 874 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 875 { 876 int dma_ch; 877 878 spin_lock(&host->irq_lock); 879 host->req_in_progress = 0; 880 dma_ch = host->dma_ch; 881 spin_unlock(&host->irq_lock); 882 883 omap_hsmmc_disable_irq(host); 884 /* Do not complete the request if DMA is still in progress */ 885 if (mrq->data && host->use_dma && dma_ch != -1) 886 return; 887 host->mrq = NULL; 888 mmc_request_done(host->mmc, mrq); 889 } 890 891 /* 892 * Notify the transfer complete to MMC core 893 */ 894 static void 895 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 896 { 897 if (!data) { 898 struct mmc_request *mrq = host->mrq; 899 900 /* TC before CC from CMD6 - don't know why, but it happens */ 901 if (host->cmd && host->cmd->opcode == 6 && 902 host->response_busy) { 903 host->response_busy = 0; 904 return; 905 } 906 907 omap_hsmmc_request_done(host, mrq); 908 return; 909 } 910 911 host->data = NULL; 912 913 if (!data->error) 914 data->bytes_xfered += data->blocks * (data->blksz); 915 else 916 data->bytes_xfered = 0; 917 918 if (!data->stop) { 919 omap_hsmmc_request_done(host, data->mrq); 920 return; 921 } 922 omap_hsmmc_start_command(host, data->stop, NULL); 923 } 924 925 /* 926 * Notify the core about command completion 927 */ 928 static void 929 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 930 { 931 host->cmd = NULL; 932 933 if (cmd->flags & MMC_RSP_PRESENT) { 934 if (cmd->flags & MMC_RSP_136) { 935 /* response type 2 */ 936 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 937 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 938 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 939 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 940 } else { 941 /* response types 1, 1b, 3, 4, 5, 6 */ 942 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 943 } 944 } 945 if ((host->data == NULL && !host->response_busy) || cmd->error) 946 omap_hsmmc_request_done(host, cmd->mrq); 947 } 948 949 /* 950 * DMA clean up for command errors 951 */ 952 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 953 { 954 int dma_ch; 955 956 host->data->error = errno; 957 958 spin_lock(&host->irq_lock); 959 dma_ch = host->dma_ch; 960 host->dma_ch = -1; 961 spin_unlock(&host->irq_lock); 962 963 if (host->use_dma && dma_ch != -1) { 964 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, 965 host->data->sg_len, 966 omap_hsmmc_get_dma_dir(host, host->data)); 967 omap_free_dma(dma_ch); 968 } 969 host->data = NULL; 970 } 971 972 /* 973 * Readable error output 974 */ 975 #ifdef CONFIG_MMC_DEBUG 976 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 977 { 978 /* --- means reserved bit without definition at documentation */ 979 static const char *omap_hsmmc_status_bits[] = { 980 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 981 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 982 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 983 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 984 }; 985 char res[256]; 986 char *buf = res; 987 int len, i; 988 989 len = sprintf(buf, "MMC IRQ 0x%x :", status); 990 buf += len; 991 992 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 993 if (status & (1 << i)) { 994 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 995 buf += len; 996 } 997 998 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 999 } 1000 #endif /* CONFIG_MMC_DEBUG */ 1001 1002 /* 1003 * MMC controller internal state machines reset 1004 * 1005 * Used to reset command or data internal state machines, using respectively 1006 * SRC or SRD bit of SYSCTL register 1007 * Can be called from interrupt context 1008 */ 1009 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 1010 unsigned long bit) 1011 { 1012 unsigned long i = 0; 1013 unsigned long limit = (loops_per_jiffy * 1014 msecs_to_jiffies(MMC_TIMEOUT_MS)); 1015 1016 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1017 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 1018 1019 /* 1020 * OMAP4 ES2 and greater has an updated reset logic. 1021 * Monitor a 0->1 transition first 1022 */ 1023 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1024 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 1025 && (i++ < limit)) 1026 cpu_relax(); 1027 } 1028 i = 0; 1029 1030 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 1031 (i++ < limit)) 1032 cpu_relax(); 1033 1034 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1035 dev_err(mmc_dev(host->mmc), 1036 "Timeout waiting on controller reset in %s\n", 1037 __func__); 1038 } 1039 1040 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1041 { 1042 struct mmc_data *data; 1043 int end_cmd = 0, end_trans = 0; 1044 1045 if (!host->req_in_progress) { 1046 do { 1047 OMAP_HSMMC_WRITE(host->base, STAT, status); 1048 /* Flush posted write */ 1049 status = OMAP_HSMMC_READ(host->base, STAT); 1050 } while (status & INT_EN_MASK); 1051 return; 1052 } 1053 1054 data = host->data; 1055 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1056 1057 if (status & ERR) { 1058 #ifdef CONFIG_MMC_DEBUG 1059 omap_hsmmc_report_irq(host, status); 1060 #endif 1061 if ((status & CMD_TIMEOUT) || 1062 (status & CMD_CRC)) { 1063 if (host->cmd) { 1064 if (status & CMD_TIMEOUT) { 1065 omap_hsmmc_reset_controller_fsm(host, 1066 SRC); 1067 host->cmd->error = -ETIMEDOUT; 1068 } else { 1069 host->cmd->error = -EILSEQ; 1070 } 1071 end_cmd = 1; 1072 } 1073 if (host->data || host->response_busy) { 1074 if (host->data) 1075 omap_hsmmc_dma_cleanup(host, 1076 -ETIMEDOUT); 1077 host->response_busy = 0; 1078 omap_hsmmc_reset_controller_fsm(host, SRD); 1079 } 1080 } 1081 if ((status & DATA_TIMEOUT) || 1082 (status & DATA_CRC)) { 1083 if (host->data || host->response_busy) { 1084 int err = (status & DATA_TIMEOUT) ? 1085 -ETIMEDOUT : -EILSEQ; 1086 1087 if (host->data) 1088 omap_hsmmc_dma_cleanup(host, err); 1089 else 1090 host->mrq->cmd->error = err; 1091 host->response_busy = 0; 1092 omap_hsmmc_reset_controller_fsm(host, SRD); 1093 end_trans = 1; 1094 } 1095 } 1096 if (status & CARD_ERR) { 1097 dev_dbg(mmc_dev(host->mmc), 1098 "Ignoring card err CMD%d\n", host->cmd->opcode); 1099 if (host->cmd) 1100 end_cmd = 1; 1101 if (host->data) 1102 end_trans = 1; 1103 } 1104 } 1105 1106 OMAP_HSMMC_WRITE(host->base, STAT, status); 1107 1108 if (end_cmd || ((status & CC) && host->cmd)) 1109 omap_hsmmc_cmd_done(host, host->cmd); 1110 if ((end_trans || (status & TC)) && host->mrq) 1111 omap_hsmmc_xfer_done(host, data); 1112 } 1113 1114 /* 1115 * MMC controller IRQ handler 1116 */ 1117 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1118 { 1119 struct omap_hsmmc_host *host = dev_id; 1120 int status; 1121 1122 status = OMAP_HSMMC_READ(host->base, STAT); 1123 do { 1124 omap_hsmmc_do_irq(host, status); 1125 /* Flush posted write */ 1126 status = OMAP_HSMMC_READ(host->base, STAT); 1127 } while (status & INT_EN_MASK); 1128 1129 return IRQ_HANDLED; 1130 } 1131 1132 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1133 { 1134 unsigned long i; 1135 1136 OMAP_HSMMC_WRITE(host->base, HCTL, 1137 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1138 for (i = 0; i < loops_per_jiffy; i++) { 1139 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1140 break; 1141 cpu_relax(); 1142 } 1143 } 1144 1145 /* 1146 * Switch MMC interface voltage ... only relevant for MMC1. 1147 * 1148 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1149 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1150 * Some chips, like eMMC ones, use internal transceivers. 1151 */ 1152 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1153 { 1154 u32 reg_val = 0; 1155 int ret; 1156 1157 /* Disable the clocks */ 1158 clk_disable(host->fclk); 1159 clk_disable(host->iclk); 1160 if (host->got_dbclk) 1161 clk_disable(host->dbclk); 1162 1163 /* Turn the power off */ 1164 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1165 1166 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1167 if (!ret) 1168 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1169 vdd); 1170 clk_enable(host->iclk); 1171 clk_enable(host->fclk); 1172 if (host->got_dbclk) 1173 clk_enable(host->dbclk); 1174 1175 if (ret != 0) 1176 goto err; 1177 1178 OMAP_HSMMC_WRITE(host->base, HCTL, 1179 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1180 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1181 1182 /* 1183 * If a MMC dual voltage card is detected, the set_ios fn calls 1184 * this fn with VDD bit set for 1.8V. Upon card removal from the 1185 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1186 * 1187 * Cope with a bit of slop in the range ... per data sheets: 1188 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1189 * but recommended values are 1.71V to 1.89V 1190 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1191 * but recommended values are 2.7V to 3.3V 1192 * 1193 * Board setup code shouldn't permit anything very out-of-range. 1194 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1195 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1196 */ 1197 if ((1 << vdd) <= MMC_VDD_23_24) 1198 reg_val |= SDVS18; 1199 else 1200 reg_val |= SDVS30; 1201 1202 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1203 set_sd_bus_power(host); 1204 1205 return 0; 1206 err: 1207 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1208 return ret; 1209 } 1210 1211 /* Protect the card while the cover is open */ 1212 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1213 { 1214 if (!mmc_slot(host).get_cover_state) 1215 return; 1216 1217 host->reqs_blocked = 0; 1218 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1219 if (host->protect_card) { 1220 printk(KERN_INFO "%s: cover is closed, " 1221 "card is now accessible\n", 1222 mmc_hostname(host->mmc)); 1223 host->protect_card = 0; 1224 } 1225 } else { 1226 if (!host->protect_card) { 1227 printk(KERN_INFO "%s: cover is open, " 1228 "card is now inaccessible\n", 1229 mmc_hostname(host->mmc)); 1230 host->protect_card = 1; 1231 } 1232 } 1233 } 1234 1235 /* 1236 * Work Item to notify the core about card insertion/removal 1237 */ 1238 static void omap_hsmmc_detect(struct work_struct *work) 1239 { 1240 struct omap_hsmmc_host *host = 1241 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1242 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1243 int carddetect; 1244 1245 if (host->suspended) 1246 return; 1247 1248 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1249 1250 if (slot->card_detect) 1251 carddetect = slot->card_detect(host->dev, host->slot_id); 1252 else { 1253 omap_hsmmc_protect_card(host); 1254 carddetect = -ENOSYS; 1255 } 1256 1257 if (carddetect) 1258 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1259 else 1260 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1261 } 1262 1263 /* 1264 * ISR for handling card insertion and removal 1265 */ 1266 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1267 { 1268 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1269 1270 if (host->suspended) 1271 return IRQ_HANDLED; 1272 schedule_work(&host->mmc_carddetect_work); 1273 1274 return IRQ_HANDLED; 1275 } 1276 1277 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 1278 struct mmc_data *data) 1279 { 1280 int sync_dev; 1281 1282 if (data->flags & MMC_DATA_WRITE) 1283 sync_dev = host->dma_line_tx; 1284 else 1285 sync_dev = host->dma_line_rx; 1286 return sync_dev; 1287 } 1288 1289 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 1290 struct mmc_data *data, 1291 struct scatterlist *sgl) 1292 { 1293 int blksz, nblk, dma_ch; 1294 1295 dma_ch = host->dma_ch; 1296 if (data->flags & MMC_DATA_WRITE) { 1297 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1298 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1299 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1300 sg_dma_address(sgl), 0, 0); 1301 } else { 1302 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1303 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1304 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1305 sg_dma_address(sgl), 0, 0); 1306 } 1307 1308 blksz = host->data->blksz; 1309 nblk = sg_dma_len(sgl) / blksz; 1310 1311 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 1312 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 1313 omap_hsmmc_get_dma_sync_dev(host, data), 1314 !(data->flags & MMC_DATA_WRITE)); 1315 1316 omap_start_dma(dma_ch); 1317 } 1318 1319 /* 1320 * DMA call back function 1321 */ 1322 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1323 { 1324 struct omap_hsmmc_host *host = cb_data; 1325 struct mmc_data *data = host->mrq->data; 1326 int dma_ch, req_in_progress; 1327 1328 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1329 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1330 ch_status); 1331 return; 1332 } 1333 1334 spin_lock(&host->irq_lock); 1335 if (host->dma_ch < 0) { 1336 spin_unlock(&host->irq_lock); 1337 return; 1338 } 1339 1340 host->dma_sg_idx++; 1341 if (host->dma_sg_idx < host->dma_len) { 1342 /* Fire up the next transfer. */ 1343 omap_hsmmc_config_dma_params(host, data, 1344 data->sg + host->dma_sg_idx); 1345 spin_unlock(&host->irq_lock); 1346 return; 1347 } 1348 1349 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1350 omap_hsmmc_get_dma_dir(host, data)); 1351 1352 req_in_progress = host->req_in_progress; 1353 dma_ch = host->dma_ch; 1354 host->dma_ch = -1; 1355 spin_unlock(&host->irq_lock); 1356 1357 omap_free_dma(dma_ch); 1358 1359 /* If DMA has finished after TC, complete the request */ 1360 if (!req_in_progress) { 1361 struct mmc_request *mrq = host->mrq; 1362 1363 host->mrq = NULL; 1364 mmc_request_done(host->mmc, mrq); 1365 } 1366 } 1367 1368 /* 1369 * Routine to configure and start DMA for the MMC card 1370 */ 1371 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1372 struct mmc_request *req) 1373 { 1374 int dma_ch = 0, ret = 0, i; 1375 struct mmc_data *data = req->data; 1376 1377 /* Sanity check: all the SG entries must be aligned by block size. */ 1378 for (i = 0; i < data->sg_len; i++) { 1379 struct scatterlist *sgl; 1380 1381 sgl = data->sg + i; 1382 if (sgl->length % data->blksz) 1383 return -EINVAL; 1384 } 1385 if ((data->blksz % 4) != 0) 1386 /* REVISIT: The MMC buffer increments only when MSB is written. 1387 * Return error for blksz which is non multiple of four. 1388 */ 1389 return -EINVAL; 1390 1391 BUG_ON(host->dma_ch != -1); 1392 1393 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 1394 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1395 if (ret != 0) { 1396 dev_err(mmc_dev(host->mmc), 1397 "%s: omap_request_dma() failed with %d\n", 1398 mmc_hostname(host->mmc), ret); 1399 return ret; 1400 } 1401 1402 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1403 data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 1404 host->dma_ch = dma_ch; 1405 host->dma_sg_idx = 0; 1406 1407 omap_hsmmc_config_dma_params(host, data, data->sg); 1408 1409 return 0; 1410 } 1411 1412 static void set_data_timeout(struct omap_hsmmc_host *host, 1413 unsigned int timeout_ns, 1414 unsigned int timeout_clks) 1415 { 1416 unsigned int timeout, cycle_ns; 1417 uint32_t reg, clkd, dto = 0; 1418 1419 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1420 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1421 if (clkd == 0) 1422 clkd = 1; 1423 1424 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1425 timeout = timeout_ns / cycle_ns; 1426 timeout += timeout_clks; 1427 if (timeout) { 1428 while ((timeout & 0x80000000) == 0) { 1429 dto += 1; 1430 timeout <<= 1; 1431 } 1432 dto = 31 - dto; 1433 timeout <<= 1; 1434 if (timeout && dto) 1435 dto += 1; 1436 if (dto >= 13) 1437 dto -= 13; 1438 else 1439 dto = 0; 1440 if (dto > 14) 1441 dto = 14; 1442 } 1443 1444 reg &= ~DTO_MASK; 1445 reg |= dto << DTO_SHIFT; 1446 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1447 } 1448 1449 /* 1450 * Configure block length for MMC/SD cards and initiate the transfer. 1451 */ 1452 static int 1453 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1454 { 1455 int ret; 1456 host->data = req->data; 1457 1458 if (req->data == NULL) { 1459 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1460 /* 1461 * Set an arbitrary 100ms data timeout for commands with 1462 * busy signal. 1463 */ 1464 if (req->cmd->flags & MMC_RSP_BUSY) 1465 set_data_timeout(host, 100000000U, 0); 1466 return 0; 1467 } 1468 1469 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1470 | (req->data->blocks << 16)); 1471 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1472 1473 if (host->use_dma) { 1474 ret = omap_hsmmc_start_dma_transfer(host, req); 1475 if (ret != 0) { 1476 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1477 return ret; 1478 } 1479 } 1480 return 0; 1481 } 1482 1483 /* 1484 * Request function. for read/write operation 1485 */ 1486 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1487 { 1488 struct omap_hsmmc_host *host = mmc_priv(mmc); 1489 int err; 1490 1491 BUG_ON(host->req_in_progress); 1492 BUG_ON(host->dma_ch != -1); 1493 if (host->protect_card) { 1494 if (host->reqs_blocked < 3) { 1495 /* 1496 * Ensure the controller is left in a consistent 1497 * state by resetting the command and data state 1498 * machines. 1499 */ 1500 omap_hsmmc_reset_controller_fsm(host, SRD); 1501 omap_hsmmc_reset_controller_fsm(host, SRC); 1502 host->reqs_blocked += 1; 1503 } 1504 req->cmd->error = -EBADF; 1505 if (req->data) 1506 req->data->error = -EBADF; 1507 req->cmd->retries = 0; 1508 mmc_request_done(mmc, req); 1509 return; 1510 } else if (host->reqs_blocked) 1511 host->reqs_blocked = 0; 1512 WARN_ON(host->mrq != NULL); 1513 host->mrq = req; 1514 err = omap_hsmmc_prepare_data(host, req); 1515 if (err) { 1516 req->cmd->error = err; 1517 if (req->data) 1518 req->data->error = err; 1519 host->mrq = NULL; 1520 mmc_request_done(mmc, req); 1521 return; 1522 } 1523 1524 omap_hsmmc_start_command(host, req->cmd, req->data); 1525 } 1526 1527 /* Routine to configure clock values. Exposed API to core */ 1528 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1529 { 1530 struct omap_hsmmc_host *host = mmc_priv(mmc); 1531 u16 dsor = 0; 1532 unsigned long regval; 1533 unsigned long timeout; 1534 u32 con; 1535 int do_send_init_stream = 0; 1536 1537 mmc_host_enable(host->mmc); 1538 1539 if (ios->power_mode != host->power_mode) { 1540 switch (ios->power_mode) { 1541 case MMC_POWER_OFF: 1542 mmc_slot(host).set_power(host->dev, host->slot_id, 1543 0, 0); 1544 host->vdd = 0; 1545 break; 1546 case MMC_POWER_UP: 1547 mmc_slot(host).set_power(host->dev, host->slot_id, 1548 1, ios->vdd); 1549 host->vdd = ios->vdd; 1550 break; 1551 case MMC_POWER_ON: 1552 do_send_init_stream = 1; 1553 break; 1554 } 1555 host->power_mode = ios->power_mode; 1556 } 1557 1558 /* FIXME: set registers based only on changes to ios */ 1559 1560 con = OMAP_HSMMC_READ(host->base, CON); 1561 switch (mmc->ios.bus_width) { 1562 case MMC_BUS_WIDTH_8: 1563 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 1564 break; 1565 case MMC_BUS_WIDTH_4: 1566 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1567 OMAP_HSMMC_WRITE(host->base, HCTL, 1568 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1569 break; 1570 case MMC_BUS_WIDTH_1: 1571 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1572 OMAP_HSMMC_WRITE(host->base, HCTL, 1573 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1574 break; 1575 } 1576 1577 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1578 /* Only MMC1 can interface at 3V without some flavor 1579 * of external transceiver; but they all handle 1.8V. 1580 */ 1581 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1582 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1583 /* 1584 * The mmc_select_voltage fn of the core does 1585 * not seem to set the power_mode to 1586 * MMC_POWER_UP upon recalculating the voltage. 1587 * vdd 1.8v. 1588 */ 1589 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1590 dev_dbg(mmc_dev(host->mmc), 1591 "Switch operation failed\n"); 1592 } 1593 } 1594 1595 if (ios->clock) { 1596 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1597 if (dsor < 1) 1598 dsor = 1; 1599 1600 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1601 dsor++; 1602 1603 if (dsor > 250) 1604 dsor = 250; 1605 } 1606 omap_hsmmc_stop_clock(host); 1607 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1608 regval = regval & ~(CLKD_MASK); 1609 regval = regval | (dsor << 6) | (DTO << 16); 1610 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1611 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1612 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1613 1614 /* Wait till the ICS bit is set */ 1615 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 1616 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1617 && time_before(jiffies, timeout)) 1618 msleep(1); 1619 1620 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1621 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1622 1623 if (do_send_init_stream) 1624 send_init_stream(host); 1625 1626 con = OMAP_HSMMC_READ(host->base, CON); 1627 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1628 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1629 else 1630 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 1631 1632 if (host->power_mode == MMC_POWER_OFF) 1633 mmc_host_disable(host->mmc); 1634 else 1635 mmc_host_lazy_disable(host->mmc); 1636 } 1637 1638 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1639 { 1640 struct omap_hsmmc_host *host = mmc_priv(mmc); 1641 1642 if (!mmc_slot(host).card_detect) 1643 return -ENOSYS; 1644 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1645 } 1646 1647 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1648 { 1649 struct omap_hsmmc_host *host = mmc_priv(mmc); 1650 1651 if (!mmc_slot(host).get_ro) 1652 return -ENOSYS; 1653 return mmc_slot(host).get_ro(host->dev, 0); 1654 } 1655 1656 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1657 { 1658 struct omap_hsmmc_host *host = mmc_priv(mmc); 1659 1660 if (mmc_slot(host).init_card) 1661 mmc_slot(host).init_card(card); 1662 } 1663 1664 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1665 { 1666 u32 hctl, capa, value; 1667 1668 /* Only MMC1 supports 3.0V */ 1669 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1670 hctl = SDVS30; 1671 capa = VS30 | VS18; 1672 } else { 1673 hctl = SDVS18; 1674 capa = VS18; 1675 } 1676 1677 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1678 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1679 1680 value = OMAP_HSMMC_READ(host->base, CAPA); 1681 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1682 1683 /* Set the controller to AUTO IDLE mode */ 1684 value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 1685 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 1686 1687 /* Set SD bus power bit */ 1688 set_sd_bus_power(host); 1689 } 1690 1691 /* 1692 * Dynamic power saving handling, FSM: 1693 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 1694 * ^___________| | | 1695 * |______________________|______________________| 1696 * 1697 * ENABLED: mmc host is fully functional 1698 * DISABLED: fclk is off 1699 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1700 * REGSLEEP: fclk is off, voltage regulator is asleep 1701 * OFF: fclk is off, voltage regulator is off 1702 * 1703 * Transition handlers return the timeout for the next state transition 1704 * or negative error. 1705 */ 1706 1707 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1708 1709 /* Handler for [ENABLED -> DISABLED] transition */ 1710 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1711 { 1712 omap_hsmmc_context_save(host); 1713 clk_disable(host->fclk); 1714 host->dpm_state = DISABLED; 1715 1716 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1717 1718 if (host->power_mode == MMC_POWER_OFF) 1719 return 0; 1720 1721 return OMAP_MMC_SLEEP_TIMEOUT; 1722 } 1723 1724 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 1725 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1726 { 1727 int err, new_state; 1728 1729 if (!mmc_try_claim_host(host->mmc)) 1730 return 0; 1731 1732 clk_enable(host->fclk); 1733 omap_hsmmc_context_restore(host); 1734 if (mmc_card_can_sleep(host->mmc)) { 1735 err = mmc_card_sleep(host->mmc); 1736 if (err < 0) { 1737 clk_disable(host->fclk); 1738 mmc_release_host(host->mmc); 1739 return err; 1740 } 1741 new_state = CARDSLEEP; 1742 } else { 1743 new_state = REGSLEEP; 1744 } 1745 if (mmc_slot(host).set_sleep) 1746 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 1747 new_state == CARDSLEEP); 1748 /* FIXME: turn off bus power and perhaps interrupts too */ 1749 clk_disable(host->fclk); 1750 host->dpm_state = new_state; 1751 1752 mmc_release_host(host->mmc); 1753 1754 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 1755 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1756 1757 if (mmc_slot(host).no_off) 1758 return 0; 1759 1760 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1761 mmc_slot(host).card_detect || 1762 (mmc_slot(host).get_cover_state && 1763 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 1764 return OMAP_MMC_OFF_TIMEOUT; 1765 1766 return 0; 1767 } 1768 1769 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 1770 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 1771 { 1772 if (!mmc_try_claim_host(host->mmc)) 1773 return 0; 1774 1775 if (mmc_slot(host).no_off) 1776 return 0; 1777 1778 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1779 mmc_slot(host).card_detect || 1780 (mmc_slot(host).get_cover_state && 1781 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 1782 mmc_release_host(host->mmc); 1783 return 0; 1784 } 1785 1786 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1787 host->vdd = 0; 1788 host->power_mode = MMC_POWER_OFF; 1789 1790 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 1791 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1792 1793 host->dpm_state = OFF; 1794 1795 mmc_release_host(host->mmc); 1796 1797 return 0; 1798 } 1799 1800 /* Handler for [DISABLED -> ENABLED] transition */ 1801 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1802 { 1803 int err; 1804 1805 err = clk_enable(host->fclk); 1806 if (err < 0) 1807 return err; 1808 1809 omap_hsmmc_context_restore(host); 1810 host->dpm_state = ENABLED; 1811 1812 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1813 1814 return 0; 1815 } 1816 1817 /* Handler for [SLEEP -> ENABLED] transition */ 1818 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 1819 { 1820 if (!mmc_try_claim_host(host->mmc)) 1821 return 0; 1822 1823 clk_enable(host->fclk); 1824 omap_hsmmc_context_restore(host); 1825 if (mmc_slot(host).set_sleep) 1826 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 1827 host->vdd, host->dpm_state == CARDSLEEP); 1828 if (mmc_card_can_sleep(host->mmc)) 1829 mmc_card_awake(host->mmc); 1830 1831 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 1832 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1833 1834 host->dpm_state = ENABLED; 1835 1836 mmc_release_host(host->mmc); 1837 1838 return 0; 1839 } 1840 1841 /* Handler for [OFF -> ENABLED] transition */ 1842 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1843 { 1844 clk_enable(host->fclk); 1845 1846 omap_hsmmc_context_restore(host); 1847 omap_hsmmc_conf_bus_power(host); 1848 mmc_power_restore_host(host->mmc); 1849 1850 host->dpm_state = ENABLED; 1851 1852 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1853 1854 return 0; 1855 } 1856 1857 /* 1858 * Bring MMC host to ENABLED from any other PM state. 1859 */ 1860 static int omap_hsmmc_enable(struct mmc_host *mmc) 1861 { 1862 struct omap_hsmmc_host *host = mmc_priv(mmc); 1863 1864 switch (host->dpm_state) { 1865 case DISABLED: 1866 return omap_hsmmc_disabled_to_enabled(host); 1867 case CARDSLEEP: 1868 case REGSLEEP: 1869 return omap_hsmmc_sleep_to_enabled(host); 1870 case OFF: 1871 return omap_hsmmc_off_to_enabled(host); 1872 default: 1873 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1874 return -EINVAL; 1875 } 1876 } 1877 1878 /* 1879 * Bring MMC host in PM state (one level deeper). 1880 */ 1881 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1882 { 1883 struct omap_hsmmc_host *host = mmc_priv(mmc); 1884 1885 switch (host->dpm_state) { 1886 case ENABLED: { 1887 int delay; 1888 1889 delay = omap_hsmmc_enabled_to_disabled(host); 1890 if (lazy || delay < 0) 1891 return delay; 1892 return 0; 1893 } 1894 case DISABLED: 1895 return omap_hsmmc_disabled_to_sleep(host); 1896 case CARDSLEEP: 1897 case REGSLEEP: 1898 return omap_hsmmc_sleep_to_off(host); 1899 default: 1900 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1901 return -EINVAL; 1902 } 1903 } 1904 1905 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1906 { 1907 struct omap_hsmmc_host *host = mmc_priv(mmc); 1908 int err; 1909 1910 err = clk_enable(host->fclk); 1911 if (err) 1912 return err; 1913 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 1914 omap_hsmmc_context_restore(host); 1915 return 0; 1916 } 1917 1918 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1919 { 1920 struct omap_hsmmc_host *host = mmc_priv(mmc); 1921 1922 omap_hsmmc_context_save(host); 1923 clk_disable(host->fclk); 1924 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1925 return 0; 1926 } 1927 1928 static const struct mmc_host_ops omap_hsmmc_ops = { 1929 .enable = omap_hsmmc_enable_fclk, 1930 .disable = omap_hsmmc_disable_fclk, 1931 .request = omap_hsmmc_request, 1932 .set_ios = omap_hsmmc_set_ios, 1933 .get_cd = omap_hsmmc_get_cd, 1934 .get_ro = omap_hsmmc_get_ro, 1935 .init_card = omap_hsmmc_init_card, 1936 /* NYET -- enable_sdio_irq */ 1937 }; 1938 1939 static const struct mmc_host_ops omap_hsmmc_ps_ops = { 1940 .enable = omap_hsmmc_enable, 1941 .disable = omap_hsmmc_disable, 1942 .request = omap_hsmmc_request, 1943 .set_ios = omap_hsmmc_set_ios, 1944 .get_cd = omap_hsmmc_get_cd, 1945 .get_ro = omap_hsmmc_get_ro, 1946 .init_card = omap_hsmmc_init_card, 1947 /* NYET -- enable_sdio_irq */ 1948 }; 1949 1950 #ifdef CONFIG_DEBUG_FS 1951 1952 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1953 { 1954 struct mmc_host *mmc = s->private; 1955 struct omap_hsmmc_host *host = mmc_priv(mmc); 1956 int context_loss = 0; 1957 1958 if (host->pdata->get_context_loss_count) 1959 context_loss = host->pdata->get_context_loss_count(host->dev); 1960 1961 seq_printf(s, "mmc%d:\n" 1962 " enabled:\t%d\n" 1963 " dpm_state:\t%d\n" 1964 " nesting_cnt:\t%d\n" 1965 " ctx_loss:\t%d:%d\n" 1966 "\nregs:\n", 1967 mmc->index, mmc->enabled ? 1 : 0, 1968 host->dpm_state, mmc->nesting_cnt, 1969 host->context_loss, context_loss); 1970 1971 if (host->suspended || host->dpm_state == OFF) { 1972 seq_printf(s, "host suspended, can't read registers\n"); 1973 return 0; 1974 } 1975 1976 if (clk_enable(host->fclk) != 0) { 1977 seq_printf(s, "can't read the regs\n"); 1978 return 0; 1979 } 1980 1981 seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1982 OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1983 seq_printf(s, "CON:\t\t0x%08x\n", 1984 OMAP_HSMMC_READ(host->base, CON)); 1985 seq_printf(s, "HCTL:\t\t0x%08x\n", 1986 OMAP_HSMMC_READ(host->base, HCTL)); 1987 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1988 OMAP_HSMMC_READ(host->base, SYSCTL)); 1989 seq_printf(s, "IE:\t\t0x%08x\n", 1990 OMAP_HSMMC_READ(host->base, IE)); 1991 seq_printf(s, "ISE:\t\t0x%08x\n", 1992 OMAP_HSMMC_READ(host->base, ISE)); 1993 seq_printf(s, "CAPA:\t\t0x%08x\n", 1994 OMAP_HSMMC_READ(host->base, CAPA)); 1995 1996 clk_disable(host->fclk); 1997 1998 return 0; 1999 } 2000 2001 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 2002 { 2003 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 2004 } 2005 2006 static const struct file_operations mmc_regs_fops = { 2007 .open = omap_hsmmc_regs_open, 2008 .read = seq_read, 2009 .llseek = seq_lseek, 2010 .release = single_release, 2011 }; 2012 2013 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 2014 { 2015 if (mmc->debugfs_root) 2016 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 2017 mmc, &mmc_regs_fops); 2018 } 2019 2020 #else 2021 2022 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 2023 { 2024 } 2025 2026 #endif 2027 2028 static int __init omap_hsmmc_probe(struct platform_device *pdev) 2029 { 2030 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 2031 struct mmc_host *mmc; 2032 struct omap_hsmmc_host *host = NULL; 2033 struct resource *res; 2034 int ret, irq; 2035 2036 if (pdata == NULL) { 2037 dev_err(&pdev->dev, "Platform Data is missing\n"); 2038 return -ENXIO; 2039 } 2040 2041 if (pdata->nr_slots == 0) { 2042 dev_err(&pdev->dev, "No Slots\n"); 2043 return -ENXIO; 2044 } 2045 2046 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2047 irq = platform_get_irq(pdev, 0); 2048 if (res == NULL || irq < 0) 2049 return -ENXIO; 2050 2051 res->start += pdata->reg_offset; 2052 res->end += pdata->reg_offset; 2053 res = request_mem_region(res->start, resource_size(res), pdev->name); 2054 if (res == NULL) 2055 return -EBUSY; 2056 2057 ret = omap_hsmmc_gpio_init(pdata); 2058 if (ret) 2059 goto err; 2060 2061 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2062 if (!mmc) { 2063 ret = -ENOMEM; 2064 goto err_alloc; 2065 } 2066 2067 host = mmc_priv(mmc); 2068 host->mmc = mmc; 2069 host->pdata = pdata; 2070 host->dev = &pdev->dev; 2071 host->use_dma = 1; 2072 host->dev->dma_mask = &pdata->dma_mask; 2073 host->dma_ch = -1; 2074 host->irq = irq; 2075 host->id = pdev->id; 2076 host->slot_id = 0; 2077 host->mapbase = res->start; 2078 host->base = ioremap(host->mapbase, SZ_4K); 2079 host->power_mode = MMC_POWER_OFF; 2080 2081 platform_set_drvdata(pdev, host); 2082 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2083 2084 if (mmc_slot(host).power_saving) 2085 mmc->ops = &omap_hsmmc_ps_ops; 2086 else 2087 mmc->ops = &omap_hsmmc_ops; 2088 2089 /* 2090 * If regulator_disable can only put vcc_aux to sleep then there is 2091 * no off state. 2092 */ 2093 if (mmc_slot(host).vcc_aux_disable_is_sleep) 2094 mmc_slot(host).no_off = 1; 2095 2096 mmc->f_min = 400000; 2097 mmc->f_max = 52000000; 2098 2099 spin_lock_init(&host->irq_lock); 2100 2101 host->iclk = clk_get(&pdev->dev, "ick"); 2102 if (IS_ERR(host->iclk)) { 2103 ret = PTR_ERR(host->iclk); 2104 host->iclk = NULL; 2105 goto err1; 2106 } 2107 host->fclk = clk_get(&pdev->dev, "fck"); 2108 if (IS_ERR(host->fclk)) { 2109 ret = PTR_ERR(host->fclk); 2110 host->fclk = NULL; 2111 clk_put(host->iclk); 2112 goto err1; 2113 } 2114 2115 omap_hsmmc_context_save(host); 2116 2117 mmc->caps |= MMC_CAP_DISABLE; 2118 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 2119 /* we start off in DISABLED state */ 2120 host->dpm_state = DISABLED; 2121 2122 if (clk_enable(host->iclk) != 0) { 2123 clk_put(host->iclk); 2124 clk_put(host->fclk); 2125 goto err1; 2126 } 2127 2128 if (mmc_host_enable(host->mmc) != 0) { 2129 clk_disable(host->iclk); 2130 clk_put(host->iclk); 2131 clk_put(host->fclk); 2132 goto err1; 2133 } 2134 2135 if (cpu_is_omap2430()) { 2136 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 2137 /* 2138 * MMC can still work without debounce clock. 2139 */ 2140 if (IS_ERR(host->dbclk)) 2141 dev_warn(mmc_dev(host->mmc), 2142 "Failed to get debounce clock\n"); 2143 else 2144 host->got_dbclk = 1; 2145 2146 if (host->got_dbclk) 2147 if (clk_enable(host->dbclk) != 0) 2148 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 2149 " clk failed\n"); 2150 } 2151 2152 /* Since we do only SG emulation, we can have as many segs 2153 * as we want. */ 2154 mmc->max_segs = 1024; 2155 2156 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2157 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2158 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2159 mmc->max_seg_size = mmc->max_req_size; 2160 2161 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2162 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2163 2164 mmc->caps |= mmc_slot(host).caps; 2165 if (mmc->caps & MMC_CAP_8_BIT_DATA) 2166 mmc->caps |= MMC_CAP_4_BIT_DATA; 2167 2168 if (mmc_slot(host).nonremovable) 2169 mmc->caps |= MMC_CAP_NONREMOVABLE; 2170 2171 omap_hsmmc_conf_bus_power(host); 2172 2173 /* Select DMA lines */ 2174 switch (host->id) { 2175 case OMAP_MMC1_DEVID: 2176 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 2177 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2178 break; 2179 case OMAP_MMC2_DEVID: 2180 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2181 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2182 break; 2183 case OMAP_MMC3_DEVID: 2184 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2185 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2186 break; 2187 case OMAP_MMC4_DEVID: 2188 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 2189 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 2190 break; 2191 case OMAP_MMC5_DEVID: 2192 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 2193 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 2194 break; 2195 default: 2196 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2197 goto err_irq; 2198 } 2199 2200 /* Request IRQ for MMC operations */ 2201 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2202 mmc_hostname(mmc), host); 2203 if (ret) { 2204 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2205 goto err_irq; 2206 } 2207 2208 if (pdata->init != NULL) { 2209 if (pdata->init(&pdev->dev) != 0) { 2210 dev_dbg(mmc_dev(host->mmc), 2211 "Unable to configure MMC IRQs\n"); 2212 goto err_irq_cd_init; 2213 } 2214 } 2215 2216 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2217 ret = omap_hsmmc_reg_get(host); 2218 if (ret) 2219 goto err_reg; 2220 host->use_reg = 1; 2221 } 2222 2223 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2224 2225 /* Request IRQ for card detect */ 2226 if ((mmc_slot(host).card_detect_irq)) { 2227 ret = request_irq(mmc_slot(host).card_detect_irq, 2228 omap_hsmmc_cd_handler, 2229 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2230 | IRQF_DISABLED, 2231 mmc_hostname(mmc), host); 2232 if (ret) { 2233 dev_dbg(mmc_dev(host->mmc), 2234 "Unable to grab MMC CD IRQ\n"); 2235 goto err_irq_cd; 2236 } 2237 pdata->suspend = omap_hsmmc_suspend_cdirq; 2238 pdata->resume = omap_hsmmc_resume_cdirq; 2239 } 2240 2241 omap_hsmmc_disable_irq(host); 2242 2243 mmc_host_lazy_disable(host->mmc); 2244 2245 omap_hsmmc_protect_card(host); 2246 2247 mmc_add_host(mmc); 2248 2249 if (mmc_slot(host).name != NULL) { 2250 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2251 if (ret < 0) 2252 goto err_slot_name; 2253 } 2254 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2255 ret = device_create_file(&mmc->class_dev, 2256 &dev_attr_cover_switch); 2257 if (ret < 0) 2258 goto err_slot_name; 2259 } 2260 2261 omap_hsmmc_debugfs(mmc); 2262 2263 return 0; 2264 2265 err_slot_name: 2266 mmc_remove_host(mmc); 2267 free_irq(mmc_slot(host).card_detect_irq, host); 2268 err_irq_cd: 2269 if (host->use_reg) 2270 omap_hsmmc_reg_put(host); 2271 err_reg: 2272 if (host->pdata->cleanup) 2273 host->pdata->cleanup(&pdev->dev); 2274 err_irq_cd_init: 2275 free_irq(host->irq, host); 2276 err_irq: 2277 mmc_host_disable(host->mmc); 2278 clk_disable(host->iclk); 2279 clk_put(host->fclk); 2280 clk_put(host->iclk); 2281 if (host->got_dbclk) { 2282 clk_disable(host->dbclk); 2283 clk_put(host->dbclk); 2284 } 2285 err1: 2286 iounmap(host->base); 2287 platform_set_drvdata(pdev, NULL); 2288 mmc_free_host(mmc); 2289 err_alloc: 2290 omap_hsmmc_gpio_free(pdata); 2291 err: 2292 release_mem_region(res->start, resource_size(res)); 2293 return ret; 2294 } 2295 2296 static int omap_hsmmc_remove(struct platform_device *pdev) 2297 { 2298 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2299 struct resource *res; 2300 2301 if (host) { 2302 mmc_host_enable(host->mmc); 2303 mmc_remove_host(host->mmc); 2304 if (host->use_reg) 2305 omap_hsmmc_reg_put(host); 2306 if (host->pdata->cleanup) 2307 host->pdata->cleanup(&pdev->dev); 2308 free_irq(host->irq, host); 2309 if (mmc_slot(host).card_detect_irq) 2310 free_irq(mmc_slot(host).card_detect_irq, host); 2311 flush_work_sync(&host->mmc_carddetect_work); 2312 2313 mmc_host_disable(host->mmc); 2314 clk_disable(host->iclk); 2315 clk_put(host->fclk); 2316 clk_put(host->iclk); 2317 if (host->got_dbclk) { 2318 clk_disable(host->dbclk); 2319 clk_put(host->dbclk); 2320 } 2321 2322 mmc_free_host(host->mmc); 2323 iounmap(host->base); 2324 omap_hsmmc_gpio_free(pdev->dev.platform_data); 2325 } 2326 2327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2328 if (res) 2329 release_mem_region(res->start, resource_size(res)); 2330 platform_set_drvdata(pdev, NULL); 2331 2332 return 0; 2333 } 2334 2335 #ifdef CONFIG_PM 2336 static int omap_hsmmc_suspend(struct device *dev) 2337 { 2338 int ret = 0; 2339 struct platform_device *pdev = to_platform_device(dev); 2340 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2341 2342 if (host && host->suspended) 2343 return 0; 2344 2345 if (host) { 2346 host->suspended = 1; 2347 if (host->pdata->suspend) { 2348 ret = host->pdata->suspend(&pdev->dev, 2349 host->slot_id); 2350 if (ret) { 2351 dev_dbg(mmc_dev(host->mmc), 2352 "Unable to handle MMC board" 2353 " level suspend\n"); 2354 host->suspended = 0; 2355 return ret; 2356 } 2357 } 2358 cancel_work_sync(&host->mmc_carddetect_work); 2359 ret = mmc_suspend_host(host->mmc); 2360 mmc_host_enable(host->mmc); 2361 if (ret == 0) { 2362 omap_hsmmc_disable_irq(host); 2363 OMAP_HSMMC_WRITE(host->base, HCTL, 2364 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2365 mmc_host_disable(host->mmc); 2366 clk_disable(host->iclk); 2367 if (host->got_dbclk) 2368 clk_disable(host->dbclk); 2369 } else { 2370 host->suspended = 0; 2371 if (host->pdata->resume) { 2372 ret = host->pdata->resume(&pdev->dev, 2373 host->slot_id); 2374 if (ret) 2375 dev_dbg(mmc_dev(host->mmc), 2376 "Unmask interrupt failed\n"); 2377 } 2378 mmc_host_disable(host->mmc); 2379 } 2380 2381 } 2382 return ret; 2383 } 2384 2385 /* Routine to resume the MMC device */ 2386 static int omap_hsmmc_resume(struct device *dev) 2387 { 2388 int ret = 0; 2389 struct platform_device *pdev = to_platform_device(dev); 2390 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2391 2392 if (host && !host->suspended) 2393 return 0; 2394 2395 if (host) { 2396 ret = clk_enable(host->iclk); 2397 if (ret) 2398 goto clk_en_err; 2399 2400 if (mmc_host_enable(host->mmc) != 0) { 2401 clk_disable(host->iclk); 2402 goto clk_en_err; 2403 } 2404 2405 if (host->got_dbclk) 2406 clk_enable(host->dbclk); 2407 2408 omap_hsmmc_conf_bus_power(host); 2409 2410 if (host->pdata->resume) { 2411 ret = host->pdata->resume(&pdev->dev, host->slot_id); 2412 if (ret) 2413 dev_dbg(mmc_dev(host->mmc), 2414 "Unmask interrupt failed\n"); 2415 } 2416 2417 omap_hsmmc_protect_card(host); 2418 2419 /* Notify the core to resume the host */ 2420 ret = mmc_resume_host(host->mmc); 2421 if (ret == 0) 2422 host->suspended = 0; 2423 2424 mmc_host_lazy_disable(host->mmc); 2425 } 2426 2427 return ret; 2428 2429 clk_en_err: 2430 dev_dbg(mmc_dev(host->mmc), 2431 "Failed to enable MMC clocks during resume\n"); 2432 return ret; 2433 } 2434 2435 #else 2436 #define omap_hsmmc_suspend NULL 2437 #define omap_hsmmc_resume NULL 2438 #endif 2439 2440 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2441 .suspend = omap_hsmmc_suspend, 2442 .resume = omap_hsmmc_resume, 2443 }; 2444 2445 static struct platform_driver omap_hsmmc_driver = { 2446 .remove = omap_hsmmc_remove, 2447 .driver = { 2448 .name = DRIVER_NAME, 2449 .owner = THIS_MODULE, 2450 .pm = &omap_hsmmc_dev_pm_ops, 2451 }, 2452 }; 2453 2454 static int __init omap_hsmmc_init(void) 2455 { 2456 /* Register the MMC driver */ 2457 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2458 } 2459 2460 static void __exit omap_hsmmc_cleanup(void) 2461 { 2462 /* Unregister MMC driver */ 2463 platform_driver_unregister(&omap_hsmmc_driver); 2464 } 2465 2466 module_init(omap_hsmmc_init); 2467 module_exit(omap_hsmmc_cleanup); 2468 2469 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2470 MODULE_LICENSE("GPL"); 2471 MODULE_ALIAS("platform:" DRIVER_NAME); 2472 MODULE_AUTHOR("Texas Instruments Inc"); 2473