1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 25 * USA 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/pnp.h> 33 #include <linux/io.h> 34 #include <linux/interrupt.h> 35 #include <linux/sched.h> 36 #include <linux/slab.h> 37 #include <media/rc-core.h> 38 #include <linux/pci_ids.h> 39 40 #include "nuvoton-cir.h" 41 42 /* write val to config reg */ 43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) 44 { 45 outb(reg, nvt->cr_efir); 46 outb(val, nvt->cr_efdr); 47 } 48 49 /* read val from config reg */ 50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) 51 { 52 outb(reg, nvt->cr_efir); 53 return inb(nvt->cr_efdr); 54 } 55 56 /* update config register bit without changing other bits */ 57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) 58 { 59 u8 tmp = nvt_cr_read(nvt, reg) | val; 60 nvt_cr_write(nvt, tmp, reg); 61 } 62 63 /* clear config register bit without changing other bits */ 64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) 65 { 66 u8 tmp = nvt_cr_read(nvt, reg) & ~val; 67 nvt_cr_write(nvt, tmp, reg); 68 } 69 70 /* enter extended function mode */ 71 static inline void nvt_efm_enable(struct nvt_dev *nvt) 72 { 73 /* Enabling Extended Function Mode explicitly requires writing 2x */ 74 outb(EFER_EFM_ENABLE, nvt->cr_efir); 75 outb(EFER_EFM_ENABLE, nvt->cr_efir); 76 } 77 78 /* exit extended function mode */ 79 static inline void nvt_efm_disable(struct nvt_dev *nvt) 80 { 81 outb(EFER_EFM_DISABLE, nvt->cr_efir); 82 } 83 84 /* 85 * When you want to address a specific logical device, write its logical 86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing 87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. 88 */ 89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) 90 { 91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir); 92 outb(ldev, nvt->cr_efdr); 93 } 94 95 /* write val to cir config register */ 96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) 97 { 98 outb(val, nvt->cir_addr + offset); 99 } 100 101 /* read val from cir config register */ 102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) 103 { 104 u8 val; 105 106 val = inb(nvt->cir_addr + offset); 107 108 return val; 109 } 110 111 /* write val to cir wake register */ 112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, 113 u8 val, u8 offset) 114 { 115 outb(val, nvt->cir_wake_addr + offset); 116 } 117 118 /* read val from cir wake config register */ 119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) 120 { 121 u8 val; 122 123 val = inb(nvt->cir_wake_addr + offset); 124 125 return val; 126 } 127 128 /* dump current cir register contents */ 129 static void cir_dump_regs(struct nvt_dev *nvt) 130 { 131 nvt_efm_enable(nvt); 132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 133 134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); 135 pr_info(" * CR CIR ACTIVE : 0x%x\n", 136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 137 pr_info(" * CR CIR BASE ADDR: 0x%x\n", 138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 140 pr_info(" * CR CIR IRQ NUM: 0x%x\n", 141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 142 143 nvt_efm_disable(nvt); 144 145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); 146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); 147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); 148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); 149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); 150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); 151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); 152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); 153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); 154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); 155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); 156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); 157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); 158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); 159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); 160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); 161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); 162 } 163 164 /* dump current cir wake register contents */ 165 static void cir_wake_dump_regs(struct nvt_dev *nvt) 166 { 167 u8 i, fifo_len; 168 169 nvt_efm_enable(nvt); 170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 171 172 pr_info("%s: Dump CIR WAKE logical device registers:\n", 173 NVT_DRIVER_NAME); 174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", 175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", 177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", 180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 181 182 nvt_efm_disable(nvt); 183 184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); 185 pr_info(" * IRCON: 0x%x\n", 186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); 187 pr_info(" * IRSTS: 0x%x\n", 188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); 189 pr_info(" * IREN: 0x%x\n", 190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); 191 pr_info(" * FIFO CMP DEEP: 0x%x\n", 192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); 193 pr_info(" * FIFO CMP TOL: 0x%x\n", 194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); 195 pr_info(" * FIFO COUNT: 0x%x\n", 196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); 197 pr_info(" * SLCH: 0x%x\n", 198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); 199 pr_info(" * SLCL: 0x%x\n", 200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); 201 pr_info(" * FIFOCON: 0x%x\n", 202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); 203 pr_info(" * SRXFSTS: 0x%x\n", 204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); 205 pr_info(" * SAMPLE RX FIFO: 0x%x\n", 206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); 207 pr_info(" * WR FIFO DATA: 0x%x\n", 208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); 209 pr_info(" * RD FIFO ONLY: 0x%x\n", 210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n", 212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); 213 pr_info(" * FIFO IGNORE: 0x%x\n", 214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); 215 pr_info(" * IRFSM: 0x%x\n", 216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); 217 218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); 219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); 220 pr_info("* Contents ="); 221 for (i = 0; i < fifo_len; i++) 222 pr_cont(" %02x", 223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 224 pr_cont("\n"); 225 } 226 227 /* detect hardware features */ 228 static int nvt_hw_detect(struct nvt_dev *nvt) 229 { 230 unsigned long flags; 231 u8 chip_major, chip_minor; 232 int ret = 0; 233 char chip_id[12]; 234 bool chip_unknown = false; 235 236 nvt_efm_enable(nvt); 237 238 /* Check if we're wired for the alternate EFER setup */ 239 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); 240 if (chip_major == 0xff) { 241 nvt->cr_efir = CR_EFIR2; 242 nvt->cr_efdr = CR_EFDR2; 243 nvt_efm_enable(nvt); 244 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); 245 } 246 247 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); 248 249 /* these are the known working chip revisions... */ 250 switch (chip_major) { 251 case CHIP_ID_HIGH_667: 252 strcpy(chip_id, "w83667hg\0"); 253 if (chip_minor != CHIP_ID_LOW_667) 254 chip_unknown = true; 255 break; 256 case CHIP_ID_HIGH_677B: 257 strcpy(chip_id, "w83677hg\0"); 258 if (chip_minor != CHIP_ID_LOW_677B2 && 259 chip_minor != CHIP_ID_LOW_677B3) 260 chip_unknown = true; 261 break; 262 case CHIP_ID_HIGH_677C: 263 strcpy(chip_id, "w83677hg-c\0"); 264 if (chip_minor != CHIP_ID_LOW_677C) 265 chip_unknown = true; 266 break; 267 default: 268 strcpy(chip_id, "w836x7hg\0"); 269 chip_unknown = true; 270 break; 271 } 272 273 /* warn, but still let the driver load, if we don't know this chip */ 274 if (chip_unknown) 275 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, " 276 "it may not work...", chip_id, chip_major, chip_minor); 277 else 278 nvt_dbg("%s: chip id: 0x%02x 0x%02x", 279 chip_id, chip_major, chip_minor); 280 281 nvt_efm_disable(nvt); 282 283 spin_lock_irqsave(&nvt->nvt_lock, flags); 284 nvt->chip_major = chip_major; 285 nvt->chip_minor = chip_minor; 286 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 287 288 return ret; 289 } 290 291 static void nvt_cir_ldev_init(struct nvt_dev *nvt) 292 { 293 u8 val, psreg, psmask, psval; 294 295 if (nvt->chip_major == CHIP_ID_HIGH_667) { 296 psreg = CR_MULTIFUNC_PIN_SEL; 297 psmask = MULTIFUNC_PIN_SEL_MASK; 298 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; 299 } else { 300 psreg = CR_OUTPUT_PIN_SEL; 301 psmask = OUTPUT_PIN_SEL_MASK; 302 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; 303 } 304 305 /* output pin selection: enable CIR, with WB sensor enabled */ 306 val = nvt_cr_read(nvt, psreg); 307 val &= psmask; 308 val |= psval; 309 nvt_cr_write(nvt, val, psreg); 310 311 /* Select CIR logical device and enable */ 312 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 313 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 314 315 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); 316 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); 317 318 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); 319 320 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", 321 nvt->cir_addr, nvt->cir_irq); 322 } 323 324 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) 325 { 326 /* Select ACPI logical device, enable it and CIR Wake */ 327 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); 328 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 329 330 /* Enable CIR Wake via PSOUT# (Pin60) */ 331 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); 332 333 /* enable cir interrupt of mouse/keyboard IRQ event */ 334 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); 335 336 /* enable pme interrupt of cir wakeup event */ 337 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); 338 339 /* Select CIR Wake logical device and enable */ 340 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 341 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 342 343 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); 344 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); 345 346 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); 347 348 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d", 349 nvt->cir_wake_addr, nvt->cir_wake_irq); 350 } 351 352 /* clear out the hardware's cir rx fifo */ 353 static void nvt_clear_cir_fifo(struct nvt_dev *nvt) 354 { 355 u8 val; 356 357 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); 358 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); 359 } 360 361 /* clear out the hardware's cir wake rx fifo */ 362 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) 363 { 364 u8 val; 365 366 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); 367 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, 368 CIR_WAKE_FIFOCON); 369 } 370 371 /* clear out the hardware's cir tx fifo */ 372 static void nvt_clear_tx_fifo(struct nvt_dev *nvt) 373 { 374 u8 val; 375 376 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); 377 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); 378 } 379 380 /* enable RX Trigger Level Reach and Packet End interrupts */ 381 static void nvt_set_cir_iren(struct nvt_dev *nvt) 382 { 383 u8 iren; 384 385 iren = CIR_IREN_RTR | CIR_IREN_PE; 386 nvt_cir_reg_write(nvt, iren, CIR_IREN); 387 } 388 389 static void nvt_cir_regs_init(struct nvt_dev *nvt) 390 { 391 /* set sample limit count (PE interrupt raised when reached) */ 392 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); 393 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); 394 395 /* set fifo irq trigger levels */ 396 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | 397 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); 398 399 /* 400 * Enable TX and RX, specify carrier on = low, off = high, and set 401 * sample period (currently 50us) 402 */ 403 nvt_cir_reg_write(nvt, 404 CIR_IRCON_TXEN | CIR_IRCON_RXEN | 405 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, 406 CIR_IRCON); 407 408 /* clear hardware rx and tx fifos */ 409 nvt_clear_cir_fifo(nvt); 410 nvt_clear_tx_fifo(nvt); 411 412 /* clear any and all stray interrupts */ 413 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 414 415 /* and finally, enable interrupts */ 416 nvt_set_cir_iren(nvt); 417 } 418 419 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) 420 { 421 /* set number of bytes needed for wake from s3 (default 65) */ 422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES, 423 CIR_WAKE_FIFO_CMP_DEEP); 424 425 /* set tolerance/variance allowed per byte during wake compare */ 426 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE, 427 CIR_WAKE_FIFO_CMP_TOL); 428 429 /* set sample limit count (PE interrupt raised when reached) */ 430 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH); 431 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL); 432 433 /* set cir wake fifo rx trigger level (currently 67) */ 434 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV, 435 CIR_WAKE_FIFOCON); 436 437 /* 438 * Enable TX and RX, specific carrier on = low, off = high, and set 439 * sample period (currently 50us) 440 */ 441 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | 442 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | 443 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, 444 CIR_WAKE_IRCON); 445 446 /* clear cir wake rx fifo */ 447 nvt_clear_cir_wake_fifo(nvt); 448 449 /* clear any and all stray interrupts */ 450 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); 451 } 452 453 static void nvt_enable_wake(struct nvt_dev *nvt) 454 { 455 nvt_efm_enable(nvt); 456 457 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); 458 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); 459 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); 460 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); 461 462 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 463 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 464 465 nvt_efm_disable(nvt); 466 467 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | 468 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | 469 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, 470 CIR_WAKE_IRCON); 471 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); 472 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); 473 } 474 475 #if 0 /* Currently unused */ 476 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ 477 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) 478 { 479 u32 count, carrier, duration = 0; 480 int i; 481 482 count = nvt_cir_reg_read(nvt, CIR_FCCL) | 483 nvt_cir_reg_read(nvt, CIR_FCCH) << 8; 484 485 for (i = 0; i < nvt->pkts; i++) { 486 if (nvt->buf[i] & BUF_PULSE_BIT) 487 duration += nvt->buf[i] & BUF_LEN_MASK; 488 } 489 490 duration *= SAMPLE_PERIOD; 491 492 if (!count || !duration) { 493 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)", 494 count, duration); 495 return 0; 496 } 497 498 carrier = MS_TO_NS(count) / duration; 499 500 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) 501 nvt_dbg("WTF? Carrier frequency out of range!"); 502 503 nvt_dbg("Carrier frequency: %u (count %u, duration %u)", 504 carrier, count, duration); 505 506 return carrier; 507 } 508 #endif 509 /* 510 * set carrier frequency 511 * 512 * set carrier on 2 registers: CP & CC 513 * always set CP as 0x81 514 * set CC by SPEC, CC = 3MHz/carrier - 1 515 */ 516 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) 517 { 518 struct nvt_dev *nvt = dev->priv; 519 u16 val; 520 521 if (carrier == 0) 522 return -EINVAL; 523 524 nvt_cir_reg_write(nvt, 1, CIR_CP); 525 val = 3000000 / (carrier) - 1; 526 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); 527 528 nvt_dbg("cp: 0x%x cc: 0x%x\n", 529 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); 530 531 return 0; 532 } 533 534 /* 535 * nvt_tx_ir 536 * 537 * 1) clean TX fifo first (handled by AP) 538 * 2) copy data from user space 539 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU 540 * 4) send 9 packets to TX FIFO to open TTR 541 * in interrupt_handler: 542 * 5) send all data out 543 * go back to write(): 544 * 6) disable TX interrupts, re-enable RX interupts 545 * 546 * The key problem of this function is user space data may larger than 547 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to 548 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf 549 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to 550 * set TXFCONT as 0xff, until buf_count less than 0xff. 551 */ 552 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) 553 { 554 struct nvt_dev *nvt = dev->priv; 555 unsigned long flags; 556 unsigned int i; 557 u8 iren; 558 int ret; 559 560 spin_lock_irqsave(&nvt->tx.lock, flags); 561 562 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); 563 nvt->tx.buf_count = (ret * sizeof(unsigned)); 564 565 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); 566 567 nvt->tx.cur_buf_num = 0; 568 569 /* save currently enabled interrupts */ 570 iren = nvt_cir_reg_read(nvt, CIR_IREN); 571 572 /* now disable all interrupts, save TFU & TTR */ 573 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); 574 575 nvt->tx.tx_state = ST_TX_REPLY; 576 577 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | 578 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); 579 580 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ 581 for (i = 0; i < 9; i++) 582 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); 583 584 spin_unlock_irqrestore(&nvt->tx.lock, flags); 585 586 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); 587 588 spin_lock_irqsave(&nvt->tx.lock, flags); 589 nvt->tx.tx_state = ST_TX_NONE; 590 spin_unlock_irqrestore(&nvt->tx.lock, flags); 591 592 /* restore enabled interrupts to prior state */ 593 nvt_cir_reg_write(nvt, iren, CIR_IREN); 594 595 return ret; 596 } 597 598 /* dump contents of the last rx buffer we got from the hw rx fifo */ 599 static void nvt_dump_rx_buf(struct nvt_dev *nvt) 600 { 601 int i; 602 603 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); 604 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) 605 printk(KERN_CONT "0x%02x ", nvt->buf[i]); 606 printk(KERN_CONT "\n"); 607 } 608 609 /* 610 * Process raw data in rx driver buffer, store it in raw IR event kfifo, 611 * trigger decode when appropriate. 612 * 613 * We get IR data samples one byte at a time. If the msb is set, its a pulse, 614 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD 615 * (default 50us) intervals for that pulse/space. A discrete signal is 616 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 617 * to signal more IR coming (repeats) or end of IR, respectively. We store 618 * sample data in the raw event kfifo until we see 0x7<something> (except f) 619 * or 0x80, at which time, we trigger a decode operation. 620 */ 621 static void nvt_process_rx_ir_data(struct nvt_dev *nvt) 622 { 623 DEFINE_IR_RAW_EVENT(rawir); 624 u8 sample; 625 int i; 626 627 nvt_dbg_verbose("%s firing", __func__); 628 629 if (debug) 630 nvt_dump_rx_buf(nvt); 631 632 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); 633 634 init_ir_raw_event(&rawir); 635 636 for (i = 0; i < nvt->pkts; i++) { 637 sample = nvt->buf[i]; 638 639 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); 640 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) 641 * SAMPLE_PERIOD); 642 643 nvt_dbg("Storing %s with duration %d", 644 rawir.pulse ? "pulse" : "space", rawir.duration); 645 646 ir_raw_event_store_with_filter(nvt->rdev, &rawir); 647 648 /* 649 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE 650 * indicates end of IR signal, but new data incoming. In both 651 * cases, it means we're ready to call ir_raw_event_handle 652 */ 653 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) { 654 nvt_dbg("Calling ir_raw_event_handle (signal end)\n"); 655 ir_raw_event_handle(nvt->rdev); 656 } 657 } 658 659 nvt->pkts = 0; 660 661 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n"); 662 ir_raw_event_handle(nvt->rdev); 663 664 nvt_dbg_verbose("%s done", __func__); 665 } 666 667 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) 668 { 669 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!"); 670 671 nvt->pkts = 0; 672 nvt_clear_cir_fifo(nvt); 673 ir_raw_event_reset(nvt->rdev); 674 } 675 676 /* copy data from hardware rx fifo into driver buffer */ 677 static void nvt_get_rx_ir_data(struct nvt_dev *nvt) 678 { 679 unsigned long flags; 680 u8 fifocount, val; 681 unsigned int b_idx; 682 bool overrun = false; 683 int i; 684 685 /* Get count of how many bytes to read from RX FIFO */ 686 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); 687 /* if we get 0xff, probably means the logical dev is disabled */ 688 if (fifocount == 0xff) 689 return; 690 /* watch out for a fifo overrun condition */ 691 else if (fifocount > RX_BUF_LEN) { 692 overrun = true; 693 fifocount = RX_BUF_LEN; 694 } 695 696 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); 697 698 spin_lock_irqsave(&nvt->nvt_lock, flags); 699 700 b_idx = nvt->pkts; 701 702 /* This should never happen, but lets check anyway... */ 703 if (b_idx + fifocount > RX_BUF_LEN) { 704 nvt_process_rx_ir_data(nvt); 705 b_idx = 0; 706 } 707 708 /* Read fifocount bytes from CIR Sample RX FIFO register */ 709 for (i = 0; i < fifocount; i++) { 710 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); 711 nvt->buf[b_idx + i] = val; 712 } 713 714 nvt->pkts += fifocount; 715 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); 716 717 nvt_process_rx_ir_data(nvt); 718 719 if (overrun) 720 nvt_handle_rx_fifo_overrun(nvt); 721 722 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 723 } 724 725 static void nvt_cir_log_irqs(u8 status, u8 iren) 726 { 727 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", 728 status, iren, 729 status & CIR_IRSTS_RDR ? " RDR" : "", 730 status & CIR_IRSTS_RTR ? " RTR" : "", 731 status & CIR_IRSTS_PE ? " PE" : "", 732 status & CIR_IRSTS_RFO ? " RFO" : "", 733 status & CIR_IRSTS_TE ? " TE" : "", 734 status & CIR_IRSTS_TTR ? " TTR" : "", 735 status & CIR_IRSTS_TFU ? " TFU" : "", 736 status & CIR_IRSTS_GH ? " GH" : "", 737 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | 738 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | 739 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); 740 } 741 742 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) 743 { 744 unsigned long flags; 745 bool tx_inactive; 746 u8 tx_state; 747 748 spin_lock_irqsave(&nvt->tx.lock, flags); 749 tx_state = nvt->tx.tx_state; 750 spin_unlock_irqrestore(&nvt->tx.lock, flags); 751 752 tx_inactive = (tx_state == ST_TX_NONE); 753 754 return tx_inactive; 755 } 756 757 /* interrupt service routine for incoming and outgoing CIR data */ 758 static irqreturn_t nvt_cir_isr(int irq, void *data) 759 { 760 struct nvt_dev *nvt = data; 761 u8 status, iren, cur_state; 762 unsigned long flags; 763 764 nvt_dbg_verbose("%s firing", __func__); 765 766 nvt_efm_enable(nvt); 767 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 768 nvt_efm_disable(nvt); 769 770 /* 771 * Get IR Status register contents. Write 1 to ack/clear 772 * 773 * bit: reg name - description 774 * 7: CIR_IRSTS_RDR - RX Data Ready 775 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach 776 * 5: CIR_IRSTS_PE - Packet End 777 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) 778 * 3: CIR_IRSTS_TE - TX FIFO Empty 779 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach 780 * 1: CIR_IRSTS_TFU - TX FIFO Underrun 781 * 0: CIR_IRSTS_GH - Min Length Detected 782 */ 783 status = nvt_cir_reg_read(nvt, CIR_IRSTS); 784 if (!status) { 785 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); 786 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 787 return IRQ_RETVAL(IRQ_NONE); 788 } 789 790 /* ack/clear all irq flags we've got */ 791 nvt_cir_reg_write(nvt, status, CIR_IRSTS); 792 nvt_cir_reg_write(nvt, 0, CIR_IRSTS); 793 794 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */ 795 iren = nvt_cir_reg_read(nvt, CIR_IREN); 796 if (!iren) { 797 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__); 798 return IRQ_RETVAL(IRQ_NONE); 799 } 800 801 if (debug) 802 nvt_cir_log_irqs(status, iren); 803 804 if (status & CIR_IRSTS_RTR) { 805 /* FIXME: add code for study/learn mode */ 806 /* We only do rx if not tx'ing */ 807 if (nvt_cir_tx_inactive(nvt)) 808 nvt_get_rx_ir_data(nvt); 809 } 810 811 if (status & CIR_IRSTS_PE) { 812 if (nvt_cir_tx_inactive(nvt)) 813 nvt_get_rx_ir_data(nvt); 814 815 spin_lock_irqsave(&nvt->nvt_lock, flags); 816 817 cur_state = nvt->study_state; 818 819 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 820 821 if (cur_state == ST_STUDY_NONE) 822 nvt_clear_cir_fifo(nvt); 823 } 824 825 if (status & CIR_IRSTS_TE) 826 nvt_clear_tx_fifo(nvt); 827 828 if (status & CIR_IRSTS_TTR) { 829 unsigned int pos, count; 830 u8 tmp; 831 832 spin_lock_irqsave(&nvt->tx.lock, flags); 833 834 pos = nvt->tx.cur_buf_num; 835 count = nvt->tx.buf_count; 836 837 /* Write data into the hardware tx fifo while pos < count */ 838 if (pos < count) { 839 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); 840 nvt->tx.cur_buf_num++; 841 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ 842 } else { 843 tmp = nvt_cir_reg_read(nvt, CIR_IREN); 844 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); 845 } 846 847 spin_unlock_irqrestore(&nvt->tx.lock, flags); 848 849 } 850 851 if (status & CIR_IRSTS_TFU) { 852 spin_lock_irqsave(&nvt->tx.lock, flags); 853 if (nvt->tx.tx_state == ST_TX_REPLY) { 854 nvt->tx.tx_state = ST_TX_REQUEST; 855 wake_up(&nvt->tx.queue); 856 } 857 spin_unlock_irqrestore(&nvt->tx.lock, flags); 858 } 859 860 nvt_dbg_verbose("%s done", __func__); 861 return IRQ_RETVAL(IRQ_HANDLED); 862 } 863 864 /* Interrupt service routine for CIR Wake */ 865 static irqreturn_t nvt_cir_wake_isr(int irq, void *data) 866 { 867 u8 status, iren, val; 868 struct nvt_dev *nvt = data; 869 unsigned long flags; 870 871 nvt_dbg_wake("%s firing", __func__); 872 873 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS); 874 if (!status) 875 return IRQ_RETVAL(IRQ_NONE); 876 877 if (status & CIR_WAKE_IRSTS_IR_PENDING) 878 nvt_clear_cir_wake_fifo(nvt); 879 880 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS); 881 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS); 882 883 /* Interrupt may be shared with CIR, bail if Wake not enabled */ 884 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN); 885 if (!iren) { 886 nvt_dbg_wake("%s exiting, wake not enabled", __func__); 887 return IRQ_RETVAL(IRQ_HANDLED); 888 } 889 890 if ((status & CIR_WAKE_IRSTS_PE) && 891 (nvt->wake_state == ST_WAKE_START)) { 892 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) { 893 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); 894 nvt_dbg("setting wake up key: 0x%x", val); 895 } 896 897 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); 898 spin_lock_irqsave(&nvt->nvt_lock, flags); 899 nvt->wake_state = ST_WAKE_FINISH; 900 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 901 } 902 903 nvt_dbg_wake("%s done", __func__); 904 return IRQ_RETVAL(IRQ_HANDLED); 905 } 906 907 static void nvt_enable_cir(struct nvt_dev *nvt) 908 { 909 /* set function enable flags */ 910 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | 911 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, 912 CIR_IRCON); 913 914 nvt_efm_enable(nvt); 915 916 /* enable the CIR logical device */ 917 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 918 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 919 920 nvt_efm_disable(nvt); 921 922 /* clear all pending interrupts */ 923 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 924 925 /* enable interrupts */ 926 nvt_set_cir_iren(nvt); 927 } 928 929 static void nvt_disable_cir(struct nvt_dev *nvt) 930 { 931 /* disable CIR interrupts */ 932 nvt_cir_reg_write(nvt, 0, CIR_IREN); 933 934 /* clear any and all pending interrupts */ 935 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 936 937 /* clear all function enable flags */ 938 nvt_cir_reg_write(nvt, 0, CIR_IRCON); 939 940 /* clear hardware rx and tx fifos */ 941 nvt_clear_cir_fifo(nvt); 942 nvt_clear_tx_fifo(nvt); 943 944 nvt_efm_enable(nvt); 945 946 /* disable the CIR logical device */ 947 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 948 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); 949 950 nvt_efm_disable(nvt); 951 } 952 953 static int nvt_open(struct rc_dev *dev) 954 { 955 struct nvt_dev *nvt = dev->priv; 956 unsigned long flags; 957 958 spin_lock_irqsave(&nvt->nvt_lock, flags); 959 nvt_enable_cir(nvt); 960 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 961 962 return 0; 963 } 964 965 static void nvt_close(struct rc_dev *dev) 966 { 967 struct nvt_dev *nvt = dev->priv; 968 unsigned long flags; 969 970 spin_lock_irqsave(&nvt->nvt_lock, flags); 971 nvt_disable_cir(nvt); 972 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 973 } 974 975 /* Allocate memory, probe hardware, and initialize everything */ 976 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) 977 { 978 struct nvt_dev *nvt; 979 struct rc_dev *rdev; 980 int ret = -ENOMEM; 981 982 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL); 983 if (!nvt) 984 return ret; 985 986 /* input device for IR remote (and tx) */ 987 rdev = rc_allocate_device(); 988 if (!rdev) 989 goto exit_free_dev_rdev; 990 991 ret = -ENODEV; 992 /* validate pnp resources */ 993 if (!pnp_port_valid(pdev, 0) || 994 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { 995 dev_err(&pdev->dev, "IR PNP Port not valid!\n"); 996 goto exit_free_dev_rdev; 997 } 998 999 if (!pnp_irq_valid(pdev, 0)) { 1000 dev_err(&pdev->dev, "PNP IRQ not valid!\n"); 1001 goto exit_free_dev_rdev; 1002 } 1003 1004 if (!pnp_port_valid(pdev, 1) || 1005 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { 1006 dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); 1007 goto exit_free_dev_rdev; 1008 } 1009 1010 nvt->cir_addr = pnp_port_start(pdev, 0); 1011 nvt->cir_irq = pnp_irq(pdev, 0); 1012 1013 nvt->cir_wake_addr = pnp_port_start(pdev, 1); 1014 /* irq is always shared between cir and cir wake */ 1015 nvt->cir_wake_irq = nvt->cir_irq; 1016 1017 nvt->cr_efir = CR_EFIR; 1018 nvt->cr_efdr = CR_EFDR; 1019 1020 spin_lock_init(&nvt->nvt_lock); 1021 spin_lock_init(&nvt->tx.lock); 1022 1023 pnp_set_drvdata(pdev, nvt); 1024 nvt->pdev = pdev; 1025 1026 init_waitqueue_head(&nvt->tx.queue); 1027 1028 ret = nvt_hw_detect(nvt); 1029 if (ret) 1030 goto exit_free_dev_rdev; 1031 1032 /* Initialize CIR & CIR Wake Logical Devices */ 1033 nvt_efm_enable(nvt); 1034 nvt_cir_ldev_init(nvt); 1035 nvt_cir_wake_ldev_init(nvt); 1036 nvt_efm_disable(nvt); 1037 1038 /* Initialize CIR & CIR Wake Config Registers */ 1039 nvt_cir_regs_init(nvt); 1040 nvt_cir_wake_regs_init(nvt); 1041 1042 /* Set up the rc device */ 1043 rdev->priv = nvt; 1044 rdev->driver_type = RC_DRIVER_IR_RAW; 1045 rdev->allowed_protos = RC_BIT_ALL; 1046 rdev->open = nvt_open; 1047 rdev->close = nvt_close; 1048 rdev->tx_ir = nvt_tx_ir; 1049 rdev->s_tx_carrier = nvt_set_tx_carrier; 1050 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; 1051 rdev->input_phys = "nuvoton/cir0"; 1052 rdev->input_id.bustype = BUS_HOST; 1053 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; 1054 rdev->input_id.product = nvt->chip_major; 1055 rdev->input_id.version = nvt->chip_minor; 1056 rdev->dev.parent = &pdev->dev; 1057 rdev->driver_name = NVT_DRIVER_NAME; 1058 rdev->map_name = RC_MAP_RC6_MCE; 1059 rdev->timeout = MS_TO_NS(100); 1060 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ 1061 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); 1062 #if 0 1063 rdev->min_timeout = XYZ; 1064 rdev->max_timeout = XYZ; 1065 /* tx bits */ 1066 rdev->tx_resolution = XYZ; 1067 #endif 1068 nvt->rdev = rdev; 1069 1070 ret = rc_register_device(rdev); 1071 if (ret) 1072 goto exit_free_dev_rdev; 1073 1074 ret = -EBUSY; 1075 /* now claim resources */ 1076 if (!request_region(nvt->cir_addr, 1077 CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) 1078 goto exit_unregister_device; 1079 1080 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED, 1081 NVT_DRIVER_NAME, (void *)nvt)) 1082 goto exit_release_cir_addr; 1083 1084 if (!request_region(nvt->cir_wake_addr, 1085 CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) 1086 goto exit_free_irq; 1087 1088 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED, 1089 NVT_DRIVER_NAME, (void *)nvt)) 1090 goto exit_release_cir_wake_addr; 1091 1092 device_init_wakeup(&pdev->dev, true); 1093 1094 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n"); 1095 if (debug) { 1096 cir_dump_regs(nvt); 1097 cir_wake_dump_regs(nvt); 1098 } 1099 1100 return 0; 1101 1102 exit_release_cir_wake_addr: 1103 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); 1104 exit_free_irq: 1105 free_irq(nvt->cir_irq, nvt); 1106 exit_release_cir_addr: 1107 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); 1108 exit_unregister_device: 1109 rc_unregister_device(rdev); 1110 exit_free_dev_rdev: 1111 rc_free_device(rdev); 1112 kfree(nvt); 1113 1114 return ret; 1115 } 1116 1117 static void nvt_remove(struct pnp_dev *pdev) 1118 { 1119 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1120 unsigned long flags; 1121 1122 spin_lock_irqsave(&nvt->nvt_lock, flags); 1123 /* disable CIR */ 1124 nvt_cir_reg_write(nvt, 0, CIR_IREN); 1125 nvt_disable_cir(nvt); 1126 /* enable CIR Wake (for IR power-on) */ 1127 nvt_enable_wake(nvt); 1128 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 1129 1130 /* free resources */ 1131 free_irq(nvt->cir_irq, nvt); 1132 free_irq(nvt->cir_wake_irq, nvt); 1133 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); 1134 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); 1135 1136 rc_unregister_device(nvt->rdev); 1137 1138 kfree(nvt); 1139 } 1140 1141 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) 1142 { 1143 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1144 unsigned long flags; 1145 1146 nvt_dbg("%s called", __func__); 1147 1148 /* zero out misc state tracking */ 1149 spin_lock_irqsave(&nvt->nvt_lock, flags); 1150 nvt->study_state = ST_STUDY_NONE; 1151 nvt->wake_state = ST_WAKE_NONE; 1152 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 1153 1154 spin_lock_irqsave(&nvt->tx.lock, flags); 1155 nvt->tx.tx_state = ST_TX_NONE; 1156 spin_unlock_irqrestore(&nvt->tx.lock, flags); 1157 1158 /* disable all CIR interrupts */ 1159 nvt_cir_reg_write(nvt, 0, CIR_IREN); 1160 1161 nvt_efm_enable(nvt); 1162 1163 /* disable cir logical dev */ 1164 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 1165 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); 1166 1167 nvt_efm_disable(nvt); 1168 1169 /* make sure wake is enabled */ 1170 nvt_enable_wake(nvt); 1171 1172 return 0; 1173 } 1174 1175 static int nvt_resume(struct pnp_dev *pdev) 1176 { 1177 int ret = 0; 1178 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1179 1180 nvt_dbg("%s called", __func__); 1181 1182 /* open interrupt */ 1183 nvt_set_cir_iren(nvt); 1184 1185 /* Enable CIR logical device */ 1186 nvt_efm_enable(nvt); 1187 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 1188 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 1189 1190 nvt_efm_disable(nvt); 1191 1192 nvt_cir_regs_init(nvt); 1193 nvt_cir_wake_regs_init(nvt); 1194 1195 return ret; 1196 } 1197 1198 static void nvt_shutdown(struct pnp_dev *pdev) 1199 { 1200 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1201 nvt_enable_wake(nvt); 1202 } 1203 1204 static const struct pnp_device_id nvt_ids[] = { 1205 { "WEC0530", 0 }, /* CIR */ 1206 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ 1207 { "", 0 }, 1208 }; 1209 1210 static struct pnp_driver nvt_driver = { 1211 .name = NVT_DRIVER_NAME, 1212 .id_table = nvt_ids, 1213 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, 1214 .probe = nvt_probe, 1215 .remove = nvt_remove, 1216 .suspend = nvt_suspend, 1217 .resume = nvt_resume, 1218 .shutdown = nvt_shutdown, 1219 }; 1220 1221 static int nvt_init(void) 1222 { 1223 return pnp_register_driver(&nvt_driver); 1224 } 1225 1226 static void nvt_exit(void) 1227 { 1228 pnp_unregister_driver(&nvt_driver); 1229 } 1230 1231 module_param(debug, int, S_IRUGO | S_IWUSR); 1232 MODULE_PARM_DESC(debug, "Enable debugging output"); 1233 1234 MODULE_DEVICE_TABLE(pnp, nvt_ids); 1235 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); 1236 1237 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); 1238 MODULE_LICENSE("GPL"); 1239 1240 module_init(nvt_init); 1241 module_exit(nvt_exit); 1242