1 /* 2 * avm_fritz.c low level stuff for AVM FRITZ!CARD PCI ISDN cards 3 * Thanks to AVM, Berlin for informations 4 * 5 * Author Karsten Keil <keil@isdn4linux.de> 6 * 7 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/delay.h> 27 #include <linux/mISDNhw.h> 28 #include <linux/slab.h> 29 #include <asm/unaligned.h> 30 #include "ipac.h" 31 32 33 #define AVMFRITZ_REV "2.1" 34 35 static int AVM_cnt; 36 static int debug; 37 38 enum { 39 AVM_FRITZ_PCI, 40 AVM_FRITZ_PCIV2, 41 }; 42 43 #define HDLC_FIFO 0x0 44 #define HDLC_STATUS 0x4 45 #define CHIP_WINDOW 0x10 46 47 #define CHIP_INDEX 0x4 48 #define AVM_HDLC_1 0x00 49 #define AVM_HDLC_2 0x01 50 #define AVM_ISAC_FIFO 0x02 51 #define AVM_ISAC_REG_LOW 0x04 52 #define AVM_ISAC_REG_HIGH 0x06 53 54 #define AVM_STATUS0_IRQ_ISAC 0x01 55 #define AVM_STATUS0_IRQ_HDLC 0x02 56 #define AVM_STATUS0_IRQ_TIMER 0x04 57 #define AVM_STATUS0_IRQ_MASK 0x07 58 59 #define AVM_STATUS0_RESET 0x01 60 #define AVM_STATUS0_DIS_TIMER 0x02 61 #define AVM_STATUS0_RES_TIMER 0x04 62 #define AVM_STATUS0_ENA_IRQ 0x08 63 #define AVM_STATUS0_TESTBIT 0x10 64 65 #define AVM_STATUS1_INT_SEL 0x0f 66 #define AVM_STATUS1_ENA_IOM 0x80 67 68 #define HDLC_MODE_ITF_FLG 0x01 69 #define HDLC_MODE_TRANS 0x02 70 #define HDLC_MODE_CCR_7 0x04 71 #define HDLC_MODE_CCR_16 0x08 72 #define HDLC_MODE_TESTLOOP 0x80 73 74 #define HDLC_INT_XPR 0x80 75 #define HDLC_INT_XDU 0x40 76 #define HDLC_INT_RPR 0x20 77 #define HDLC_INT_MASK 0xE0 78 79 #define HDLC_STAT_RME 0x01 80 #define HDLC_STAT_RDO 0x10 81 #define HDLC_STAT_CRCVFRRAB 0x0E 82 #define HDLC_STAT_CRCVFR 0x06 83 #define HDLC_STAT_RML_MASK 0x3f00 84 85 #define HDLC_CMD_XRS 0x80 86 #define HDLC_CMD_XME 0x01 87 #define HDLC_CMD_RRS 0x20 88 #define HDLC_CMD_XML_MASK 0x3f00 89 #define HDLC_FIFO_SIZE 32 90 91 /* Fritz PCI v2.0 */ 92 93 #define AVM_HDLC_FIFO_1 0x10 94 #define AVM_HDLC_FIFO_2 0x18 95 96 #define AVM_HDLC_STATUS_1 0x14 97 #define AVM_HDLC_STATUS_2 0x1c 98 99 #define AVM_ISACX_INDEX 0x04 100 #define AVM_ISACX_DATA 0x08 101 102 /* data struct */ 103 #define LOG_SIZE 63 104 105 struct hdlc_stat_reg { 106 #ifdef __BIG_ENDIAN 107 u8 fill; 108 u8 mode; 109 u8 xml; 110 u8 cmd; 111 #else 112 u8 cmd; 113 u8 xml; 114 u8 mode; 115 u8 fill; 116 #endif 117 } __attribute__((packed)); 118 119 struct hdlc_hw { 120 union { 121 u32 ctrl; 122 struct hdlc_stat_reg sr; 123 } ctrl; 124 u32 stat; 125 }; 126 127 struct fritzcard { 128 struct list_head list; 129 struct pci_dev *pdev; 130 char name[MISDN_MAX_IDLEN]; 131 u8 type; 132 u8 ctrlreg; 133 u16 irq; 134 u32 irqcnt; 135 u32 addr; 136 spinlock_t lock; /* hw lock */ 137 struct isac_hw isac; 138 struct hdlc_hw hdlc[2]; 139 struct bchannel bch[2]; 140 char log[LOG_SIZE + 1]; 141 }; 142 143 static LIST_HEAD(Cards); 144 static DEFINE_RWLOCK(card_lock); /* protect Cards */ 145 146 static void 147 _set_debug(struct fritzcard *card) 148 { 149 card->isac.dch.debug = debug; 150 card->bch[0].debug = debug; 151 card->bch[1].debug = debug; 152 } 153 154 static int 155 set_debug(const char *val, struct kernel_param *kp) 156 { 157 int ret; 158 struct fritzcard *card; 159 160 ret = param_set_uint(val, kp); 161 if (!ret) { 162 read_lock(&card_lock); 163 list_for_each_entry(card, &Cards, list) 164 _set_debug(card); 165 read_unlock(&card_lock); 166 } 167 return ret; 168 } 169 170 MODULE_AUTHOR("Karsten Keil"); 171 MODULE_LICENSE("GPL v2"); 172 MODULE_VERSION(AVMFRITZ_REV); 173 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR); 174 MODULE_PARM_DESC(debug, "avmfritz debug mask"); 175 176 /* Interface functions */ 177 178 static u8 179 ReadISAC_V1(void *p, u8 offset) 180 { 181 struct fritzcard *fc = p; 182 u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW; 183 184 outb(idx, fc->addr + CHIP_INDEX); 185 return inb(fc->addr + CHIP_WINDOW + (offset & 0xf)); 186 } 187 188 static void 189 WriteISAC_V1(void *p, u8 offset, u8 value) 190 { 191 struct fritzcard *fc = p; 192 u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW; 193 194 outb(idx, fc->addr + CHIP_INDEX); 195 outb(value, fc->addr + CHIP_WINDOW + (offset & 0xf)); 196 } 197 198 static void 199 ReadFiFoISAC_V1(void *p, u8 off, u8 *data, int size) 200 { 201 struct fritzcard *fc = p; 202 203 outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX); 204 insb(fc->addr + CHIP_WINDOW, data, size); 205 } 206 207 static void 208 WriteFiFoISAC_V1(void *p, u8 off, u8 *data, int size) 209 { 210 struct fritzcard *fc = p; 211 212 outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX); 213 outsb(fc->addr + CHIP_WINDOW, data, size); 214 } 215 216 static u8 217 ReadISAC_V2(void *p, u8 offset) 218 { 219 struct fritzcard *fc = p; 220 221 outl(offset, fc->addr + AVM_ISACX_INDEX); 222 return 0xff & inl(fc->addr + AVM_ISACX_DATA); 223 } 224 225 static void 226 WriteISAC_V2(void *p, u8 offset, u8 value) 227 { 228 struct fritzcard *fc = p; 229 230 outl(offset, fc->addr + AVM_ISACX_INDEX); 231 outl(value, fc->addr + AVM_ISACX_DATA); 232 } 233 234 static void 235 ReadFiFoISAC_V2(void *p, u8 off, u8 *data, int size) 236 { 237 struct fritzcard *fc = p; 238 int i; 239 240 outl(off, fc->addr + AVM_ISACX_INDEX); 241 for (i = 0; i < size; i++) 242 data[i] = 0xff & inl(fc->addr + AVM_ISACX_DATA); 243 } 244 245 static void 246 WriteFiFoISAC_V2(void *p, u8 off, u8 *data, int size) 247 { 248 struct fritzcard *fc = p; 249 int i; 250 251 outl(off, fc->addr + AVM_ISACX_INDEX); 252 for (i = 0; i < size; i++) 253 outl(data[i], fc->addr + AVM_ISACX_DATA); 254 } 255 256 static struct bchannel * 257 Sel_BCS(struct fritzcard *fc, u32 channel) 258 { 259 if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) && 260 (fc->bch[0].nr & channel)) 261 return &fc->bch[0]; 262 else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) && 263 (fc->bch[1].nr & channel)) 264 return &fc->bch[1]; 265 else 266 return NULL; 267 } 268 269 static inline void 270 __write_ctrl_pci(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) { 271 u32 idx = channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1; 272 273 outl(idx, fc->addr + CHIP_INDEX); 274 outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS); 275 } 276 277 static inline void 278 __write_ctrl_pciv2(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) { 279 outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 : 280 AVM_HDLC_STATUS_1)); 281 } 282 283 void 284 write_ctrl(struct bchannel *bch, int which) { 285 struct fritzcard *fc = bch->hw; 286 struct hdlc_hw *hdlc; 287 288 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 289 pr_debug("%s: hdlc %c wr%x ctrl %x\n", fc->name, '@' + bch->nr, 290 which, hdlc->ctrl.ctrl); 291 switch (fc->type) { 292 case AVM_FRITZ_PCIV2: 293 __write_ctrl_pciv2(fc, hdlc, bch->nr); 294 break; 295 case AVM_FRITZ_PCI: 296 __write_ctrl_pci(fc, hdlc, bch->nr); 297 break; 298 } 299 } 300 301 302 static inline u32 303 __read_status_pci(u_long addr, u32 channel) 304 { 305 outl(channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1, addr + CHIP_INDEX); 306 return inl(addr + CHIP_WINDOW + HDLC_STATUS); 307 } 308 309 static inline u32 310 __read_status_pciv2(u_long addr, u32 channel) 311 { 312 return inl(addr + (channel == 2 ? AVM_HDLC_STATUS_2 : 313 AVM_HDLC_STATUS_1)); 314 } 315 316 317 static u32 318 read_status(struct fritzcard *fc, u32 channel) 319 { 320 switch (fc->type) { 321 case AVM_FRITZ_PCIV2: 322 return __read_status_pciv2(fc->addr, channel); 323 case AVM_FRITZ_PCI: 324 return __read_status_pci(fc->addr, channel); 325 } 326 /* dummy */ 327 return 0; 328 } 329 330 static void 331 enable_hwirq(struct fritzcard *fc) 332 { 333 fc->ctrlreg |= AVM_STATUS0_ENA_IRQ; 334 outb(fc->ctrlreg, fc->addr + 2); 335 } 336 337 static void 338 disable_hwirq(struct fritzcard *fc) 339 { 340 fc->ctrlreg &= ~AVM_STATUS0_ENA_IRQ; 341 outb(fc->ctrlreg, fc->addr + 2); 342 } 343 344 static int 345 modehdlc(struct bchannel *bch, int protocol) 346 { 347 struct fritzcard *fc = bch->hw; 348 struct hdlc_hw *hdlc; 349 350 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 351 pr_debug("%s: hdlc %c protocol %x-->%x ch %d\n", fc->name, 352 '@' + bch->nr, bch->state, protocol, bch->nr); 353 hdlc->ctrl.ctrl = 0; 354 switch (protocol) { 355 case -1: /* used for init */ 356 bch->state = -1; 357 case ISDN_P_NONE: 358 if (bch->state == ISDN_P_NONE) 359 break; 360 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 361 hdlc->ctrl.sr.mode = HDLC_MODE_TRANS; 362 write_ctrl(bch, 5); 363 bch->state = ISDN_P_NONE; 364 test_and_clear_bit(FLG_HDLC, &bch->Flags); 365 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags); 366 break; 367 case ISDN_P_B_RAW: 368 bch->state = protocol; 369 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 370 hdlc->ctrl.sr.mode = HDLC_MODE_TRANS; 371 write_ctrl(bch, 5); 372 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; 373 write_ctrl(bch, 1); 374 hdlc->ctrl.sr.cmd = 0; 375 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags); 376 break; 377 case ISDN_P_B_HDLC: 378 bch->state = protocol; 379 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 380 hdlc->ctrl.sr.mode = HDLC_MODE_ITF_FLG; 381 write_ctrl(bch, 5); 382 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; 383 write_ctrl(bch, 1); 384 hdlc->ctrl.sr.cmd = 0; 385 test_and_set_bit(FLG_HDLC, &bch->Flags); 386 break; 387 default: 388 pr_info("%s: protocol not known %x\n", fc->name, protocol); 389 return -ENOPROTOOPT; 390 } 391 return 0; 392 } 393 394 static void 395 hdlc_empty_fifo(struct bchannel *bch, int count) 396 { 397 u32 *ptr; 398 u8 *p; 399 u32 val, addr; 400 int cnt = 0; 401 struct fritzcard *fc = bch->hw; 402 403 pr_debug("%s: %s %d\n", fc->name, __func__, count); 404 if (!bch->rx_skb) { 405 bch->rx_skb = mI_alloc_skb(bch->maxlen, GFP_ATOMIC); 406 if (!bch->rx_skb) { 407 pr_info("%s: B receive out of memory\n", 408 fc->name); 409 return; 410 } 411 } 412 if ((bch->rx_skb->len + count) > bch->maxlen) { 413 pr_debug("%s: overrun %d\n", fc->name, 414 bch->rx_skb->len + count); 415 return; 416 } 417 p = skb_put(bch->rx_skb, count); 418 ptr = (u32 *)p; 419 if (AVM_FRITZ_PCIV2 == fc->type) 420 addr = fc->addr + (bch->nr == 2 ? 421 AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1); 422 else { 423 addr = fc->addr + CHIP_WINDOW; 424 outl(bch->nr == 2 ? AVM_HDLC_2 : AVM_HDLC_1, fc->addr); 425 } 426 while (cnt < count) { 427 val = le32_to_cpu(inl(addr)); 428 put_unaligned(val, ptr); 429 ptr++; 430 cnt += 4; 431 } 432 if (debug & DEBUG_HW_BFIFO) { 433 snprintf(fc->log, LOG_SIZE, "B%1d-recv %s %d ", 434 bch->nr, fc->name, count); 435 print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count); 436 } 437 } 438 439 static void 440 hdlc_fill_fifo(struct bchannel *bch) 441 { 442 struct fritzcard *fc = bch->hw; 443 struct hdlc_hw *hdlc; 444 int count, cnt = 0; 445 u8 *p; 446 u32 *ptr, val, addr; 447 448 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 449 if (!bch->tx_skb) 450 return; 451 count = bch->tx_skb->len - bch->tx_idx; 452 if (count <= 0) 453 return; 454 p = bch->tx_skb->data + bch->tx_idx; 455 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME; 456 if (count > HDLC_FIFO_SIZE) { 457 count = HDLC_FIFO_SIZE; 458 } else { 459 if (test_bit(FLG_HDLC, &bch->Flags)) 460 hdlc->ctrl.sr.cmd |= HDLC_CMD_XME; 461 } 462 pr_debug("%s: %s %d/%d/%d", fc->name, __func__, count, 463 bch->tx_idx, bch->tx_skb->len); 464 ptr = (u32 *)p; 465 bch->tx_idx += count; 466 hdlc->ctrl.sr.xml = ((count == HDLC_FIFO_SIZE) ? 0 : count); 467 if (AVM_FRITZ_PCIV2 == fc->type) { 468 __write_ctrl_pciv2(fc, hdlc, bch->nr); 469 addr = fc->addr + (bch->nr == 2 ? 470 AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1); 471 } else { 472 __write_ctrl_pci(fc, hdlc, bch->nr); 473 addr = fc->addr + CHIP_WINDOW; 474 } 475 while (cnt < count) { 476 val = get_unaligned(ptr); 477 outl(cpu_to_le32(val), addr); 478 ptr++; 479 cnt += 4; 480 } 481 if (debug & DEBUG_HW_BFIFO) { 482 snprintf(fc->log, LOG_SIZE, "B%1d-send %s %d ", 483 bch->nr, fc->name, count); 484 print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count); 485 } 486 } 487 488 static void 489 HDLC_irq_xpr(struct bchannel *bch) 490 { 491 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len) 492 hdlc_fill_fifo(bch); 493 else { 494 if (bch->tx_skb) { 495 /* send confirm, on trans, free on hdlc. */ 496 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) 497 confirm_Bsend(bch); 498 dev_kfree_skb(bch->tx_skb); 499 } 500 if (get_next_bframe(bch)) 501 hdlc_fill_fifo(bch); 502 } 503 } 504 505 static void 506 HDLC_irq(struct bchannel *bch, u32 stat) 507 { 508 struct fritzcard *fc = bch->hw; 509 int len; 510 struct hdlc_hw *hdlc; 511 512 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 513 pr_debug("%s: ch%d stat %#x\n", fc->name, bch->nr, stat); 514 if (stat & HDLC_INT_RPR) { 515 if (stat & HDLC_STAT_RDO) { 516 hdlc->ctrl.sr.xml = 0; 517 hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS; 518 write_ctrl(bch, 1); 519 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS; 520 write_ctrl(bch, 1); 521 if (bch->rx_skb) 522 skb_trim(bch->rx_skb, 0); 523 } else { 524 len = (stat & HDLC_STAT_RML_MASK) >> 8; 525 if (!len) 526 len = 32; 527 hdlc_empty_fifo(bch, len); 528 if (!bch->rx_skb) 529 goto handle_tx; 530 if ((stat & HDLC_STAT_RME) || test_bit(FLG_TRANSPARENT, 531 &bch->Flags)) { 532 if (((stat & HDLC_STAT_CRCVFRRAB) == 533 HDLC_STAT_CRCVFR) || 534 test_bit(FLG_TRANSPARENT, &bch->Flags)) { 535 recv_Bchannel(bch, 0); 536 } else { 537 pr_debug("%s: got invalid frame\n", 538 fc->name); 539 skb_trim(bch->rx_skb, 0); 540 } 541 } 542 } 543 } 544 handle_tx: 545 if (stat & HDLC_INT_XDU) { 546 /* Here we lost an TX interrupt, so 547 * restart transmitting the whole frame on HDLC 548 * in transparent mode we send the next data 549 */ 550 if (bch->tx_skb) 551 pr_debug("%s: ch%d XDU len(%d) idx(%d) Flags(%lx)\n", 552 fc->name, bch->nr, bch->tx_skb->len, 553 bch->tx_idx, bch->Flags); 554 else 555 pr_debug("%s: ch%d XDU no tx_skb Flags(%lx)\n", 556 fc->name, bch->nr, bch->Flags); 557 if (bch->tx_skb && bch->tx_skb->len) { 558 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 559 bch->tx_idx = 0; 560 } 561 hdlc->ctrl.sr.xml = 0; 562 hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS; 563 write_ctrl(bch, 1); 564 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS; 565 HDLC_irq_xpr(bch); 566 return; 567 } else if (stat & HDLC_INT_XPR) 568 HDLC_irq_xpr(bch); 569 } 570 571 static inline void 572 HDLC_irq_main(struct fritzcard *fc) 573 { 574 u32 stat; 575 struct bchannel *bch; 576 577 stat = read_status(fc, 1); 578 if (stat & HDLC_INT_MASK) { 579 bch = Sel_BCS(fc, 1); 580 if (bch) 581 HDLC_irq(bch, stat); 582 else 583 pr_debug("%s: spurious ch1 IRQ\n", fc->name); 584 } 585 stat = read_status(fc, 2); 586 if (stat & HDLC_INT_MASK) { 587 bch = Sel_BCS(fc, 2); 588 if (bch) 589 HDLC_irq(bch, stat); 590 else 591 pr_debug("%s: spurious ch2 IRQ\n", fc->name); 592 } 593 } 594 595 static irqreturn_t 596 avm_fritz_interrupt(int intno, void *dev_id) 597 { 598 struct fritzcard *fc = dev_id; 599 u8 val; 600 u8 sval; 601 602 spin_lock(&fc->lock); 603 sval = inb(fc->addr + 2); 604 pr_debug("%s: irq stat0 %x\n", fc->name, sval); 605 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) { 606 /* shared IRQ from other HW */ 607 spin_unlock(&fc->lock); 608 return IRQ_NONE; 609 } 610 fc->irqcnt++; 611 612 if (!(sval & AVM_STATUS0_IRQ_ISAC)) { 613 val = ReadISAC_V1(fc, ISAC_ISTA); 614 mISDNisac_irq(&fc->isac, val); 615 } 616 if (!(sval & AVM_STATUS0_IRQ_HDLC)) 617 HDLC_irq_main(fc); 618 spin_unlock(&fc->lock); 619 return IRQ_HANDLED; 620 } 621 622 static irqreturn_t 623 avm_fritzv2_interrupt(int intno, void *dev_id) 624 { 625 struct fritzcard *fc = dev_id; 626 u8 val; 627 u8 sval; 628 629 spin_lock(&fc->lock); 630 sval = inb(fc->addr + 2); 631 pr_debug("%s: irq stat0 %x\n", fc->name, sval); 632 if (!(sval & AVM_STATUS0_IRQ_MASK)) { 633 /* shared IRQ from other HW */ 634 spin_unlock(&fc->lock); 635 return IRQ_NONE; 636 } 637 fc->irqcnt++; 638 639 if (sval & AVM_STATUS0_IRQ_HDLC) 640 HDLC_irq_main(fc); 641 if (sval & AVM_STATUS0_IRQ_ISAC) { 642 val = ReadISAC_V2(fc, ISACX_ISTA); 643 mISDNisac_irq(&fc->isac, val); 644 } 645 if (sval & AVM_STATUS0_IRQ_TIMER) { 646 pr_debug("%s: timer irq\n", fc->name); 647 outb(fc->ctrlreg | AVM_STATUS0_RES_TIMER, fc->addr + 2); 648 udelay(1); 649 outb(fc->ctrlreg, fc->addr + 2); 650 } 651 spin_unlock(&fc->lock); 652 return IRQ_HANDLED; 653 } 654 655 static int 656 avm_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb) 657 { 658 struct bchannel *bch = container_of(ch, struct bchannel, ch); 659 struct fritzcard *fc = bch->hw; 660 int ret = -EINVAL; 661 struct mISDNhead *hh = mISDN_HEAD_P(skb); 662 u32 id; 663 u_long flags; 664 665 switch (hh->prim) { 666 case PH_DATA_REQ: 667 spin_lock_irqsave(&fc->lock, flags); 668 ret = bchannel_senddata(bch, skb); 669 if (ret > 0) { /* direct TX */ 670 id = hh->id; /* skb can be freed */ 671 hdlc_fill_fifo(bch); 672 ret = 0; 673 spin_unlock_irqrestore(&fc->lock, flags); 674 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 675 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 676 } else 677 spin_unlock_irqrestore(&fc->lock, flags); 678 return ret; 679 case PH_ACTIVATE_REQ: 680 spin_lock_irqsave(&fc->lock, flags); 681 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 682 ret = modehdlc(bch, ch->protocol); 683 else 684 ret = 0; 685 spin_unlock_irqrestore(&fc->lock, flags); 686 if (!ret) 687 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 688 NULL, GFP_KERNEL); 689 break; 690 case PH_DEACTIVATE_REQ: 691 spin_lock_irqsave(&fc->lock, flags); 692 mISDN_clear_bchannel(bch); 693 modehdlc(bch, ISDN_P_NONE); 694 spin_unlock_irqrestore(&fc->lock, flags); 695 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 696 NULL, GFP_KERNEL); 697 ret = 0; 698 break; 699 } 700 if (!ret) 701 dev_kfree_skb(skb); 702 return ret; 703 } 704 705 static void 706 inithdlc(struct fritzcard *fc) 707 { 708 modehdlc(&fc->bch[0], -1); 709 modehdlc(&fc->bch[1], -1); 710 } 711 712 void 713 clear_pending_hdlc_ints(struct fritzcard *fc) 714 { 715 u32 val; 716 717 val = read_status(fc, 1); 718 pr_debug("%s: HDLC 1 STA %x\n", fc->name, val); 719 val = read_status(fc, 2); 720 pr_debug("%s: HDLC 2 STA %x\n", fc->name, val); 721 } 722 723 static void 724 reset_avm(struct fritzcard *fc) 725 { 726 switch (fc->type) { 727 case AVM_FRITZ_PCI: 728 fc->ctrlreg = AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER; 729 break; 730 case AVM_FRITZ_PCIV2: 731 fc->ctrlreg = AVM_STATUS0_RESET; 732 break; 733 } 734 if (debug & DEBUG_HW) 735 pr_notice("%s: reset\n", fc->name); 736 disable_hwirq(fc); 737 mdelay(5); 738 switch (fc->type) { 739 case AVM_FRITZ_PCI: 740 fc->ctrlreg = AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER; 741 disable_hwirq(fc); 742 outb(AVM_STATUS1_ENA_IOM, fc->addr + 3); 743 break; 744 case AVM_FRITZ_PCIV2: 745 fc->ctrlreg = 0; 746 disable_hwirq(fc); 747 break; 748 } 749 mdelay(1); 750 if (debug & DEBUG_HW) 751 pr_notice("%s: S0/S1 %x/%x\n", fc->name, 752 inb(fc->addr + 2), inb(fc->addr + 3)); 753 } 754 755 static int 756 init_card(struct fritzcard *fc) 757 { 758 int ret, cnt = 3; 759 u_long flags; 760 761 reset_avm(fc); /* disable IRQ */ 762 if (fc->type == AVM_FRITZ_PCIV2) 763 ret = request_irq(fc->irq, avm_fritzv2_interrupt, 764 IRQF_SHARED, fc->name, fc); 765 else 766 ret = request_irq(fc->irq, avm_fritz_interrupt, 767 IRQF_SHARED, fc->name, fc); 768 if (ret) { 769 pr_info("%s: couldn't get interrupt %d\n", 770 fc->name, fc->irq); 771 return ret; 772 } 773 while (cnt--) { 774 spin_lock_irqsave(&fc->lock, flags); 775 ret = fc->isac.init(&fc->isac); 776 if (ret) { 777 spin_unlock_irqrestore(&fc->lock, flags); 778 pr_info("%s: ISAC init failed with %d\n", 779 fc->name, ret); 780 break; 781 } 782 clear_pending_hdlc_ints(fc); 783 inithdlc(fc); 784 enable_hwirq(fc); 785 /* RESET Receiver and Transmitter */ 786 if (AVM_FRITZ_PCIV2 == fc->type) { 787 WriteISAC_V2(fc, ISACX_MASK, 0); 788 WriteISAC_V2(fc, ISACX_CMDRD, 0x41); 789 } else { 790 WriteISAC_V1(fc, ISAC_MASK, 0); 791 WriteISAC_V1(fc, ISAC_CMDR, 0x41); 792 } 793 spin_unlock_irqrestore(&fc->lock, flags); 794 /* Timeout 10ms */ 795 msleep_interruptible(10); 796 if (debug & DEBUG_HW) 797 pr_notice("%s: IRQ %d count %d\n", fc->name, 798 fc->irq, fc->irqcnt); 799 if (!fc->irqcnt) { 800 pr_info("%s: IRQ(%d) getting no IRQs during init %d\n", 801 fc->name, fc->irq, 3 - cnt); 802 reset_avm(fc); 803 } else 804 return 0; 805 } 806 free_irq(fc->irq, fc); 807 return -EIO; 808 } 809 810 static int 811 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 812 { 813 int ret = 0; 814 struct fritzcard *fc = bch->hw; 815 816 switch (cq->op) { 817 case MISDN_CTRL_GETOP: 818 cq->op = 0; 819 break; 820 /* Nothing implemented yet */ 821 case MISDN_CTRL_FILL_EMPTY: 822 default: 823 pr_info("%s: %s unknown Op %x\n", fc->name, __func__, cq->op); 824 ret = -EINVAL; 825 break; 826 } 827 return ret; 828 } 829 830 static int 831 avm_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 832 { 833 struct bchannel *bch = container_of(ch, struct bchannel, ch); 834 struct fritzcard *fc = bch->hw; 835 int ret = -EINVAL; 836 u_long flags; 837 838 pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg); 839 switch (cmd) { 840 case CLOSE_CHANNEL: 841 test_and_clear_bit(FLG_OPEN, &bch->Flags); 842 if (test_bit(FLG_ACTIVE, &bch->Flags)) { 843 spin_lock_irqsave(&fc->lock, flags); 844 mISDN_freebchannel(bch); 845 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags); 846 test_and_clear_bit(FLG_ACTIVE, &bch->Flags); 847 modehdlc(bch, ISDN_P_NONE); 848 spin_unlock_irqrestore(&fc->lock, flags); 849 } 850 ch->protocol = ISDN_P_NONE; 851 ch->peer = NULL; 852 module_put(THIS_MODULE); 853 ret = 0; 854 break; 855 case CONTROL_CHANNEL: 856 ret = channel_bctrl(bch, arg); 857 break; 858 default: 859 pr_info("%s: %s unknown prim(%x)\n", fc->name, __func__, cmd); 860 } 861 return ret; 862 } 863 864 static int 865 channel_ctrl(struct fritzcard *fc, struct mISDN_ctrl_req *cq) 866 { 867 int ret = 0; 868 869 switch (cq->op) { 870 case MISDN_CTRL_GETOP: 871 cq->op = MISDN_CTRL_LOOP; 872 break; 873 case MISDN_CTRL_LOOP: 874 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ 875 if (cq->channel < 0 || cq->channel > 3) { 876 ret = -EINVAL; 877 break; 878 } 879 ret = fc->isac.ctrl(&fc->isac, HW_TESTLOOP, cq->channel); 880 break; 881 default: 882 pr_info("%s: %s unknown Op %x\n", fc->name, __func__, cq->op); 883 ret = -EINVAL; 884 break; 885 } 886 return ret; 887 } 888 889 static int 890 open_bchannel(struct fritzcard *fc, struct channel_req *rq) 891 { 892 struct bchannel *bch; 893 894 if (rq->adr.channel > 2) 895 return -EINVAL; 896 if (rq->protocol == ISDN_P_NONE) 897 return -EINVAL; 898 bch = &fc->bch[rq->adr.channel - 1]; 899 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 900 return -EBUSY; /* b-channel can be only open once */ 901 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 902 bch->ch.protocol = rq->protocol; 903 rq->ch = &bch->ch; 904 return 0; 905 } 906 907 /* 908 * device control function 909 */ 910 static int 911 avm_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 912 { 913 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 914 struct dchannel *dch = container_of(dev, struct dchannel, dev); 915 struct fritzcard *fc = dch->hw; 916 struct channel_req *rq; 917 int err = 0; 918 919 pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg); 920 switch (cmd) { 921 case OPEN_CHANNEL: 922 rq = arg; 923 if (rq->protocol == ISDN_P_TE_S0) 924 err = fc->isac.open(&fc->isac, rq); 925 else 926 err = open_bchannel(fc, rq); 927 if (err) 928 break; 929 if (!try_module_get(THIS_MODULE)) 930 pr_info("%s: cannot get module\n", fc->name); 931 break; 932 case CLOSE_CHANNEL: 933 pr_debug("%s: dev(%d) close from %p\n", fc->name, dch->dev.id, 934 __builtin_return_address(0)); 935 module_put(THIS_MODULE); 936 break; 937 case CONTROL_CHANNEL: 938 err = channel_ctrl(fc, arg); 939 break; 940 default: 941 pr_debug("%s: %s unknown command %x\n", 942 fc->name, __func__, cmd); 943 return -EINVAL; 944 } 945 return err; 946 } 947 948 int 949 setup_fritz(struct fritzcard *fc) 950 { 951 u32 val, ver; 952 953 if (!request_region(fc->addr, 32, fc->name)) { 954 pr_info("%s: AVM config port %x-%x already in use\n", 955 fc->name, fc->addr, fc->addr + 31); 956 return -EIO; 957 } 958 switch (fc->type) { 959 case AVM_FRITZ_PCI: 960 val = inl(fc->addr); 961 outl(AVM_HDLC_1, fc->addr + CHIP_INDEX); 962 ver = inl(fc->addr + CHIP_WINDOW + HDLC_STATUS) >> 24; 963 if (debug & DEBUG_HW) { 964 pr_notice("%s: PCI stat %#x\n", fc->name, val); 965 pr_notice("%s: PCI Class %X Rev %d\n", fc->name, 966 val & 0xff, (val >> 8) & 0xff); 967 pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf); 968 } 969 ASSIGN_FUNC(V1, ISAC, fc->isac); 970 fc->isac.type = IPAC_TYPE_ISAC; 971 break; 972 case AVM_FRITZ_PCIV2: 973 val = inl(fc->addr); 974 ver = inl(fc->addr + AVM_HDLC_STATUS_1) >> 24; 975 if (debug & DEBUG_HW) { 976 pr_notice("%s: PCI V2 stat %#x\n", fc->name, val); 977 pr_notice("%s: PCI V2 Class %X Rev %d\n", fc->name, 978 val & 0xff, (val>>8) & 0xff); 979 pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf); 980 } 981 ASSIGN_FUNC(V2, ISAC, fc->isac); 982 fc->isac.type = IPAC_TYPE_ISACX; 983 break; 984 default: 985 release_region(fc->addr, 32); 986 pr_info("%s: AVM unknown type %d\n", fc->name, fc->type); 987 return -ENODEV; 988 } 989 pr_notice("%s: %s config irq:%d base:0x%X\n", fc->name, 990 (fc->type == AVM_FRITZ_PCI) ? "AVM Fritz!CARD PCI" : 991 "AVM Fritz!CARD PCIv2", fc->irq, fc->addr); 992 return 0; 993 } 994 995 static void 996 release_card(struct fritzcard *card) 997 { 998 u_long flags; 999 1000 disable_hwirq(card); 1001 spin_lock_irqsave(&card->lock, flags); 1002 modehdlc(&card->bch[0], ISDN_P_NONE); 1003 modehdlc(&card->bch[1], ISDN_P_NONE); 1004 spin_unlock_irqrestore(&card->lock, flags); 1005 card->isac.release(&card->isac); 1006 free_irq(card->irq, card); 1007 mISDN_freebchannel(&card->bch[1]); 1008 mISDN_freebchannel(&card->bch[0]); 1009 mISDN_unregister_device(&card->isac.dch.dev); 1010 release_region(card->addr, 32); 1011 pci_disable_device(card->pdev); 1012 pci_set_drvdata(card->pdev, NULL); 1013 write_lock_irqsave(&card_lock, flags); 1014 list_del(&card->list); 1015 write_unlock_irqrestore(&card_lock, flags); 1016 kfree(card); 1017 AVM_cnt--; 1018 } 1019 1020 static int __devinit 1021 setup_instance(struct fritzcard *card) 1022 { 1023 int i, err; 1024 u_long flags; 1025 1026 snprintf(card->name, MISDN_MAX_IDLEN - 1, "AVM.%d", AVM_cnt + 1); 1027 write_lock_irqsave(&card_lock, flags); 1028 list_add_tail(&card->list, &Cards); 1029 write_unlock_irqrestore(&card_lock, flags); 1030 1031 _set_debug(card); 1032 card->isac.name = card->name; 1033 spin_lock_init(&card->lock); 1034 card->isac.hwlock = &card->lock; 1035 mISDNisac_init(&card->isac, card); 1036 1037 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1038 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1039 card->isac.dch.dev.D.ctrl = avm_dctrl; 1040 for (i = 0; i < 2; i++) { 1041 card->bch[i].nr = i + 1; 1042 set_channelmap(i + 1, card->isac.dch.dev.channelmap); 1043 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM); 1044 card->bch[i].hw = card; 1045 card->bch[i].ch.send = avm_l2l1B; 1046 card->bch[i].ch.ctrl = avm_bctrl; 1047 card->bch[i].ch.nr = i + 1; 1048 list_add(&card->bch[i].ch.list, &card->isac.dch.dev.bchannels); 1049 } 1050 err = setup_fritz(card); 1051 if (err) 1052 goto error; 1053 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev, 1054 card->name); 1055 if (err) 1056 goto error_reg; 1057 err = init_card(card); 1058 if (!err) { 1059 AVM_cnt++; 1060 pr_notice("AVM %d cards installed DEBUG\n", AVM_cnt); 1061 return 0; 1062 } 1063 mISDN_unregister_device(&card->isac.dch.dev); 1064 error_reg: 1065 release_region(card->addr, 32); 1066 error: 1067 card->isac.release(&card->isac); 1068 mISDN_freebchannel(&card->bch[1]); 1069 mISDN_freebchannel(&card->bch[0]); 1070 write_lock_irqsave(&card_lock, flags); 1071 list_del(&card->list); 1072 write_unlock_irqrestore(&card_lock, flags); 1073 kfree(card); 1074 return err; 1075 } 1076 1077 static int __devinit 1078 fritzpci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1079 { 1080 int err = -ENOMEM; 1081 struct fritzcard *card; 1082 1083 card = kzalloc(sizeof(struct fritzcard), GFP_KERNEL); 1084 if (!card) { 1085 pr_info("No kmem for fritzcard\n"); 1086 return err; 1087 } 1088 if (pdev->device == PCI_DEVICE_ID_AVM_A1_V2) 1089 card->type = AVM_FRITZ_PCIV2; 1090 else 1091 card->type = AVM_FRITZ_PCI; 1092 card->pdev = pdev; 1093 err = pci_enable_device(pdev); 1094 if (err) { 1095 kfree(card); 1096 return err; 1097 } 1098 1099 pr_notice("mISDN: found adapter %s at %s\n", 1100 (char *) ent->driver_data, pci_name(pdev)); 1101 1102 card->addr = pci_resource_start(pdev, 1); 1103 card->irq = pdev->irq; 1104 pci_set_drvdata(pdev, card); 1105 err = setup_instance(card); 1106 if (err) 1107 pci_set_drvdata(pdev, NULL); 1108 return err; 1109 } 1110 1111 static void __devexit 1112 fritz_remove_pci(struct pci_dev *pdev) 1113 { 1114 struct fritzcard *card = pci_get_drvdata(pdev); 1115 1116 if (card) 1117 release_card(card); 1118 else 1119 if (debug) 1120 pr_info("%s: drvdata already removed\n", __func__); 1121 } 1122 1123 static struct pci_device_id fcpci_ids[] __devinitdata = { 1124 { PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1, PCI_ANY_ID, PCI_ANY_ID, 1125 0, 0, (unsigned long) "Fritz!Card PCI"}, 1126 { PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1_V2, PCI_ANY_ID, PCI_ANY_ID, 1127 0, 0, (unsigned long) "Fritz!Card PCI v2" }, 1128 { } 1129 }; 1130 MODULE_DEVICE_TABLE(pci, fcpci_ids); 1131 1132 static struct pci_driver fcpci_driver = { 1133 .name = "fcpci", 1134 .probe = fritzpci_probe, 1135 .remove = __devexit_p(fritz_remove_pci), 1136 .id_table = fcpci_ids, 1137 }; 1138 1139 static int __init AVM_init(void) 1140 { 1141 int err; 1142 1143 pr_notice("AVM Fritz PCI driver Rev. %s\n", AVMFRITZ_REV); 1144 err = pci_register_driver(&fcpci_driver); 1145 return err; 1146 } 1147 1148 static void __exit AVM_cleanup(void) 1149 { 1150 pci_unregister_driver(&fcpci_driver); 1151 } 1152 1153 module_init(AVM_init); 1154 module_exit(AVM_cleanup); 1155