1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/acpi.h> 37 #include <linux/irqdomain.h> 38 #include <linux/interrupt.h> 39 #include <linux/percpu.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqchip/arm-gic.h> 44 45 #include <asm/cputype.h> 46 #include <asm/irq.h> 47 #include <asm/exception.h> 48 #include <asm/smp_plat.h> 49 #include <asm/virt.h> 50 51 #include "irq-gic-common.h" 52 53 #ifdef CONFIG_ARM64 54 #include <asm/cpufeature.h> 55 56 static void gic_check_cpu_features(void) 57 { 58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 59 TAINT_CPU_OUT_OF_SPEC, 60 "GICv3 system registers enabled, broken firmware!\n"); 61 } 62 #else 63 #define gic_check_cpu_features() do { } while(0) 64 #endif 65 66 union gic_base { 67 void __iomem *common_base; 68 void __percpu * __iomem *percpu_base; 69 }; 70 71 struct gic_chip_data { 72 struct irq_chip chip; 73 union gic_base dist_base; 74 union gic_base cpu_base; 75 void __iomem *raw_dist_base; 76 void __iomem *raw_cpu_base; 77 u32 percpu_offset; 78 #ifdef CONFIG_CPU_PM 79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 83 u32 __percpu *saved_ppi_enable; 84 u32 __percpu *saved_ppi_active; 85 u32 __percpu *saved_ppi_conf; 86 #endif 87 struct irq_domain *domain; 88 unsigned int gic_irqs; 89 #ifdef CONFIG_GIC_NON_BANKED 90 void __iomem *(*get_base)(union gic_base *); 91 #endif 92 }; 93 94 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 95 96 /* 97 * The GIC mapping of CPU interfaces does not necessarily match 98 * the logical CPU numbering. Let's use a mapping as returned 99 * by the GIC itself. 100 */ 101 #define NR_GIC_CPU_IF 8 102 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 103 104 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 105 106 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 107 108 static struct gic_kvm_info gic_v2_kvm_info; 109 110 #ifdef CONFIG_GIC_NON_BANKED 111 static void __iomem *gic_get_percpu_base(union gic_base *base) 112 { 113 return raw_cpu_read(*base->percpu_base); 114 } 115 116 static void __iomem *gic_get_common_base(union gic_base *base) 117 { 118 return base->common_base; 119 } 120 121 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 122 { 123 return data->get_base(&data->dist_base); 124 } 125 126 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 127 { 128 return data->get_base(&data->cpu_base); 129 } 130 131 static inline void gic_set_base_accessor(struct gic_chip_data *data, 132 void __iomem *(*f)(union gic_base *)) 133 { 134 data->get_base = f; 135 } 136 #else 137 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 138 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 139 #define gic_set_base_accessor(d, f) 140 #endif 141 142 static inline void __iomem *gic_dist_base(struct irq_data *d) 143 { 144 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 145 return gic_data_dist_base(gic_data); 146 } 147 148 static inline void __iomem *gic_cpu_base(struct irq_data *d) 149 { 150 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 151 return gic_data_cpu_base(gic_data); 152 } 153 154 static inline unsigned int gic_irq(struct irq_data *d) 155 { 156 return d->hwirq; 157 } 158 159 static inline bool cascading_gic_irq(struct irq_data *d) 160 { 161 void *data = irq_data_get_irq_handler_data(d); 162 163 /* 164 * If handler_data is set, this is a cascading interrupt, and 165 * it cannot possibly be forwarded. 166 */ 167 return data != NULL; 168 } 169 170 /* 171 * Routines to acknowledge, disable and enable interrupts 172 */ 173 static void gic_poke_irq(struct irq_data *d, u32 offset) 174 { 175 u32 mask = 1 << (gic_irq(d) % 32); 176 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 177 } 178 179 static int gic_peek_irq(struct irq_data *d, u32 offset) 180 { 181 u32 mask = 1 << (gic_irq(d) % 32); 182 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 183 } 184 185 static void gic_mask_irq(struct irq_data *d) 186 { 187 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 188 } 189 190 static void gic_eoimode1_mask_irq(struct irq_data *d) 191 { 192 gic_mask_irq(d); 193 /* 194 * When masking a forwarded interrupt, make sure it is 195 * deactivated as well. 196 * 197 * This ensures that an interrupt that is getting 198 * disabled/masked will not get "stuck", because there is 199 * noone to deactivate it (guest is being terminated). 200 */ 201 if (irqd_is_forwarded_to_vcpu(d)) 202 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 203 } 204 205 static void gic_unmask_irq(struct irq_data *d) 206 { 207 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 208 } 209 210 static void gic_eoi_irq(struct irq_data *d) 211 { 212 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 213 } 214 215 static void gic_eoimode1_eoi_irq(struct irq_data *d) 216 { 217 /* Do not deactivate an IRQ forwarded to a vcpu. */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 return; 220 221 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 222 } 223 224 static int gic_irq_set_irqchip_state(struct irq_data *d, 225 enum irqchip_irq_state which, bool val) 226 { 227 u32 reg; 228 229 switch (which) { 230 case IRQCHIP_STATE_PENDING: 231 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 232 break; 233 234 case IRQCHIP_STATE_ACTIVE: 235 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 236 break; 237 238 case IRQCHIP_STATE_MASKED: 239 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 240 break; 241 242 default: 243 return -EINVAL; 244 } 245 246 gic_poke_irq(d, reg); 247 return 0; 248 } 249 250 static int gic_irq_get_irqchip_state(struct irq_data *d, 251 enum irqchip_irq_state which, bool *val) 252 { 253 switch (which) { 254 case IRQCHIP_STATE_PENDING: 255 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 256 break; 257 258 case IRQCHIP_STATE_ACTIVE: 259 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 260 break; 261 262 case IRQCHIP_STATE_MASKED: 263 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 264 break; 265 266 default: 267 return -EINVAL; 268 } 269 270 return 0; 271 } 272 273 static int gic_set_type(struct irq_data *d, unsigned int type) 274 { 275 void __iomem *base = gic_dist_base(d); 276 unsigned int gicirq = gic_irq(d); 277 278 /* Interrupt configuration for SGIs can't be changed */ 279 if (gicirq < 16) 280 return -EINVAL; 281 282 /* SPIs have restrictions on the supported types */ 283 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 284 type != IRQ_TYPE_EDGE_RISING) 285 return -EINVAL; 286 287 return gic_configure_irq(gicirq, type, base, NULL); 288 } 289 290 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 291 { 292 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 293 if (cascading_gic_irq(d)) 294 return -EINVAL; 295 296 if (vcpu) 297 irqd_set_forwarded_to_vcpu(d); 298 else 299 irqd_clr_forwarded_to_vcpu(d); 300 return 0; 301 } 302 303 #ifdef CONFIG_SMP 304 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 305 bool force) 306 { 307 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 308 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 309 u32 val, mask, bit; 310 unsigned long flags; 311 312 if (!force) 313 cpu = cpumask_any_and(mask_val, cpu_online_mask); 314 else 315 cpu = cpumask_first(mask_val); 316 317 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 318 return -EINVAL; 319 320 raw_spin_lock_irqsave(&irq_controller_lock, flags); 321 mask = 0xff << shift; 322 bit = gic_cpu_map[cpu] << shift; 323 val = readl_relaxed(reg) & ~mask; 324 writel_relaxed(val | bit, reg); 325 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 326 327 return IRQ_SET_MASK_OK_DONE; 328 } 329 #endif 330 331 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 332 { 333 u32 irqstat, irqnr; 334 struct gic_chip_data *gic = &gic_data[0]; 335 void __iomem *cpu_base = gic_data_cpu_base(gic); 336 337 do { 338 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 339 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 340 341 if (likely(irqnr > 15 && irqnr < 1020)) { 342 if (static_key_true(&supports_deactivate)) 343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 344 handle_domain_irq(gic->domain, irqnr, regs); 345 continue; 346 } 347 if (irqnr < 16) { 348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 349 if (static_key_true(&supports_deactivate)) 350 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 351 #ifdef CONFIG_SMP 352 /* 353 * Ensure any shared data written by the CPU sending 354 * the IPI is read after we've read the ACK register 355 * on the GIC. 356 * 357 * Pairs with the write barrier in gic_raise_softirq 358 */ 359 smp_rmb(); 360 handle_IPI(irqnr, regs); 361 #endif 362 continue; 363 } 364 break; 365 } while (1); 366 } 367 368 static void gic_handle_cascade_irq(struct irq_desc *desc) 369 { 370 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 371 struct irq_chip *chip = irq_desc_get_chip(desc); 372 unsigned int cascade_irq, gic_irq; 373 unsigned long status; 374 375 chained_irq_enter(chip, desc); 376 377 raw_spin_lock(&irq_controller_lock); 378 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 379 raw_spin_unlock(&irq_controller_lock); 380 381 gic_irq = (status & GICC_IAR_INT_ID_MASK); 382 if (gic_irq == GICC_INT_SPURIOUS) 383 goto out; 384 385 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 386 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 387 handle_bad_irq(desc); 388 else 389 generic_handle_irq(cascade_irq); 390 391 out: 392 chained_irq_exit(chip, desc); 393 } 394 395 static struct irq_chip gic_chip = { 396 .irq_mask = gic_mask_irq, 397 .irq_unmask = gic_unmask_irq, 398 .irq_eoi = gic_eoi_irq, 399 .irq_set_type = gic_set_type, 400 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 401 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 402 .flags = IRQCHIP_SET_TYPE_MASKED | 403 IRQCHIP_SKIP_SET_WAKE | 404 IRQCHIP_MASK_ON_SUSPEND, 405 }; 406 407 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 408 { 409 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 410 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 411 &gic_data[gic_nr]); 412 } 413 414 static u8 gic_get_cpumask(struct gic_chip_data *gic) 415 { 416 void __iomem *base = gic_data_dist_base(gic); 417 u32 mask, i; 418 419 for (i = mask = 0; i < 32; i += 4) { 420 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 421 mask |= mask >> 16; 422 mask |= mask >> 8; 423 if (mask) 424 break; 425 } 426 427 if (!mask && num_possible_cpus() > 1) 428 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 429 430 return mask; 431 } 432 433 static void gic_cpu_if_up(struct gic_chip_data *gic) 434 { 435 void __iomem *cpu_base = gic_data_cpu_base(gic); 436 u32 bypass = 0; 437 u32 mode = 0; 438 439 if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) 440 mode = GIC_CPU_CTRL_EOImodeNS; 441 442 /* 443 * Preserve bypass disable bits to be written back later 444 */ 445 bypass = readl(cpu_base + GIC_CPU_CTRL); 446 bypass &= GICC_DIS_BYPASS_MASK; 447 448 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 449 } 450 451 452 static void __init gic_dist_init(struct gic_chip_data *gic) 453 { 454 unsigned int i; 455 u32 cpumask; 456 unsigned int gic_irqs = gic->gic_irqs; 457 void __iomem *base = gic_data_dist_base(gic); 458 459 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 460 461 /* 462 * Set all global interrupts to this CPU only. 463 */ 464 cpumask = gic_get_cpumask(gic); 465 cpumask |= cpumask << 8; 466 cpumask |= cpumask << 16; 467 for (i = 32; i < gic_irqs; i += 4) 468 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 469 470 gic_dist_config(base, gic_irqs, NULL); 471 472 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 473 } 474 475 static int gic_cpu_init(struct gic_chip_data *gic) 476 { 477 void __iomem *dist_base = gic_data_dist_base(gic); 478 void __iomem *base = gic_data_cpu_base(gic); 479 unsigned int cpu_mask, cpu = smp_processor_id(); 480 int i; 481 482 /* 483 * Setting up the CPU map is only relevant for the primary GIC 484 * because any nested/secondary GICs do not directly interface 485 * with the CPU(s). 486 */ 487 if (gic == &gic_data[0]) { 488 /* 489 * Get what the GIC says our CPU mask is. 490 */ 491 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 492 return -EINVAL; 493 494 gic_check_cpu_features(); 495 cpu_mask = gic_get_cpumask(gic); 496 gic_cpu_map[cpu] = cpu_mask; 497 498 /* 499 * Clear our mask from the other map entries in case they're 500 * still undefined. 501 */ 502 for (i = 0; i < NR_GIC_CPU_IF; i++) 503 if (i != cpu) 504 gic_cpu_map[i] &= ~cpu_mask; 505 } 506 507 gic_cpu_config(dist_base, NULL); 508 509 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 510 gic_cpu_if_up(gic); 511 512 return 0; 513 } 514 515 int gic_cpu_if_down(unsigned int gic_nr) 516 { 517 void __iomem *cpu_base; 518 u32 val = 0; 519 520 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 521 return -EINVAL; 522 523 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 524 val = readl(cpu_base + GIC_CPU_CTRL); 525 val &= ~GICC_ENABLE; 526 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 527 528 return 0; 529 } 530 531 #ifdef CONFIG_CPU_PM 532 /* 533 * Saves the GIC distributor registers during suspend or idle. Must be called 534 * with interrupts disabled but before powering down the GIC. After calling 535 * this function, no interrupts will be delivered by the GIC, and another 536 * platform-specific wakeup source must be enabled. 537 */ 538 static void gic_dist_save(struct gic_chip_data *gic) 539 { 540 unsigned int gic_irqs; 541 void __iomem *dist_base; 542 int i; 543 544 if (WARN_ON(!gic)) 545 return; 546 547 gic_irqs = gic->gic_irqs; 548 dist_base = gic_data_dist_base(gic); 549 550 if (!dist_base) 551 return; 552 553 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 554 gic->saved_spi_conf[i] = 555 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 556 557 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 558 gic->saved_spi_target[i] = 559 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 560 561 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 562 gic->saved_spi_enable[i] = 563 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 564 565 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 566 gic->saved_spi_active[i] = 567 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 568 } 569 570 /* 571 * Restores the GIC distributor registers during resume or when coming out of 572 * idle. Must be called before enabling interrupts. If a level interrupt 573 * that occured while the GIC was suspended is still present, it will be 574 * handled normally, but any edge interrupts that occured will not be seen by 575 * the GIC and need to be handled by the platform-specific wakeup source. 576 */ 577 static void gic_dist_restore(struct gic_chip_data *gic) 578 { 579 unsigned int gic_irqs; 580 unsigned int i; 581 void __iomem *dist_base; 582 583 if (WARN_ON(!gic)) 584 return; 585 586 gic_irqs = gic->gic_irqs; 587 dist_base = gic_data_dist_base(gic); 588 589 if (!dist_base) 590 return; 591 592 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 593 594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 595 writel_relaxed(gic->saved_spi_conf[i], 596 dist_base + GIC_DIST_CONFIG + i * 4); 597 598 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 599 writel_relaxed(GICD_INT_DEF_PRI_X4, 600 dist_base + GIC_DIST_PRI + i * 4); 601 602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 603 writel_relaxed(gic->saved_spi_target[i], 604 dist_base + GIC_DIST_TARGET + i * 4); 605 606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 607 writel_relaxed(GICD_INT_EN_CLR_X32, 608 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 609 writel_relaxed(gic->saved_spi_enable[i], 610 dist_base + GIC_DIST_ENABLE_SET + i * 4); 611 } 612 613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 614 writel_relaxed(GICD_INT_EN_CLR_X32, 615 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 616 writel_relaxed(gic->saved_spi_active[i], 617 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 618 } 619 620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 621 } 622 623 static void gic_cpu_save(struct gic_chip_data *gic) 624 { 625 int i; 626 u32 *ptr; 627 void __iomem *dist_base; 628 void __iomem *cpu_base; 629 630 if (WARN_ON(!gic)) 631 return; 632 633 dist_base = gic_data_dist_base(gic); 634 cpu_base = gic_data_cpu_base(gic); 635 636 if (!dist_base || !cpu_base) 637 return; 638 639 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 640 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 641 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 642 643 ptr = raw_cpu_ptr(gic->saved_ppi_active); 644 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 645 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 646 647 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 648 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 649 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 650 651 } 652 653 static void gic_cpu_restore(struct gic_chip_data *gic) 654 { 655 int i; 656 u32 *ptr; 657 void __iomem *dist_base; 658 void __iomem *cpu_base; 659 660 if (WARN_ON(!gic)) 661 return; 662 663 dist_base = gic_data_dist_base(gic); 664 cpu_base = gic_data_cpu_base(gic); 665 666 if (!dist_base || !cpu_base) 667 return; 668 669 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 670 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 671 writel_relaxed(GICD_INT_EN_CLR_X32, 672 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 673 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 674 } 675 676 ptr = raw_cpu_ptr(gic->saved_ppi_active); 677 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 678 writel_relaxed(GICD_INT_EN_CLR_X32, 679 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 680 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 681 } 682 683 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 684 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 685 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 686 687 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 688 writel_relaxed(GICD_INT_DEF_PRI_X4, 689 dist_base + GIC_DIST_PRI + i * 4); 690 691 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 692 gic_cpu_if_up(gic); 693 } 694 695 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 696 { 697 int i; 698 699 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 700 #ifdef CONFIG_GIC_NON_BANKED 701 /* Skip over unused GICs */ 702 if (!gic_data[i].get_base) 703 continue; 704 #endif 705 switch (cmd) { 706 case CPU_PM_ENTER: 707 gic_cpu_save(&gic_data[i]); 708 break; 709 case CPU_PM_ENTER_FAILED: 710 case CPU_PM_EXIT: 711 gic_cpu_restore(&gic_data[i]); 712 break; 713 case CPU_CLUSTER_PM_ENTER: 714 gic_dist_save(&gic_data[i]); 715 break; 716 case CPU_CLUSTER_PM_ENTER_FAILED: 717 case CPU_CLUSTER_PM_EXIT: 718 gic_dist_restore(&gic_data[i]); 719 break; 720 } 721 } 722 723 return NOTIFY_OK; 724 } 725 726 static struct notifier_block gic_notifier_block = { 727 .notifier_call = gic_notifier, 728 }; 729 730 static int __init gic_pm_init(struct gic_chip_data *gic) 731 { 732 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 733 sizeof(u32)); 734 if (WARN_ON(!gic->saved_ppi_enable)) 735 return -ENOMEM; 736 737 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 738 sizeof(u32)); 739 if (WARN_ON(!gic->saved_ppi_active)) 740 goto free_ppi_enable; 741 742 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 743 sizeof(u32)); 744 if (WARN_ON(!gic->saved_ppi_conf)) 745 goto free_ppi_active; 746 747 if (gic == &gic_data[0]) 748 cpu_pm_register_notifier(&gic_notifier_block); 749 750 return 0; 751 752 free_ppi_active: 753 free_percpu(gic->saved_ppi_active); 754 free_ppi_enable: 755 free_percpu(gic->saved_ppi_enable); 756 757 return -ENOMEM; 758 } 759 #else 760 static int __init gic_pm_init(struct gic_chip_data *gic) 761 { 762 return 0; 763 } 764 #endif 765 766 #ifdef CONFIG_SMP 767 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 768 { 769 int cpu; 770 unsigned long flags, map = 0; 771 772 raw_spin_lock_irqsave(&irq_controller_lock, flags); 773 774 /* Convert our logical CPU mask into a physical one. */ 775 for_each_cpu(cpu, mask) 776 map |= gic_cpu_map[cpu]; 777 778 /* 779 * Ensure that stores to Normal memory are visible to the 780 * other CPUs before they observe us issuing the IPI. 781 */ 782 dmb(ishst); 783 784 /* this always happens on GIC0 */ 785 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 786 787 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 788 } 789 #endif 790 791 #ifdef CONFIG_BL_SWITCHER 792 /* 793 * gic_send_sgi - send a SGI directly to given CPU interface number 794 * 795 * cpu_id: the ID for the destination CPU interface 796 * irq: the IPI number to send a SGI for 797 */ 798 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 799 { 800 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 801 cpu_id = 1 << cpu_id; 802 /* this always happens on GIC0 */ 803 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 804 } 805 806 /* 807 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 808 * 809 * @cpu: the logical CPU number to get the GIC ID for. 810 * 811 * Return the CPU interface ID for the given logical CPU number, 812 * or -1 if the CPU number is too large or the interface ID is 813 * unknown (more than one bit set). 814 */ 815 int gic_get_cpu_id(unsigned int cpu) 816 { 817 unsigned int cpu_bit; 818 819 if (cpu >= NR_GIC_CPU_IF) 820 return -1; 821 cpu_bit = gic_cpu_map[cpu]; 822 if (cpu_bit & (cpu_bit - 1)) 823 return -1; 824 return __ffs(cpu_bit); 825 } 826 827 /* 828 * gic_migrate_target - migrate IRQs to another CPU interface 829 * 830 * @new_cpu_id: the CPU target ID to migrate IRQs to 831 * 832 * Migrate all peripheral interrupts with a target matching the current CPU 833 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 834 * is also updated. Targets to other CPU interfaces are unchanged. 835 * This must be called with IRQs locally disabled. 836 */ 837 void gic_migrate_target(unsigned int new_cpu_id) 838 { 839 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 840 void __iomem *dist_base; 841 int i, ror_val, cpu = smp_processor_id(); 842 u32 val, cur_target_mask, active_mask; 843 844 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 845 846 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 847 if (!dist_base) 848 return; 849 gic_irqs = gic_data[gic_nr].gic_irqs; 850 851 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 852 cur_target_mask = 0x01010101 << cur_cpu_id; 853 ror_val = (cur_cpu_id - new_cpu_id) & 31; 854 855 raw_spin_lock(&irq_controller_lock); 856 857 /* Update the target interface for this logical CPU */ 858 gic_cpu_map[cpu] = 1 << new_cpu_id; 859 860 /* 861 * Find all the peripheral interrupts targetting the current 862 * CPU interface and migrate them to the new CPU interface. 863 * We skip DIST_TARGET 0 to 7 as they are read-only. 864 */ 865 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 866 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 867 active_mask = val & cur_target_mask; 868 if (active_mask) { 869 val &= ~active_mask; 870 val |= ror32(active_mask, ror_val); 871 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 872 } 873 } 874 875 raw_spin_unlock(&irq_controller_lock); 876 877 /* 878 * Now let's migrate and clear any potential SGIs that might be 879 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 880 * is a banked register, we can only forward the SGI using 881 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 882 * doesn't use that information anyway. 883 * 884 * For the same reason we do not adjust SGI source information 885 * for previously sent SGIs by us to other CPUs either. 886 */ 887 for (i = 0; i < 16; i += 4) { 888 int j; 889 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 890 if (!val) 891 continue; 892 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 893 for (j = i; j < i + 4; j++) { 894 if (val & 0xff) 895 writel_relaxed((1 << (new_cpu_id + 16)) | j, 896 dist_base + GIC_DIST_SOFTINT); 897 val >>= 8; 898 } 899 } 900 } 901 902 /* 903 * gic_get_sgir_physaddr - get the physical address for the SGI register 904 * 905 * REturn the physical address of the SGI register to be used 906 * by some early assembly code when the kernel is not yet available. 907 */ 908 static unsigned long gic_dist_physaddr; 909 910 unsigned long gic_get_sgir_physaddr(void) 911 { 912 if (!gic_dist_physaddr) 913 return 0; 914 return gic_dist_physaddr + GIC_DIST_SOFTINT; 915 } 916 917 void __init gic_init_physaddr(struct device_node *node) 918 { 919 struct resource res; 920 if (of_address_to_resource(node, 0, &res) == 0) { 921 gic_dist_physaddr = res.start; 922 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 923 } 924 } 925 926 #else 927 #define gic_init_physaddr(node) do { } while (0) 928 #endif 929 930 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 931 irq_hw_number_t hw) 932 { 933 struct gic_chip_data *gic = d->host_data; 934 935 if (hw < 32) { 936 irq_set_percpu_devid(irq); 937 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 938 handle_percpu_devid_irq, NULL, NULL); 939 irq_set_status_flags(irq, IRQ_NOAUTOEN); 940 } else { 941 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 942 handle_fasteoi_irq, NULL, NULL); 943 irq_set_probe(irq); 944 } 945 return 0; 946 } 947 948 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 949 { 950 } 951 952 static int gic_irq_domain_translate(struct irq_domain *d, 953 struct irq_fwspec *fwspec, 954 unsigned long *hwirq, 955 unsigned int *type) 956 { 957 if (is_of_node(fwspec->fwnode)) { 958 if (fwspec->param_count < 3) 959 return -EINVAL; 960 961 /* Get the interrupt number and add 16 to skip over SGIs */ 962 *hwirq = fwspec->param[1] + 16; 963 964 /* 965 * For SPIs, we need to add 16 more to get the GIC irq 966 * ID number 967 */ 968 if (!fwspec->param[0]) 969 *hwirq += 16; 970 971 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 972 return 0; 973 } 974 975 if (is_fwnode_irqchip(fwspec->fwnode)) { 976 if(fwspec->param_count != 2) 977 return -EINVAL; 978 979 *hwirq = fwspec->param[0]; 980 *type = fwspec->param[1]; 981 return 0; 982 } 983 984 return -EINVAL; 985 } 986 987 #ifdef CONFIG_SMP 988 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 989 void *hcpu) 990 { 991 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 992 gic_cpu_init(&gic_data[0]); 993 return NOTIFY_OK; 994 } 995 996 /* 997 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 998 * priority because the GIC needs to be up before the ARM generic timers. 999 */ 1000 static struct notifier_block gic_cpu_notifier = { 1001 .notifier_call = gic_secondary_init, 1002 .priority = 100, 1003 }; 1004 #endif 1005 1006 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1007 unsigned int nr_irqs, void *arg) 1008 { 1009 int i, ret; 1010 irq_hw_number_t hwirq; 1011 unsigned int type = IRQ_TYPE_NONE; 1012 struct irq_fwspec *fwspec = arg; 1013 1014 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1015 if (ret) 1016 return ret; 1017 1018 for (i = 0; i < nr_irqs; i++) 1019 gic_irq_domain_map(domain, virq + i, hwirq + i); 1020 1021 return 0; 1022 } 1023 1024 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1025 .translate = gic_irq_domain_translate, 1026 .alloc = gic_irq_domain_alloc, 1027 .free = irq_domain_free_irqs_top, 1028 }; 1029 1030 static const struct irq_domain_ops gic_irq_domain_ops = { 1031 .map = gic_irq_domain_map, 1032 .unmap = gic_irq_domain_unmap, 1033 }; 1034 1035 static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start, 1036 struct fwnode_handle *handle) 1037 { 1038 irq_hw_number_t hwirq_base; 1039 int gic_irqs, irq_base, i, ret; 1040 1041 if (WARN_ON(!gic || gic->domain)) 1042 return -EINVAL; 1043 1044 /* Initialize irq_chip */ 1045 gic->chip = gic_chip; 1046 1047 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { 1048 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1049 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1050 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1051 gic->chip.name = kasprintf(GFP_KERNEL, "GICv2"); 1052 } else { 1053 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", 1054 (int)(gic - &gic_data[0])); 1055 } 1056 1057 #ifdef CONFIG_SMP 1058 if (gic == &gic_data[0]) 1059 gic->chip.irq_set_affinity = gic_set_affinity; 1060 #endif 1061 1062 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1063 /* Frankein-GIC without banked registers... */ 1064 unsigned int cpu; 1065 1066 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1067 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1068 if (WARN_ON(!gic->dist_base.percpu_base || 1069 !gic->cpu_base.percpu_base)) { 1070 ret = -ENOMEM; 1071 goto error; 1072 } 1073 1074 for_each_possible_cpu(cpu) { 1075 u32 mpidr = cpu_logical_map(cpu); 1076 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1077 unsigned long offset = gic->percpu_offset * core_id; 1078 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1079 gic->raw_dist_base + offset; 1080 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1081 gic->raw_cpu_base + offset; 1082 } 1083 1084 gic_set_base_accessor(gic, gic_get_percpu_base); 1085 } else { 1086 /* Normal, sane GIC... */ 1087 WARN(gic->percpu_offset, 1088 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1089 gic->percpu_offset); 1090 gic->dist_base.common_base = gic->raw_dist_base; 1091 gic->cpu_base.common_base = gic->raw_cpu_base; 1092 gic_set_base_accessor(gic, gic_get_common_base); 1093 } 1094 1095 /* 1096 * Find out how many interrupts are supported. 1097 * The GIC only supports up to 1020 interrupt sources. 1098 */ 1099 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1100 gic_irqs = (gic_irqs + 1) * 32; 1101 if (gic_irqs > 1020) 1102 gic_irqs = 1020; 1103 gic->gic_irqs = gic_irqs; 1104 1105 if (handle) { /* DT/ACPI */ 1106 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1107 &gic_irq_domain_hierarchy_ops, 1108 gic); 1109 } else { /* Legacy support */ 1110 /* 1111 * For primary GICs, skip over SGIs. 1112 * For secondary GICs, skip over PPIs, too. 1113 */ 1114 if (gic == &gic_data[0] && (irq_start & 31) > 0) { 1115 hwirq_base = 16; 1116 if (irq_start != -1) 1117 irq_start = (irq_start & ~31) + 16; 1118 } else { 1119 hwirq_base = 32; 1120 } 1121 1122 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1123 1124 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1125 numa_node_id()); 1126 if (irq_base < 0) { 1127 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1128 irq_start); 1129 irq_base = irq_start; 1130 } 1131 1132 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1133 hwirq_base, &gic_irq_domain_ops, gic); 1134 } 1135 1136 if (WARN_ON(!gic->domain)) { 1137 ret = -ENODEV; 1138 goto error; 1139 } 1140 1141 if (gic == &gic_data[0]) { 1142 /* 1143 * Initialize the CPU interface map to all CPUs. 1144 * It will be refined as each CPU probes its ID. 1145 * This is only necessary for the primary GIC. 1146 */ 1147 for (i = 0; i < NR_GIC_CPU_IF; i++) 1148 gic_cpu_map[i] = 0xff; 1149 #ifdef CONFIG_SMP 1150 set_smp_cross_call(gic_raise_softirq); 1151 register_cpu_notifier(&gic_cpu_notifier); 1152 #endif 1153 set_handle_irq(gic_handle_irq); 1154 if (static_key_true(&supports_deactivate)) 1155 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1156 } 1157 1158 gic_dist_init(gic); 1159 ret = gic_cpu_init(gic); 1160 if (ret) 1161 goto error; 1162 1163 ret = gic_pm_init(gic); 1164 if (ret) 1165 goto error; 1166 1167 return 0; 1168 1169 error: 1170 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1171 free_percpu(gic->dist_base.percpu_base); 1172 free_percpu(gic->cpu_base.percpu_base); 1173 } 1174 1175 kfree(gic->chip.name); 1176 1177 return ret; 1178 } 1179 1180 void __init gic_init(unsigned int gic_nr, int irq_start, 1181 void __iomem *dist_base, void __iomem *cpu_base) 1182 { 1183 struct gic_chip_data *gic; 1184 1185 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) 1186 return; 1187 1188 /* 1189 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1190 * bother with these... 1191 */ 1192 static_key_slow_dec(&supports_deactivate); 1193 1194 gic = &gic_data[gic_nr]; 1195 gic->raw_dist_base = dist_base; 1196 gic->raw_cpu_base = cpu_base; 1197 1198 __gic_init_bases(gic, irq_start, NULL); 1199 } 1200 1201 static void gic_teardown(struct gic_chip_data *gic) 1202 { 1203 if (WARN_ON(!gic)) 1204 return; 1205 1206 if (gic->raw_dist_base) 1207 iounmap(gic->raw_dist_base); 1208 if (gic->raw_cpu_base) 1209 iounmap(gic->raw_cpu_base); 1210 } 1211 1212 #ifdef CONFIG_OF 1213 static int gic_cnt __initdata; 1214 1215 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1216 { 1217 struct resource cpuif_res; 1218 1219 of_address_to_resource(node, 1, &cpuif_res); 1220 1221 if (!is_hyp_mode_available()) 1222 return false; 1223 if (resource_size(&cpuif_res) < SZ_8K) 1224 return false; 1225 if (resource_size(&cpuif_res) == SZ_128K) { 1226 u32 val_low, val_high; 1227 1228 /* 1229 * Verify that we have the first 4kB of a GIC400 1230 * aliased over the first 64kB by checking the 1231 * GICC_IIDR register on both ends. 1232 */ 1233 val_low = readl_relaxed(*base + GIC_CPU_IDENT); 1234 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); 1235 if ((val_low & 0xffff0fff) != 0x0202043B || 1236 val_low != val_high) 1237 return false; 1238 1239 /* 1240 * Move the base up by 60kB, so that we have a 8kB 1241 * contiguous region, which allows us to use GICC_DIR 1242 * at its normal offset. Please pass me that bucket. 1243 */ 1244 *base += 0xf000; 1245 cpuif_res.start += 0xf000; 1246 pr_warn("GIC: Adjusting CPU interface base to %pa", 1247 &cpuif_res.start); 1248 } 1249 1250 return true; 1251 } 1252 1253 static int __init gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1254 { 1255 if (!gic || !node) 1256 return -EINVAL; 1257 1258 gic->raw_dist_base = of_iomap(node, 0); 1259 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1260 goto error; 1261 1262 gic->raw_cpu_base = of_iomap(node, 1); 1263 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1264 goto error; 1265 1266 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1267 gic->percpu_offset = 0; 1268 1269 return 0; 1270 1271 error: 1272 gic_teardown(gic); 1273 1274 return -ENOMEM; 1275 } 1276 1277 static void __init gic_of_setup_kvm_info(struct device_node *node) 1278 { 1279 int ret; 1280 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1281 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1282 1283 gic_v2_kvm_info.type = GIC_V2; 1284 1285 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1286 if (!gic_v2_kvm_info.maint_irq) 1287 return; 1288 1289 ret = of_address_to_resource(node, 2, vctrl_res); 1290 if (ret) 1291 return; 1292 1293 ret = of_address_to_resource(node, 3, vcpu_res); 1294 if (ret) 1295 return; 1296 1297 gic_set_kvm_info(&gic_v2_kvm_info); 1298 } 1299 1300 int __init 1301 gic_of_init(struct device_node *node, struct device_node *parent) 1302 { 1303 struct gic_chip_data *gic; 1304 int irq, ret; 1305 1306 if (WARN_ON(!node)) 1307 return -ENODEV; 1308 1309 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1310 return -EINVAL; 1311 1312 gic = &gic_data[gic_cnt]; 1313 1314 ret = gic_of_setup(gic, node); 1315 if (ret) 1316 return ret; 1317 1318 /* 1319 * Disable split EOI/Deactivate if either HYP is not available 1320 * or the CPU interface is too small. 1321 */ 1322 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1323 static_key_slow_dec(&supports_deactivate); 1324 1325 ret = __gic_init_bases(gic, -1, &node->fwnode); 1326 if (ret) { 1327 gic_teardown(gic); 1328 return ret; 1329 } 1330 1331 if (!gic_cnt) { 1332 gic_init_physaddr(node); 1333 gic_of_setup_kvm_info(node); 1334 } 1335 1336 if (parent) { 1337 irq = irq_of_parse_and_map(node, 0); 1338 gic_cascade_irq(gic_cnt, irq); 1339 } 1340 1341 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1342 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1343 1344 gic_cnt++; 1345 return 0; 1346 } 1347 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1348 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1349 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1350 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1351 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1352 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1353 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1354 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1355 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1356 1357 #endif 1358 1359 #ifdef CONFIG_ACPI 1360 static struct 1361 { 1362 phys_addr_t cpu_phys_base; 1363 u32 maint_irq; 1364 int maint_irq_mode; 1365 phys_addr_t vctrl_base; 1366 phys_addr_t vcpu_base; 1367 } acpi_data __initdata; 1368 1369 static int __init 1370 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1371 const unsigned long end) 1372 { 1373 struct acpi_madt_generic_interrupt *processor; 1374 phys_addr_t gic_cpu_base; 1375 static int cpu_base_assigned; 1376 1377 processor = (struct acpi_madt_generic_interrupt *)header; 1378 1379 if (BAD_MADT_GICC_ENTRY(processor, end)) 1380 return -EINVAL; 1381 1382 /* 1383 * There is no support for non-banked GICv1/2 register in ACPI spec. 1384 * All CPU interface addresses have to be the same. 1385 */ 1386 gic_cpu_base = processor->base_address; 1387 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1388 return -EINVAL; 1389 1390 acpi_data.cpu_phys_base = gic_cpu_base; 1391 acpi_data.maint_irq = processor->vgic_interrupt; 1392 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1393 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1394 acpi_data.vctrl_base = processor->gich_base_address; 1395 acpi_data.vcpu_base = processor->gicv_base_address; 1396 1397 cpu_base_assigned = 1; 1398 return 0; 1399 } 1400 1401 /* The things you have to do to just *count* something... */ 1402 static int __init acpi_dummy_func(struct acpi_subtable_header *header, 1403 const unsigned long end) 1404 { 1405 return 0; 1406 } 1407 1408 static bool __init acpi_gic_redist_is_present(void) 1409 { 1410 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1411 acpi_dummy_func, 0) > 0; 1412 } 1413 1414 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1415 struct acpi_probe_entry *ape) 1416 { 1417 struct acpi_madt_generic_distributor *dist; 1418 dist = (struct acpi_madt_generic_distributor *)header; 1419 1420 return (dist->version == ape->driver_data && 1421 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1422 !acpi_gic_redist_is_present())); 1423 } 1424 1425 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1426 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1427 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1428 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1429 1430 static void __init gic_acpi_setup_kvm_info(void) 1431 { 1432 int irq; 1433 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1434 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1435 1436 gic_v2_kvm_info.type = GIC_V2; 1437 1438 if (!acpi_data.vctrl_base) 1439 return; 1440 1441 vctrl_res->flags = IORESOURCE_MEM; 1442 vctrl_res->start = acpi_data.vctrl_base; 1443 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1444 1445 if (!acpi_data.vcpu_base) 1446 return; 1447 1448 vcpu_res->flags = IORESOURCE_MEM; 1449 vcpu_res->start = acpi_data.vcpu_base; 1450 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1451 1452 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1453 acpi_data.maint_irq_mode, 1454 ACPI_ACTIVE_HIGH); 1455 if (irq <= 0) 1456 return; 1457 1458 gic_v2_kvm_info.maint_irq = irq; 1459 1460 gic_set_kvm_info(&gic_v2_kvm_info); 1461 } 1462 1463 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, 1464 const unsigned long end) 1465 { 1466 struct acpi_madt_generic_distributor *dist; 1467 struct fwnode_handle *domain_handle; 1468 struct gic_chip_data *gic = &gic_data[0]; 1469 int count, ret; 1470 1471 /* Collect CPU base addresses */ 1472 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1473 gic_acpi_parse_madt_cpu, 0); 1474 if (count <= 0) { 1475 pr_err("No valid GICC entries exist\n"); 1476 return -EINVAL; 1477 } 1478 1479 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1480 if (!gic->raw_cpu_base) { 1481 pr_err("Unable to map GICC registers\n"); 1482 return -ENOMEM; 1483 } 1484 1485 dist = (struct acpi_madt_generic_distributor *)header; 1486 gic->raw_dist_base = ioremap(dist->base_address, 1487 ACPI_GICV2_DIST_MEM_SIZE); 1488 if (!gic->raw_dist_base) { 1489 pr_err("Unable to map GICD registers\n"); 1490 gic_teardown(gic); 1491 return -ENOMEM; 1492 } 1493 1494 /* 1495 * Disable split EOI/Deactivate if HYP is not available. ACPI 1496 * guarantees that we'll always have a GICv2, so the CPU 1497 * interface will always be the right size. 1498 */ 1499 if (!is_hyp_mode_available()) 1500 static_key_slow_dec(&supports_deactivate); 1501 1502 /* 1503 * Initialize GIC instance zero (no multi-GIC support). 1504 */ 1505 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); 1506 if (!domain_handle) { 1507 pr_err("Unable to allocate domain handle\n"); 1508 gic_teardown(gic); 1509 return -ENOMEM; 1510 } 1511 1512 ret = __gic_init_bases(gic, -1, domain_handle); 1513 if (ret) { 1514 pr_err("Failed to initialise GIC\n"); 1515 irq_domain_free_fwnode(domain_handle); 1516 gic_teardown(gic); 1517 return ret; 1518 } 1519 1520 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1521 1522 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1523 gicv2m_init(NULL, gic_data[0].domain); 1524 1525 gic_acpi_setup_kvm_info(); 1526 1527 return 0; 1528 } 1529 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1530 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1531 gic_v2_acpi_init); 1532 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1533 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1534 gic_v2_acpi_init); 1535 #endif 1536