1 /* 2 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 3 * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef RXE_PARAM_H 35 #define RXE_PARAM_H 36 37 #include <uapi/rdma/rdma_user_rxe.h> 38 39 static inline enum ib_mtu rxe_mtu_int_to_enum(int mtu) 40 { 41 if (mtu < 256) 42 return 0; 43 else if (mtu < 512) 44 return IB_MTU_256; 45 else if (mtu < 1024) 46 return IB_MTU_512; 47 else if (mtu < 2048) 48 return IB_MTU_1024; 49 else if (mtu < 4096) 50 return IB_MTU_2048; 51 else 52 return IB_MTU_4096; 53 } 54 55 /* Find the IB mtu for a given network MTU. */ 56 static inline enum ib_mtu eth_mtu_int_to_enum(int mtu) 57 { 58 mtu -= RXE_MAX_HDR_LENGTH; 59 60 return rxe_mtu_int_to_enum(mtu); 61 } 62 63 /* default/initial rxe device parameter settings */ 64 enum rxe_device_param { 65 RXE_MAX_MR_SIZE = -1ull, 66 RXE_PAGE_SIZE_CAP = 0xfffff000, 67 RXE_MAX_QP = 0x10000, 68 RXE_MAX_QP_WR = 0x4000, 69 RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR 70 | IB_DEVICE_BAD_QKEY_CNTR 71 | IB_DEVICE_AUTO_PATH_MIG 72 | IB_DEVICE_CHANGE_PHY_PORT 73 | IB_DEVICE_UD_AV_PORT_ENFORCE 74 | IB_DEVICE_PORT_ACTIVE_EVENT 75 | IB_DEVICE_SYS_IMAGE_GUID 76 | IB_DEVICE_RC_RNR_NAK_GEN 77 | IB_DEVICE_SRQ_RESIZE 78 | IB_DEVICE_MEM_MGT_EXTENSIONS 79 | IB_DEVICE_ALLOW_USER_UNREG, 80 RXE_MAX_SGE = 32, 81 RXE_MAX_WQE_SIZE = sizeof(struct rxe_send_wqe) + 82 sizeof(struct ib_sge) * RXE_MAX_SGE, 83 RXE_MAX_INLINE_DATA = RXE_MAX_WQE_SIZE - 84 sizeof(struct rxe_send_wqe), 85 RXE_MAX_SGE_RD = 32, 86 RXE_MAX_CQ = 16384, 87 RXE_MAX_LOG_CQE = 15, 88 RXE_MAX_MR = 256 * 1024, 89 RXE_MAX_PD = 0x7ffc, 90 RXE_MAX_QP_RD_ATOM = 128, 91 RXE_MAX_RES_RD_ATOM = 0x3f000, 92 RXE_MAX_QP_INIT_RD_ATOM = 128, 93 RXE_MAX_MCAST_GRP = 8192, 94 RXE_MAX_MCAST_QP_ATTACH = 56, 95 RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000, 96 RXE_MAX_AH = 100, 97 RXE_MAX_SRQ = 960, 98 RXE_MAX_SRQ_WR = 0x4000, 99 RXE_MIN_SRQ_WR = 1, 100 RXE_MAX_SRQ_SGE = 27, 101 RXE_MIN_SRQ_SGE = 1, 102 RXE_MAX_FMR_PAGE_LIST_LEN = 512, 103 RXE_MAX_PKEYS = 64, 104 RXE_LOCAL_CA_ACK_DELAY = 15, 105 106 RXE_MAX_UCONTEXT = 512, 107 108 RXE_NUM_PORT = 1, 109 110 RXE_MIN_QP_INDEX = 16, 111 RXE_MAX_QP_INDEX = 0x00020000, 112 113 RXE_MIN_SRQ_INDEX = 0x00020001, 114 RXE_MAX_SRQ_INDEX = 0x00040000, 115 116 RXE_MIN_MR_INDEX = 0x00000001, 117 RXE_MAX_MR_INDEX = 0x00040000, 118 RXE_MIN_MW_INDEX = 0x00040001, 119 RXE_MAX_MW_INDEX = 0x00060000, 120 RXE_MAX_PKT_PER_ACK = 64, 121 122 RXE_MAX_UNACKED_PSNS = 128, 123 124 /* Max inflight SKBs per queue pair */ 125 RXE_INFLIGHT_SKBS_PER_QP_HIGH = 64, 126 RXE_INFLIGHT_SKBS_PER_QP_LOW = 16, 127 128 /* Delay before calling arbiter timer */ 129 RXE_NSEC_ARB_TIMER_DELAY = 200, 130 }; 131 132 /* default/initial rxe port parameters */ 133 enum rxe_port_param { 134 RXE_PORT_GID_TBL_LEN = 1024, 135 RXE_PORT_PORT_CAP_FLAGS = RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP, 136 RXE_PORT_MAX_MSG_SZ = 0x800000, 137 RXE_PORT_BAD_PKEY_CNTR = 0, 138 RXE_PORT_QKEY_VIOL_CNTR = 0, 139 RXE_PORT_LID = 0, 140 RXE_PORT_SM_LID = 0, 141 RXE_PORT_SM_SL = 0, 142 RXE_PORT_LMC = 0, 143 RXE_PORT_MAX_VL_NUM = 1, 144 RXE_PORT_SUBNET_TIMEOUT = 0, 145 RXE_PORT_INIT_TYPE_REPLY = 0, 146 RXE_PORT_ACTIVE_WIDTH = IB_WIDTH_1X, 147 RXE_PORT_ACTIVE_SPEED = 1, 148 RXE_PORT_PKEY_TBL_LEN = 64, 149 RXE_PORT_PHYS_STATE = IB_PORT_PHYS_STATE_POLLING, 150 RXE_PORT_SUBNET_PREFIX = 0xfe80000000000000ULL, 151 }; 152 153 /* default/initial port info parameters */ 154 enum rxe_port_info_param { 155 RXE_PORT_INFO_VL_CAP = 4, /* 1-8 */ 156 RXE_PORT_INFO_MTU_CAP = 5, /* 4096 */ 157 RXE_PORT_INFO_OPER_VL = 1, /* 1 */ 158 }; 159 160 #endif /* RXE_PARAM_H */ 161