1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_smi.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 53 #include "srq.h" 54 55 #define mlx5_ib_dbg(_dev, format, arg...) \ 56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_err(_dev, format, arg...) \ 60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define mlx5_ib_warn(_dev, format, arg...) \ 64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 65 __LINE__, current->pid, ##arg) 66 67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 68 sizeof(((type *)0)->fld) <= (sz)) 69 #define MLX5_IB_DEFAULT_UIDX 0xffffff 70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 71 72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 73 74 enum { 75 MLX5_IB_MMAP_CMD_SHIFT = 8, 76 MLX5_IB_MMAP_CMD_MASK = 0xff, 77 }; 78 79 enum { 80 MLX5_RES_SCAT_DATA32_CQE = 0x1, 81 MLX5_RES_SCAT_DATA64_CQE = 0x2, 82 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 83 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 84 }; 85 86 enum mlx5_ib_mad_ifc_flags { 87 MLX5_MAD_IFC_IGNORE_MKEY = 1, 88 MLX5_MAD_IFC_IGNORE_BKEY = 2, 89 MLX5_MAD_IFC_NET_VIEW = 4, 90 }; 91 92 enum { 93 MLX5_CROSS_CHANNEL_BFREG = 0, 94 }; 95 96 enum { 97 MLX5_CQE_VERSION_V0, 98 MLX5_CQE_VERSION_V1, 99 }; 100 101 enum { 102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 103 MLX5_TM_MAX_SGE = 1, 104 }; 105 106 enum { 107 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 108 MLX5_IB_INVALID_BFREG = BIT(31), 109 }; 110 111 enum { 112 MLX5_MAX_MEMIC_PAGES = 0x100, 113 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 114 }; 115 116 enum { 117 MLX5_MEMIC_BASE_ALIGN = 6, 118 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 119 }; 120 121 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \ 122 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 123 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 124 125 struct mlx5_ib_ucontext { 126 struct ib_ucontext ibucontext; 127 struct list_head db_page_list; 128 129 /* protect doorbell record alloc/free 130 */ 131 struct mutex db_page_mutex; 132 struct mlx5_bfreg_info bfregi; 133 u8 cqe_version; 134 /* Transport Domain number */ 135 u32 tdn; 136 137 u64 lib_caps; 138 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); 139 u16 devx_uid; 140 /* For RoCE LAG TX affinity */ 141 atomic_t tx_port_affinity; 142 }; 143 144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 145 { 146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 147 } 148 149 struct mlx5_ib_pd { 150 struct ib_pd ibpd; 151 u32 pdn; 152 u16 uid; 153 }; 154 155 enum { 156 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 157 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 158 MLX5_IB_FLOW_ACTION_DECAP, 159 }; 160 161 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 162 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 163 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 164 #error "Invalid number of bypass priorities" 165 #endif 166 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 167 168 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 169 #define MLX5_IB_NUM_SNIFFER_FTS 2 170 #define MLX5_IB_NUM_EGRESS_FTS 1 171 struct mlx5_ib_flow_prio { 172 struct mlx5_flow_table *flow_table; 173 unsigned int refcount; 174 }; 175 176 struct mlx5_ib_flow_handler { 177 struct list_head list; 178 struct ib_flow ibflow; 179 struct mlx5_ib_flow_prio *prio; 180 struct mlx5_flow_handle *rule; 181 struct ib_counters *ibcounters; 182 struct mlx5_ib_dev *dev; 183 struct mlx5_ib_flow_matcher *flow_matcher; 184 }; 185 186 struct mlx5_ib_flow_matcher { 187 struct mlx5_ib_match_params matcher_mask; 188 int mask_len; 189 enum mlx5_ib_flow_type flow_type; 190 enum mlx5_flow_namespace_type ns_type; 191 u16 priority; 192 struct mlx5_core_dev *mdev; 193 atomic_t usecnt; 194 u8 match_criteria_enable; 195 }; 196 197 struct mlx5_ib_flow_db { 198 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 199 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 200 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 201 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 202 struct mlx5_ib_flow_prio fdb; 203 struct mlx5_flow_table *lag_demux_ft; 204 /* Protect flow steering bypass flow tables 205 * when add/del flow rules. 206 * only single add/removal of flow steering rule could be done 207 * simultaneously. 208 */ 209 struct mutex lock; 210 }; 211 212 /* Use macros here so that don't have to duplicate 213 * enum ib_send_flags and enum ib_qp_type for low-level driver 214 */ 215 216 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 217 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 218 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 219 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 220 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 221 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 222 223 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 224 /* 225 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 226 * creates the actual hardware QP. 227 */ 228 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 229 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 230 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 231 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 232 233 #define MLX5_IB_UMR_OCTOWORD 16 234 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 235 236 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 237 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 238 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 239 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 240 #define MLX5_IB_UPD_XLT_PD BIT(4) 241 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 242 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 243 244 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 245 * 246 * These flags are intended for internal use by the mlx5_ib driver, and they 247 * rely on the range reserved for that use in the ib_qp_create_flags enum. 248 */ 249 250 /* Create a UD QP whose source QP number is 1 */ 251 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 252 { 253 return IB_QP_CREATE_RESERVED_START; 254 } 255 256 struct wr_list { 257 u16 opcode; 258 u16 next; 259 }; 260 261 enum mlx5_ib_rq_flags { 262 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 263 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 264 }; 265 266 struct mlx5_ib_wq { 267 struct mlx5_frag_buf_ctrl fbc; 268 u64 *wrid; 269 u32 *wr_data; 270 struct wr_list *w_list; 271 unsigned *wqe_head; 272 u16 unsig_count; 273 274 /* serialize post to the work queue 275 */ 276 spinlock_t lock; 277 int wqe_cnt; 278 int max_post; 279 int max_gs; 280 int offset; 281 int wqe_shift; 282 unsigned head; 283 unsigned tail; 284 u16 cur_post; 285 void *cur_edge; 286 }; 287 288 enum mlx5_ib_wq_flags { 289 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 290 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 291 }; 292 293 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 294 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 295 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 296 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 297 298 struct mlx5_ib_rwq { 299 struct ib_wq ibwq; 300 struct mlx5_core_qp core_qp; 301 u32 rq_num_pas; 302 u32 log_rq_stride; 303 u32 log_rq_size; 304 u32 rq_page_offset; 305 u32 log_page_size; 306 u32 log_num_strides; 307 u32 two_byte_shift_en; 308 u32 single_stride_log_num_of_bytes; 309 struct ib_umem *umem; 310 size_t buf_size; 311 unsigned int page_shift; 312 int create_type; 313 struct mlx5_db db; 314 u32 user_index; 315 u32 wqe_count; 316 u32 wqe_shift; 317 int wq_sig; 318 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 319 }; 320 321 enum { 322 MLX5_QP_USER, 323 MLX5_QP_KERNEL, 324 MLX5_QP_EMPTY 325 }; 326 327 enum { 328 MLX5_WQ_USER, 329 MLX5_WQ_KERNEL 330 }; 331 332 struct mlx5_ib_rwq_ind_table { 333 struct ib_rwq_ind_table ib_rwq_ind_tbl; 334 u32 rqtn; 335 u16 uid; 336 }; 337 338 struct mlx5_ib_ubuffer { 339 struct ib_umem *umem; 340 int buf_size; 341 u64 buf_addr; 342 }; 343 344 struct mlx5_ib_qp_base { 345 struct mlx5_ib_qp *container_mibqp; 346 struct mlx5_core_qp mqp; 347 struct mlx5_ib_ubuffer ubuffer; 348 }; 349 350 struct mlx5_ib_qp_trans { 351 struct mlx5_ib_qp_base base; 352 u16 xrcdn; 353 u8 alt_port; 354 u8 atomic_rd_en; 355 u8 resp_depth; 356 }; 357 358 struct mlx5_ib_rss_qp { 359 u32 tirn; 360 }; 361 362 struct mlx5_ib_rq { 363 struct mlx5_ib_qp_base base; 364 struct mlx5_ib_wq *rq; 365 struct mlx5_ib_ubuffer ubuffer; 366 struct mlx5_db *doorbell; 367 u32 tirn; 368 u8 state; 369 u32 flags; 370 }; 371 372 struct mlx5_ib_sq { 373 struct mlx5_ib_qp_base base; 374 struct mlx5_ib_wq *sq; 375 struct mlx5_ib_ubuffer ubuffer; 376 struct mlx5_db *doorbell; 377 struct mlx5_flow_handle *flow_rule; 378 u32 tisn; 379 u8 state; 380 }; 381 382 struct mlx5_ib_raw_packet_qp { 383 struct mlx5_ib_sq sq; 384 struct mlx5_ib_rq rq; 385 }; 386 387 struct mlx5_bf { 388 int buf_size; 389 unsigned long offset; 390 struct mlx5_sq_bfreg *bfreg; 391 }; 392 393 struct mlx5_ib_dct { 394 struct mlx5_core_dct mdct; 395 u32 *in; 396 }; 397 398 struct mlx5_ib_qp { 399 struct ib_qp ibqp; 400 union { 401 struct mlx5_ib_qp_trans trans_qp; 402 struct mlx5_ib_raw_packet_qp raw_packet_qp; 403 struct mlx5_ib_rss_qp rss_qp; 404 struct mlx5_ib_dct dct; 405 }; 406 struct mlx5_frag_buf buf; 407 408 struct mlx5_db db; 409 struct mlx5_ib_wq rq; 410 411 u8 sq_signal_bits; 412 u8 next_fence; 413 struct mlx5_ib_wq sq; 414 415 /* serialize qp state modifications 416 */ 417 struct mutex mutex; 418 u32 flags; 419 u8 port; 420 u8 state; 421 int wq_sig; 422 int scat_cqe; 423 int max_inline_data; 424 struct mlx5_bf bf; 425 int has_rq; 426 427 /* only for user space QPs. For kernel 428 * we have it from the bf object 429 */ 430 int bfregn; 431 432 int create_type; 433 434 /* Store signature errors */ 435 bool signature_en; 436 437 struct list_head qps_list; 438 struct list_head cq_recv_list; 439 struct list_head cq_send_list; 440 struct mlx5_rate_limit rl; 441 u32 underlay_qpn; 442 u32 flags_en; 443 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 444 enum ib_qp_type qp_sub_type; 445 }; 446 447 struct mlx5_ib_cq_buf { 448 struct mlx5_frag_buf_ctrl fbc; 449 struct mlx5_frag_buf frag_buf; 450 struct ib_umem *umem; 451 int cqe_size; 452 int nent; 453 }; 454 455 enum mlx5_ib_qp_flags { 456 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 457 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 458 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 459 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 460 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 461 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 462 /* QP uses 1 as its source QP number */ 463 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 464 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 465 MLX5_IB_QP_RSS = 1 << 8, 466 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 467 MLX5_IB_QP_UNDERLAY = 1 << 10, 468 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 469 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 470 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13, 471 }; 472 473 struct mlx5_umr_wr { 474 struct ib_send_wr wr; 475 u64 virt_addr; 476 u64 offset; 477 struct ib_pd *pd; 478 unsigned int page_shift; 479 unsigned int xlt_size; 480 u64 length; 481 int access_flags; 482 u32 mkey; 483 }; 484 485 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 486 { 487 return container_of(wr, struct mlx5_umr_wr, wr); 488 } 489 490 struct mlx5_shared_mr_info { 491 int mr_id; 492 struct ib_umem *umem; 493 }; 494 495 enum mlx5_ib_cq_pr_flags { 496 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 497 }; 498 499 struct mlx5_ib_cq { 500 struct ib_cq ibcq; 501 struct mlx5_core_cq mcq; 502 struct mlx5_ib_cq_buf buf; 503 struct mlx5_db db; 504 505 /* serialize access to the CQ 506 */ 507 spinlock_t lock; 508 509 /* protect resize cq 510 */ 511 struct mutex resize_mutex; 512 struct mlx5_ib_cq_buf *resize_buf; 513 struct ib_umem *resize_umem; 514 int cqe_size; 515 struct list_head list_send_qp; 516 struct list_head list_recv_qp; 517 u32 create_flags; 518 struct list_head wc_list; 519 enum ib_cq_notify_flags notify_flags; 520 struct work_struct notify_work; 521 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 522 }; 523 524 struct mlx5_ib_wc { 525 struct ib_wc wc; 526 struct list_head list; 527 }; 528 529 struct mlx5_ib_srq { 530 struct ib_srq ibsrq; 531 struct mlx5_core_srq msrq; 532 struct mlx5_frag_buf buf; 533 struct mlx5_db db; 534 struct mlx5_frag_buf_ctrl fbc; 535 u64 *wrid; 536 /* protect SRQ hanlding 537 */ 538 spinlock_t lock; 539 int head; 540 int tail; 541 u16 wqe_ctr; 542 struct ib_umem *umem; 543 /* serialize arming a SRQ 544 */ 545 struct mutex mutex; 546 int wq_sig; 547 }; 548 549 struct mlx5_ib_xrcd { 550 struct ib_xrcd ibxrcd; 551 u32 xrcdn; 552 }; 553 554 enum mlx5_ib_mtt_access_flags { 555 MLX5_IB_MTT_READ = (1 << 0), 556 MLX5_IB_MTT_WRITE = (1 << 1), 557 }; 558 559 struct mlx5_ib_dm { 560 struct ib_dm ibdm; 561 phys_addr_t dev_addr; 562 u32 type; 563 size_t size; 564 union { 565 struct { 566 u32 obj_id; 567 } icm_dm; 568 /* other dm types specific params should be added here */ 569 }; 570 }; 571 572 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 573 574 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 575 IB_ACCESS_REMOTE_WRITE |\ 576 IB_ACCESS_REMOTE_READ |\ 577 IB_ACCESS_REMOTE_ATOMIC |\ 578 IB_ZERO_BASED) 579 580 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 581 IB_ACCESS_REMOTE_WRITE |\ 582 IB_ACCESS_REMOTE_READ |\ 583 IB_ZERO_BASED) 584 585 struct mlx5_ib_mr { 586 struct ib_mr ibmr; 587 void *descs; 588 dma_addr_t desc_map; 589 int ndescs; 590 int max_descs; 591 int desc_size; 592 int access_mode; 593 struct mlx5_core_mkey mmkey; 594 struct ib_umem *umem; 595 struct mlx5_shared_mr_info *smr_info; 596 struct list_head list; 597 int order; 598 bool allocated_from_cache; 599 int npages; 600 struct mlx5_ib_dev *dev; 601 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 602 struct mlx5_core_sig_ctx *sig; 603 int live; 604 void *descs_alloc; 605 int access_flags; /* Needed for rereg MR */ 606 607 struct mlx5_ib_mr *parent; 608 atomic_t num_leaf_free; 609 wait_queue_head_t q_leaf_free; 610 struct mlx5_async_work cb_work; 611 atomic_t num_pending_prefetch; 612 }; 613 614 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 615 { 616 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 617 mr->umem->is_odp; 618 } 619 620 struct mlx5_ib_mw { 621 struct ib_mw ibmw; 622 struct mlx5_core_mkey mmkey; 623 int ndescs; 624 }; 625 626 struct mlx5_ib_devx_mr { 627 struct mlx5_core_mkey mmkey; 628 int ndescs; 629 struct rcu_head rcu; 630 }; 631 632 struct mlx5_ib_umr_context { 633 struct ib_cqe cqe; 634 enum ib_wc_status status; 635 struct completion done; 636 }; 637 638 struct umr_common { 639 struct ib_pd *pd; 640 struct ib_cq *cq; 641 struct ib_qp *qp; 642 /* control access to UMR QP 643 */ 644 struct semaphore sem; 645 }; 646 647 enum { 648 MLX5_FMR_INVALID, 649 MLX5_FMR_VALID, 650 MLX5_FMR_BUSY, 651 }; 652 653 struct mlx5_cache_ent { 654 struct list_head head; 655 /* sync access to the cahce entry 656 */ 657 spinlock_t lock; 658 659 660 char name[4]; 661 u32 order; 662 u32 xlt; 663 u32 access_mode; 664 u32 page; 665 666 u32 size; 667 u32 cur; 668 u32 miss; 669 u32 limit; 670 671 struct mlx5_ib_dev *dev; 672 struct work_struct work; 673 struct delayed_work dwork; 674 int pending; 675 struct completion compl; 676 }; 677 678 struct mlx5_mr_cache { 679 struct workqueue_struct *wq; 680 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 681 int stopped; 682 struct dentry *root; 683 unsigned long last_add; 684 }; 685 686 struct mlx5_ib_gsi_qp; 687 688 struct mlx5_ib_port_resources { 689 struct mlx5_ib_resources *devr; 690 struct mlx5_ib_gsi_qp *gsi; 691 struct work_struct pkey_change_work; 692 }; 693 694 struct mlx5_ib_resources { 695 struct ib_cq *c0; 696 struct ib_xrcd *x0; 697 struct ib_xrcd *x1; 698 struct ib_pd *p0; 699 struct ib_srq *s0; 700 struct ib_srq *s1; 701 struct mlx5_ib_port_resources ports[2]; 702 /* Protects changes to the port resources */ 703 struct mutex mutex; 704 }; 705 706 struct mlx5_ib_counters { 707 const char **names; 708 size_t *offsets; 709 u32 num_q_counters; 710 u32 num_cong_counters; 711 u32 num_ext_ppcnt_counters; 712 u16 set_id; 713 bool set_id_valid; 714 }; 715 716 struct mlx5_ib_multiport_info; 717 718 struct mlx5_ib_multiport { 719 struct mlx5_ib_multiport_info *mpi; 720 /* To be held when accessing the multiport info */ 721 spinlock_t mpi_lock; 722 }; 723 724 struct mlx5_roce { 725 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 726 * netdev pointer 727 */ 728 rwlock_t netdev_lock; 729 struct net_device *netdev; 730 struct notifier_block nb; 731 atomic_t tx_port_affinity; 732 enum ib_port_state last_port_state; 733 struct mlx5_ib_dev *dev; 734 u8 native_port_num; 735 }; 736 737 struct mlx5_ib_port { 738 struct mlx5_ib_counters cnts; 739 struct mlx5_ib_multiport mp; 740 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 741 struct mlx5_roce roce; 742 struct mlx5_eswitch_rep *rep; 743 }; 744 745 struct mlx5_ib_dbg_param { 746 int offset; 747 struct mlx5_ib_dev *dev; 748 struct dentry *dentry; 749 u8 port_num; 750 }; 751 752 enum mlx5_ib_dbg_cc_types { 753 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 754 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 755 MLX5_IB_DBG_CC_RP_TIME_RESET, 756 MLX5_IB_DBG_CC_RP_BYTE_RESET, 757 MLX5_IB_DBG_CC_RP_THRESHOLD, 758 MLX5_IB_DBG_CC_RP_AI_RATE, 759 MLX5_IB_DBG_CC_RP_HAI_RATE, 760 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 761 MLX5_IB_DBG_CC_RP_MIN_RATE, 762 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 763 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 764 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 765 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 766 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 767 MLX5_IB_DBG_CC_RP_GD, 768 MLX5_IB_DBG_CC_NP_CNP_DSCP, 769 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 770 MLX5_IB_DBG_CC_NP_CNP_PRIO, 771 MLX5_IB_DBG_CC_MAX, 772 }; 773 774 struct mlx5_ib_dbg_cc_params { 775 struct dentry *root; 776 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 777 }; 778 779 enum { 780 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 781 }; 782 783 struct mlx5_ib_dbg_delay_drop { 784 struct dentry *dir_debugfs; 785 struct dentry *rqs_cnt_debugfs; 786 struct dentry *events_cnt_debugfs; 787 struct dentry *timeout_debugfs; 788 }; 789 790 struct mlx5_ib_delay_drop { 791 struct mlx5_ib_dev *dev; 792 struct work_struct delay_drop_work; 793 /* serialize setting of delay drop */ 794 struct mutex lock; 795 u32 timeout; 796 bool activate; 797 atomic_t events_cnt; 798 atomic_t rqs_cnt; 799 struct mlx5_ib_dbg_delay_drop *dbg; 800 }; 801 802 enum mlx5_ib_stages { 803 MLX5_IB_STAGE_INIT, 804 MLX5_IB_STAGE_FLOW_DB, 805 MLX5_IB_STAGE_CAPS, 806 MLX5_IB_STAGE_NON_DEFAULT_CB, 807 MLX5_IB_STAGE_ROCE, 808 MLX5_IB_STAGE_SRQ, 809 MLX5_IB_STAGE_DEVICE_RESOURCES, 810 MLX5_IB_STAGE_DEVICE_NOTIFIER, 811 MLX5_IB_STAGE_ODP, 812 MLX5_IB_STAGE_COUNTERS, 813 MLX5_IB_STAGE_CONG_DEBUGFS, 814 MLX5_IB_STAGE_UAR, 815 MLX5_IB_STAGE_BFREG, 816 MLX5_IB_STAGE_PRE_IB_REG_UMR, 817 MLX5_IB_STAGE_WHITELIST_UID, 818 MLX5_IB_STAGE_IB_REG, 819 MLX5_IB_STAGE_POST_IB_REG_UMR, 820 MLX5_IB_STAGE_DELAY_DROP, 821 MLX5_IB_STAGE_CLASS_ATTR, 822 MLX5_IB_STAGE_MAX, 823 }; 824 825 struct mlx5_ib_stage { 826 int (*init)(struct mlx5_ib_dev *dev); 827 void (*cleanup)(struct mlx5_ib_dev *dev); 828 }; 829 830 #define STAGE_CREATE(_stage, _init, _cleanup) \ 831 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 832 833 struct mlx5_ib_profile { 834 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 835 }; 836 837 struct mlx5_ib_multiport_info { 838 struct list_head list; 839 struct mlx5_ib_dev *ibdev; 840 struct mlx5_core_dev *mdev; 841 struct notifier_block mdev_events; 842 struct completion unref_comp; 843 u64 sys_image_guid; 844 u32 mdev_refcnt; 845 bool is_master; 846 bool unaffiliate; 847 }; 848 849 struct mlx5_ib_flow_action { 850 struct ib_flow_action ib_action; 851 union { 852 struct { 853 u64 ib_flags; 854 struct mlx5_accel_esp_xfrm *ctx; 855 } esp_aes_gcm; 856 struct { 857 struct mlx5_ib_dev *dev; 858 u32 sub_type; 859 u32 action_id; 860 } flow_action_raw; 861 }; 862 }; 863 864 struct mlx5_dm { 865 struct mlx5_core_dev *dev; 866 /* This lock is used to protect the access to the shared 867 * allocation map when concurrent requests by different 868 * processes are handled. 869 */ 870 spinlock_t lock; 871 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 872 unsigned long *steering_sw_icm_alloc_blocks; 873 unsigned long *header_modify_sw_icm_alloc_blocks; 874 }; 875 876 struct mlx5_read_counters_attr { 877 struct mlx5_fc *hw_cntrs_hndl; 878 u64 *out; 879 u32 flags; 880 }; 881 882 enum mlx5_ib_counters_type { 883 MLX5_IB_COUNTERS_FLOW, 884 }; 885 886 struct mlx5_ib_mcounters { 887 struct ib_counters ibcntrs; 888 enum mlx5_ib_counters_type type; 889 /* number of counters supported for this counters type */ 890 u32 counters_num; 891 struct mlx5_fc *hw_cntrs_hndl; 892 /* read function for this counters type */ 893 int (*read_counters)(struct ib_device *ibdev, 894 struct mlx5_read_counters_attr *read_attr); 895 /* max index set as part of create_flow */ 896 u32 cntrs_max_index; 897 /* number of counters data entries (<description,index> pair) */ 898 u32 ncounters; 899 /* counters data array for descriptions and indexes */ 900 struct mlx5_ib_flow_counters_desc *counters_data; 901 /* protects access to mcounters internal data */ 902 struct mutex mcntrs_mutex; 903 }; 904 905 static inline struct mlx5_ib_mcounters * 906 to_mcounters(struct ib_counters *ibcntrs) 907 { 908 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 909 } 910 911 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 912 bool is_egress, 913 struct mlx5_flow_act *action); 914 struct mlx5_ib_lb_state { 915 /* protect the user_td */ 916 struct mutex mutex; 917 u32 user_td; 918 int qps; 919 bool enabled; 920 }; 921 922 struct mlx5_ib_pf_eq { 923 struct mlx5_ib_dev *dev; 924 struct mlx5_eq *core; 925 struct work_struct work; 926 spinlock_t lock; /* Pagefaults spinlock */ 927 struct workqueue_struct *wq; 928 mempool_t *pool; 929 }; 930 931 struct mlx5_ib_dev { 932 struct ib_device ib_dev; 933 struct mlx5_core_dev *mdev; 934 struct notifier_block mdev_events; 935 int num_ports; 936 /* serialize update of capability mask 937 */ 938 struct mutex cap_mask_mutex; 939 bool ib_active; 940 struct umr_common umrc; 941 /* sync used page count stats 942 */ 943 struct mlx5_ib_resources devr; 944 struct mlx5_mr_cache cache; 945 struct timer_list delay_timer; 946 /* Prevents soft lock on massive reg MRs */ 947 struct mutex slow_path_mutex; 948 int fill_delay; 949 struct ib_odp_caps odp_caps; 950 u64 odp_max_size; 951 struct mlx5_ib_pf_eq odp_pf_eq; 952 953 /* 954 * Sleepable RCU that prevents destruction of MRs while they are still 955 * being used by a page fault handler. 956 */ 957 struct srcu_struct mr_srcu; 958 u32 null_mkey; 959 struct mlx5_ib_flow_db *flow_db; 960 /* protect resources needed as part of reset flow */ 961 spinlock_t reset_flow_resource_lock; 962 struct list_head qp_list; 963 /* Array with num_ports elements */ 964 struct mlx5_ib_port *port; 965 struct mlx5_sq_bfreg bfreg; 966 struct mlx5_sq_bfreg fp_bfreg; 967 struct mlx5_ib_delay_drop delay_drop; 968 const struct mlx5_ib_profile *profile; 969 bool is_rep; 970 int lag_active; 971 972 struct mlx5_ib_lb_state lb; 973 u8 umr_fence; 974 struct list_head ib_dev_list; 975 u64 sys_image_guid; 976 struct mlx5_dm dm; 977 u16 devx_whitelist_uid; 978 struct mlx5_srq_table srq_table; 979 struct mlx5_async_ctx async_ctx; 980 int free_port; 981 }; 982 983 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 984 { 985 return container_of(mcq, struct mlx5_ib_cq, mcq); 986 } 987 988 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 989 { 990 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 991 } 992 993 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 994 { 995 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 996 } 997 998 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 999 { 1000 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1001 udata, struct mlx5_ib_ucontext, ibucontext); 1002 1003 return to_mdev(context->ibucontext.device); 1004 } 1005 1006 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1007 { 1008 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1009 } 1010 1011 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1012 { 1013 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1014 } 1015 1016 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1017 { 1018 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1019 } 1020 1021 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 1022 { 1023 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 1024 } 1025 1026 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1027 { 1028 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1029 } 1030 1031 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1032 { 1033 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1034 } 1035 1036 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1037 { 1038 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1039 } 1040 1041 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1042 { 1043 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1044 } 1045 1046 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1047 { 1048 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1049 } 1050 1051 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1052 { 1053 return container_of(msrq, struct mlx5_ib_srq, msrq); 1054 } 1055 1056 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1057 { 1058 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1059 } 1060 1061 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1062 { 1063 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1064 } 1065 1066 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1067 { 1068 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1069 } 1070 1071 static inline struct mlx5_ib_flow_action * 1072 to_mflow_act(struct ib_flow_action *ibact) 1073 { 1074 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1075 } 1076 1077 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1078 struct ib_udata *udata, unsigned long virt, 1079 struct mlx5_db *db); 1080 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1081 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1082 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1083 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1084 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags, 1085 struct ib_udata *udata); 1086 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1087 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1088 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1089 struct ib_udata *udata); 1090 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1091 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1092 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1093 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1094 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1095 const struct ib_recv_wr **bad_wr); 1096 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1097 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1098 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1099 struct ib_qp_init_attr *init_attr, 1100 struct ib_udata *udata); 1101 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1102 int attr_mask, struct ib_udata *udata); 1103 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1104 struct ib_qp_init_attr *qp_init_attr); 1105 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1106 void mlx5_ib_drain_sq(struct ib_qp *qp); 1107 void mlx5_ib_drain_rq(struct ib_qp *qp); 1108 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1109 const struct ib_send_wr **bad_wr); 1110 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1111 const struct ib_recv_wr **bad_wr); 1112 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1113 int buflen, size_t *bc); 1114 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1115 int buflen, size_t *bc); 1116 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 1117 void *buffer, int buflen, size_t *bc); 1118 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 1119 const struct ib_cq_init_attr *attr, 1120 struct ib_udata *udata); 1121 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1122 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1123 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1124 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1125 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1126 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1127 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1128 u64 virt_addr, int access_flags, 1129 struct ib_udata *udata); 1130 int mlx5_ib_advise_mr(struct ib_pd *pd, 1131 enum ib_uverbs_advise_mr_advice advice, 1132 u32 flags, 1133 struct ib_sge *sg_list, 1134 u32 num_sge, 1135 struct uverbs_attr_bundle *attrs); 1136 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1137 struct ib_udata *udata); 1138 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1139 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1140 int page_shift, int flags); 1141 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1142 struct ib_udata *udata, 1143 int access_flags); 1144 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1145 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1146 u64 length, u64 virt_addr, int access_flags, 1147 struct ib_pd *pd, struct ib_udata *udata); 1148 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1149 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1150 u32 max_num_sg, struct ib_udata *udata); 1151 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1152 unsigned int *sg_offset); 1153 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1154 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1155 const struct ib_mad_hdr *in, size_t in_mad_size, 1156 struct ib_mad_hdr *out, size_t *out_mad_size, 1157 u16 *out_mad_pkey_index); 1158 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1159 struct ib_udata *udata); 1160 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1161 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1162 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1163 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1164 struct ib_smp *out_mad); 1165 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1166 __be64 *sys_image_guid); 1167 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1168 u16 *max_pkeys); 1169 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1170 u32 *vendor_id); 1171 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1172 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1173 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1174 u16 *pkey); 1175 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1176 union ib_gid *gid); 1177 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1178 struct ib_port_attr *props); 1179 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1180 struct ib_port_attr *props); 1181 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1182 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1183 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1184 unsigned long max_page_shift, 1185 int *count, int *shift, 1186 int *ncont, int *order); 1187 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1188 int page_shift, size_t offset, size_t num_pages, 1189 __be64 *pas, int access_flags); 1190 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1191 int page_shift, __be64 *pas, int access_flags); 1192 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1193 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1194 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1195 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1196 1197 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1198 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1199 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1200 struct ib_mr_status *mr_status); 1201 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1202 struct ib_wq_init_attr *init_attr, 1203 struct ib_udata *udata); 1204 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1205 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1206 u32 wq_attr_mask, struct ib_udata *udata); 1207 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1208 struct ib_rwq_ind_table_init_attr *init_attr, 1209 struct ib_udata *udata); 1210 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1211 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1212 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1213 struct ib_ucontext *context, 1214 struct ib_dm_alloc_attr *attr, 1215 struct uverbs_attr_bundle *attrs); 1216 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1217 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1218 struct ib_dm_mr_attr *attr, 1219 struct uverbs_attr_bundle *attrs); 1220 1221 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1222 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1223 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1224 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1225 int __init mlx5_ib_odp_init(void); 1226 void mlx5_ib_odp_cleanup(void); 1227 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start, 1228 unsigned long end); 1229 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1230 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1231 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1232 1233 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1234 enum ib_uverbs_advise_mr_advice advice, 1235 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1236 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1237 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1238 { 1239 return; 1240 } 1241 1242 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1243 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1244 static inline int mlx5_ib_odp_init(void) { return 0; } 1245 static inline void mlx5_ib_odp_cleanup(void) {} 1246 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1247 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1248 size_t nentries, struct mlx5_ib_mr *mr, 1249 int flags) {} 1250 1251 static inline int 1252 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1253 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1254 struct ib_sge *sg_list, u32 num_sge) 1255 { 1256 return -EOPNOTSUPP; 1257 } 1258 static inline void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, 1259 unsigned long start, 1260 unsigned long end){}; 1261 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1262 1263 /* Needed for rep profile */ 1264 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1265 const struct mlx5_ib_profile *profile, 1266 int stage); 1267 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1268 const struct mlx5_ib_profile *profile); 1269 1270 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1271 u8 port, struct ifla_vf_info *info); 1272 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1273 u8 port, int state); 1274 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1275 u8 port, struct ifla_vf_stats *stats); 1276 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1277 u64 guid, int type); 1278 1279 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1280 const struct ib_gid_attr *attr); 1281 1282 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1283 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1284 1285 /* GSI QP helper functions */ 1286 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1287 struct ib_qp_init_attr *init_attr); 1288 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1289 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1290 int attr_mask); 1291 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1292 int qp_attr_mask, 1293 struct ib_qp_init_attr *qp_init_attr); 1294 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1295 const struct ib_send_wr **bad_wr); 1296 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1297 const struct ib_recv_wr **bad_wr); 1298 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1299 1300 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1301 1302 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1303 int bfregn); 1304 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1305 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1306 u8 ib_port_num, 1307 u8 *native_port_num); 1308 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1309 u8 port_num); 1310 1311 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1312 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user); 1313 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1314 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); 1315 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1316 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1317 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1318 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1319 struct mlx5_flow_act *flow_act, u32 counter_id, 1320 void *cmd_in, int inlen, int dest_id, int dest_type); 1321 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1322 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 *counter_id); 1323 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root); 1324 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1325 #else 1326 static inline int 1327 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1328 bool is_user) { return -EOPNOTSUPP; } 1329 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1330 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1331 int *dest_type) 1332 { 1333 return false; 1334 } 1335 static inline void 1336 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1337 { 1338 return; 1339 }; 1340 #endif 1341 static inline void init_query_mad(struct ib_smp *mad) 1342 { 1343 mad->base_version = 1; 1344 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1345 mad->class_version = 1; 1346 mad->method = IB_MGMT_METHOD_GET; 1347 } 1348 1349 static inline u8 convert_access(int acc) 1350 { 1351 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1352 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1353 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1354 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1355 MLX5_PERM_LOCAL_READ; 1356 } 1357 1358 static inline int is_qp1(enum ib_qp_type qp_type) 1359 { 1360 return qp_type == MLX5_IB_QPT_HW_GSI; 1361 } 1362 1363 #define MLX5_MAX_UMR_SHIFT 16 1364 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1365 1366 static inline u32 check_cq_create_flags(u32 flags) 1367 { 1368 /* 1369 * It returns non-zero value for unsupported CQ 1370 * create flags, otherwise it returns zero. 1371 */ 1372 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1373 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1374 } 1375 1376 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1377 u32 *user_index) 1378 { 1379 if (cqe_version) { 1380 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1381 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1382 return -EINVAL; 1383 *user_index = cmd_uidx; 1384 } else { 1385 *user_index = MLX5_IB_DEFAULT_UIDX; 1386 } 1387 1388 return 0; 1389 } 1390 1391 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1392 struct mlx5_ib_create_qp *ucmd, 1393 int inlen, 1394 u32 *user_index) 1395 { 1396 u8 cqe_version = ucontext->cqe_version; 1397 1398 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1399 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1400 return 0; 1401 1402 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1403 !!cqe_version)) 1404 return -EINVAL; 1405 1406 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1407 } 1408 1409 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1410 struct mlx5_ib_create_srq *ucmd, 1411 int inlen, 1412 u32 *user_index) 1413 { 1414 u8 cqe_version = ucontext->cqe_version; 1415 1416 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1417 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1418 return 0; 1419 1420 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1421 !!cqe_version)) 1422 return -EINVAL; 1423 1424 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1425 } 1426 1427 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1428 { 1429 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1430 MLX5_UARS_IN_PAGE : 1; 1431 } 1432 1433 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1434 struct mlx5_bfreg_info *bfregi) 1435 { 1436 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1437 } 1438 1439 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1440 void mlx5_ib_put_xlt_emergency_page(void); 1441 1442 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1443 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1444 bool dyn_bfreg); 1445 #endif /* MLX5_IB_H */ 1446