1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 250 { 251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 252 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 253 struct mlx4_port_gid_table *port_gid_table; 254 int free = -1, found = -1; 255 int ret = 0; 256 int hw_update = 0; 257 int i; 258 struct gid_entry *gids = NULL; 259 260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 261 return -EINVAL; 262 263 if (attr->port_num > MLX4_MAX_PORTS) 264 return -EINVAL; 265 266 if (!context) 267 return -EINVAL; 268 269 port_gid_table = &iboe->gids[attr->port_num - 1]; 270 spin_lock_bh(&iboe->lock); 271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 272 if (!memcmp(&port_gid_table->gids[i].gid, 273 &attr->gid, sizeof(attr->gid)) && 274 port_gid_table->gids[i].gid_type == attr->gid_type) { 275 found = i; 276 break; 277 } 278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 279 free = i; /* HW has space */ 280 } 281 282 if (found < 0) { 283 if (free < 0) { 284 ret = -ENOSPC; 285 } else { 286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 287 if (!port_gid_table->gids[free].ctx) { 288 ret = -ENOMEM; 289 } else { 290 *context = port_gid_table->gids[free].ctx; 291 memcpy(&port_gid_table->gids[free].gid, 292 &attr->gid, sizeof(attr->gid)); 293 port_gid_table->gids[free].gid_type = attr->gid_type; 294 port_gid_table->gids[free].ctx->real_index = free; 295 port_gid_table->gids[free].ctx->refcount = 1; 296 hw_update = 1; 297 } 298 } 299 } else { 300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 301 *context = ctx; 302 ctx->refcount++; 303 } 304 if (!ret && hw_update) { 305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 306 GFP_ATOMIC); 307 if (!gids) { 308 ret = -ENOMEM; 309 } else { 310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 312 gids[i].gid_type = port_gid_table->gids[i].gid_type; 313 } 314 } 315 } 316 spin_unlock_bh(&iboe->lock); 317 318 if (!ret && hw_update) { 319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 320 kfree(gids); 321 } 322 323 return ret; 324 } 325 326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 327 { 328 struct gid_cache_context *ctx = *context; 329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 330 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 331 struct mlx4_port_gid_table *port_gid_table; 332 int ret = 0; 333 int hw_update = 0; 334 struct gid_entry *gids = NULL; 335 336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 337 return -EINVAL; 338 339 if (attr->port_num > MLX4_MAX_PORTS) 340 return -EINVAL; 341 342 port_gid_table = &iboe->gids[attr->port_num - 1]; 343 spin_lock_bh(&iboe->lock); 344 if (ctx) { 345 ctx->refcount--; 346 if (!ctx->refcount) { 347 unsigned int real_index = ctx->real_index; 348 349 memset(&port_gid_table->gids[real_index].gid, 0, 350 sizeof(port_gid_table->gids[real_index].gid)); 351 kfree(port_gid_table->gids[real_index].ctx); 352 port_gid_table->gids[real_index].ctx = NULL; 353 hw_update = 1; 354 } 355 } 356 if (!ret && hw_update) { 357 int i; 358 359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 360 GFP_ATOMIC); 361 if (!gids) { 362 ret = -ENOMEM; 363 } else { 364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 365 memcpy(&gids[i].gid, 366 &port_gid_table->gids[i].gid, 367 sizeof(union ib_gid)); 368 gids[i].gid_type = 369 port_gid_table->gids[i].gid_type; 370 } 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 const struct ib_gid_attr *attr) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 struct mlx4_port_gid_table *port_gid_table; 388 int real_index = -EINVAL; 389 int i; 390 unsigned long flags; 391 u8 port_num = attr->port_num; 392 393 if (port_num > MLX4_MAX_PORTS) 394 return -EINVAL; 395 396 if (mlx4_is_bonded(ibdev->dev)) 397 port_num = 1; 398 399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 400 return attr->index; 401 402 spin_lock_irqsave(&iboe->lock, flags); 403 port_gid_table = &iboe->gids[port_num - 1]; 404 405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 406 if (!memcmp(&port_gid_table->gids[i].gid, 407 &attr->gid, sizeof(attr->gid)) && 408 attr->gid_type == port_gid_table->gids[i].gid_type) { 409 ctx = port_gid_table->gids[i].ctx; 410 break; 411 } 412 if (ctx) 413 real_index = ctx->real_index; 414 spin_unlock_irqrestore(&iboe->lock, flags); 415 return real_index; 416 } 417 418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 419 sizeof(((type *)0)->fld) <= (sz)) 420 421 static int mlx4_ib_query_device(struct ib_device *ibdev, 422 struct ib_device_attr *props, 423 struct ib_udata *uhw) 424 { 425 struct mlx4_ib_dev *dev = to_mdev(ibdev); 426 struct ib_smp *in_mad = NULL; 427 struct ib_smp *out_mad = NULL; 428 int err; 429 int have_ib_ports; 430 struct mlx4_uverbs_ex_query_device cmd; 431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 432 struct mlx4_clock_params clock_params; 433 434 if (uhw->inlen) { 435 if (uhw->inlen < sizeof(cmd)) 436 return -EINVAL; 437 438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 439 if (err) 440 return err; 441 442 if (cmd.comp_mask) 443 return -EINVAL; 444 445 if (cmd.reserved) 446 return -EINVAL; 447 } 448 449 resp.response_length = offsetof(typeof(resp), response_length) + 450 sizeof(resp.response_length); 451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 453 err = -ENOMEM; 454 if (!in_mad || !out_mad) 455 goto out; 456 457 init_query_mad(in_mad); 458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 459 460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 461 1, NULL, NULL, in_mad, out_mad); 462 if (err) 463 goto out; 464 465 memset(props, 0, sizeof *props); 466 467 have_ib_ports = num_ib_ports(dev->dev); 468 469 props->fw_ver = dev->dev->caps.fw_ver; 470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 471 IB_DEVICE_PORT_ACTIVE_EVENT | 472 IB_DEVICE_SYS_IMAGE_GUID | 473 IB_DEVICE_RC_RNR_NAK_GEN | 474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 485 if (dev->dev->caps.max_gso_sz && 486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 488 props->device_cap_flags |= IB_DEVICE_UD_TSO; 489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 496 props->device_cap_flags |= IB_DEVICE_XRC; 497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 502 else 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 504 } 505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 507 508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 509 510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 511 0xffffff; 512 props->vendor_part_id = dev->dev->persist->pdev->device; 513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 515 516 props->max_mr_size = ~0ull; 517 props->page_size_cap = dev->dev->caps.page_size_cap; 518 props->max_qp = dev->dev->quotas.qp; 519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 520 props->max_send_sge = dev->dev->caps.max_sq_sg; 521 props->max_recv_sge = dev->dev->caps.max_rq_sg; 522 props->max_sge_rd = MLX4_MAX_SGE_RD; 523 props->max_cq = dev->dev->quotas.cq; 524 props->max_cqe = dev->dev->caps.max_cqes; 525 props->max_mr = dev->dev->quotas.mpt; 526 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 527 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 528 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 529 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 530 props->max_srq = dev->dev->quotas.srq; 531 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 532 props->max_srq_sge = dev->dev->caps.max_srq_sge; 533 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 534 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 535 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 536 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 537 props->masked_atomic_cap = props->atomic_cap; 538 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 539 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 540 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 541 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 542 props->max_mcast_grp; 543 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 544 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 545 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 546 props->max_ah = INT_MAX; 547 548 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 549 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 550 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 551 props->rss_caps.max_rwq_indirection_tables = 552 props->max_qp; 553 props->rss_caps.max_rwq_indirection_table_size = 554 dev->dev->caps.max_rss_tbl_sz; 555 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 556 props->max_wq_type_rq = props->max_qp; 557 } 558 559 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 560 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 561 } 562 563 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 564 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 565 566 if (!mlx4_is_slave(dev->dev)) 567 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 568 569 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 570 resp.response_length += sizeof(resp.hca_core_clock_offset); 571 if (!err && !mlx4_is_slave(dev->dev)) { 572 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 573 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 574 } 575 } 576 577 if (uhw->outlen >= resp.response_length + 578 sizeof(resp.max_inl_recv_sz)) { 579 resp.response_length += sizeof(resp.max_inl_recv_sz); 580 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 581 sizeof(struct mlx4_wqe_data_seg); 582 } 583 584 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 585 if (props->rss_caps.supported_qpts) { 586 resp.rss_caps.rx_hash_function = 587 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 588 589 resp.rss_caps.rx_hash_fields_mask = 590 MLX4_IB_RX_HASH_SRC_IPV4 | 591 MLX4_IB_RX_HASH_DST_IPV4 | 592 MLX4_IB_RX_HASH_SRC_IPV6 | 593 MLX4_IB_RX_HASH_DST_IPV6 | 594 MLX4_IB_RX_HASH_SRC_PORT_TCP | 595 MLX4_IB_RX_HASH_DST_PORT_TCP | 596 MLX4_IB_RX_HASH_SRC_PORT_UDP | 597 MLX4_IB_RX_HASH_DST_PORT_UDP; 598 599 if (dev->dev->caps.tunnel_offload_mode == 600 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 601 resp.rss_caps.rx_hash_fields_mask |= 602 MLX4_IB_RX_HASH_INNER; 603 } 604 resp.response_length = offsetof(typeof(resp), rss_caps) + 605 sizeof(resp.rss_caps); 606 } 607 608 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 609 if (dev->dev->caps.max_gso_sz && 610 ((mlx4_ib_port_link_layer(ibdev, 1) == 611 IB_LINK_LAYER_ETHERNET) || 612 (mlx4_ib_port_link_layer(ibdev, 2) == 613 IB_LINK_LAYER_ETHERNET))) { 614 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 615 resp.tso_caps.supported_qpts |= 616 1 << IB_QPT_RAW_PACKET; 617 } 618 resp.response_length = offsetof(typeof(resp), tso_caps) + 619 sizeof(resp.tso_caps); 620 } 621 622 if (uhw->outlen) { 623 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 624 if (err) 625 goto out; 626 } 627 out: 628 kfree(in_mad); 629 kfree(out_mad); 630 631 return err; 632 } 633 634 static enum rdma_link_layer 635 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 636 { 637 struct mlx4_dev *dev = to_mdev(device)->dev; 638 639 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 640 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 641 } 642 643 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 644 struct ib_port_attr *props, int netw_view) 645 { 646 struct ib_smp *in_mad = NULL; 647 struct ib_smp *out_mad = NULL; 648 int ext_active_speed; 649 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 650 int err = -ENOMEM; 651 652 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 653 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 654 if (!in_mad || !out_mad) 655 goto out; 656 657 init_query_mad(in_mad); 658 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 659 in_mad->attr_mod = cpu_to_be32(port); 660 661 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 662 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 663 664 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 665 in_mad, out_mad); 666 if (err) 667 goto out; 668 669 670 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 671 props->lmc = out_mad->data[34] & 0x7; 672 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 673 props->sm_sl = out_mad->data[36] & 0xf; 674 props->state = out_mad->data[32] & 0xf; 675 props->phys_state = out_mad->data[33] >> 4; 676 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 677 if (netw_view) 678 props->gid_tbl_len = out_mad->data[50]; 679 else 680 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 681 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 682 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 683 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 684 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 685 props->active_width = out_mad->data[31] & 0xf; 686 props->active_speed = out_mad->data[35] >> 4; 687 props->max_mtu = out_mad->data[41] & 0xf; 688 props->active_mtu = out_mad->data[36] >> 4; 689 props->subnet_timeout = out_mad->data[51] & 0x1f; 690 props->max_vl_num = out_mad->data[37] >> 4; 691 props->init_type_reply = out_mad->data[41] >> 4; 692 693 /* Check if extended speeds (EDR/FDR/...) are supported */ 694 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 695 ext_active_speed = out_mad->data[62] >> 4; 696 697 switch (ext_active_speed) { 698 case 1: 699 props->active_speed = IB_SPEED_FDR; 700 break; 701 case 2: 702 props->active_speed = IB_SPEED_EDR; 703 break; 704 } 705 } 706 707 /* If reported active speed is QDR, check if is FDR-10 */ 708 if (props->active_speed == IB_SPEED_QDR) { 709 init_query_mad(in_mad); 710 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 711 in_mad->attr_mod = cpu_to_be32(port); 712 713 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 714 NULL, NULL, in_mad, out_mad); 715 if (err) 716 goto out; 717 718 /* Checking LinkSpeedActive for FDR-10 */ 719 if (out_mad->data[15] & 0x1) 720 props->active_speed = IB_SPEED_FDR10; 721 } 722 723 /* Avoid wrong speed value returned by FW if the IB link is down. */ 724 if (props->state == IB_PORT_DOWN) 725 props->active_speed = IB_SPEED_SDR; 726 727 out: 728 kfree(in_mad); 729 kfree(out_mad); 730 return err; 731 } 732 733 static u8 state_to_phys_state(enum ib_port_state state) 734 { 735 return state == IB_PORT_ACTIVE ? 5 : 3; 736 } 737 738 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 739 struct ib_port_attr *props) 740 { 741 742 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 743 struct mlx4_ib_iboe *iboe = &mdev->iboe; 744 struct net_device *ndev; 745 enum ib_mtu tmp; 746 struct mlx4_cmd_mailbox *mailbox; 747 int err = 0; 748 int is_bonded = mlx4_is_bonded(mdev->dev); 749 750 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 751 if (IS_ERR(mailbox)) 752 return PTR_ERR(mailbox); 753 754 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 755 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 756 MLX4_CMD_WRAPPED); 757 if (err) 758 goto out; 759 760 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 761 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 762 IB_WIDTH_4X : IB_WIDTH_1X; 763 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 764 IB_SPEED_FDR : IB_SPEED_QDR; 765 props->port_cap_flags = IB_PORT_CM_SUP; 766 props->ip_gids = true; 767 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 768 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 769 props->pkey_tbl_len = 1; 770 props->max_mtu = IB_MTU_4096; 771 props->max_vl_num = 2; 772 props->state = IB_PORT_DOWN; 773 props->phys_state = state_to_phys_state(props->state); 774 props->active_mtu = IB_MTU_256; 775 spin_lock_bh(&iboe->lock); 776 ndev = iboe->netdevs[port - 1]; 777 if (ndev && is_bonded) { 778 rcu_read_lock(); /* required to get upper dev */ 779 ndev = netdev_master_upper_dev_get_rcu(ndev); 780 rcu_read_unlock(); 781 } 782 if (!ndev) 783 goto out_unlock; 784 785 tmp = iboe_get_mtu(ndev->mtu); 786 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 787 788 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 789 IB_PORT_ACTIVE : IB_PORT_DOWN; 790 props->phys_state = state_to_phys_state(props->state); 791 out_unlock: 792 spin_unlock_bh(&iboe->lock); 793 out: 794 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 795 return err; 796 } 797 798 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 799 struct ib_port_attr *props, int netw_view) 800 { 801 int err; 802 803 /* props being zeroed by the caller, avoid zeroing it here */ 804 805 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 806 ib_link_query_port(ibdev, port, props, netw_view) : 807 eth_link_query_port(ibdev, port, props); 808 809 return err; 810 } 811 812 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 813 struct ib_port_attr *props) 814 { 815 /* returns host view */ 816 return __mlx4_ib_query_port(ibdev, port, props, 0); 817 } 818 819 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 820 union ib_gid *gid, int netw_view) 821 { 822 struct ib_smp *in_mad = NULL; 823 struct ib_smp *out_mad = NULL; 824 int err = -ENOMEM; 825 struct mlx4_ib_dev *dev = to_mdev(ibdev); 826 int clear = 0; 827 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 828 829 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 830 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 831 if (!in_mad || !out_mad) 832 goto out; 833 834 init_query_mad(in_mad); 835 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 836 in_mad->attr_mod = cpu_to_be32(port); 837 838 if (mlx4_is_mfunc(dev->dev) && netw_view) 839 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 840 841 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 842 if (err) 843 goto out; 844 845 memcpy(gid->raw, out_mad->data + 8, 8); 846 847 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 848 if (index) { 849 /* For any index > 0, return the null guid */ 850 err = 0; 851 clear = 1; 852 goto out; 853 } 854 } 855 856 init_query_mad(in_mad); 857 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 858 in_mad->attr_mod = cpu_to_be32(index / 8); 859 860 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 861 NULL, NULL, in_mad, out_mad); 862 if (err) 863 goto out; 864 865 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 866 867 out: 868 if (clear) 869 memset(gid->raw + 8, 0, 8); 870 kfree(in_mad); 871 kfree(out_mad); 872 return err; 873 } 874 875 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 876 union ib_gid *gid) 877 { 878 if (rdma_protocol_ib(ibdev, port)) 879 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 880 return 0; 881 } 882 883 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 884 { 885 union sl2vl_tbl_to_u64 sl2vl64; 886 struct ib_smp *in_mad = NULL; 887 struct ib_smp *out_mad = NULL; 888 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 889 int err = -ENOMEM; 890 int jj; 891 892 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 893 *sl2vl_tbl = 0; 894 return 0; 895 } 896 897 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 898 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 899 if (!in_mad || !out_mad) 900 goto out; 901 902 init_query_mad(in_mad); 903 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 904 in_mad->attr_mod = 0; 905 906 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 907 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 908 909 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 910 in_mad, out_mad); 911 if (err) 912 goto out; 913 914 for (jj = 0; jj < 8; jj++) 915 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 916 *sl2vl_tbl = sl2vl64.sl64; 917 918 out: 919 kfree(in_mad); 920 kfree(out_mad); 921 return err; 922 } 923 924 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 925 { 926 u64 sl2vl; 927 int i; 928 int err; 929 930 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 931 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 932 continue; 933 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 934 if (err) { 935 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 936 i, err); 937 sl2vl = 0; 938 } 939 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 940 } 941 } 942 943 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 944 u16 *pkey, int netw_view) 945 { 946 struct ib_smp *in_mad = NULL; 947 struct ib_smp *out_mad = NULL; 948 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 949 int err = -ENOMEM; 950 951 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 952 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 953 if (!in_mad || !out_mad) 954 goto out; 955 956 init_query_mad(in_mad); 957 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 958 in_mad->attr_mod = cpu_to_be32(index / 32); 959 960 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 961 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 962 963 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 964 in_mad, out_mad); 965 if (err) 966 goto out; 967 968 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 969 970 out: 971 kfree(in_mad); 972 kfree(out_mad); 973 return err; 974 } 975 976 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 977 { 978 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 979 } 980 981 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 982 struct ib_device_modify *props) 983 { 984 struct mlx4_cmd_mailbox *mailbox; 985 unsigned long flags; 986 987 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 988 return -EOPNOTSUPP; 989 990 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 991 return 0; 992 993 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 994 return -EOPNOTSUPP; 995 996 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 997 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 998 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 999 1000 /* 1001 * If possible, pass node desc to FW, so it can generate 1002 * a 144 trap. If cmd fails, just ignore. 1003 */ 1004 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1005 if (IS_ERR(mailbox)) 1006 return 0; 1007 1008 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1009 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1010 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1011 1012 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1013 1014 return 0; 1015 } 1016 1017 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1018 u32 cap_mask) 1019 { 1020 struct mlx4_cmd_mailbox *mailbox; 1021 int err; 1022 1023 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1024 if (IS_ERR(mailbox)) 1025 return PTR_ERR(mailbox); 1026 1027 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1028 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1029 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1030 } else { 1031 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1032 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1033 } 1034 1035 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1036 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1037 MLX4_CMD_WRAPPED); 1038 1039 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1040 return err; 1041 } 1042 1043 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1044 struct ib_port_modify *props) 1045 { 1046 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1047 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1048 struct ib_port_attr attr; 1049 u32 cap_mask; 1050 int err; 1051 1052 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1053 * of whether port link layer is ETH or IB. For ETH ports, qkey 1054 * violations and port capabilities are not meaningful. 1055 */ 1056 if (is_eth) 1057 return 0; 1058 1059 mutex_lock(&mdev->cap_mask_mutex); 1060 1061 err = ib_query_port(ibdev, port, &attr); 1062 if (err) 1063 goto out; 1064 1065 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1066 ~props->clr_port_cap_mask; 1067 1068 err = mlx4_ib_SET_PORT(mdev, port, 1069 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1070 cap_mask); 1071 1072 out: 1073 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1074 return err; 1075 } 1076 1077 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1078 struct ib_udata *udata) 1079 { 1080 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1081 struct mlx4_ib_ucontext *context; 1082 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1083 struct mlx4_ib_alloc_ucontext_resp resp; 1084 int err; 1085 1086 if (!dev->ib_active) 1087 return ERR_PTR(-EAGAIN); 1088 1089 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1090 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1091 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1092 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1093 } else { 1094 resp.dev_caps = dev->dev->caps.userspace_caps; 1095 resp.qp_tab_size = dev->dev->caps.num_qps; 1096 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1097 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1098 resp.cqe_size = dev->dev->caps.cqe_size; 1099 } 1100 1101 context = kzalloc(sizeof(*context), GFP_KERNEL); 1102 if (!context) 1103 return ERR_PTR(-ENOMEM); 1104 1105 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1106 if (err) { 1107 kfree(context); 1108 return ERR_PTR(err); 1109 } 1110 1111 INIT_LIST_HEAD(&context->db_page_list); 1112 mutex_init(&context->db_page_mutex); 1113 1114 INIT_LIST_HEAD(&context->wqn_ranges_list); 1115 mutex_init(&context->wqn_ranges_mutex); 1116 1117 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1118 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1119 else 1120 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1121 1122 if (err) { 1123 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1124 kfree(context); 1125 return ERR_PTR(-EFAULT); 1126 } 1127 1128 return &context->ibucontext; 1129 } 1130 1131 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1132 { 1133 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1134 1135 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1136 kfree(context); 1137 1138 return 0; 1139 } 1140 1141 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1142 { 1143 /* vma_open is called when a new VMA is created on top of our VMA. 1144 * This is done through either mremap flow or split_vma (usually due 1145 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1146 * vma, as this VMA is strongly hardware related. Therefore we set the 1147 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1148 * calling us again and trying to do incorrect actions. We assume that 1149 * the original vma size is exactly a single page that there will be no 1150 * "splitting" operations on. 1151 */ 1152 area->vm_ops = NULL; 1153 } 1154 1155 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1156 { 1157 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1158 1159 /* It's guaranteed that all VMAs opened on a FD are closed before the 1160 * file itself is closed, therefore no sync is needed with the regular 1161 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1162 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1163 * The close operation is usually called under mm->mmap_sem except when 1164 * process is exiting. The exiting case is handled explicitly as part 1165 * of mlx4_ib_disassociate_ucontext. 1166 */ 1167 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1168 area->vm_private_data; 1169 1170 /* set the vma context pointer to null in the mlx4_ib driver's private 1171 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1172 */ 1173 mlx4_ib_vma_priv_data->vma = NULL; 1174 } 1175 1176 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1177 .open = mlx4_ib_vma_open, 1178 .close = mlx4_ib_vma_close 1179 }; 1180 1181 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1182 { 1183 int i; 1184 struct vm_area_struct *vma; 1185 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1186 1187 /* need to protect from a race on closing the vma as part of 1188 * mlx4_ib_vma_close(). 1189 */ 1190 for (i = 0; i < HW_BAR_COUNT; i++) { 1191 vma = context->hw_bar_info[i].vma; 1192 if (!vma) 1193 continue; 1194 1195 zap_vma_ptes(context->hw_bar_info[i].vma, 1196 context->hw_bar_info[i].vma->vm_start, PAGE_SIZE); 1197 1198 context->hw_bar_info[i].vma->vm_flags &= 1199 ~(VM_SHARED | VM_MAYSHARE); 1200 /* context going to be destroyed, should not access ops any more */ 1201 context->hw_bar_info[i].vma->vm_ops = NULL; 1202 } 1203 } 1204 1205 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1206 struct mlx4_ib_vma_private_data *vma_private_data) 1207 { 1208 vma_private_data->vma = vma; 1209 vma->vm_private_data = vma_private_data; 1210 vma->vm_ops = &mlx4_ib_vm_ops; 1211 } 1212 1213 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1214 { 1215 struct mlx4_ib_dev *dev = to_mdev(context->device); 1216 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1217 1218 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1219 return -EINVAL; 1220 1221 if (vma->vm_pgoff == 0) { 1222 /* We prevent double mmaping on same context */ 1223 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1224 return -EINVAL; 1225 1226 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1227 1228 if (io_remap_pfn_range(vma, vma->vm_start, 1229 to_mucontext(context)->uar.pfn, 1230 PAGE_SIZE, vma->vm_page_prot)) 1231 return -EAGAIN; 1232 1233 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1234 1235 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1236 /* We prevent double mmaping on same context */ 1237 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1238 return -EINVAL; 1239 1240 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1241 1242 if (io_remap_pfn_range(vma, vma->vm_start, 1243 to_mucontext(context)->uar.pfn + 1244 dev->dev->caps.num_uars, 1245 PAGE_SIZE, vma->vm_page_prot)) 1246 return -EAGAIN; 1247 1248 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1249 1250 } else if (vma->vm_pgoff == 3) { 1251 struct mlx4_clock_params params; 1252 int ret; 1253 1254 /* We prevent double mmaping on same context */ 1255 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1256 return -EINVAL; 1257 1258 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1259 1260 if (ret) 1261 return ret; 1262 1263 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1264 if (io_remap_pfn_range(vma, vma->vm_start, 1265 (pci_resource_start(dev->dev->persist->pdev, 1266 params.bar) + 1267 params.offset) 1268 >> PAGE_SHIFT, 1269 PAGE_SIZE, vma->vm_page_prot)) 1270 return -EAGAIN; 1271 1272 mlx4_ib_set_vma_data(vma, 1273 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1274 } else { 1275 return -EINVAL; 1276 } 1277 1278 return 0; 1279 } 1280 1281 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1282 struct ib_ucontext *context, 1283 struct ib_udata *udata) 1284 { 1285 struct mlx4_ib_pd *pd; 1286 int err; 1287 1288 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 1289 if (!pd) 1290 return ERR_PTR(-ENOMEM); 1291 1292 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1293 if (err) { 1294 kfree(pd); 1295 return ERR_PTR(err); 1296 } 1297 1298 if (context) 1299 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1300 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1301 kfree(pd); 1302 return ERR_PTR(-EFAULT); 1303 } 1304 return &pd->ibpd; 1305 } 1306 1307 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1308 { 1309 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1310 kfree(pd); 1311 1312 return 0; 1313 } 1314 1315 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1316 struct ib_ucontext *context, 1317 struct ib_udata *udata) 1318 { 1319 struct mlx4_ib_xrcd *xrcd; 1320 struct ib_cq_init_attr cq_attr = {}; 1321 int err; 1322 1323 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1324 return ERR_PTR(-ENOSYS); 1325 1326 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1327 if (!xrcd) 1328 return ERR_PTR(-ENOMEM); 1329 1330 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1331 if (err) 1332 goto err1; 1333 1334 xrcd->pd = ib_alloc_pd(ibdev, 0); 1335 if (IS_ERR(xrcd->pd)) { 1336 err = PTR_ERR(xrcd->pd); 1337 goto err2; 1338 } 1339 1340 cq_attr.cqe = 1; 1341 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1342 if (IS_ERR(xrcd->cq)) { 1343 err = PTR_ERR(xrcd->cq); 1344 goto err3; 1345 } 1346 1347 return &xrcd->ibxrcd; 1348 1349 err3: 1350 ib_dealloc_pd(xrcd->pd); 1351 err2: 1352 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1353 err1: 1354 kfree(xrcd); 1355 return ERR_PTR(err); 1356 } 1357 1358 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1359 { 1360 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1361 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1362 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1363 kfree(xrcd); 1364 1365 return 0; 1366 } 1367 1368 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1369 { 1370 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1371 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1372 struct mlx4_ib_gid_entry *ge; 1373 1374 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1375 if (!ge) 1376 return -ENOMEM; 1377 1378 ge->gid = *gid; 1379 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1380 ge->port = mqp->port; 1381 ge->added = 1; 1382 } 1383 1384 mutex_lock(&mqp->mutex); 1385 list_add_tail(&ge->list, &mqp->gid_list); 1386 mutex_unlock(&mqp->mutex); 1387 1388 return 0; 1389 } 1390 1391 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1392 struct mlx4_ib_counters *ctr_table) 1393 { 1394 struct counter_index *counter, *tmp_count; 1395 1396 mutex_lock(&ctr_table->mutex); 1397 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1398 list) { 1399 if (counter->allocated) 1400 mlx4_counter_free(ibdev->dev, counter->index); 1401 list_del(&counter->list); 1402 kfree(counter); 1403 } 1404 mutex_unlock(&ctr_table->mutex); 1405 } 1406 1407 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1408 union ib_gid *gid) 1409 { 1410 struct net_device *ndev; 1411 int ret = 0; 1412 1413 if (!mqp->port) 1414 return 0; 1415 1416 spin_lock_bh(&mdev->iboe.lock); 1417 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1418 if (ndev) 1419 dev_hold(ndev); 1420 spin_unlock_bh(&mdev->iboe.lock); 1421 1422 if (ndev) { 1423 ret = 1; 1424 dev_put(ndev); 1425 } 1426 1427 return ret; 1428 } 1429 1430 struct mlx4_ib_steering { 1431 struct list_head list; 1432 struct mlx4_flow_reg_id reg_id; 1433 union ib_gid gid; 1434 }; 1435 1436 #define LAST_ETH_FIELD vlan_tag 1437 #define LAST_IB_FIELD sl 1438 #define LAST_IPV4_FIELD dst_ip 1439 #define LAST_TCP_UDP_FIELD src_port 1440 1441 /* Field is the last supported field */ 1442 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1443 memchr_inv((void *)&filter.field +\ 1444 sizeof(filter.field), 0,\ 1445 sizeof(filter) -\ 1446 offsetof(typeof(filter), field) -\ 1447 sizeof(filter.field)) 1448 1449 static int parse_flow_attr(struct mlx4_dev *dev, 1450 u32 qp_num, 1451 union ib_flow_spec *ib_spec, 1452 struct _rule_hw *mlx4_spec) 1453 { 1454 enum mlx4_net_trans_rule_id type; 1455 1456 switch (ib_spec->type) { 1457 case IB_FLOW_SPEC_ETH: 1458 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1459 return -ENOTSUPP; 1460 1461 type = MLX4_NET_TRANS_RULE_ID_ETH; 1462 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1463 ETH_ALEN); 1464 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1465 ETH_ALEN); 1466 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1467 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1468 break; 1469 case IB_FLOW_SPEC_IB: 1470 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1471 return -ENOTSUPP; 1472 1473 type = MLX4_NET_TRANS_RULE_ID_IB; 1474 mlx4_spec->ib.l3_qpn = 1475 cpu_to_be32(qp_num); 1476 mlx4_spec->ib.qpn_mask = 1477 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1478 break; 1479 1480 1481 case IB_FLOW_SPEC_IPV4: 1482 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1483 return -ENOTSUPP; 1484 1485 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1486 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1487 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1488 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1489 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1490 break; 1491 1492 case IB_FLOW_SPEC_TCP: 1493 case IB_FLOW_SPEC_UDP: 1494 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1495 return -ENOTSUPP; 1496 1497 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1498 MLX4_NET_TRANS_RULE_ID_TCP : 1499 MLX4_NET_TRANS_RULE_ID_UDP; 1500 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1501 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1502 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1503 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1504 break; 1505 1506 default: 1507 return -EINVAL; 1508 } 1509 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1510 mlx4_hw_rule_sz(dev, type) < 0) 1511 return -EINVAL; 1512 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1513 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1514 return mlx4_hw_rule_sz(dev, type); 1515 } 1516 1517 struct default_rules { 1518 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1519 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1520 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1521 __u8 link_layer; 1522 }; 1523 static const struct default_rules default_table[] = { 1524 { 1525 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1526 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1527 .rules_create_list = {IB_FLOW_SPEC_IB}, 1528 .link_layer = IB_LINK_LAYER_INFINIBAND 1529 } 1530 }; 1531 1532 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1533 struct ib_flow_attr *flow_attr) 1534 { 1535 int i, j, k; 1536 void *ib_flow; 1537 const struct default_rules *pdefault_rules = default_table; 1538 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1539 1540 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1541 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1542 memset(&field_types, 0, sizeof(field_types)); 1543 1544 if (link_layer != pdefault_rules->link_layer) 1545 continue; 1546 1547 ib_flow = flow_attr + 1; 1548 /* we assume the specs are sorted */ 1549 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1550 j < flow_attr->num_of_specs; k++) { 1551 union ib_flow_spec *current_flow = 1552 (union ib_flow_spec *)ib_flow; 1553 1554 /* same layer but different type */ 1555 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1556 (pdefault_rules->mandatory_fields[k] & 1557 IB_FLOW_SPEC_LAYER_MASK)) && 1558 (current_flow->type != 1559 pdefault_rules->mandatory_fields[k])) 1560 goto out; 1561 1562 /* same layer, try match next one */ 1563 if (current_flow->type == 1564 pdefault_rules->mandatory_fields[k]) { 1565 j++; 1566 ib_flow += 1567 ((union ib_flow_spec *)ib_flow)->size; 1568 } 1569 } 1570 1571 ib_flow = flow_attr + 1; 1572 for (j = 0; j < flow_attr->num_of_specs; 1573 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1574 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1575 /* same layer and same type */ 1576 if (((union ib_flow_spec *)ib_flow)->type == 1577 pdefault_rules->mandatory_not_fields[k]) 1578 goto out; 1579 1580 return i; 1581 } 1582 out: 1583 return -1; 1584 } 1585 1586 static int __mlx4_ib_create_default_rules( 1587 struct mlx4_ib_dev *mdev, 1588 struct ib_qp *qp, 1589 const struct default_rules *pdefault_rules, 1590 struct _rule_hw *mlx4_spec) { 1591 int size = 0; 1592 int i; 1593 1594 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1595 int ret; 1596 union ib_flow_spec ib_spec; 1597 switch (pdefault_rules->rules_create_list[i]) { 1598 case 0: 1599 /* no rule */ 1600 continue; 1601 case IB_FLOW_SPEC_IB: 1602 ib_spec.type = IB_FLOW_SPEC_IB; 1603 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1604 1605 break; 1606 default: 1607 /* invalid rule */ 1608 return -EINVAL; 1609 } 1610 /* We must put empty rule, qpn is being ignored */ 1611 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1612 mlx4_spec); 1613 if (ret < 0) { 1614 pr_info("invalid parsing\n"); 1615 return -EINVAL; 1616 } 1617 1618 mlx4_spec = (void *)mlx4_spec + ret; 1619 size += ret; 1620 } 1621 return size; 1622 } 1623 1624 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1625 int domain, 1626 enum mlx4_net_trans_promisc_mode flow_type, 1627 u64 *reg_id) 1628 { 1629 int ret, i; 1630 int size = 0; 1631 void *ib_flow; 1632 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1633 struct mlx4_cmd_mailbox *mailbox; 1634 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1635 int default_flow; 1636 1637 static const u16 __mlx4_domain[] = { 1638 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1639 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1640 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1641 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1642 }; 1643 1644 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1645 pr_err("Invalid priority value %d\n", flow_attr->priority); 1646 return -EINVAL; 1647 } 1648 1649 if (domain >= IB_FLOW_DOMAIN_NUM) { 1650 pr_err("Invalid domain value %d\n", domain); 1651 return -EINVAL; 1652 } 1653 1654 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1655 return -EINVAL; 1656 1657 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1658 if (IS_ERR(mailbox)) 1659 return PTR_ERR(mailbox); 1660 ctrl = mailbox->buf; 1661 1662 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1663 flow_attr->priority); 1664 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1665 ctrl->port = flow_attr->port; 1666 ctrl->qpn = cpu_to_be32(qp->qp_num); 1667 1668 ib_flow = flow_attr + 1; 1669 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1670 /* Add default flows */ 1671 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1672 if (default_flow >= 0) { 1673 ret = __mlx4_ib_create_default_rules( 1674 mdev, qp, default_table + default_flow, 1675 mailbox->buf + size); 1676 if (ret < 0) { 1677 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1678 return -EINVAL; 1679 } 1680 size += ret; 1681 } 1682 for (i = 0; i < flow_attr->num_of_specs; i++) { 1683 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1684 mailbox->buf + size); 1685 if (ret < 0) { 1686 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1687 return -EINVAL; 1688 } 1689 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1690 size += ret; 1691 } 1692 1693 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1694 flow_attr->num_of_specs == 1) { 1695 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1696 enum ib_flow_spec_type header_spec = 1697 ((union ib_flow_spec *)(flow_attr + 1))->type; 1698 1699 if (header_spec == IB_FLOW_SPEC_ETH) 1700 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1701 } 1702 1703 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1704 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1705 MLX4_CMD_NATIVE); 1706 if (ret == -ENOMEM) 1707 pr_err("mcg table is full. Fail to register network rule.\n"); 1708 else if (ret == -ENXIO) 1709 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1710 else if (ret) 1711 pr_err("Invalid argument. Fail to register network rule.\n"); 1712 1713 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1714 return ret; 1715 } 1716 1717 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1718 { 1719 int err; 1720 err = mlx4_cmd(dev, reg_id, 0, 0, 1721 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1722 MLX4_CMD_NATIVE); 1723 if (err) 1724 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1725 reg_id); 1726 return err; 1727 } 1728 1729 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1730 u64 *reg_id) 1731 { 1732 void *ib_flow; 1733 union ib_flow_spec *ib_spec; 1734 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1735 int err = 0; 1736 1737 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1738 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1739 return 0; /* do nothing */ 1740 1741 ib_flow = flow_attr + 1; 1742 ib_spec = (union ib_flow_spec *)ib_flow; 1743 1744 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1745 return 0; /* do nothing */ 1746 1747 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1748 flow_attr->port, qp->qp_num, 1749 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1750 reg_id); 1751 return err; 1752 } 1753 1754 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1755 struct ib_flow_attr *flow_attr, 1756 enum mlx4_net_trans_promisc_mode *type) 1757 { 1758 int err = 0; 1759 1760 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1761 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1762 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1763 return -EOPNOTSUPP; 1764 } 1765 1766 if (flow_attr->num_of_specs == 0) { 1767 type[0] = MLX4_FS_MC_SNIFFER; 1768 type[1] = MLX4_FS_UC_SNIFFER; 1769 } else { 1770 union ib_flow_spec *ib_spec; 1771 1772 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1773 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1774 return -EINVAL; 1775 1776 /* if all is zero than MC and UC */ 1777 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1778 type[0] = MLX4_FS_MC_SNIFFER; 1779 type[1] = MLX4_FS_UC_SNIFFER; 1780 } else { 1781 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1782 ib_spec->eth.mask.dst_mac[1], 1783 ib_spec->eth.mask.dst_mac[2], 1784 ib_spec->eth.mask.dst_mac[3], 1785 ib_spec->eth.mask.dst_mac[4], 1786 ib_spec->eth.mask.dst_mac[5]}; 1787 1788 /* Above xor was only on MC bit, non empty mask is valid 1789 * only if this bit is set and rest are zero. 1790 */ 1791 if (!is_zero_ether_addr(&mac[0])) 1792 return -EINVAL; 1793 1794 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1795 type[0] = MLX4_FS_MC_SNIFFER; 1796 else 1797 type[0] = MLX4_FS_UC_SNIFFER; 1798 } 1799 } 1800 1801 return err; 1802 } 1803 1804 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1805 struct ib_flow_attr *flow_attr, 1806 int domain, struct ib_udata *udata) 1807 { 1808 int err = 0, i = 0, j = 0; 1809 struct mlx4_ib_flow *mflow; 1810 enum mlx4_net_trans_promisc_mode type[2]; 1811 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1812 int is_bonded = mlx4_is_bonded(dev); 1813 1814 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1815 return ERR_PTR(-EINVAL); 1816 1817 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1818 return ERR_PTR(-EOPNOTSUPP); 1819 1820 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1821 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1822 return ERR_PTR(-EOPNOTSUPP); 1823 1824 if (udata && 1825 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1826 return ERR_PTR(-EOPNOTSUPP); 1827 1828 memset(type, 0, sizeof(type)); 1829 1830 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1831 if (!mflow) { 1832 err = -ENOMEM; 1833 goto err_free; 1834 } 1835 1836 switch (flow_attr->type) { 1837 case IB_FLOW_ATTR_NORMAL: 1838 /* If dont trap flag (continue match) is set, under specific 1839 * condition traffic be replicated to given qp, 1840 * without stealing it 1841 */ 1842 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1843 err = mlx4_ib_add_dont_trap_rule(dev, 1844 flow_attr, 1845 type); 1846 if (err) 1847 goto err_free; 1848 } else { 1849 type[0] = MLX4_FS_REGULAR; 1850 } 1851 break; 1852 1853 case IB_FLOW_ATTR_ALL_DEFAULT: 1854 type[0] = MLX4_FS_ALL_DEFAULT; 1855 break; 1856 1857 case IB_FLOW_ATTR_MC_DEFAULT: 1858 type[0] = MLX4_FS_MC_DEFAULT; 1859 break; 1860 1861 case IB_FLOW_ATTR_SNIFFER: 1862 type[0] = MLX4_FS_MIRROR_RX_PORT; 1863 type[1] = MLX4_FS_MIRROR_SX_PORT; 1864 break; 1865 1866 default: 1867 err = -EINVAL; 1868 goto err_free; 1869 } 1870 1871 while (i < ARRAY_SIZE(type) && type[i]) { 1872 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1873 &mflow->reg_id[i].id); 1874 if (err) 1875 goto err_create_flow; 1876 if (is_bonded) { 1877 /* Application always sees one port so the mirror rule 1878 * must be on port #2 1879 */ 1880 flow_attr->port = 2; 1881 err = __mlx4_ib_create_flow(qp, flow_attr, 1882 domain, type[j], 1883 &mflow->reg_id[j].mirror); 1884 flow_attr->port = 1; 1885 if (err) 1886 goto err_create_flow; 1887 j++; 1888 } 1889 1890 i++; 1891 } 1892 1893 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1894 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1895 &mflow->reg_id[i].id); 1896 if (err) 1897 goto err_create_flow; 1898 1899 if (is_bonded) { 1900 flow_attr->port = 2; 1901 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1902 &mflow->reg_id[j].mirror); 1903 flow_attr->port = 1; 1904 if (err) 1905 goto err_create_flow; 1906 j++; 1907 } 1908 /* function to create mirror rule */ 1909 i++; 1910 } 1911 1912 return &mflow->ibflow; 1913 1914 err_create_flow: 1915 while (i) { 1916 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1917 mflow->reg_id[i].id); 1918 i--; 1919 } 1920 1921 while (j) { 1922 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1923 mflow->reg_id[j].mirror); 1924 j--; 1925 } 1926 err_free: 1927 kfree(mflow); 1928 return ERR_PTR(err); 1929 } 1930 1931 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1932 { 1933 int err, ret = 0; 1934 int i = 0; 1935 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1936 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1937 1938 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1939 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1940 if (err) 1941 ret = err; 1942 if (mflow->reg_id[i].mirror) { 1943 err = __mlx4_ib_destroy_flow(mdev->dev, 1944 mflow->reg_id[i].mirror); 1945 if (err) 1946 ret = err; 1947 } 1948 i++; 1949 } 1950 1951 kfree(mflow); 1952 return ret; 1953 } 1954 1955 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1956 { 1957 int err; 1958 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1959 struct mlx4_dev *dev = mdev->dev; 1960 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1961 struct mlx4_ib_steering *ib_steering = NULL; 1962 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1963 struct mlx4_flow_reg_id reg_id; 1964 1965 if (mdev->dev->caps.steering_mode == 1966 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1967 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1968 if (!ib_steering) 1969 return -ENOMEM; 1970 } 1971 1972 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1973 !!(mqp->flags & 1974 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1975 prot, ®_id.id); 1976 if (err) { 1977 pr_err("multicast attach op failed, err %d\n", err); 1978 goto err_malloc; 1979 } 1980 1981 reg_id.mirror = 0; 1982 if (mlx4_is_bonded(dev)) { 1983 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1984 (mqp->port == 1) ? 2 : 1, 1985 !!(mqp->flags & 1986 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1987 prot, ®_id.mirror); 1988 if (err) 1989 goto err_add; 1990 } 1991 1992 err = add_gid_entry(ibqp, gid); 1993 if (err) 1994 goto err_add; 1995 1996 if (ib_steering) { 1997 memcpy(ib_steering->gid.raw, gid->raw, 16); 1998 ib_steering->reg_id = reg_id; 1999 mutex_lock(&mqp->mutex); 2000 list_add(&ib_steering->list, &mqp->steering_rules); 2001 mutex_unlock(&mqp->mutex); 2002 } 2003 return 0; 2004 2005 err_add: 2006 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2007 prot, reg_id.id); 2008 if (reg_id.mirror) 2009 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2010 prot, reg_id.mirror); 2011 err_malloc: 2012 kfree(ib_steering); 2013 2014 return err; 2015 } 2016 2017 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2018 { 2019 struct mlx4_ib_gid_entry *ge; 2020 struct mlx4_ib_gid_entry *tmp; 2021 struct mlx4_ib_gid_entry *ret = NULL; 2022 2023 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2024 if (!memcmp(raw, ge->gid.raw, 16)) { 2025 ret = ge; 2026 break; 2027 } 2028 } 2029 2030 return ret; 2031 } 2032 2033 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2034 { 2035 int err; 2036 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2037 struct mlx4_dev *dev = mdev->dev; 2038 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2039 struct net_device *ndev; 2040 struct mlx4_ib_gid_entry *ge; 2041 struct mlx4_flow_reg_id reg_id = {0, 0}; 2042 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2043 2044 if (mdev->dev->caps.steering_mode == 2045 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2046 struct mlx4_ib_steering *ib_steering; 2047 2048 mutex_lock(&mqp->mutex); 2049 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2050 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2051 list_del(&ib_steering->list); 2052 break; 2053 } 2054 } 2055 mutex_unlock(&mqp->mutex); 2056 if (&ib_steering->list == &mqp->steering_rules) { 2057 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2058 return -EINVAL; 2059 } 2060 reg_id = ib_steering->reg_id; 2061 kfree(ib_steering); 2062 } 2063 2064 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2065 prot, reg_id.id); 2066 if (err) 2067 return err; 2068 2069 if (mlx4_is_bonded(dev)) { 2070 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2071 prot, reg_id.mirror); 2072 if (err) 2073 return err; 2074 } 2075 2076 mutex_lock(&mqp->mutex); 2077 ge = find_gid_entry(mqp, gid->raw); 2078 if (ge) { 2079 spin_lock_bh(&mdev->iboe.lock); 2080 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2081 if (ndev) 2082 dev_hold(ndev); 2083 spin_unlock_bh(&mdev->iboe.lock); 2084 if (ndev) 2085 dev_put(ndev); 2086 list_del(&ge->list); 2087 kfree(ge); 2088 } else 2089 pr_warn("could not find mgid entry\n"); 2090 2091 mutex_unlock(&mqp->mutex); 2092 2093 return 0; 2094 } 2095 2096 static int init_node_data(struct mlx4_ib_dev *dev) 2097 { 2098 struct ib_smp *in_mad = NULL; 2099 struct ib_smp *out_mad = NULL; 2100 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2101 int err = -ENOMEM; 2102 2103 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2104 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2105 if (!in_mad || !out_mad) 2106 goto out; 2107 2108 init_query_mad(in_mad); 2109 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2110 if (mlx4_is_master(dev->dev)) 2111 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2112 2113 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2114 if (err) 2115 goto out; 2116 2117 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2118 2119 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2120 2121 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2122 if (err) 2123 goto out; 2124 2125 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2126 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2127 2128 out: 2129 kfree(in_mad); 2130 kfree(out_mad); 2131 return err; 2132 } 2133 2134 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2135 char *buf) 2136 { 2137 struct mlx4_ib_dev *dev = 2138 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2139 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2140 } 2141 2142 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2143 char *buf) 2144 { 2145 struct mlx4_ib_dev *dev = 2146 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2147 return sprintf(buf, "%x\n", dev->dev->rev_id); 2148 } 2149 2150 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2151 char *buf) 2152 { 2153 struct mlx4_ib_dev *dev = 2154 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2155 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2156 dev->dev->board_id); 2157 } 2158 2159 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2160 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2161 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2162 2163 static struct device_attribute *mlx4_class_attributes[] = { 2164 &dev_attr_hw_rev, 2165 &dev_attr_hca_type, 2166 &dev_attr_board_id 2167 }; 2168 2169 struct diag_counter { 2170 const char *name; 2171 u32 offset; 2172 }; 2173 2174 #define DIAG_COUNTER(_name, _offset) \ 2175 { .name = #_name, .offset = _offset } 2176 2177 static const struct diag_counter diag_basic[] = { 2178 DIAG_COUNTER(rq_num_lle, 0x00), 2179 DIAG_COUNTER(sq_num_lle, 0x04), 2180 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2181 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2182 DIAG_COUNTER(rq_num_lpe, 0x18), 2183 DIAG_COUNTER(sq_num_lpe, 0x1C), 2184 DIAG_COUNTER(rq_num_wrfe, 0x20), 2185 DIAG_COUNTER(sq_num_wrfe, 0x24), 2186 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2187 DIAG_COUNTER(sq_num_bre, 0x34), 2188 DIAG_COUNTER(sq_num_rire, 0x44), 2189 DIAG_COUNTER(rq_num_rire, 0x48), 2190 DIAG_COUNTER(sq_num_rae, 0x4C), 2191 DIAG_COUNTER(rq_num_rae, 0x50), 2192 DIAG_COUNTER(sq_num_roe, 0x54), 2193 DIAG_COUNTER(sq_num_tree, 0x5C), 2194 DIAG_COUNTER(sq_num_rree, 0x64), 2195 DIAG_COUNTER(rq_num_rnr, 0x68), 2196 DIAG_COUNTER(sq_num_rnr, 0x6C), 2197 DIAG_COUNTER(rq_num_oos, 0x100), 2198 DIAG_COUNTER(sq_num_oos, 0x104), 2199 }; 2200 2201 static const struct diag_counter diag_ext[] = { 2202 DIAG_COUNTER(rq_num_dup, 0x130), 2203 DIAG_COUNTER(sq_num_to, 0x134), 2204 }; 2205 2206 static const struct diag_counter diag_device_only[] = { 2207 DIAG_COUNTER(num_cqovf, 0x1A0), 2208 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2209 }; 2210 2211 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2212 u8 port_num) 2213 { 2214 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2215 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2216 2217 if (!diag[!!port_num].name) 2218 return NULL; 2219 2220 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2221 diag[!!port_num].num_counters, 2222 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2223 } 2224 2225 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2226 struct rdma_hw_stats *stats, 2227 u8 port, int index) 2228 { 2229 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2230 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2231 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2232 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2233 int ret; 2234 int i; 2235 2236 ret = mlx4_query_diag_counters(dev->dev, 2237 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2238 diag[!!port].offset, hw_value, 2239 diag[!!port].num_counters, port); 2240 2241 if (ret) 2242 return ret; 2243 2244 for (i = 0; i < diag[!!port].num_counters; i++) 2245 stats->value[i] = hw_value[i]; 2246 2247 return diag[!!port].num_counters; 2248 } 2249 2250 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2251 const char ***name, 2252 u32 **offset, 2253 u32 *num, 2254 bool port) 2255 { 2256 u32 num_counters; 2257 2258 num_counters = ARRAY_SIZE(diag_basic); 2259 2260 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2261 num_counters += ARRAY_SIZE(diag_ext); 2262 2263 if (!port) 2264 num_counters += ARRAY_SIZE(diag_device_only); 2265 2266 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2267 if (!*name) 2268 return -ENOMEM; 2269 2270 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2271 if (!*offset) 2272 goto err_name; 2273 2274 *num = num_counters; 2275 2276 return 0; 2277 2278 err_name: 2279 kfree(*name); 2280 return -ENOMEM; 2281 } 2282 2283 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2284 const char **name, 2285 u32 *offset, 2286 bool port) 2287 { 2288 int i; 2289 int j; 2290 2291 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2292 name[i] = diag_basic[i].name; 2293 offset[i] = diag_basic[i].offset; 2294 } 2295 2296 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2297 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2298 name[j] = diag_ext[i].name; 2299 offset[j] = diag_ext[i].offset; 2300 } 2301 } 2302 2303 if (!port) { 2304 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2305 name[j] = diag_device_only[i].name; 2306 offset[j] = diag_device_only[i].offset; 2307 } 2308 } 2309 } 2310 2311 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2312 { 2313 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2314 int i; 2315 int ret; 2316 bool per_port = !!(ibdev->dev->caps.flags2 & 2317 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2318 2319 if (mlx4_is_slave(ibdev->dev)) 2320 return 0; 2321 2322 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2323 /* i == 1 means we are building port counters */ 2324 if (i && !per_port) 2325 continue; 2326 2327 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2328 &diag[i].offset, 2329 &diag[i].num_counters, i); 2330 if (ret) 2331 goto err_alloc; 2332 2333 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2334 diag[i].offset, i); 2335 } 2336 2337 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2338 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2339 2340 return 0; 2341 2342 err_alloc: 2343 if (i) { 2344 kfree(diag[i - 1].name); 2345 kfree(diag[i - 1].offset); 2346 } 2347 2348 return ret; 2349 } 2350 2351 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2352 { 2353 int i; 2354 2355 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2356 kfree(ibdev->diag_counters[i].offset); 2357 kfree(ibdev->diag_counters[i].name); 2358 } 2359 } 2360 2361 #define MLX4_IB_INVALID_MAC ((u64)-1) 2362 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2363 struct net_device *dev, 2364 int port) 2365 { 2366 u64 new_smac = 0; 2367 u64 release_mac = MLX4_IB_INVALID_MAC; 2368 struct mlx4_ib_qp *qp; 2369 2370 read_lock(&dev_base_lock); 2371 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2372 read_unlock(&dev_base_lock); 2373 2374 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2375 2376 /* no need for update QP1 and mac registration in non-SRIOV */ 2377 if (!mlx4_is_mfunc(ibdev->dev)) 2378 return; 2379 2380 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2381 qp = ibdev->qp1_proxy[port - 1]; 2382 if (qp) { 2383 int new_smac_index; 2384 u64 old_smac; 2385 struct mlx4_update_qp_params update_params; 2386 2387 mutex_lock(&qp->mutex); 2388 old_smac = qp->pri.smac; 2389 if (new_smac == old_smac) 2390 goto unlock; 2391 2392 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2393 2394 if (new_smac_index < 0) 2395 goto unlock; 2396 2397 update_params.smac_index = new_smac_index; 2398 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2399 &update_params)) { 2400 release_mac = new_smac; 2401 goto unlock; 2402 } 2403 /* if old port was zero, no mac was yet registered for this QP */ 2404 if (qp->pri.smac_port) 2405 release_mac = old_smac; 2406 qp->pri.smac = new_smac; 2407 qp->pri.smac_port = port; 2408 qp->pri.smac_index = new_smac_index; 2409 } 2410 2411 unlock: 2412 if (release_mac != MLX4_IB_INVALID_MAC) 2413 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2414 if (qp) 2415 mutex_unlock(&qp->mutex); 2416 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2417 } 2418 2419 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2420 struct net_device *dev, 2421 unsigned long event) 2422 2423 { 2424 struct mlx4_ib_iboe *iboe; 2425 int update_qps_port = -1; 2426 int port; 2427 2428 ASSERT_RTNL(); 2429 2430 iboe = &ibdev->iboe; 2431 2432 spin_lock_bh(&iboe->lock); 2433 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2434 2435 iboe->netdevs[port - 1] = 2436 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2437 2438 if (dev == iboe->netdevs[port - 1] && 2439 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2440 event == NETDEV_UP || event == NETDEV_CHANGE)) 2441 update_qps_port = port; 2442 2443 } 2444 spin_unlock_bh(&iboe->lock); 2445 2446 if (update_qps_port > 0) 2447 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2448 } 2449 2450 static int mlx4_ib_netdev_event(struct notifier_block *this, 2451 unsigned long event, void *ptr) 2452 { 2453 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2454 struct mlx4_ib_dev *ibdev; 2455 2456 if (!net_eq(dev_net(dev), &init_net)) 2457 return NOTIFY_DONE; 2458 2459 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2460 mlx4_ib_scan_netdevs(ibdev, dev, event); 2461 2462 return NOTIFY_DONE; 2463 } 2464 2465 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2466 { 2467 int port; 2468 int slave; 2469 int i; 2470 2471 if (mlx4_is_master(ibdev->dev)) { 2472 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2473 ++slave) { 2474 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2475 for (i = 0; 2476 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2477 ++i) { 2478 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2479 /* master has the identity virt2phys pkey mapping */ 2480 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2481 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2482 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2483 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2484 } 2485 } 2486 } 2487 /* initialize pkey cache */ 2488 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2489 for (i = 0; 2490 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2491 ++i) 2492 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2493 (i) ? 0 : 0xFFFF; 2494 } 2495 } 2496 } 2497 2498 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2499 { 2500 int i, j, eq = 0, total_eqs = 0; 2501 2502 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2503 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2504 if (!ibdev->eq_table) 2505 return; 2506 2507 for (i = 1; i <= dev->caps.num_ports; i++) { 2508 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2509 j++, total_eqs++) { 2510 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2511 continue; 2512 ibdev->eq_table[eq] = total_eqs; 2513 if (!mlx4_assign_eq(dev, i, 2514 &ibdev->eq_table[eq])) 2515 eq++; 2516 else 2517 ibdev->eq_table[eq] = -1; 2518 } 2519 } 2520 2521 for (i = eq; i < dev->caps.num_comp_vectors; 2522 ibdev->eq_table[i++] = -1) 2523 ; 2524 2525 /* Advertise the new number of EQs to clients */ 2526 ibdev->ib_dev.num_comp_vectors = eq; 2527 } 2528 2529 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2530 { 2531 int i; 2532 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2533 2534 /* no eqs were allocated */ 2535 if (!ibdev->eq_table) 2536 return; 2537 2538 /* Reset the advertised EQ number */ 2539 ibdev->ib_dev.num_comp_vectors = 0; 2540 2541 for (i = 0; i < total_eqs; i++) 2542 mlx4_release_eq(dev, ibdev->eq_table[i]); 2543 2544 kfree(ibdev->eq_table); 2545 ibdev->eq_table = NULL; 2546 } 2547 2548 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2549 struct ib_port_immutable *immutable) 2550 { 2551 struct ib_port_attr attr; 2552 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2553 int err; 2554 2555 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2556 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2557 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2558 } else { 2559 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2560 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2561 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2562 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2563 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2564 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2565 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2566 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2567 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2568 } 2569 2570 err = ib_query_port(ibdev, port_num, &attr); 2571 if (err) 2572 return err; 2573 2574 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2575 immutable->gid_tbl_len = attr.gid_tbl_len; 2576 2577 return 0; 2578 } 2579 2580 static void get_fw_ver_str(struct ib_device *device, char *str) 2581 { 2582 struct mlx4_ib_dev *dev = 2583 container_of(device, struct mlx4_ib_dev, ib_dev); 2584 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2585 (int) (dev->dev->caps.fw_ver >> 32), 2586 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2587 (int) dev->dev->caps.fw_ver & 0xffff); 2588 } 2589 2590 static void *mlx4_ib_add(struct mlx4_dev *dev) 2591 { 2592 struct mlx4_ib_dev *ibdev; 2593 int num_ports = 0; 2594 int i, j; 2595 int err; 2596 struct mlx4_ib_iboe *iboe; 2597 int ib_num_ports = 0; 2598 int num_req_counters; 2599 int allocated; 2600 u32 counter_index; 2601 struct counter_index *new_counter_index = NULL; 2602 2603 pr_info_once("%s", mlx4_ib_version); 2604 2605 num_ports = 0; 2606 mlx4_foreach_ib_transport_port(i, dev) 2607 num_ports++; 2608 2609 /* No point in registering a device with no ports... */ 2610 if (num_ports == 0) 2611 return NULL; 2612 2613 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2614 if (!ibdev) { 2615 dev_err(&dev->persist->pdev->dev, 2616 "Device struct alloc failed\n"); 2617 return NULL; 2618 } 2619 2620 iboe = &ibdev->iboe; 2621 2622 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2623 goto err_dealloc; 2624 2625 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2626 goto err_pd; 2627 2628 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2629 PAGE_SIZE); 2630 if (!ibdev->uar_map) 2631 goto err_uar; 2632 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2633 2634 ibdev->dev = dev; 2635 ibdev->bond_next_port = 0; 2636 2637 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2638 ibdev->ib_dev.owner = THIS_MODULE; 2639 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2640 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2641 ibdev->num_ports = num_ports; 2642 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2643 1 : ibdev->num_ports; 2644 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2645 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2646 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2647 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2648 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2649 2650 if (dev->caps.userspace_caps) 2651 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2652 else 2653 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2654 2655 ibdev->ib_dev.uverbs_cmd_mask = 2656 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2657 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2658 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2659 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2660 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2661 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2662 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2663 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2664 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2665 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2666 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2667 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2668 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2669 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2670 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2671 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2672 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2673 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2674 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2675 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2676 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2677 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2678 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2679 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2680 2681 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2682 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2683 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2684 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2685 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2686 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2687 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2688 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2689 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2690 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2691 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2692 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2693 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2694 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2695 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2696 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2697 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2698 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2699 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2700 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2701 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2702 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2703 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2704 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2705 ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq; 2706 ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq; 2707 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2708 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2709 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2710 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2711 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2712 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2713 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2714 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2715 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2716 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2717 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2718 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2719 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2720 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2721 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2722 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2723 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2724 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2725 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2726 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2727 2728 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2729 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2730 2731 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2732 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2733 IB_LINK_LAYER_ETHERNET) || 2734 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2735 IB_LINK_LAYER_ETHERNET))) { 2736 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2737 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2738 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2739 ibdev->ib_dev.create_rwq_ind_table = 2740 mlx4_ib_create_rwq_ind_table; 2741 ibdev->ib_dev.destroy_rwq_ind_table = 2742 mlx4_ib_destroy_rwq_ind_table; 2743 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2744 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2745 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2746 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2747 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2748 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2749 } 2750 2751 if (!mlx4_is_slave(ibdev->dev)) { 2752 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2753 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2754 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2755 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2756 } 2757 2758 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2759 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2760 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2761 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2762 2763 ibdev->ib_dev.uverbs_cmd_mask |= 2764 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2765 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2766 } 2767 2768 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2769 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2770 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2771 ibdev->ib_dev.uverbs_cmd_mask |= 2772 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2773 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2774 } 2775 2776 if (check_flow_steering_support(dev)) { 2777 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2778 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2779 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2780 2781 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2782 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2783 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2784 } 2785 2786 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2787 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2788 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2789 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2790 2791 mlx4_ib_alloc_eqs(dev, ibdev); 2792 2793 spin_lock_init(&iboe->lock); 2794 2795 if (init_node_data(ibdev)) 2796 goto err_map; 2797 mlx4_init_sl2vl_tbl(ibdev); 2798 2799 for (i = 0; i < ibdev->num_ports; ++i) { 2800 mutex_init(&ibdev->counters_table[i].mutex); 2801 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2802 } 2803 2804 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2805 for (i = 0; i < num_req_counters; ++i) { 2806 mutex_init(&ibdev->qp1_proxy_lock[i]); 2807 allocated = 0; 2808 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2809 IB_LINK_LAYER_ETHERNET) { 2810 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2811 MLX4_RES_USAGE_DRIVER); 2812 /* if failed to allocate a new counter, use default */ 2813 if (err) 2814 counter_index = 2815 mlx4_get_default_counter_index(dev, 2816 i + 1); 2817 else 2818 allocated = 1; 2819 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2820 counter_index = mlx4_get_default_counter_index(dev, 2821 i + 1); 2822 } 2823 new_counter_index = kmalloc(sizeof(*new_counter_index), 2824 GFP_KERNEL); 2825 if (!new_counter_index) { 2826 if (allocated) 2827 mlx4_counter_free(ibdev->dev, counter_index); 2828 goto err_counter; 2829 } 2830 new_counter_index->index = counter_index; 2831 new_counter_index->allocated = allocated; 2832 list_add_tail(&new_counter_index->list, 2833 &ibdev->counters_table[i].counters_list); 2834 ibdev->counters_table[i].default_counter = counter_index; 2835 pr_info("counter index %d for port %d allocated %d\n", 2836 counter_index, i + 1, allocated); 2837 } 2838 if (mlx4_is_bonded(dev)) 2839 for (i = 1; i < ibdev->num_ports ; ++i) { 2840 new_counter_index = 2841 kmalloc(sizeof(struct counter_index), 2842 GFP_KERNEL); 2843 if (!new_counter_index) 2844 goto err_counter; 2845 new_counter_index->index = counter_index; 2846 new_counter_index->allocated = 0; 2847 list_add_tail(&new_counter_index->list, 2848 &ibdev->counters_table[i].counters_list); 2849 ibdev->counters_table[i].default_counter = 2850 counter_index; 2851 } 2852 2853 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2854 ib_num_ports++; 2855 2856 spin_lock_init(&ibdev->sm_lock); 2857 mutex_init(&ibdev->cap_mask_mutex); 2858 INIT_LIST_HEAD(&ibdev->qp_list); 2859 spin_lock_init(&ibdev->reset_flow_resource_lock); 2860 2861 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2862 ib_num_ports) { 2863 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2864 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2865 MLX4_IB_UC_STEER_QPN_ALIGN, 2866 &ibdev->steer_qpn_base, 0, 2867 MLX4_RES_USAGE_DRIVER); 2868 if (err) 2869 goto err_counter; 2870 2871 ibdev->ib_uc_qpns_bitmap = 2872 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2873 sizeof(long), 2874 GFP_KERNEL); 2875 if (!ibdev->ib_uc_qpns_bitmap) 2876 goto err_steer_qp_release; 2877 2878 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2879 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2880 ibdev->steer_qpn_count); 2881 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2882 dev, ibdev->steer_qpn_base, 2883 ibdev->steer_qpn_base + 2884 ibdev->steer_qpn_count - 1); 2885 if (err) 2886 goto err_steer_free_bitmap; 2887 } else { 2888 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2889 ibdev->steer_qpn_count); 2890 } 2891 } 2892 2893 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2894 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2895 2896 if (mlx4_ib_alloc_diag_counters(ibdev)) 2897 goto err_steer_free_bitmap; 2898 2899 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4; 2900 if (ib_register_device(&ibdev->ib_dev, NULL)) 2901 goto err_diag_counters; 2902 2903 if (mlx4_ib_mad_init(ibdev)) 2904 goto err_reg; 2905 2906 if (mlx4_ib_init_sriov(ibdev)) 2907 goto err_mad; 2908 2909 if (!iboe->nb.notifier_call) { 2910 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2911 err = register_netdevice_notifier(&iboe->nb); 2912 if (err) { 2913 iboe->nb.notifier_call = NULL; 2914 goto err_notif; 2915 } 2916 } 2917 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2918 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2919 if (err) 2920 goto err_notif; 2921 } 2922 2923 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2924 if (device_create_file(&ibdev->ib_dev.dev, 2925 mlx4_class_attributes[j])) 2926 goto err_notif; 2927 } 2928 2929 ibdev->ib_active = true; 2930 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2931 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2932 &ibdev->ib_dev); 2933 2934 if (mlx4_is_mfunc(ibdev->dev)) 2935 init_pkeys(ibdev); 2936 2937 /* create paravirt contexts for any VFs which are active */ 2938 if (mlx4_is_master(ibdev->dev)) { 2939 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2940 if (j == mlx4_master_func_num(ibdev->dev)) 2941 continue; 2942 if (mlx4_is_slave_active(ibdev->dev, j)) 2943 do_slave_init(ibdev, j, 1); 2944 } 2945 } 2946 return ibdev; 2947 2948 err_notif: 2949 if (ibdev->iboe.nb.notifier_call) { 2950 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2951 pr_warn("failure unregistering notifier\n"); 2952 ibdev->iboe.nb.notifier_call = NULL; 2953 } 2954 flush_workqueue(wq); 2955 2956 mlx4_ib_close_sriov(ibdev); 2957 2958 err_mad: 2959 mlx4_ib_mad_cleanup(ibdev); 2960 2961 err_reg: 2962 ib_unregister_device(&ibdev->ib_dev); 2963 2964 err_diag_counters: 2965 mlx4_ib_diag_cleanup(ibdev); 2966 2967 err_steer_free_bitmap: 2968 kfree(ibdev->ib_uc_qpns_bitmap); 2969 2970 err_steer_qp_release: 2971 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2972 ibdev->steer_qpn_count); 2973 err_counter: 2974 for (i = 0; i < ibdev->num_ports; ++i) 2975 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2976 2977 err_map: 2978 mlx4_ib_free_eqs(dev, ibdev); 2979 iounmap(ibdev->uar_map); 2980 2981 err_uar: 2982 mlx4_uar_free(dev, &ibdev->priv_uar); 2983 2984 err_pd: 2985 mlx4_pd_free(dev, ibdev->priv_pdn); 2986 2987 err_dealloc: 2988 ib_dealloc_device(&ibdev->ib_dev); 2989 2990 return NULL; 2991 } 2992 2993 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2994 { 2995 int offset; 2996 2997 WARN_ON(!dev->ib_uc_qpns_bitmap); 2998 2999 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 3000 dev->steer_qpn_count, 3001 get_count_order(count)); 3002 if (offset < 0) 3003 return offset; 3004 3005 *qpn = dev->steer_qpn_base + offset; 3006 return 0; 3007 } 3008 3009 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 3010 { 3011 if (!qpn || 3012 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 3013 return; 3014 3015 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 3016 qpn, dev->steer_qpn_base)) 3017 /* not supposed to be here */ 3018 return; 3019 3020 bitmap_release_region(dev->ib_uc_qpns_bitmap, 3021 qpn - dev->steer_qpn_base, 3022 get_count_order(count)); 3023 } 3024 3025 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 3026 int is_attach) 3027 { 3028 int err; 3029 size_t flow_size; 3030 struct ib_flow_attr *flow = NULL; 3031 struct ib_flow_spec_ib *ib_spec; 3032 3033 if (is_attach) { 3034 flow_size = sizeof(struct ib_flow_attr) + 3035 sizeof(struct ib_flow_spec_ib); 3036 flow = kzalloc(flow_size, GFP_KERNEL); 3037 if (!flow) 3038 return -ENOMEM; 3039 flow->port = mqp->port; 3040 flow->num_of_specs = 1; 3041 flow->size = flow_size; 3042 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3043 ib_spec->type = IB_FLOW_SPEC_IB; 3044 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3045 /* Add an empty rule for IB L2 */ 3046 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3047 3048 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3049 IB_FLOW_DOMAIN_NIC, 3050 MLX4_FS_REGULAR, 3051 &mqp->reg_id); 3052 } else { 3053 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3054 } 3055 kfree(flow); 3056 return err; 3057 } 3058 3059 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3060 { 3061 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3062 int p; 3063 int i; 3064 3065 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3066 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3067 ibdev->ib_active = false; 3068 flush_workqueue(wq); 3069 3070 mlx4_ib_close_sriov(ibdev); 3071 mlx4_ib_mad_cleanup(ibdev); 3072 ib_unregister_device(&ibdev->ib_dev); 3073 mlx4_ib_diag_cleanup(ibdev); 3074 if (ibdev->iboe.nb.notifier_call) { 3075 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3076 pr_warn("failure unregistering notifier\n"); 3077 ibdev->iboe.nb.notifier_call = NULL; 3078 } 3079 3080 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3081 ibdev->steer_qpn_count); 3082 kfree(ibdev->ib_uc_qpns_bitmap); 3083 3084 iounmap(ibdev->uar_map); 3085 for (p = 0; p < ibdev->num_ports; ++p) 3086 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3087 3088 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3089 mlx4_CLOSE_PORT(dev, p); 3090 3091 mlx4_ib_free_eqs(dev, ibdev); 3092 3093 mlx4_uar_free(dev, &ibdev->priv_uar); 3094 mlx4_pd_free(dev, ibdev->priv_pdn); 3095 ib_dealloc_device(&ibdev->ib_dev); 3096 } 3097 3098 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3099 { 3100 struct mlx4_ib_demux_work **dm = NULL; 3101 struct mlx4_dev *dev = ibdev->dev; 3102 int i; 3103 unsigned long flags; 3104 struct mlx4_active_ports actv_ports; 3105 unsigned int ports; 3106 unsigned int first_port; 3107 3108 if (!mlx4_is_master(dev)) 3109 return; 3110 3111 actv_ports = mlx4_get_active_ports(dev, slave); 3112 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3113 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3114 3115 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3116 if (!dm) 3117 return; 3118 3119 for (i = 0; i < ports; i++) { 3120 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3121 if (!dm[i]) { 3122 while (--i >= 0) 3123 kfree(dm[i]); 3124 goto out; 3125 } 3126 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3127 dm[i]->port = first_port + i + 1; 3128 dm[i]->slave = slave; 3129 dm[i]->do_init = do_init; 3130 dm[i]->dev = ibdev; 3131 } 3132 /* initialize or tear down tunnel QPs for the slave */ 3133 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3134 if (!ibdev->sriov.is_going_down) { 3135 for (i = 0; i < ports; i++) 3136 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3137 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3138 } else { 3139 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3140 for (i = 0; i < ports; i++) 3141 kfree(dm[i]); 3142 } 3143 out: 3144 kfree(dm); 3145 return; 3146 } 3147 3148 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3149 { 3150 struct mlx4_ib_qp *mqp; 3151 unsigned long flags_qp; 3152 unsigned long flags_cq; 3153 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3154 struct list_head cq_notify_list; 3155 struct mlx4_cq *mcq; 3156 unsigned long flags; 3157 3158 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3159 INIT_LIST_HEAD(&cq_notify_list); 3160 3161 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3162 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3163 3164 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3165 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3166 if (mqp->sq.tail != mqp->sq.head) { 3167 send_mcq = to_mcq(mqp->ibqp.send_cq); 3168 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3169 if (send_mcq->mcq.comp && 3170 mqp->ibqp.send_cq->comp_handler) { 3171 if (!send_mcq->mcq.reset_notify_added) { 3172 send_mcq->mcq.reset_notify_added = 1; 3173 list_add_tail(&send_mcq->mcq.reset_notify, 3174 &cq_notify_list); 3175 } 3176 } 3177 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3178 } 3179 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3180 /* Now, handle the QP's receive queue */ 3181 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3182 /* no handling is needed for SRQ */ 3183 if (!mqp->ibqp.srq) { 3184 if (mqp->rq.tail != mqp->rq.head) { 3185 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3186 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3187 if (recv_mcq->mcq.comp && 3188 mqp->ibqp.recv_cq->comp_handler) { 3189 if (!recv_mcq->mcq.reset_notify_added) { 3190 recv_mcq->mcq.reset_notify_added = 1; 3191 list_add_tail(&recv_mcq->mcq.reset_notify, 3192 &cq_notify_list); 3193 } 3194 } 3195 spin_unlock_irqrestore(&recv_mcq->lock, 3196 flags_cq); 3197 } 3198 } 3199 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3200 } 3201 3202 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3203 mcq->comp(mcq); 3204 } 3205 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3206 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3207 } 3208 3209 static void handle_bonded_port_state_event(struct work_struct *work) 3210 { 3211 struct ib_event_work *ew = 3212 container_of(work, struct ib_event_work, work); 3213 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3214 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3215 int i; 3216 struct ib_event ibev; 3217 3218 kfree(ew); 3219 spin_lock_bh(&ibdev->iboe.lock); 3220 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3221 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3222 enum ib_port_state curr_port_state; 3223 3224 if (!curr_netdev) 3225 continue; 3226 3227 curr_port_state = 3228 (netif_running(curr_netdev) && 3229 netif_carrier_ok(curr_netdev)) ? 3230 IB_PORT_ACTIVE : IB_PORT_DOWN; 3231 3232 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3233 curr_port_state : IB_PORT_ACTIVE; 3234 } 3235 spin_unlock_bh(&ibdev->iboe.lock); 3236 3237 ibev.device = &ibdev->ib_dev; 3238 ibev.element.port_num = 1; 3239 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3240 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3241 3242 ib_dispatch_event(&ibev); 3243 } 3244 3245 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3246 { 3247 u64 sl2vl; 3248 int err; 3249 3250 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3251 if (err) { 3252 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3253 port, err); 3254 sl2vl = 0; 3255 } 3256 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3257 } 3258 3259 static void ib_sl2vl_update_work(struct work_struct *work) 3260 { 3261 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3262 struct mlx4_ib_dev *mdev = ew->ib_dev; 3263 int port = ew->port; 3264 3265 mlx4_ib_sl2vl_update(mdev, port); 3266 3267 kfree(ew); 3268 } 3269 3270 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3271 int port) 3272 { 3273 struct ib_event_work *ew; 3274 3275 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3276 if (ew) { 3277 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3278 ew->port = port; 3279 ew->ib_dev = ibdev; 3280 queue_work(wq, &ew->work); 3281 } 3282 } 3283 3284 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3285 enum mlx4_dev_event event, unsigned long param) 3286 { 3287 struct ib_event ibev; 3288 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3289 struct mlx4_eqe *eqe = NULL; 3290 struct ib_event_work *ew; 3291 int p = 0; 3292 3293 if (mlx4_is_bonded(dev) && 3294 ((event == MLX4_DEV_EVENT_PORT_UP) || 3295 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3296 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3297 if (!ew) 3298 return; 3299 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3300 ew->ib_dev = ibdev; 3301 queue_work(wq, &ew->work); 3302 return; 3303 } 3304 3305 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3306 eqe = (struct mlx4_eqe *)param; 3307 else 3308 p = (int) param; 3309 3310 switch (event) { 3311 case MLX4_DEV_EVENT_PORT_UP: 3312 if (p > ibdev->num_ports) 3313 return; 3314 if (!mlx4_is_slave(dev) && 3315 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3316 IB_LINK_LAYER_INFINIBAND) { 3317 if (mlx4_is_master(dev)) 3318 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3319 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3320 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3321 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3322 } 3323 ibev.event = IB_EVENT_PORT_ACTIVE; 3324 break; 3325 3326 case MLX4_DEV_EVENT_PORT_DOWN: 3327 if (p > ibdev->num_ports) 3328 return; 3329 ibev.event = IB_EVENT_PORT_ERR; 3330 break; 3331 3332 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3333 ibdev->ib_active = false; 3334 ibev.event = IB_EVENT_DEVICE_FATAL; 3335 mlx4_ib_handle_catas_error(ibdev); 3336 break; 3337 3338 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3339 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3340 if (!ew) 3341 break; 3342 3343 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3344 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3345 ew->ib_dev = ibdev; 3346 /* need to queue only for port owner, which uses GEN_EQE */ 3347 if (mlx4_is_master(dev)) 3348 queue_work(wq, &ew->work); 3349 else 3350 handle_port_mgmt_change_event(&ew->work); 3351 return; 3352 3353 case MLX4_DEV_EVENT_SLAVE_INIT: 3354 /* here, p is the slave id */ 3355 do_slave_init(ibdev, p, 1); 3356 if (mlx4_is_master(dev)) { 3357 int i; 3358 3359 for (i = 1; i <= ibdev->num_ports; i++) { 3360 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3361 == IB_LINK_LAYER_INFINIBAND) 3362 mlx4_ib_slave_alias_guid_event(ibdev, 3363 p, i, 3364 1); 3365 } 3366 } 3367 return; 3368 3369 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3370 if (mlx4_is_master(dev)) { 3371 int i; 3372 3373 for (i = 1; i <= ibdev->num_ports; i++) { 3374 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3375 == IB_LINK_LAYER_INFINIBAND) 3376 mlx4_ib_slave_alias_guid_event(ibdev, 3377 p, i, 3378 0); 3379 } 3380 } 3381 /* here, p is the slave id */ 3382 do_slave_init(ibdev, p, 0); 3383 return; 3384 3385 default: 3386 return; 3387 } 3388 3389 ibev.device = ibdev_ptr; 3390 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3391 3392 ib_dispatch_event(&ibev); 3393 } 3394 3395 static struct mlx4_interface mlx4_ib_interface = { 3396 .add = mlx4_ib_add, 3397 .remove = mlx4_ib_remove, 3398 .event = mlx4_ib_event, 3399 .protocol = MLX4_PROT_IB_IPV6, 3400 .flags = MLX4_INTFF_BONDING 3401 }; 3402 3403 static int __init mlx4_ib_init(void) 3404 { 3405 int err; 3406 3407 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3408 if (!wq) 3409 return -ENOMEM; 3410 3411 err = mlx4_ib_mcg_init(); 3412 if (err) 3413 goto clean_wq; 3414 3415 err = mlx4_register_interface(&mlx4_ib_interface); 3416 if (err) 3417 goto clean_mcg; 3418 3419 return 0; 3420 3421 clean_mcg: 3422 mlx4_ib_mcg_destroy(); 3423 3424 clean_wq: 3425 destroy_workqueue(wq); 3426 return err; 3427 } 3428 3429 static void __exit mlx4_ib_cleanup(void) 3430 { 3431 mlx4_unregister_interface(&mlx4_ib_interface); 3432 mlx4_ib_mcg_destroy(); 3433 destroy_workqueue(wq); 3434 } 3435 3436 module_init(mlx4_ib_init); 3437 module_exit(mlx4_ib_cleanup); 3438