1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 #include "hns_roce_debugfs.h" 39 40 #define PCI_REVISION_ID_HIP08 0x21 41 #define PCI_REVISION_ID_HIP09 0x30 42 43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 44 45 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 46 47 #define BA_BYTE_LEN 8 48 49 #define HNS_ROCE_MIN_CQE_NUM 0x40 50 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 51 52 #define HNS_ROCE_MAX_IRQ_NUM 128 53 54 #define HNS_ROCE_SGE_IN_WQE 2 55 #define HNS_ROCE_SGE_SHIFT 4 56 57 #define EQ_ENABLE 1 58 #define EQ_DISABLE 0 59 60 #define HNS_ROCE_CEQ 0 61 #define HNS_ROCE_AEQ 1 62 63 #define HNS_ROCE_CEQE_SIZE 0x4 64 #define HNS_ROCE_AEQE_SIZE 0x10 65 66 #define HNS_ROCE_V3_EQE_SIZE 0x40 67 68 #define HNS_ROCE_V2_CQE_SIZE 32 69 #define HNS_ROCE_V3_CQE_SIZE 64 70 71 #define HNS_ROCE_V2_QPC_SZ 256 72 #define HNS_ROCE_V3_QPC_SZ 512 73 74 #define HNS_ROCE_MAX_PORTS 6 75 #define HNS_ROCE_GID_SIZE 16 76 #define HNS_ROCE_SGE_SIZE 16 77 #define HNS_ROCE_DWQE_SIZE 65536 78 79 #define HNS_ROCE_HOP_NUM_0 0xff 80 81 #define MR_TYPE_MR 0x00 82 #define MR_TYPE_FRMR 0x01 83 #define MR_TYPE_DMA 0x03 84 85 #define HNS_ROCE_FRMR_MAX_PA 512 86 87 #define PKEY_ID 0xffff 88 #define NODE_DESC_SIZE 64 89 #define DB_REG_OFFSET 0x1000 90 91 /* Configure to HW for PAGE_SIZE larger than 4KB */ 92 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 93 94 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 95 #define SRQ_DB_REG 0x230 96 97 #define HNS_ROCE_QP_BANK_NUM 8 98 #define HNS_ROCE_CQ_BANK_NUM 4 99 100 #define CQ_BANKID_SHIFT 2 101 #define CQ_BANKID_MASK GENMASK(1, 0) 102 103 enum { 104 SERV_TYPE_RC, 105 SERV_TYPE_UC, 106 SERV_TYPE_RD, 107 SERV_TYPE_UD, 108 SERV_TYPE_XRC = 5, 109 }; 110 111 enum hns_roce_event { 112 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 113 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 114 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 115 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 116 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 117 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 118 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 119 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 120 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 121 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 122 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 123 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 124 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 125 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 126 /* 0x10 and 0x11 is unused in currently application case */ 127 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 128 HNS_ROCE_EVENT_TYPE_MB = 0x13, 129 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 130 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 131 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 132 }; 133 134 enum { 135 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 136 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 137 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 138 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 139 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 140 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 141 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 142 HNS_ROCE_CAP_FLAG_MW = BIT(7), 143 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 144 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 145 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 146 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 147 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 148 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 149 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 150 HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22), 151 }; 152 153 #define HNS_ROCE_DB_TYPE_COUNT 2 154 #define HNS_ROCE_DB_UNIT_SIZE 4 155 156 enum { 157 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 158 }; 159 160 enum hns_roce_reset_stage { 161 HNS_ROCE_STATE_NON_RST, 162 HNS_ROCE_STATE_RST_BEF_DOWN, 163 HNS_ROCE_STATE_RST_DOWN, 164 HNS_ROCE_STATE_RST_UNINIT, 165 HNS_ROCE_STATE_RST_INIT, 166 HNS_ROCE_STATE_RST_INITED, 167 }; 168 169 enum hns_roce_instance_state { 170 HNS_ROCE_STATE_NON_INIT, 171 HNS_ROCE_STATE_INIT, 172 HNS_ROCE_STATE_INITED, 173 HNS_ROCE_STATE_UNINIT, 174 }; 175 176 enum { 177 HNS_ROCE_RST_DIRECT_RETURN = 0, 178 }; 179 180 #define HNS_ROCE_CMD_SUCCESS 1 181 182 /* The minimum page size is 4K for hardware */ 183 #define HNS_HW_PAGE_SHIFT 12 184 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 185 186 struct hns_roce_uar { 187 u64 pfn; 188 unsigned long index; 189 unsigned long logic_idx; 190 }; 191 192 enum hns_roce_mmap_type { 193 HNS_ROCE_MMAP_TYPE_DB = 1, 194 HNS_ROCE_MMAP_TYPE_DWQE, 195 }; 196 197 struct hns_user_mmap_entry { 198 struct rdma_user_mmap_entry rdma_entry; 199 enum hns_roce_mmap_type mmap_type; 200 u64 address; 201 }; 202 203 struct hns_roce_ucontext { 204 struct ib_ucontext ibucontext; 205 struct hns_roce_uar uar; 206 struct list_head page_list; 207 struct mutex page_mutex; 208 struct hns_user_mmap_entry *db_mmap_entry; 209 u32 config; 210 }; 211 212 struct hns_roce_pd { 213 struct ib_pd ibpd; 214 unsigned long pdn; 215 }; 216 217 struct hns_roce_xrcd { 218 struct ib_xrcd ibxrcd; 219 u32 xrcdn; 220 }; 221 222 struct hns_roce_bitmap { 223 /* Bitmap Traversal last a bit which is 1 */ 224 unsigned long last; 225 unsigned long top; 226 unsigned long max; 227 unsigned long reserved_top; 228 unsigned long mask; 229 spinlock_t lock; 230 unsigned long *table; 231 }; 232 233 struct hns_roce_ida { 234 struct ida ida; 235 u32 min; /* Lowest ID to allocate. */ 236 u32 max; /* Highest ID to allocate. */ 237 }; 238 239 /* For Hardware Entry Memory */ 240 struct hns_roce_hem_table { 241 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 242 u32 type; 243 /* HEM array elment num */ 244 unsigned long num_hem; 245 /* Single obj size */ 246 unsigned long obj_size; 247 unsigned long table_chunk_size; 248 struct mutex mutex; 249 struct hns_roce_hem **hem; 250 u64 **bt_l1; 251 dma_addr_t *bt_l1_dma_addr; 252 u64 **bt_l0; 253 dma_addr_t *bt_l0_dma_addr; 254 }; 255 256 struct hns_roce_buf_region { 257 u32 offset; /* page offset */ 258 u32 count; /* page count */ 259 int hopnum; /* addressing hop num */ 260 }; 261 262 #define HNS_ROCE_MAX_BT_REGION 3 263 #define HNS_ROCE_MAX_BT_LEVEL 3 264 struct hns_roce_hem_list { 265 struct list_head root_bt; 266 /* link all bt dma mem by hop config */ 267 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 268 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 269 dma_addr_t root_ba; /* pointer to the root ba table */ 270 }; 271 272 struct hns_roce_buf_attr { 273 struct { 274 size_t size; /* region size */ 275 int hopnum; /* multi-hop addressing hop num */ 276 } region[HNS_ROCE_MAX_BT_REGION]; 277 unsigned int region_count; /* valid region count */ 278 unsigned int page_shift; /* buffer page shift */ 279 unsigned int user_access; /* umem access flag */ 280 bool mtt_only; /* only alloc buffer-required MTT memory */ 281 }; 282 283 struct hns_roce_hem_cfg { 284 dma_addr_t root_ba; /* root BA table's address */ 285 bool is_direct; /* addressing without BA table */ 286 unsigned int ba_pg_shift; /* BA table page shift */ 287 unsigned int buf_pg_shift; /* buffer page shift */ 288 unsigned int buf_pg_count; /* buffer page count */ 289 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 290 unsigned int region_count; 291 }; 292 293 /* memory translate region */ 294 struct hns_roce_mtr { 295 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 296 struct ib_umem *umem; /* user space buffer */ 297 struct hns_roce_buf *kmem; /* kernel space buffer */ 298 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 299 }; 300 301 struct hns_roce_mw { 302 struct ib_mw ibmw; 303 u32 pdn; 304 u32 rkey; 305 int enabled; /* MW's active status */ 306 u32 pbl_hop_num; 307 u32 pbl_ba_pg_sz; 308 u32 pbl_buf_pg_sz; 309 }; 310 311 struct hns_roce_mr { 312 struct ib_mr ibmr; 313 u64 iova; /* MR's virtual original addr */ 314 u64 size; /* Address range of MR */ 315 u32 key; /* Key of MR */ 316 u32 pd; /* PD num of MR */ 317 u32 access; /* Access permission of MR */ 318 int enabled; /* MR's active status */ 319 int type; /* MR's register type */ 320 u32 pbl_hop_num; /* multi-hop number */ 321 struct hns_roce_mtr pbl_mtr; 322 u32 npages; 323 dma_addr_t *page_list; 324 }; 325 326 struct hns_roce_mr_table { 327 struct hns_roce_ida mtpt_ida; 328 struct hns_roce_hem_table mtpt_table; 329 }; 330 331 struct hns_roce_wq { 332 u64 *wrid; /* Work request ID */ 333 spinlock_t lock; 334 u32 wqe_cnt; /* WQE num */ 335 u32 max_gs; 336 u32 rsv_sge; 337 u32 offset; 338 u32 wqe_shift; /* WQE size */ 339 u32 head; 340 u32 tail; 341 void __iomem *db_reg; 342 u32 ext_sge_cnt; 343 }; 344 345 struct hns_roce_sge { 346 unsigned int sge_cnt; /* SGE num */ 347 u32 offset; 348 u32 sge_shift; /* SGE size */ 349 }; 350 351 struct hns_roce_buf_list { 352 void *buf; 353 dma_addr_t map; 354 }; 355 356 /* 357 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 358 * dma address range. 359 * 360 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 361 * 362 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 363 * the allocated size is smaller than the required size. 364 */ 365 enum { 366 HNS_ROCE_BUF_DIRECT = BIT(0), 367 HNS_ROCE_BUF_NOSLEEP = BIT(1), 368 HNS_ROCE_BUF_NOFAIL = BIT(2), 369 }; 370 371 struct hns_roce_buf { 372 struct hns_roce_buf_list *trunk_list; 373 u32 ntrunks; 374 u32 npages; 375 unsigned int trunk_shift; 376 unsigned int page_shift; 377 }; 378 379 struct hns_roce_db_pgdir { 380 struct list_head list; 381 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 382 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 383 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 384 u32 *page; 385 dma_addr_t db_dma; 386 }; 387 388 struct hns_roce_user_db_page { 389 struct list_head list; 390 struct ib_umem *umem; 391 unsigned long user_virt; 392 refcount_t refcount; 393 }; 394 395 struct hns_roce_db { 396 u32 *db_record; 397 union { 398 struct hns_roce_db_pgdir *pgdir; 399 struct hns_roce_user_db_page *user_page; 400 } u; 401 dma_addr_t dma; 402 void *virt_addr; 403 unsigned long index; 404 unsigned long order; 405 }; 406 407 struct hns_roce_cq { 408 struct ib_cq ib_cq; 409 struct hns_roce_mtr mtr; 410 struct hns_roce_db db; 411 u32 flags; 412 spinlock_t lock; 413 u32 cq_depth; 414 u32 cons_index; 415 u32 *set_ci_db; 416 void __iomem *db_reg; 417 int arm_sn; 418 int cqe_size; 419 unsigned long cqn; 420 u32 vector; 421 refcount_t refcount; 422 struct completion free; 423 struct list_head sq_list; /* all qps on this send cq */ 424 struct list_head rq_list; /* all qps on this recv cq */ 425 int is_armed; /* cq is armed */ 426 struct list_head node; /* all armed cqs are on a list */ 427 }; 428 429 struct hns_roce_idx_que { 430 struct hns_roce_mtr mtr; 431 u32 entry_shift; 432 unsigned long *bitmap; 433 u32 head; 434 u32 tail; 435 }; 436 437 struct hns_roce_srq { 438 struct ib_srq ibsrq; 439 unsigned long srqn; 440 u32 wqe_cnt; 441 int max_gs; 442 u32 rsv_sge; 443 u32 wqe_shift; 444 u32 cqn; 445 u32 xrcdn; 446 void __iomem *db_reg; 447 448 refcount_t refcount; 449 struct completion free; 450 451 struct hns_roce_mtr buf_mtr; 452 453 u64 *wrid; 454 struct hns_roce_idx_que idx_que; 455 spinlock_t lock; 456 struct mutex mutex; 457 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 458 struct hns_roce_db rdb; 459 u32 cap_flags; 460 }; 461 462 struct hns_roce_uar_table { 463 struct hns_roce_bitmap bitmap; 464 }; 465 466 struct hns_roce_bank { 467 struct ida ida; 468 u32 inuse; /* Number of IDs allocated */ 469 u32 min; /* Lowest ID to allocate. */ 470 u32 max; /* Highest ID to allocate. */ 471 u32 next; /* Next ID to allocate. */ 472 }; 473 474 struct hns_roce_idx_table { 475 u32 *spare_idx; 476 u32 head; 477 u32 tail; 478 }; 479 480 struct hns_roce_qp_table { 481 struct hns_roce_hem_table qp_table; 482 struct hns_roce_hem_table irrl_table; 483 struct hns_roce_hem_table trrl_table; 484 struct hns_roce_hem_table sccc_table; 485 struct mutex scc_mutex; 486 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 487 struct mutex bank_mutex; 488 struct hns_roce_idx_table idx_table; 489 }; 490 491 struct hns_roce_cq_table { 492 struct xarray array; 493 struct hns_roce_hem_table table; 494 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 495 struct mutex bank_mutex; 496 }; 497 498 struct hns_roce_srq_table { 499 struct hns_roce_ida srq_ida; 500 struct xarray xa; 501 struct hns_roce_hem_table table; 502 }; 503 504 struct hns_roce_av { 505 u8 port; 506 u8 gid_index; 507 u8 stat_rate; 508 u8 hop_limit; 509 u32 flowlabel; 510 u16 udp_sport; 511 u8 sl; 512 u8 tclass; 513 u8 dgid[HNS_ROCE_GID_SIZE]; 514 u8 mac[ETH_ALEN]; 515 u16 vlan_id; 516 u8 vlan_en; 517 }; 518 519 struct hns_roce_ah { 520 struct ib_ah ibah; 521 struct hns_roce_av av; 522 }; 523 524 struct hns_roce_cmd_context { 525 struct completion done; 526 int result; 527 int next; 528 u64 out_param; 529 u16 token; 530 u16 busy; 531 }; 532 533 enum hns_roce_cmdq_state { 534 HNS_ROCE_CMDQ_STATE_NORMAL, 535 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 536 }; 537 538 struct hns_roce_cmdq { 539 struct dma_pool *pool; 540 struct semaphore poll_sem; 541 /* 542 * Event mode: cmd register mutex protection, 543 * ensure to not exceed max_cmds and user use limit region 544 */ 545 struct semaphore event_sem; 546 int max_cmds; 547 spinlock_t context_lock; 548 int free_head; 549 struct hns_roce_cmd_context *context; 550 /* 551 * Process whether use event mode, init default non-zero 552 * After the event queue of cmd event ready, 553 * can switch into event mode 554 * close device, switch into poll mode(non event mode) 555 */ 556 u8 use_events; 557 enum hns_roce_cmdq_state state; 558 }; 559 560 struct hns_roce_cmd_mailbox { 561 void *buf; 562 dma_addr_t dma; 563 }; 564 565 struct hns_roce_mbox_msg { 566 u64 in_param; 567 u64 out_param; 568 u8 cmd; 569 u32 tag; 570 u16 token; 571 u8 event_en; 572 }; 573 574 struct hns_roce_dev; 575 576 enum { 577 HNS_ROCE_FLUSH_FLAG = 0, 578 }; 579 580 struct hns_roce_work { 581 struct hns_roce_dev *hr_dev; 582 struct work_struct work; 583 int event_type; 584 int sub_type; 585 u32 queue_num; 586 }; 587 588 struct hns_roce_qp { 589 struct ib_qp ibqp; 590 struct hns_roce_wq rq; 591 struct hns_roce_db rdb; 592 struct hns_roce_db sdb; 593 unsigned long en_flags; 594 enum ib_sig_type sq_signal_bits; 595 struct hns_roce_wq sq; 596 597 struct hns_roce_mtr mtr; 598 599 u32 buff_size; 600 struct mutex mutex; 601 u8 port; 602 u8 phy_port; 603 u8 sl; 604 u8 resp_depth; 605 u8 state; 606 u32 atomic_rd_en; 607 u32 qkey; 608 void (*event)(struct hns_roce_qp *qp, 609 enum hns_roce_event event_type); 610 unsigned long qpn; 611 612 u32 xrcdn; 613 614 refcount_t refcount; 615 struct completion free; 616 617 struct hns_roce_sge sge; 618 u32 next_sge; 619 enum ib_mtu path_mtu; 620 u32 max_inline_data; 621 u8 free_mr_en; 622 623 /* 0: flush needed, 1: unneeded */ 624 unsigned long flush_flag; 625 struct hns_roce_work flush_work; 626 struct list_head node; /* all qps are on a list */ 627 struct list_head rq_node; /* all recv qps are on a list */ 628 struct list_head sq_node; /* all send qps are on a list */ 629 struct hns_user_mmap_entry *dwqe_mmap_entry; 630 u32 config; 631 }; 632 633 struct hns_roce_ib_iboe { 634 spinlock_t lock; 635 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 636 struct notifier_block nb; 637 u8 phy_port[HNS_ROCE_MAX_PORTS]; 638 }; 639 640 struct hns_roce_ceqe { 641 __le32 comp; 642 __le32 rsv[15]; 643 }; 644 645 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 646 647 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 648 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 649 650 struct hns_roce_aeqe { 651 __le32 asyn; 652 union { 653 struct { 654 __le32 num; 655 u32 rsv0; 656 u32 rsv1; 657 } queue_event; 658 659 struct { 660 __le64 out_param; 661 __le16 token; 662 u8 status; 663 u8 rsv0; 664 } __packed cmd; 665 } event; 666 __le32 rsv[12]; 667 }; 668 669 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 670 671 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 672 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 673 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 674 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 675 676 struct hns_roce_eq { 677 struct hns_roce_dev *hr_dev; 678 void __iomem *db_reg; 679 680 int type_flag; /* Aeq:1 ceq:0 */ 681 int eqn; 682 u32 entries; 683 int eqe_size; 684 int irq; 685 u32 cons_index; 686 int over_ignore; 687 int coalesce; 688 int arm_st; 689 int hop_num; 690 struct hns_roce_mtr mtr; 691 u16 eq_max_cnt; 692 u32 eq_period; 693 int shift; 694 int event_type; 695 int sub_type; 696 }; 697 698 struct hns_roce_eq_table { 699 struct hns_roce_eq *eq; 700 }; 701 702 enum cong_type { 703 CONG_TYPE_DCQCN, 704 CONG_TYPE_LDCP, 705 CONG_TYPE_HC3, 706 CONG_TYPE_DIP, 707 }; 708 709 struct hns_roce_caps { 710 u64 fw_ver; 711 u8 num_ports; 712 int gid_table_len[HNS_ROCE_MAX_PORTS]; 713 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 714 int local_ca_ack_delay; 715 int num_uars; 716 u32 phy_num_uars; 717 u32 max_sq_sg; 718 u32 max_sq_inline; 719 u32 max_rq_sg; 720 u32 rsv0; 721 u32 num_qps; 722 u32 reserved_qps; 723 u32 num_srqs; 724 u32 max_wqes; 725 u32 max_srq_wrs; 726 u32 max_srq_sges; 727 u32 max_sq_desc_sz; 728 u32 max_rq_desc_sz; 729 u32 rsv2; 730 int max_qp_init_rdma; 731 int max_qp_dest_rdma; 732 u32 num_cqs; 733 u32 max_cqes; 734 u32 min_cqes; 735 u32 min_wqes; 736 u32 reserved_cqs; 737 u32 reserved_srqs; 738 int num_aeq_vectors; 739 int num_comp_vectors; 740 int num_other_vectors; 741 u32 num_mtpts; 742 u32 rsv1; 743 u32 num_srqwqe_segs; 744 u32 num_idx_segs; 745 int reserved_mrws; 746 int reserved_uars; 747 int num_pds; 748 int reserved_pds; 749 u32 num_xrcds; 750 u32 reserved_xrcds; 751 u32 mtt_entry_sz; 752 u32 cqe_sz; 753 u32 page_size_cap; 754 u32 reserved_lkey; 755 int mtpt_entry_sz; 756 int qpc_sz; 757 int irrl_entry_sz; 758 int trrl_entry_sz; 759 int cqc_entry_sz; 760 int sccc_sz; 761 int qpc_timer_entry_sz; 762 int cqc_timer_entry_sz; 763 int srqc_entry_sz; 764 int idx_entry_sz; 765 u32 pbl_ba_pg_sz; 766 u32 pbl_buf_pg_sz; 767 u32 pbl_hop_num; 768 int aeqe_depth; 769 int ceqe_depth; 770 u32 aeqe_size; 771 u32 ceqe_size; 772 enum ib_mtu max_mtu; 773 u32 qpc_bt_num; 774 u32 qpc_timer_bt_num; 775 u32 srqc_bt_num; 776 u32 cqc_bt_num; 777 u32 cqc_timer_bt_num; 778 u32 mpt_bt_num; 779 u32 eqc_bt_num; 780 u32 smac_bt_num; 781 u32 sgid_bt_num; 782 u32 sccc_bt_num; 783 u32 gmv_bt_num; 784 u32 qpc_ba_pg_sz; 785 u32 qpc_buf_pg_sz; 786 u32 qpc_hop_num; 787 u32 srqc_ba_pg_sz; 788 u32 srqc_buf_pg_sz; 789 u32 srqc_hop_num; 790 u32 cqc_ba_pg_sz; 791 u32 cqc_buf_pg_sz; 792 u32 cqc_hop_num; 793 u32 mpt_ba_pg_sz; 794 u32 mpt_buf_pg_sz; 795 u32 mpt_hop_num; 796 u32 mtt_ba_pg_sz; 797 u32 mtt_buf_pg_sz; 798 u32 mtt_hop_num; 799 u32 wqe_sq_hop_num; 800 u32 wqe_sge_hop_num; 801 u32 wqe_rq_hop_num; 802 u32 sccc_ba_pg_sz; 803 u32 sccc_buf_pg_sz; 804 u32 sccc_hop_num; 805 u32 qpc_timer_ba_pg_sz; 806 u32 qpc_timer_buf_pg_sz; 807 u32 qpc_timer_hop_num; 808 u32 cqc_timer_ba_pg_sz; 809 u32 cqc_timer_buf_pg_sz; 810 u32 cqc_timer_hop_num; 811 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 812 u32 cqe_buf_pg_sz; 813 u32 cqe_hop_num; 814 u32 srqwqe_ba_pg_sz; 815 u32 srqwqe_buf_pg_sz; 816 u32 srqwqe_hop_num; 817 u32 idx_ba_pg_sz; 818 u32 idx_buf_pg_sz; 819 u32 idx_hop_num; 820 u32 eqe_ba_pg_sz; 821 u32 eqe_buf_pg_sz; 822 u32 eqe_hop_num; 823 u32 gmv_entry_num; 824 u32 gmv_entry_sz; 825 u32 gmv_ba_pg_sz; 826 u32 gmv_buf_pg_sz; 827 u32 gmv_hop_num; 828 u32 sl_num; 829 u32 llm_buf_pg_sz; 830 u32 chunk_sz; /* chunk size in non multihop mode */ 831 u64 flags; 832 u16 default_ceq_max_cnt; 833 u16 default_ceq_period; 834 u16 default_aeq_max_cnt; 835 u16 default_aeq_period; 836 u16 default_aeq_arm_st; 837 u16 default_ceq_arm_st; 838 enum cong_type cong_type; 839 }; 840 841 enum hns_roce_device_state { 842 HNS_ROCE_DEVICE_STATE_INITED, 843 HNS_ROCE_DEVICE_STATE_RST_DOWN, 844 HNS_ROCE_DEVICE_STATE_UNINIT, 845 }; 846 847 enum hns_roce_hw_pkt_stat_index { 848 HNS_ROCE_HW_RX_RC_PKT_CNT, 849 HNS_ROCE_HW_RX_UC_PKT_CNT, 850 HNS_ROCE_HW_RX_UD_PKT_CNT, 851 HNS_ROCE_HW_RX_XRC_PKT_CNT, 852 HNS_ROCE_HW_RX_PKT_CNT, 853 HNS_ROCE_HW_RX_ERR_PKT_CNT, 854 HNS_ROCE_HW_RX_CNP_PKT_CNT, 855 HNS_ROCE_HW_TX_RC_PKT_CNT, 856 HNS_ROCE_HW_TX_UC_PKT_CNT, 857 HNS_ROCE_HW_TX_UD_PKT_CNT, 858 HNS_ROCE_HW_TX_XRC_PKT_CNT, 859 HNS_ROCE_HW_TX_PKT_CNT, 860 HNS_ROCE_HW_TX_ERR_PKT_CNT, 861 HNS_ROCE_HW_TX_CNP_PKT_CNT, 862 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 863 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 864 HNS_ROCE_HW_ECN_DB_CNT, 865 HNS_ROCE_HW_RX_BUF_CNT, 866 HNS_ROCE_HW_TRP_RX_SOF_CNT, 867 HNS_ROCE_HW_CQ_CQE_CNT, 868 HNS_ROCE_HW_CQ_POE_CNT, 869 HNS_ROCE_HW_CQ_NOTIFY_CNT, 870 HNS_ROCE_HW_CNT_TOTAL 871 }; 872 873 enum hns_roce_sw_dfx_stat_index { 874 HNS_ROCE_DFX_AEQE_CNT, 875 HNS_ROCE_DFX_CEQE_CNT, 876 HNS_ROCE_DFX_CMDS_CNT, 877 HNS_ROCE_DFX_CMDS_ERR_CNT, 878 HNS_ROCE_DFX_MBX_POSTED_CNT, 879 HNS_ROCE_DFX_MBX_POLLED_CNT, 880 HNS_ROCE_DFX_MBX_EVENT_CNT, 881 HNS_ROCE_DFX_QP_CREATE_ERR_CNT, 882 HNS_ROCE_DFX_QP_MODIFY_ERR_CNT, 883 HNS_ROCE_DFX_CQ_CREATE_ERR_CNT, 884 HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT, 885 HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT, 886 HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT, 887 HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT, 888 HNS_ROCE_DFX_MR_REG_ERR_CNT, 889 HNS_ROCE_DFX_MR_REREG_ERR_CNT, 890 HNS_ROCE_DFX_AH_CREATE_ERR_CNT, 891 HNS_ROCE_DFX_MMAP_ERR_CNT, 892 HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT, 893 HNS_ROCE_DFX_CNT_TOTAL 894 }; 895 896 struct hns_roce_hw { 897 int (*cmq_init)(struct hns_roce_dev *hr_dev); 898 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 899 int (*hw_profile)(struct hns_roce_dev *hr_dev); 900 int (*hw_init)(struct hns_roce_dev *hr_dev); 901 void (*hw_exit)(struct hns_roce_dev *hr_dev); 902 int (*post_mbox)(struct hns_roce_dev *hr_dev, 903 struct hns_roce_mbox_msg *mbox_msg); 904 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 905 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 906 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 907 const union ib_gid *gid, const struct ib_gid_attr *attr); 908 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 909 const u8 *addr); 910 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 911 struct hns_roce_mr *mr); 912 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 913 struct hns_roce_mr *mr, int flags, 914 void *mb_buf); 915 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 916 struct hns_roce_mr *mr); 917 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 918 void (*write_cqc)(struct hns_roce_dev *hr_dev, 919 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 920 dma_addr_t dma_handle); 921 int (*set_hem)(struct hns_roce_dev *hr_dev, 922 struct hns_roce_hem_table *table, int obj, u32 step_idx); 923 int (*clear_hem)(struct hns_roce_dev *hr_dev, 924 struct hns_roce_hem_table *table, int obj, 925 u32 step_idx); 926 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 927 int attr_mask, enum ib_qp_state cur_state, 928 enum ib_qp_state new_state, struct ib_udata *udata); 929 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 930 struct hns_roce_qp *hr_qp); 931 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 932 int (*init_eq)(struct hns_roce_dev *hr_dev); 933 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 934 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 935 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 936 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 937 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 938 int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer); 939 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 940 u64 *stats, u32 port, int *hw_counters); 941 const struct ib_device_ops *hns_roce_dev_ops; 942 const struct ib_device_ops *hns_roce_dev_srq_ops; 943 }; 944 945 struct hns_roce_dev { 946 struct ib_device ib_dev; 947 struct pci_dev *pci_dev; 948 struct device *dev; 949 struct hns_roce_uar priv_uar; 950 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 951 spinlock_t sm_lock; 952 bool active; 953 bool is_reset; 954 bool dis_db; 955 unsigned long reset_cnt; 956 struct hns_roce_ib_iboe iboe; 957 enum hns_roce_device_state state; 958 struct list_head qp_list; /* list of all qps on this dev */ 959 spinlock_t qp_list_lock; /* protect qp_list */ 960 struct list_head dip_list; /* list of all dest ips on this dev */ 961 spinlock_t dip_list_lock; /* protect dip_list */ 962 963 struct list_head pgdir_list; 964 struct mutex pgdir_mutex; 965 int irq[HNS_ROCE_MAX_IRQ_NUM]; 966 u8 __iomem *reg_base; 967 void __iomem *mem_base; 968 struct hns_roce_caps caps; 969 struct xarray qp_table_xa; 970 971 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 972 u64 sys_image_guid; 973 u32 vendor_id; 974 u32 vendor_part_id; 975 u32 hw_rev; 976 void __iomem *priv_addr; 977 978 struct hns_roce_cmdq cmd; 979 struct hns_roce_ida pd_ida; 980 struct hns_roce_ida xrcd_ida; 981 struct hns_roce_ida uar_ida; 982 struct hns_roce_mr_table mr_table; 983 struct hns_roce_cq_table cq_table; 984 struct hns_roce_srq_table srq_table; 985 struct hns_roce_qp_table qp_table; 986 struct hns_roce_eq_table eq_table; 987 struct hns_roce_hem_table qpc_timer_table; 988 struct hns_roce_hem_table cqc_timer_table; 989 /* GMV is the memory area that the driver allocates for the hardware 990 * to store SGID, SMAC and VLAN information. 991 */ 992 struct hns_roce_hem_table gmv_table; 993 994 int cmd_mod; 995 int loop_idc; 996 u32 sdb_offset; 997 u32 odb_offset; 998 const struct hns_roce_hw *hw; 999 void *priv; 1000 struct workqueue_struct *irq_workq; 1001 struct work_struct ecc_work; 1002 u32 func_num; 1003 u32 is_vf; 1004 u32 cong_algo_tmpl_id; 1005 u64 dwqe_page; 1006 struct hns_roce_dev_debugfs dbgfs; 1007 atomic64_t *dfx_cnt; 1008 }; 1009 1010 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1011 { 1012 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1013 } 1014 1015 static inline struct hns_roce_ucontext 1016 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1017 { 1018 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1019 } 1020 1021 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1022 { 1023 return container_of(ibpd, struct hns_roce_pd, ibpd); 1024 } 1025 1026 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1027 { 1028 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1029 } 1030 1031 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1032 { 1033 return container_of(ibah, struct hns_roce_ah, ibah); 1034 } 1035 1036 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1037 { 1038 return container_of(ibmr, struct hns_roce_mr, ibmr); 1039 } 1040 1041 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1042 { 1043 return container_of(ibmw, struct hns_roce_mw, ibmw); 1044 } 1045 1046 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1047 { 1048 return container_of(ibqp, struct hns_roce_qp, ibqp); 1049 } 1050 1051 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1052 { 1053 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1054 } 1055 1056 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1057 { 1058 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1059 } 1060 1061 static inline struct hns_user_mmap_entry * 1062 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1063 { 1064 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1065 } 1066 1067 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1068 { 1069 writeq(*(u64 *)val, dest); 1070 } 1071 1072 static inline struct hns_roce_qp 1073 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1074 { 1075 return xa_load(&hr_dev->qp_table_xa, qpn); 1076 } 1077 1078 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1079 unsigned int offset) 1080 { 1081 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1082 (offset & ((1 << buf->trunk_shift) - 1)); 1083 } 1084 1085 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1086 unsigned int offset) 1087 { 1088 return buf->trunk_list[offset >> buf->trunk_shift].map + 1089 (offset & ((1 << buf->trunk_shift) - 1)); 1090 } 1091 1092 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1093 { 1094 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1095 } 1096 1097 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1098 1099 static inline u64 to_hr_hw_page_addr(u64 addr) 1100 { 1101 return addr >> HNS_HW_PAGE_SHIFT; 1102 } 1103 1104 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1105 { 1106 return page_shift - HNS_HW_PAGE_SHIFT; 1107 } 1108 1109 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1110 { 1111 if (count > 0) 1112 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1113 1114 return 0; 1115 } 1116 1117 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1118 { 1119 return hr_hw_page_align(count << buf_shift); 1120 } 1121 1122 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1123 { 1124 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1125 } 1126 1127 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1128 { 1129 if (!count) 1130 return 0; 1131 1132 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1133 } 1134 1135 #define DSCP_SHIFT 2 1136 1137 static inline u8 get_tclass(const struct ib_global_route *grh) 1138 { 1139 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1140 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1141 } 1142 1143 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1144 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1145 1146 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1147 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1148 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1149 u64 out_param); 1150 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1151 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1152 1153 /* hns roce hw need current block and next block addr from mtt */ 1154 #define MTT_MIN_COUNT 2 1155 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1156 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1157 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1158 struct hns_roce_buf_attr *buf_attr, 1159 unsigned int page_shift, struct ib_udata *udata, 1160 unsigned long user_addr); 1161 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_mtr *mtr); 1163 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1164 dma_addr_t *pages, unsigned int page_cnt); 1165 1166 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1167 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1168 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1169 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1170 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1171 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1172 1173 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1174 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1175 1176 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1177 1178 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1179 struct ib_udata *udata); 1180 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1181 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1182 { 1183 return 0; 1184 } 1185 1186 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1187 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1188 1189 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1190 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1191 u64 virt_addr, int access_flags, 1192 struct ib_udata *udata); 1193 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1194 u64 length, u64 virt_addr, 1195 int mr_access_flags, struct ib_pd *pd, 1196 struct ib_udata *udata); 1197 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1198 u32 max_num_sg); 1199 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1200 unsigned int *sg_offset); 1201 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1202 unsigned long key_to_hw_index(u32 key); 1203 1204 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1205 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1206 1207 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1208 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1209 u32 page_shift, u32 flags); 1210 1211 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1212 int buf_cnt, struct hns_roce_buf *buf, 1213 unsigned int page_shift); 1214 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1215 int buf_cnt, struct ib_umem *umem, 1216 unsigned int page_shift); 1217 1218 int hns_roce_create_srq(struct ib_srq *srq, 1219 struct ib_srq_init_attr *srq_init_attr, 1220 struct ib_udata *udata); 1221 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1222 1223 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1224 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1225 1226 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1227 struct ib_udata *udata); 1228 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1229 int attr_mask, struct ib_udata *udata); 1230 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1231 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1232 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1233 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1234 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1235 struct ib_cq *ib_cq); 1236 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1237 struct hns_roce_cq *recv_cq); 1238 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1239 struct hns_roce_cq *recv_cq); 1240 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1241 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1242 struct ib_udata *udata); 1243 __be32 send_ieth(const struct ib_send_wr *wr); 1244 int to_hr_qp_type(int qp_type); 1245 1246 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1247 struct ib_udata *udata); 1248 1249 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1250 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1251 struct hns_roce_db *db); 1252 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1253 struct hns_roce_db *db); 1254 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1255 int order); 1256 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1257 1258 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1259 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1260 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1261 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1262 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1263 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1264 int hns_roce_init(struct hns_roce_dev *hr_dev); 1265 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1266 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1267 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1268 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1269 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1270 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1271 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1272 int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq); 1273 int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq); 1274 struct hns_user_mmap_entry * 1275 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1276 size_t length, 1277 enum hns_roce_mmap_type mmap_type); 1278 #endif /* _HNS_ROCE_DEVICE_H */ 1279