1 /* 2 * AD9523 SPI Low Jitter Clock Generator 3 * 4 * Copyright 2012 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/frequency/ad9523.h> 22 23 #define AD9523_READ (1 << 15) 24 #define AD9523_WRITE (0 << 15) 25 #define AD9523_CNT(x) (((x) - 1) << 13) 26 #define AD9523_ADDR(x) ((x) & 0xFFF) 27 28 #define AD9523_R1B (1 << 16) 29 #define AD9523_R2B (2 << 16) 30 #define AD9523_R3B (3 << 16) 31 #define AD9523_TRANSF_LEN(x) ((x) >> 16) 32 33 #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0) 34 #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2) 35 #define AD9523_PART_REGISTER (AD9523_R1B | 0x3) 36 #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4) 37 38 #define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6) 39 40 #define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11) 41 #define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13) 42 #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14) 43 #define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17) 44 #define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19) 45 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A) 46 #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B) 47 #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C) 48 #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D) 49 50 #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0) 51 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1) 52 #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2) 53 #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3) 54 #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4) 55 #define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6) 56 #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7) 57 58 #define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch)) 59 60 #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA) 61 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB) 62 63 #define AD9523_READBACK_0 (AD9523_R1B | 0x22C) 64 #define AD9523_READBACK_1 (AD9523_R1B | 0x22D) 65 66 #define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232) 67 #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233) 68 #define AD9523_IO_UPDATE (AD9523_R1B | 0x234) 69 70 #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00) 71 #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01) 72 #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02) 73 #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03) 74 75 /* AD9523_SERIAL_PORT_CONFIG */ 76 77 #define AD9523_SER_CONF_SDO_ACTIVE (1 << 7) 78 #define AD9523_SER_CONF_SOFT_RESET (1 << 5) 79 80 /* AD9523_READBACK_CTRL */ 81 #define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0) 82 83 /* AD9523_PLL1_CHARGE_PUMP_CTRL */ 84 #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F) 85 #define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7) 86 #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8) 87 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8) 88 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8) 89 #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8) 90 #define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10) 91 #define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10) 92 #define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10) 93 #define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10) 94 95 /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */ 96 #define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7) 97 #define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6) 98 #define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5) 99 #define AD9523_PLL1_REFB_RCV_EN (1 << 4) 100 #define AD9523_PLL1_REFA_RCV_EN (1 << 3) 101 #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2) 102 #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1) 103 #define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0) 104 105 /* AD9523_PLL1_REF_CTRL */ 106 #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7) 107 #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6) 108 #define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5) 109 #define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5) 110 #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4) 111 #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3) 112 #define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2) 113 #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1) 114 #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0) 115 116 /* AD9523_PLL1_MISC_CTRL */ 117 #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7) 118 #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6) 119 #define AD9523_PLL1_REF_MODE(x) ((x) << 2) 120 #define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1) 121 #define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0) 122 123 /* AD9523_PLL1_LOOP_FILTER_CTRL */ 124 #define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF) 125 126 /* AD9523_PLL2_CHARGE_PUMP */ 127 #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500) 128 129 /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */ 130 #define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6) 131 #define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0) 132 #define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a)) 133 134 /* AD9523_PLL2_CTRL */ 135 #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0) 136 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0) 137 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0) 138 #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0) 139 #define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2) 140 #define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2) 141 #define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2) 142 #define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1) 143 #define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4) 144 #define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5) 145 #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7) 146 147 /* AD9523_PLL2_VCO_CTRL */ 148 #define AD9523_PLL2_VCO_CALIBRATE (1 << 1) 149 #define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2) 150 #define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3) 151 #define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4) 152 153 /* AD9523_PLL2_VCO_DIVIDER */ 154 #define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0) 155 #define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4) 156 #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2) 157 #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6) 158 159 /* AD9523_PLL2_LOOP_FILTER_CTRL */ 160 #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0) 161 #define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3) 162 #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6) 163 #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8) 164 165 /* AD9523_PLL2_R2_DIVIDER */ 166 #define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0) 167 168 /* AD9523_CHANNEL_CLOCK_DIST */ 169 #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18) 170 #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F) 171 #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8) 172 #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1) 173 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7) 174 #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6) 175 #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5) 176 #define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4) 177 #define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0) 178 179 /* AD9523_PLL1_OUTPUT_CTRL */ 180 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7) 181 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6) 182 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5) 183 #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4) 184 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0) 185 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0) 186 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0) 187 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0) 188 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0) 189 190 /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */ 191 #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7) 192 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6) 193 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5) 194 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4) 195 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3) 196 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2) 197 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1) 198 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0) 199 200 /* AD9523_READBACK_0 */ 201 #define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7) 202 #define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6) 203 #define AD9523_READBACK_0_STAT_VCXO (1 << 5) 204 #define AD9523_READBACK_0_STAT_REF_TEST (1 << 4) 205 #define AD9523_READBACK_0_STAT_REFB (1 << 3) 206 #define AD9523_READBACK_0_STAT_REFA (1 << 2) 207 #define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1) 208 #define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0) 209 210 /* AD9523_READBACK_1 */ 211 #define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3) 212 #define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2) 213 #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0) 214 215 /* AD9523_STATUS_SIGNALS */ 216 #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16) 217 #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302) 218 /* AD9523_POWER_DOWN_CTRL */ 219 #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2) 220 #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1) 221 #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0) 222 223 /* AD9523_IO_UPDATE */ 224 #define AD9523_IO_UPDATE_EN (1 << 0) 225 226 /* AD9523_EEPROM_DATA_XFER_STATUS */ 227 #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0) 228 229 /* AD9523_EEPROM_ERROR_READBACK */ 230 #define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0) 231 232 /* AD9523_EEPROM_CTRL1 */ 233 #define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1) 234 #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0) 235 236 /* AD9523_EEPROM_CTRL2 */ 237 #define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0) 238 239 #define AD9523_NUM_CHAN 14 240 #define AD9523_NUM_CHAN_ALT_CLK_SRC 10 241 242 /* Helpers to avoid excess line breaks */ 243 #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b) 244 #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0) 245 246 enum { 247 AD9523_STAT_PLL1_LD, 248 AD9523_STAT_PLL2_LD, 249 AD9523_STAT_REFA, 250 AD9523_STAT_REFB, 251 AD9523_STAT_REF_TEST, 252 AD9523_STAT_VCXO, 253 AD9523_STAT_PLL2_FB_CLK, 254 AD9523_STAT_PLL2_REF_CLK, 255 AD9523_SYNC, 256 AD9523_EEPROM, 257 }; 258 259 enum { 260 AD9523_VCO1, 261 AD9523_VCO2, 262 AD9523_VCXO, 263 AD9523_NUM_CLK_SRC, 264 }; 265 266 struct ad9523_state { 267 struct spi_device *spi; 268 struct regulator *reg; 269 struct ad9523_platform_data *pdata; 270 struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN]; 271 272 unsigned long vcxo_freq; 273 unsigned long vco_freq; 274 unsigned long vco_out_freq[AD9523_NUM_CLK_SRC]; 275 unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC]; 276 277 /* 278 * DMA (thus cache coherency maintenance) requires the 279 * transfer buffers to live in their own cache lines. 280 */ 281 union { 282 __be32 d32; 283 u8 d8[4]; 284 } data[2] ____cacheline_aligned; 285 }; 286 287 static int ad9523_read(struct iio_dev *indio_dev, unsigned addr) 288 { 289 struct ad9523_state *st = iio_priv(indio_dev); 290 int ret; 291 292 /* We encode the register size 1..3 bytes into the register address. 293 * On transfer we get the size from the register datum, and make sure 294 * the result is properly aligned. 295 */ 296 297 struct spi_transfer t[] = { 298 { 299 .tx_buf = &st->data[0].d8[2], 300 .len = 2, 301 }, { 302 .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], 303 .len = AD9523_TRANSF_LEN(addr), 304 }, 305 }; 306 307 st->data[0].d32 = cpu_to_be32(AD9523_READ | 308 AD9523_CNT(AD9523_TRANSF_LEN(addr)) | 309 AD9523_ADDR(addr)); 310 311 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 312 if (ret < 0) 313 dev_err(&indio_dev->dev, "read failed (%d)", ret); 314 else 315 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >> 316 (8 * (3 - AD9523_TRANSF_LEN(addr)))); 317 318 return ret; 319 }; 320 321 static int ad9523_write(struct iio_dev *indio_dev, unsigned addr, unsigned val) 322 { 323 struct ad9523_state *st = iio_priv(indio_dev); 324 int ret; 325 struct spi_transfer t[] = { 326 { 327 .tx_buf = &st->data[0].d8[2], 328 .len = 2, 329 }, { 330 .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], 331 .len = AD9523_TRANSF_LEN(addr), 332 }, 333 }; 334 335 st->data[0].d32 = cpu_to_be32(AD9523_WRITE | 336 AD9523_CNT(AD9523_TRANSF_LEN(addr)) | 337 AD9523_ADDR(addr)); 338 st->data[1].d32 = cpu_to_be32(val); 339 340 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 341 342 if (ret < 0) 343 dev_err(&indio_dev->dev, "write failed (%d)", ret); 344 345 return ret; 346 } 347 348 static int ad9523_io_update(struct iio_dev *indio_dev) 349 { 350 return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN); 351 } 352 353 static int ad9523_vco_out_map(struct iio_dev *indio_dev, 354 unsigned ch, unsigned out) 355 { 356 struct ad9523_state *st = iio_priv(indio_dev); 357 int ret; 358 unsigned mask; 359 360 switch (ch) { 361 case 0 ... 3: 362 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); 363 if (ret < 0) 364 break; 365 mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch; 366 if (out) { 367 ret |= mask; 368 out = 2; 369 } else { 370 ret &= ~mask; 371 } 372 ret = ad9523_write(indio_dev, 373 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); 374 break; 375 case 4 ... 6: 376 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL); 377 if (ret < 0) 378 break; 379 mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4); 380 if (out) 381 ret |= mask; 382 else 383 ret &= ~mask; 384 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret); 385 break; 386 case 7 ... 9: 387 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); 388 if (ret < 0) 389 break; 390 mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7); 391 if (out) 392 ret |= mask; 393 else 394 ret &= ~mask; 395 ret = ad9523_write(indio_dev, 396 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); 397 break; 398 default: 399 return 0; 400 } 401 402 st->vco_out_map[ch] = out; 403 404 return ret; 405 } 406 407 static int ad9523_set_clock_provider(struct iio_dev *indio_dev, 408 unsigned ch, unsigned long freq) 409 { 410 struct ad9523_state *st = iio_priv(indio_dev); 411 long tmp1, tmp2; 412 bool use_alt_clk_src; 413 414 switch (ch) { 415 case 0 ... 3: 416 use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]); 417 break; 418 case 4 ... 9: 419 tmp1 = st->vco_out_freq[AD9523_VCO1] / freq; 420 tmp2 = st->vco_out_freq[AD9523_VCO2] / freq; 421 tmp1 *= freq; 422 tmp2 *= freq; 423 use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq)); 424 break; 425 default: 426 /* Ch 10..14: No action required, return success */ 427 return 0; 428 } 429 430 return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src); 431 } 432 433 static int ad9523_store_eeprom(struct iio_dev *indio_dev) 434 { 435 int ret, tmp; 436 437 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 438 AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS); 439 if (ret < 0) 440 return ret; 441 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2, 442 AD9523_EEPROM_CTRL2_REG2EEPROM); 443 if (ret < 0) 444 return ret; 445 446 tmp = 4; 447 do { 448 msleep(16); 449 ret = ad9523_read(indio_dev, 450 AD9523_EEPROM_DATA_XFER_STATUS); 451 if (ret < 0) 452 return ret; 453 } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--); 454 455 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0); 456 if (ret < 0) 457 return ret; 458 459 ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK); 460 if (ret < 0) 461 return ret; 462 463 if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) { 464 dev_err(&indio_dev->dev, "Verify EEPROM failed"); 465 ret = -EIO; 466 } 467 468 return ret; 469 } 470 471 static int ad9523_sync(struct iio_dev *indio_dev) 472 { 473 int ret, tmp; 474 475 ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS); 476 if (ret < 0) 477 return ret; 478 479 tmp = ret; 480 tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; 481 482 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); 483 if (ret < 0) 484 return ret; 485 486 ad9523_io_update(indio_dev); 487 tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; 488 489 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); 490 if (ret < 0) 491 return ret; 492 493 return ad9523_io_update(indio_dev); 494 } 495 496 static ssize_t ad9523_store(struct device *dev, 497 struct device_attribute *attr, 498 const char *buf, size_t len) 499 { 500 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 501 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 502 bool state; 503 int ret; 504 505 ret = strtobool(buf, &state); 506 if (ret < 0) 507 return ret; 508 509 if (!state) 510 return 0; 511 512 mutex_lock(&indio_dev->mlock); 513 switch ((u32)this_attr->address) { 514 case AD9523_SYNC: 515 ret = ad9523_sync(indio_dev); 516 break; 517 case AD9523_EEPROM: 518 ret = ad9523_store_eeprom(indio_dev); 519 break; 520 default: 521 ret = -ENODEV; 522 } 523 mutex_unlock(&indio_dev->mlock); 524 525 return ret ? ret : len; 526 } 527 528 static ssize_t ad9523_show(struct device *dev, 529 struct device_attribute *attr, 530 char *buf) 531 { 532 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 533 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 534 int ret; 535 536 mutex_lock(&indio_dev->mlock); 537 ret = ad9523_read(indio_dev, AD9523_READBACK_0); 538 if (ret >= 0) { 539 ret = sprintf(buf, "%d\n", !!(ret & (1 << 540 (u32)this_attr->address))); 541 } 542 mutex_unlock(&indio_dev->mlock); 543 544 return ret; 545 } 546 547 static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO, 548 ad9523_show, 549 NULL, 550 AD9523_STAT_PLL1_LD); 551 552 static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO, 553 ad9523_show, 554 NULL, 555 AD9523_STAT_PLL2_LD); 556 557 static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO, 558 ad9523_show, 559 NULL, 560 AD9523_STAT_REFA); 561 562 static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO, 563 ad9523_show, 564 NULL, 565 AD9523_STAT_REFB); 566 567 static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO, 568 ad9523_show, 569 NULL, 570 AD9523_STAT_REF_TEST); 571 572 static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO, 573 ad9523_show, 574 NULL, 575 AD9523_STAT_VCXO); 576 577 static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO, 578 ad9523_show, 579 NULL, 580 AD9523_STAT_PLL2_FB_CLK); 581 582 static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO, 583 ad9523_show, 584 NULL, 585 AD9523_STAT_PLL2_REF_CLK); 586 587 static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR, 588 NULL, 589 ad9523_store, 590 AD9523_SYNC); 591 592 static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR, 593 NULL, 594 ad9523_store, 595 AD9523_EEPROM); 596 597 static struct attribute *ad9523_attributes[] = { 598 &iio_dev_attr_sync_dividers.dev_attr.attr, 599 &iio_dev_attr_store_eeprom.dev_attr.attr, 600 &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr, 601 &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr, 602 &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr, 603 &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr, 604 &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr, 605 &iio_dev_attr_vcxo_clk_present.dev_attr.attr, 606 &iio_dev_attr_pll1_locked.dev_attr.attr, 607 &iio_dev_attr_pll2_locked.dev_attr.attr, 608 NULL, 609 }; 610 611 static const struct attribute_group ad9523_attribute_group = { 612 .attrs = ad9523_attributes, 613 }; 614 615 static int ad9523_read_raw(struct iio_dev *indio_dev, 616 struct iio_chan_spec const *chan, 617 int *val, 618 int *val2, 619 long m) 620 { 621 struct ad9523_state *st = iio_priv(indio_dev); 622 unsigned code; 623 int ret; 624 625 mutex_lock(&indio_dev->mlock); 626 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); 627 mutex_unlock(&indio_dev->mlock); 628 629 if (ret < 0) 630 return ret; 631 632 switch (m) { 633 case IIO_CHAN_INFO_RAW: 634 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN); 635 return IIO_VAL_INT; 636 case IIO_CHAN_INFO_FREQUENCY: 637 *val = st->vco_out_freq[st->vco_out_map[chan->channel]] / 638 AD9523_CLK_DIST_DIV_REV(ret); 639 return IIO_VAL_INT; 640 case IIO_CHAN_INFO_PHASE: 641 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) / 642 AD9523_CLK_DIST_DIV_REV(ret); 643 *val = code / 1000000; 644 *val2 = (code % 1000000) * 10; 645 return IIO_VAL_INT_PLUS_MICRO; 646 default: 647 return -EINVAL; 648 } 649 }; 650 651 static int ad9523_write_raw(struct iio_dev *indio_dev, 652 struct iio_chan_spec const *chan, 653 int val, 654 int val2, 655 long mask) 656 { 657 struct ad9523_state *st = iio_priv(indio_dev); 658 unsigned reg; 659 int ret, tmp, code; 660 661 mutex_lock(&indio_dev->mlock); 662 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); 663 if (ret < 0) 664 goto out; 665 666 reg = ret; 667 668 switch (mask) { 669 case IIO_CHAN_INFO_RAW: 670 if (val) 671 reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN; 672 else 673 reg |= AD9523_CLK_DIST_PWR_DOWN_EN; 674 break; 675 case IIO_CHAN_INFO_FREQUENCY: 676 if (val <= 0) { 677 ret = -EINVAL; 678 goto out; 679 } 680 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val); 681 if (ret < 0) 682 goto out; 683 tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val; 684 tmp = clamp(tmp, 1, 1024); 685 reg &= ~(0x3FF << 8); 686 reg |= AD9523_CLK_DIST_DIV(tmp); 687 break; 688 case IIO_CHAN_INFO_PHASE: 689 code = val * 1000000 + val2 % 1000000; 690 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592; 691 tmp = clamp(tmp, 0, 63); 692 reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0); 693 reg |= AD9523_CLK_DIST_DIV_PHASE(tmp); 694 break; 695 default: 696 ret = -EINVAL; 697 goto out; 698 } 699 700 ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel), 701 reg); 702 if (ret < 0) 703 goto out; 704 705 ad9523_io_update(indio_dev); 706 out: 707 mutex_unlock(&indio_dev->mlock); 708 return ret; 709 } 710 711 static int ad9523_reg_access(struct iio_dev *indio_dev, 712 unsigned reg, unsigned writeval, 713 unsigned *readval) 714 { 715 int ret; 716 717 mutex_lock(&indio_dev->mlock); 718 if (readval == NULL) { 719 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval); 720 ad9523_io_update(indio_dev); 721 } else { 722 ret = ad9523_read(indio_dev, reg | AD9523_R1B); 723 if (ret < 0) 724 goto out_unlock; 725 *readval = ret; 726 ret = 0; 727 } 728 729 out_unlock: 730 mutex_unlock(&indio_dev->mlock); 731 732 return ret; 733 } 734 735 static const struct iio_info ad9523_info = { 736 .read_raw = &ad9523_read_raw, 737 .write_raw = &ad9523_write_raw, 738 .debugfs_reg_access = &ad9523_reg_access, 739 .attrs = &ad9523_attribute_group, 740 .driver_module = THIS_MODULE, 741 }; 742 743 static int ad9523_setup(struct iio_dev *indio_dev) 744 { 745 struct ad9523_state *st = iio_priv(indio_dev); 746 struct ad9523_platform_data *pdata = st->pdata; 747 struct ad9523_channel_spec *chan; 748 unsigned long active_mask = 0; 749 int ret, i; 750 751 ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG, 752 AD9523_SER_CONF_SOFT_RESET | 753 (st->spi->mode & SPI_3WIRE ? 0 : 754 AD9523_SER_CONF_SDO_ACTIVE)); 755 if (ret < 0) 756 return ret; 757 758 ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL, 759 AD9523_READBACK_CTRL_READ_BUFFERED); 760 if (ret < 0) 761 return ret; 762 763 ret = ad9523_io_update(indio_dev); 764 if (ret < 0) 765 return ret; 766 767 /* 768 * PLL1 Setup 769 */ 770 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER, 771 pdata->refa_r_div); 772 if (ret < 0) 773 return ret; 774 775 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER, 776 pdata->refb_r_div); 777 if (ret < 0) 778 return ret; 779 780 ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER, 781 pdata->pll1_feedback_div); 782 if (ret < 0) 783 return ret; 784 785 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL, 786 AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata-> 787 pll1_charge_pump_current_nA) | 788 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL | 789 AD9523_PLL1_BACKLASH_PW_MIN); 790 if (ret < 0) 791 return ret; 792 793 ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL, 794 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) | 795 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) | 796 AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) | 797 AD_IF(osc_in_cmos_neg_inp_en, 798 AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) | 799 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) | 800 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN)); 801 if (ret < 0) 802 return ret; 803 804 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL, 805 AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) | 806 AD_IF(zd_in_cmos_neg_inp_en, 807 AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) | 808 AD_IF(zero_delay_mode_internal_en, 809 AD9523_PLL1_ZERO_DELAY_MODE_INT) | 810 AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) | 811 AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) | 812 AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN)); 813 if (ret < 0) 814 return ret; 815 816 ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL, 817 AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN | 818 AD9523_PLL1_REF_MODE(pdata->ref_mode)); 819 if (ret < 0) 820 return ret; 821 822 ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL, 823 AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero)); 824 if (ret < 0) 825 return ret; 826 /* 827 * PLL2 Setup 828 */ 829 830 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP, 831 AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata-> 832 pll2_charge_pump_current_nA)); 833 if (ret < 0) 834 return ret; 835 836 ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB, 837 AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) | 838 AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt)); 839 if (ret < 0) 840 return ret; 841 842 ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL, 843 AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL | 844 AD9523_PLL2_BACKLASH_CTRL_EN | 845 AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN)); 846 if (ret < 0) 847 return ret; 848 849 st->vco_freq = (pdata->vcxo_freq * (pdata->pll2_freq_doubler_en ? 2 : 1) 850 / pdata->pll2_r2_div) * AD9523_PLL2_FB_NDIV(pdata-> 851 pll2_ndiv_a_cnt, pdata->pll2_ndiv_b_cnt); 852 853 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL, 854 AD9523_PLL2_VCO_CALIBRATE); 855 if (ret < 0) 856 return ret; 857 858 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER, 859 AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) | 860 AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) | 861 AD_IFE(pll2_vco_diff_m1, 0, 862 AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) | 863 AD_IFE(pll2_vco_diff_m2, 0, 864 AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN)); 865 if (ret < 0) 866 return ret; 867 868 if (pdata->pll2_vco_diff_m1) 869 st->vco_out_freq[AD9523_VCO1] = 870 st->vco_freq / pdata->pll2_vco_diff_m1; 871 872 if (pdata->pll2_vco_diff_m2) 873 st->vco_out_freq[AD9523_VCO2] = 874 st->vco_freq / pdata->pll2_vco_diff_m2; 875 876 st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq; 877 878 ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER, 879 AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div)); 880 if (ret < 0) 881 return ret; 882 883 ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL, 884 AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) | 885 AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) | 886 AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) | 887 AD_IF(rzero_bypass_en, 888 AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN)); 889 if (ret < 0) 890 return ret; 891 892 for (i = 0; i < pdata->num_channels; i++) { 893 chan = &pdata->channels[i]; 894 if (chan->channel_num < AD9523_NUM_CHAN) { 895 __set_bit(chan->channel_num, &active_mask); 896 ret = ad9523_write(indio_dev, 897 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num), 898 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) | 899 AD9523_CLK_DIST_DIV(chan->channel_divider) | 900 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) | 901 (chan->sync_ignore_en ? 902 AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) | 903 (chan->divider_output_invert_en ? 904 AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) | 905 (chan->low_power_mode_en ? 906 AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) | 907 (chan->output_dis ? 908 AD9523_CLK_DIST_PWR_DOWN_EN : 0)); 909 if (ret < 0) 910 return ret; 911 912 ret = ad9523_vco_out_map(indio_dev, chan->channel_num, 913 chan->use_alt_clock_src); 914 if (ret < 0) 915 return ret; 916 917 st->ad9523_channels[i].type = IIO_ALTVOLTAGE; 918 st->ad9523_channels[i].output = 1; 919 st->ad9523_channels[i].indexed = 1; 920 st->ad9523_channels[i].channel = chan->channel_num; 921 st->ad9523_channels[i].extend_name = 922 chan->extended_name; 923 st->ad9523_channels[i].info_mask_separate = 924 BIT(IIO_CHAN_INFO_RAW) | 925 BIT(IIO_CHAN_INFO_PHASE) | 926 BIT(IIO_CHAN_INFO_FREQUENCY); 927 } 928 } 929 930 for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) 931 ad9523_write(indio_dev, 932 AD9523_CHANNEL_CLOCK_DIST(i), 933 AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) | 934 AD9523_CLK_DIST_PWR_DOWN_EN); 935 936 ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0); 937 if (ret < 0) 938 return ret; 939 940 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, 941 AD9523_STATUS_MONITOR_01_PLL12_LOCKED); 942 if (ret < 0) 943 return ret; 944 945 ret = ad9523_io_update(indio_dev); 946 if (ret < 0) 947 return ret; 948 949 return 0; 950 } 951 952 static int ad9523_probe(struct spi_device *spi) 953 { 954 struct ad9523_platform_data *pdata = spi->dev.platform_data; 955 struct iio_dev *indio_dev; 956 struct ad9523_state *st; 957 int ret; 958 959 if (!pdata) { 960 dev_err(&spi->dev, "no platform data?\n"); 961 return -EINVAL; 962 } 963 964 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 965 if (indio_dev == NULL) 966 return -ENOMEM; 967 968 st = iio_priv(indio_dev); 969 970 st->reg = devm_regulator_get(&spi->dev, "vcc"); 971 if (!IS_ERR(st->reg)) { 972 ret = regulator_enable(st->reg); 973 if (ret) 974 return ret; 975 } 976 977 spi_set_drvdata(spi, indio_dev); 978 st->spi = spi; 979 st->pdata = pdata; 980 981 indio_dev->dev.parent = &spi->dev; 982 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 983 spi_get_device_id(spi)->name; 984 indio_dev->info = &ad9523_info; 985 indio_dev->modes = INDIO_DIRECT_MODE; 986 indio_dev->channels = st->ad9523_channels; 987 indio_dev->num_channels = pdata->num_channels; 988 989 ret = ad9523_setup(indio_dev); 990 if (ret < 0) 991 goto error_disable_reg; 992 993 ret = iio_device_register(indio_dev); 994 if (ret) 995 goto error_disable_reg; 996 997 dev_info(&spi->dev, "probed %s\n", indio_dev->name); 998 999 return 0; 1000 1001 error_disable_reg: 1002 if (!IS_ERR(st->reg)) 1003 regulator_disable(st->reg); 1004 1005 return ret; 1006 } 1007 1008 static int ad9523_remove(struct spi_device *spi) 1009 { 1010 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1011 struct ad9523_state *st = iio_priv(indio_dev); 1012 1013 iio_device_unregister(indio_dev); 1014 1015 if (!IS_ERR(st->reg)) 1016 regulator_disable(st->reg); 1017 1018 return 0; 1019 } 1020 1021 static const struct spi_device_id ad9523_id[] = { 1022 {"ad9523-1", 9523}, 1023 {} 1024 }; 1025 MODULE_DEVICE_TABLE(spi, ad9523_id); 1026 1027 static struct spi_driver ad9523_driver = { 1028 .driver = { 1029 .name = "ad9523", 1030 .owner = THIS_MODULE, 1031 }, 1032 .probe = ad9523_probe, 1033 .remove = ad9523_remove, 1034 .id_table = ad9523_id, 1035 }; 1036 module_spi_driver(ad9523_driver); 1037 1038 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 1039 MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL"); 1040 MODULE_LICENSE("GPL v2"); 1041