1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/errno.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/hwmon.h> 11 #include <linux/hwmon-sysfs.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/sysfs.h> 20 #include <linux/thermal.h> 21 22 /* ASPEED PWM & FAN Tach Register Definition */ 23 #define ASPEED_PTCR_CTRL 0x00 24 #define ASPEED_PTCR_CLK_CTRL 0x04 25 #define ASPEED_PTCR_DUTY0_CTRL 0x08 26 #define ASPEED_PTCR_DUTY1_CTRL 0x0c 27 #define ASPEED_PTCR_TYPEM_CTRL 0x10 28 #define ASPEED_PTCR_TYPEM_CTRL1 0x14 29 #define ASPEED_PTCR_TYPEN_CTRL 0x18 30 #define ASPEED_PTCR_TYPEN_CTRL1 0x1c 31 #define ASPEED_PTCR_TACH_SOURCE 0x20 32 #define ASPEED_PTCR_TRIGGER 0x28 33 #define ASPEED_PTCR_RESULT 0x2c 34 #define ASPEED_PTCR_INTR_CTRL 0x30 35 #define ASPEED_PTCR_INTR_STS 0x34 36 #define ASPEED_PTCR_TYPEM_LIMIT 0x38 37 #define ASPEED_PTCR_TYPEN_LIMIT 0x3C 38 #define ASPEED_PTCR_CTRL_EXT 0x40 39 #define ASPEED_PTCR_CLK_CTRL_EXT 0x44 40 #define ASPEED_PTCR_DUTY2_CTRL 0x48 41 #define ASPEED_PTCR_DUTY3_CTRL 0x4c 42 #define ASPEED_PTCR_TYPEO_CTRL 0x50 43 #define ASPEED_PTCR_TYPEO_CTRL1 0x54 44 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60 45 #define ASPEED_PTCR_TYPEO_LIMIT 0x78 46 47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */ 48 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15 49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6 50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) 51 52 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14 53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5 54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) 55 56 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13 57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4 58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) 59 60 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12 61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3 62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) 63 64 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) 65 66 #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) 67 #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) 68 #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) 69 #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) 70 71 #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) 72 #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) 73 74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */ 75 /* TYPE N */ 76 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16) 77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24 78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20 79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16 80 /* TYPE M */ 81 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0) 82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8 83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4 84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0 85 86 /* 87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control 88 * 0/1/2/3 register 89 */ 90 #define DUTY_CTRL_PWM2_FALL_POINT 24 91 #define DUTY_CTRL_PWM2_RISE_POINT 16 92 #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16) 93 #define DUTY_CTRL_PWM1_FALL_POINT 8 94 #define DUTY_CTRL_PWM1_RISE_POINT 0 95 #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0) 96 97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */ 98 #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16)) 99 #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0) 100 #define TYPE_CTRL_FAN_PERIOD 16 101 #define TYPE_CTRL_FAN_MODE 4 102 #define TYPE_CTRL_FAN_DIVISION 1 103 #define TYPE_CTRL_FAN_TYPE_EN 1 104 105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */ 106 /* bit [0,1] at 0x20, bit [2] at 0x60 */ 107 #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2) 108 #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2) 109 #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2)) 110 #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) 111 112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */ 113 #define RESULT_STATUS_MASK BIT(31) 114 #define RESULT_VALUE_MASK 0xfffff 115 116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */ 117 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15 118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6 119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) 120 121 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14 122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5 123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) 124 125 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13 126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4 127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) 128 129 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12 130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3 131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) 132 133 #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) 134 #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) 135 #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) 136 #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) 137 138 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */ 139 /* TYPE O */ 140 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0) 141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8 142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0 144 145 #define PWM_MAX 255 146 147 #define BOTH_EDGES 0x02 /* 10b */ 148 149 #define M_PWM_DIV_H 0x00 150 #define M_PWM_DIV_L 0x05 151 #define M_PWM_PERIOD 0x5F 152 #define M_TACH_CLK_DIV 0x00 153 /* 154 * 5:4 Type N fan tach mode selection bit: 155 * 00: falling 156 * 01: rising 157 * 10: both 158 * 11: reserved. 159 */ 160 #define M_TACH_MODE 0x02 /* 10b */ 161 #define M_TACH_UNIT 0x0420 162 #define INIT_FAN_CTRL 0xFF 163 164 /* How long we sleep in us while waiting for an RPM result. */ 165 #define ASPEED_RPM_STATUS_SLEEP_USEC 500 166 167 #define MAX_CDEV_NAME_LEN 16 168 169 struct aspeed_cooling_device { 170 char name[16]; 171 struct aspeed_pwm_tacho_data *priv; 172 struct thermal_cooling_device *tcdev; 173 int pwm_port; 174 u8 *cooling_levels; 175 u8 max_state; 176 u8 cur_state; 177 }; 178 179 struct aspeed_pwm_tacho_data { 180 struct regmap *regmap; 181 struct reset_control *rst; 182 unsigned long clk_freq; 183 bool pwm_present[8]; 184 bool fan_tach_present[16]; 185 u8 type_pwm_clock_unit[3]; 186 u8 type_pwm_clock_division_h[3]; 187 u8 type_pwm_clock_division_l[3]; 188 u8 type_fan_tach_clock_division[3]; 189 u8 type_fan_tach_mode[3]; 190 u16 type_fan_tach_unit[3]; 191 u8 pwm_port_type[8]; 192 u8 pwm_port_fan_ctrl[8]; 193 u8 fan_tach_ch_source[16]; 194 struct aspeed_cooling_device *cdev[8]; 195 const struct attribute_group *groups[3]; 196 }; 197 198 enum type { TYPEM, TYPEN, TYPEO }; 199 200 struct type_params { 201 u32 l_value; 202 u32 h_value; 203 u32 unit_value; 204 u32 clk_ctrl_mask; 205 u32 clk_ctrl_reg; 206 u32 ctrl_reg; 207 u32 ctrl_reg1; 208 }; 209 210 static const struct type_params type_params[] = { 211 [TYPEM] = { 212 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L, 213 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H, 214 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT, 215 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK, 216 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 217 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL, 218 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1, 219 }, 220 [TYPEN] = { 221 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L, 222 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H, 223 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT, 224 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK, 225 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 226 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL, 227 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1, 228 }, 229 [TYPEO] = { 230 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L, 231 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H, 232 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT, 233 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK, 234 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT, 235 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL, 236 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1, 237 } 238 }; 239 240 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH }; 241 242 struct pwm_port_params { 243 u32 pwm_en; 244 u32 ctrl_reg; 245 u32 type_part1; 246 u32 type_part2; 247 u32 type_mask; 248 u32 duty_ctrl_rise_point; 249 u32 duty_ctrl_fall_point; 250 u32 duty_ctrl_reg; 251 u32 duty_ctrl_rise_fall_mask; 252 }; 253 254 static const struct pwm_port_params pwm_port_params[] = { 255 [PWMA] = { 256 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN, 257 .ctrl_reg = ASPEED_PTCR_CTRL, 258 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1, 259 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2, 260 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK, 261 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 262 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 263 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 264 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 265 }, 266 [PWMB] = { 267 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN, 268 .ctrl_reg = ASPEED_PTCR_CTRL, 269 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1, 270 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2, 271 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK, 272 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 273 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 274 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 275 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 276 }, 277 [PWMC] = { 278 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN, 279 .ctrl_reg = ASPEED_PTCR_CTRL, 280 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1, 281 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2, 282 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK, 283 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 284 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 285 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 286 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 287 }, 288 [PWMD] = { 289 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN, 290 .ctrl_reg = ASPEED_PTCR_CTRL, 291 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1, 292 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2, 293 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK, 294 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 295 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 296 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 297 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 298 }, 299 [PWME] = { 300 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN, 301 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 302 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1, 303 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2, 304 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK, 305 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 306 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 307 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 308 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 309 }, 310 [PWMF] = { 311 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN, 312 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 313 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1, 314 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2, 315 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK, 316 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 317 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 318 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 319 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 320 }, 321 [PWMG] = { 322 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN, 323 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 324 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1, 325 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2, 326 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK, 327 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 328 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 329 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 330 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 331 }, 332 [PWMH] = { 333 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN, 334 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 335 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1, 336 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2, 337 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK, 338 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 339 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 340 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 341 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 342 } 343 }; 344 345 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, 346 unsigned int val) 347 { 348 void __iomem *regs = (void __iomem *)context; 349 350 writel(val, regs + reg); 351 return 0; 352 } 353 354 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, 355 unsigned int *val) 356 { 357 void __iomem *regs = (void __iomem *)context; 358 359 *val = readl(regs + reg); 360 return 0; 361 } 362 363 static const struct regmap_config aspeed_pwm_tacho_regmap_config = { 364 .reg_bits = 32, 365 .val_bits = 32, 366 .reg_stride = 4, 367 .max_register = ASPEED_PTCR_TYPEO_LIMIT, 368 .reg_write = regmap_aspeed_pwm_tacho_reg_write, 369 .reg_read = regmap_aspeed_pwm_tacho_reg_read, 370 .fast_io = true, 371 }; 372 373 static void aspeed_set_clock_enable(struct regmap *regmap, bool val) 374 { 375 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 376 ASPEED_PTCR_CTRL_CLK_EN, 377 val ? ASPEED_PTCR_CTRL_CLK_EN : 0); 378 } 379 380 static void aspeed_set_clock_source(struct regmap *regmap, int val) 381 { 382 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 383 ASPEED_PTCR_CTRL_CLK_SRC, 384 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); 385 } 386 387 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type, 388 u8 div_high, u8 div_low, u8 unit) 389 { 390 u32 reg_value = ((div_high << type_params[type].h_value) | 391 (div_low << type_params[type].l_value) | 392 (unit << type_params[type].unit_value)); 393 394 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg, 395 type_params[type].clk_ctrl_mask, reg_value); 396 } 397 398 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port, 399 bool enable) 400 { 401 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 402 pwm_port_params[pwm_port].pwm_en, 403 enable ? pwm_port_params[pwm_port].pwm_en : 0); 404 } 405 406 static void aspeed_set_pwm_port_type(struct regmap *regmap, 407 u8 pwm_port, u8 type) 408 { 409 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; 410 411 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; 412 413 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 414 pwm_port_params[pwm_port].type_mask, reg_value); 415 } 416 417 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap, 418 u8 pwm_port, u8 rising, 419 u8 falling) 420 { 421 u32 reg_value = (rising << 422 pwm_port_params[pwm_port].duty_ctrl_rise_point); 423 reg_value |= (falling << 424 pwm_port_params[pwm_port].duty_ctrl_fall_point); 425 426 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg, 427 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask, 428 reg_value); 429 } 430 431 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type, 432 bool enable) 433 { 434 regmap_update_bits(regmap, type_params[type].ctrl_reg, 435 TYPE_CTRL_FAN_TYPE_EN, 436 enable ? TYPE_CTRL_FAN_TYPE_EN : 0); 437 } 438 439 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type, 440 u8 mode, u16 unit, u8 division) 441 { 442 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | 443 (unit << TYPE_CTRL_FAN_PERIOD) | 444 (division << TYPE_CTRL_FAN_DIVISION)); 445 446 regmap_update_bits(regmap, type_params[type].ctrl_reg, 447 TYPE_CTRL_FAN_MASK, reg_value); 448 regmap_update_bits(regmap, type_params[type].ctrl_reg1, 449 TYPE_CTRL_FAN1_MASK, unit << 16); 450 } 451 452 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch, 453 bool enable) 454 { 455 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 456 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch), 457 enable ? 458 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0); 459 } 460 461 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch, 462 u8 fan_tach_ch_source) 463 { 464 u32 reg_value1 = ((fan_tach_ch_source & 0x3) << 465 TACH_PWM_SOURCE_BIT01(fan_tach_ch)); 466 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) << 467 TACH_PWM_SOURCE_BIT2(fan_tach_ch)); 468 469 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE, 470 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch), 471 reg_value1); 472 473 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 474 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch), 475 reg_value2); 476 } 477 478 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv, 479 u8 index, u8 fan_ctrl) 480 { 481 u16 period, dc_time_on; 482 483 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]]; 484 period += 1; 485 dc_time_on = (fan_ctrl * period) / PWM_MAX; 486 487 if (dc_time_on == 0) { 488 aspeed_set_pwm_port_enable(priv->regmap, index, false); 489 } else { 490 if (dc_time_on == period) 491 dc_time_on = 0; 492 493 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0, 494 dc_time_on); 495 aspeed_set_pwm_port_enable(priv->regmap, index, true); 496 } 497 } 498 499 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data 500 *priv, u8 type) 501 { 502 u32 clk; 503 u16 tacho_unit; 504 u8 clk_unit, div_h, div_l, tacho_div; 505 506 clk = priv->clk_freq; 507 clk_unit = priv->type_pwm_clock_unit[type]; 508 div_h = priv->type_pwm_clock_division_h[type]; 509 div_h = 0x1 << div_h; 510 div_l = priv->type_pwm_clock_division_l[type]; 511 if (div_l == 0) 512 div_l = 1; 513 else 514 div_l = div_l * 2; 515 516 tacho_unit = priv->type_fan_tach_unit[type]; 517 tacho_div = priv->type_fan_tach_clock_division[type]; 518 519 tacho_div = 0x4 << (tacho_div * 2); 520 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); 521 } 522 523 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv, 524 u8 fan_tach_ch) 525 { 526 u32 raw_data, tach_div, clk_source, msec, usec, val; 527 u8 fan_tach_ch_source, type, mode, both; 528 int ret; 529 530 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0); 531 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch); 532 533 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch]; 534 type = priv->pwm_port_type[fan_tach_ch_source]; 535 536 msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type)); 537 usec = msec * 1000; 538 539 ret = regmap_read_poll_timeout( 540 priv->regmap, 541 ASPEED_PTCR_RESULT, 542 val, 543 (val & RESULT_STATUS_MASK), 544 ASPEED_RPM_STATUS_SLEEP_USEC, 545 usec); 546 547 /* return -ETIMEDOUT if we didn't get an answer. */ 548 if (ret) 549 return ret; 550 551 raw_data = val & RESULT_VALUE_MASK; 552 tach_div = priv->type_fan_tach_clock_division[type]; 553 /* 554 * We need the mode to determine if the raw_data is double (from 555 * counting both edges). 556 */ 557 mode = priv->type_fan_tach_mode[type]; 558 both = (mode & BOTH_EDGES) ? 1 : 0; 559 560 tach_div = (0x4 << both) << (tach_div * 2); 561 clk_source = priv->clk_freq; 562 563 if (raw_data == 0) 564 return 0; 565 566 return (clk_source * 60) / (2 * raw_data * tach_div); 567 } 568 569 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr, 570 const char *buf, size_t count) 571 { 572 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 573 int index = sensor_attr->index; 574 int ret; 575 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 576 long fan_ctrl; 577 578 ret = kstrtol(buf, 10, &fan_ctrl); 579 if (ret != 0) 580 return ret; 581 582 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX) 583 return -EINVAL; 584 585 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl) 586 return count; 587 588 priv->pwm_port_fan_ctrl[index] = fan_ctrl; 589 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl); 590 591 return count; 592 } 593 594 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr, 595 char *buf) 596 { 597 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 598 int index = sensor_attr->index; 599 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 600 601 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]); 602 } 603 604 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr, 605 char *buf) 606 { 607 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 608 int index = sensor_attr->index; 609 int rpm; 610 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 611 612 rpm = aspeed_get_fan_tach_ch_rpm(priv, index); 613 if (rpm < 0) 614 return rpm; 615 616 return sprintf(buf, "%d\n", rpm); 617 } 618 619 static umode_t pwm_is_visible(struct kobject *kobj, 620 struct attribute *a, int index) 621 { 622 struct device *dev = kobj_to_dev(kobj); 623 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 624 625 if (!priv->pwm_present[index]) 626 return 0; 627 return a->mode; 628 } 629 630 static umode_t fan_dev_is_visible(struct kobject *kobj, 631 struct attribute *a, int index) 632 { 633 struct device *dev = kobj_to_dev(kobj); 634 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 635 636 if (!priv->fan_tach_present[index]) 637 return 0; 638 return a->mode; 639 } 640 641 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0); 642 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1); 643 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2); 644 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3); 645 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4); 646 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5); 647 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6); 648 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7); 649 static struct attribute *pwm_dev_attrs[] = { 650 &sensor_dev_attr_pwm1.dev_attr.attr, 651 &sensor_dev_attr_pwm2.dev_attr.attr, 652 &sensor_dev_attr_pwm3.dev_attr.attr, 653 &sensor_dev_attr_pwm4.dev_attr.attr, 654 &sensor_dev_attr_pwm5.dev_attr.attr, 655 &sensor_dev_attr_pwm6.dev_attr.attr, 656 &sensor_dev_attr_pwm7.dev_attr.attr, 657 &sensor_dev_attr_pwm8.dev_attr.attr, 658 NULL, 659 }; 660 661 static const struct attribute_group pwm_dev_group = { 662 .attrs = pwm_dev_attrs, 663 .is_visible = pwm_is_visible, 664 }; 665 666 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0); 667 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1); 668 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2); 669 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3); 670 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4); 671 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5); 672 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6); 673 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7); 674 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8); 675 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9); 676 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10); 677 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11); 678 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12); 679 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13); 680 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14); 681 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15); 682 static struct attribute *fan_dev_attrs[] = { 683 &sensor_dev_attr_fan1_input.dev_attr.attr, 684 &sensor_dev_attr_fan2_input.dev_attr.attr, 685 &sensor_dev_attr_fan3_input.dev_attr.attr, 686 &sensor_dev_attr_fan4_input.dev_attr.attr, 687 &sensor_dev_attr_fan5_input.dev_attr.attr, 688 &sensor_dev_attr_fan6_input.dev_attr.attr, 689 &sensor_dev_attr_fan7_input.dev_attr.attr, 690 &sensor_dev_attr_fan8_input.dev_attr.attr, 691 &sensor_dev_attr_fan9_input.dev_attr.attr, 692 &sensor_dev_attr_fan10_input.dev_attr.attr, 693 &sensor_dev_attr_fan11_input.dev_attr.attr, 694 &sensor_dev_attr_fan12_input.dev_attr.attr, 695 &sensor_dev_attr_fan13_input.dev_attr.attr, 696 &sensor_dev_attr_fan14_input.dev_attr.attr, 697 &sensor_dev_attr_fan15_input.dev_attr.attr, 698 &sensor_dev_attr_fan16_input.dev_attr.attr, 699 NULL 700 }; 701 702 static const struct attribute_group fan_dev_group = { 703 .attrs = fan_dev_attrs, 704 .is_visible = fan_dev_is_visible, 705 }; 706 707 /* 708 * The clock type is type M : 709 * The PWM frequency = 24MHz / (type M clock division L bit * 710 * type M clock division H bit * (type M PWM period bit + 1)) 711 */ 712 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv) 713 { 714 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H; 715 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L; 716 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD; 717 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H, 718 M_PWM_DIV_L, M_PWM_PERIOD); 719 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true); 720 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV; 721 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT; 722 priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE; 723 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE, 724 M_TACH_UNIT, M_TACH_CLK_DIV); 725 } 726 727 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv, 728 u8 pwm_port) 729 { 730 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true); 731 priv->pwm_present[pwm_port] = true; 732 733 priv->pwm_port_type[pwm_port] = TYPEM; 734 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM); 735 736 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL; 737 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL); 738 } 739 740 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv, 741 u8 *fan_tach_ch, 742 int count, 743 u8 pwm_source) 744 { 745 u8 val, index; 746 747 for (val = 0; val < count; val++) { 748 index = fan_tach_ch[val]; 749 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true); 750 priv->fan_tach_present[index] = true; 751 priv->fan_tach_ch_source[index] = pwm_source; 752 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source); 753 } 754 } 755 756 static int 757 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 758 unsigned long *state) 759 { 760 struct aspeed_cooling_device *cdev = tcdev->devdata; 761 762 *state = cdev->max_state; 763 764 return 0; 765 } 766 767 static int 768 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 769 unsigned long *state) 770 { 771 struct aspeed_cooling_device *cdev = tcdev->devdata; 772 773 *state = cdev->cur_state; 774 775 return 0; 776 } 777 778 static int 779 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 780 unsigned long state) 781 { 782 struct aspeed_cooling_device *cdev = tcdev->devdata; 783 784 if (state > cdev->max_state) 785 return -EINVAL; 786 787 cdev->cur_state = state; 788 cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] = 789 cdev->cooling_levels[cdev->cur_state]; 790 aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port, 791 cdev->cooling_levels[cdev->cur_state]); 792 793 return 0; 794 } 795 796 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = { 797 .get_max_state = aspeed_pwm_cz_get_max_state, 798 .get_cur_state = aspeed_pwm_cz_get_cur_state, 799 .set_cur_state = aspeed_pwm_cz_set_cur_state, 800 }; 801 802 static int aspeed_create_pwm_cooling(struct device *dev, 803 struct device_node *child, 804 struct aspeed_pwm_tacho_data *priv, 805 u32 pwm_port, u8 num_levels) 806 { 807 int ret; 808 struct aspeed_cooling_device *cdev; 809 810 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 811 812 if (!cdev) 813 return -ENOMEM; 814 815 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 816 if (!cdev->cooling_levels) 817 return -ENOMEM; 818 819 cdev->max_state = num_levels - 1; 820 ret = of_property_read_u8_array(child, "cooling-levels", 821 cdev->cooling_levels, 822 num_levels); 823 if (ret) { 824 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 825 return ret; 826 } 827 snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port); 828 829 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 830 cdev->name, cdev, &aspeed_pwm_cool_ops); 831 if (IS_ERR(cdev->tcdev)) 832 return PTR_ERR(cdev->tcdev); 833 834 cdev->priv = priv; 835 cdev->pwm_port = pwm_port; 836 837 priv->cdev[pwm_port] = cdev; 838 839 return 0; 840 } 841 842 static int aspeed_create_fan(struct device *dev, 843 struct device_node *child, 844 struct aspeed_pwm_tacho_data *priv) 845 { 846 u8 *fan_tach_ch; 847 u32 pwm_port; 848 int ret, count; 849 850 ret = of_property_read_u32(child, "reg", &pwm_port); 851 if (ret) 852 return ret; 853 if (pwm_port >= ARRAY_SIZE(pwm_port_params)) 854 return -EINVAL; 855 aspeed_create_pwm_port(priv, (u8)pwm_port); 856 857 ret = of_property_count_u8_elems(child, "cooling-levels"); 858 859 if (ret > 0) { 860 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port, 861 ret); 862 if (ret) 863 return ret; 864 } 865 866 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch"); 867 if (count < 1) 868 return -EINVAL; 869 fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch), 870 GFP_KERNEL); 871 if (!fan_tach_ch) 872 return -ENOMEM; 873 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch", 874 fan_tach_ch, count); 875 if (ret) 876 return ret; 877 aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port); 878 879 return 0; 880 } 881 882 static void aspeed_pwm_tacho_remove(void *data) 883 { 884 struct aspeed_pwm_tacho_data *priv = data; 885 886 reset_control_assert(priv->rst); 887 } 888 889 static int aspeed_pwm_tacho_probe(struct platform_device *pdev) 890 { 891 struct device *dev = &pdev->dev; 892 struct device_node *np, *child; 893 struct aspeed_pwm_tacho_data *priv; 894 void __iomem *regs; 895 struct device *hwmon; 896 struct clk *clk; 897 int ret; 898 899 np = dev->of_node; 900 regs = devm_platform_ioremap_resource(pdev, 0); 901 if (IS_ERR(regs)) 902 return PTR_ERR(regs); 903 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 904 if (!priv) 905 return -ENOMEM; 906 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs, 907 &aspeed_pwm_tacho_regmap_config); 908 if (IS_ERR(priv->regmap)) 909 return PTR_ERR(priv->regmap); 910 911 priv->rst = devm_reset_control_get_exclusive(dev, NULL); 912 if (IS_ERR(priv->rst)) { 913 dev_err(dev, 914 "missing or invalid reset controller device tree entry"); 915 return PTR_ERR(priv->rst); 916 } 917 reset_control_deassert(priv->rst); 918 919 ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv); 920 if (ret) 921 return ret; 922 923 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0); 924 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0); 925 926 clk = devm_clk_get(dev, NULL); 927 if (IS_ERR(clk)) 928 return -ENODEV; 929 priv->clk_freq = clk_get_rate(clk); 930 aspeed_set_clock_enable(priv->regmap, true); 931 aspeed_set_clock_source(priv->regmap, 0); 932 933 aspeed_create_type(priv); 934 935 for_each_child_of_node(np, child) { 936 ret = aspeed_create_fan(dev, child, priv); 937 if (ret) { 938 of_node_put(child); 939 return ret; 940 } 941 } 942 943 priv->groups[0] = &pwm_dev_group; 944 priv->groups[1] = &fan_dev_group; 945 priv->groups[2] = NULL; 946 hwmon = devm_hwmon_device_register_with_groups(dev, 947 "aspeed_pwm_tacho", 948 priv, priv->groups); 949 return PTR_ERR_OR_ZERO(hwmon); 950 } 951 952 static const struct of_device_id of_pwm_tacho_match_table[] = { 953 { .compatible = "aspeed,ast2400-pwm-tacho", }, 954 { .compatible = "aspeed,ast2500-pwm-tacho", }, 955 {}, 956 }; 957 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table); 958 959 static struct platform_driver aspeed_pwm_tacho_driver = { 960 .probe = aspeed_pwm_tacho_probe, 961 .driver = { 962 .name = "aspeed_pwm_tacho", 963 .of_match_table = of_pwm_tacho_match_table, 964 }, 965 }; 966 967 module_platform_driver(aspeed_pwm_tacho_driver); 968 969 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>"); 970 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver"); 971 MODULE_LICENSE("GPL"); 972