1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> 4 */ 5 6 #include <linux/component.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 11 #include <drm/drm_crtc_helper.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_simple_kms_helper.h> 14 15 #include "sun8i_dw_hdmi.h" 16 #include "sun8i_tcon_top.h" 17 18 static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder, 19 struct drm_display_mode *mode, 20 struct drm_display_mode *adj_mode) 21 { 22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); 23 24 if (hdmi->quirks->set_rate) 25 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); 26 } 27 28 static const struct drm_encoder_helper_funcs 29 sun8i_dw_hdmi_encoder_helper_funcs = { 30 .mode_set = sun8i_dw_hdmi_encoder_mode_set, 31 }; 32 33 static enum drm_mode_status 34 sun8i_dw_hdmi_mode_valid_a83t(struct drm_connector *connector, 35 const struct drm_display_mode *mode) 36 { 37 if (mode->clock > 297000) 38 return MODE_CLOCK_HIGH; 39 40 return MODE_OK; 41 } 42 43 static enum drm_mode_status 44 sun8i_dw_hdmi_mode_valid_h6(struct drm_connector *connector, 45 const struct drm_display_mode *mode) 46 { 47 /* 48 * Controller support maximum of 594 MHz, which correlates to 49 * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than 50 * 340 MHz scrambling has to be enabled. Because scrambling is 51 * not yet implemented, just limit to 340 MHz for now. 52 */ 53 if (mode->clock > 340000) 54 return MODE_CLOCK_HIGH; 55 56 return MODE_OK; 57 } 58 59 static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node) 60 { 61 return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 62 !!of_match_node(sun8i_tcon_top_of_table, node); 63 } 64 65 static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, 66 struct device_node *node) 67 { 68 struct device_node *port, *ep, *remote, *remote_port; 69 u32 crtcs = 0; 70 71 remote = of_graph_get_remote_node(node, 0, -1); 72 if (!remote) 73 return 0; 74 75 if (sun8i_dw_hdmi_node_is_tcon_top(remote)) { 76 port = of_graph_get_port_by_id(remote, 4); 77 if (!port) 78 goto crtcs_exit; 79 80 for_each_child_of_node(port, ep) { 81 remote_port = of_graph_get_remote_port(ep); 82 if (remote_port) { 83 crtcs |= drm_of_crtc_port_mask(drm, remote_port); 84 of_node_put(remote_port); 85 } 86 } 87 } else { 88 crtcs = drm_of_find_possible_crtcs(drm, node); 89 } 90 91 crtcs_exit: 92 of_node_put(remote); 93 94 return crtcs; 95 } 96 97 static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, 98 struct platform_device **pdev_out) 99 { 100 struct platform_device *pdev; 101 struct device_node *remote; 102 103 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 104 if (!remote) 105 return -ENODEV; 106 107 if (!of_device_is_compatible(remote, "hdmi-connector")) { 108 of_node_put(remote); 109 return -ENODEV; 110 } 111 112 pdev = of_find_device_by_node(remote); 113 of_node_put(remote); 114 if (!pdev) 115 return -ENODEV; 116 117 *pdev_out = pdev; 118 return 0; 119 } 120 121 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, 122 void *data) 123 { 124 struct platform_device *pdev = to_platform_device(dev), *connector_pdev; 125 struct dw_hdmi_plat_data *plat_data; 126 struct drm_device *drm = data; 127 struct device_node *phy_node; 128 struct drm_encoder *encoder; 129 struct sun8i_dw_hdmi *hdmi; 130 int ret; 131 132 if (!pdev->dev.of_node) 133 return -ENODEV; 134 135 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 136 if (!hdmi) 137 return -ENOMEM; 138 139 plat_data = &hdmi->plat_data; 140 hdmi->dev = &pdev->dev; 141 encoder = &hdmi->encoder; 142 143 hdmi->quirks = of_device_get_match_data(dev); 144 145 encoder->possible_crtcs = 146 sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node); 147 /* 148 * If we failed to find the CRTC(s) which this encoder is 149 * supposed to be connected to, it's because the CRTC has 150 * not been registered yet. Defer probing, and hope that 151 * the required CRTC is added later. 152 */ 153 if (encoder->possible_crtcs == 0) 154 return -EPROBE_DEFER; 155 156 hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl"); 157 if (IS_ERR(hdmi->rst_ctrl)) { 158 dev_err(dev, "Could not get ctrl reset control\n"); 159 return PTR_ERR(hdmi->rst_ctrl); 160 } 161 162 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); 163 if (IS_ERR(hdmi->clk_tmds)) { 164 dev_err(dev, "Couldn't get the tmds clock\n"); 165 return PTR_ERR(hdmi->clk_tmds); 166 } 167 168 hdmi->regulator = devm_regulator_get(dev, "hvcc"); 169 if (IS_ERR(hdmi->regulator)) { 170 dev_err(dev, "Couldn't get regulator\n"); 171 return PTR_ERR(hdmi->regulator); 172 } 173 174 ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev); 175 if (!ret) { 176 hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev, 177 "ddc-en", GPIOD_OUT_HIGH); 178 platform_device_put(connector_pdev); 179 180 if (IS_ERR(hdmi->ddc_en)) { 181 dev_err(dev, "Couldn't get ddc-en gpio\n"); 182 return PTR_ERR(hdmi->ddc_en); 183 } 184 } 185 186 ret = regulator_enable(hdmi->regulator); 187 if (ret) { 188 dev_err(dev, "Failed to enable regulator\n"); 189 goto err_unref_ddc_en; 190 } 191 192 gpiod_set_value(hdmi->ddc_en, 1); 193 194 ret = reset_control_deassert(hdmi->rst_ctrl); 195 if (ret) { 196 dev_err(dev, "Could not deassert ctrl reset control\n"); 197 goto err_disable_ddc_en; 198 } 199 200 ret = clk_prepare_enable(hdmi->clk_tmds); 201 if (ret) { 202 dev_err(dev, "Could not enable tmds clock\n"); 203 goto err_assert_ctrl_reset; 204 } 205 206 phy_node = of_parse_phandle(dev->of_node, "phys", 0); 207 if (!phy_node) { 208 dev_err(dev, "Can't found PHY phandle\n"); 209 goto err_disable_clk_tmds; 210 } 211 212 ret = sun8i_hdmi_phy_probe(hdmi, phy_node); 213 of_node_put(phy_node); 214 if (ret) { 215 dev_err(dev, "Couldn't get the HDMI PHY\n"); 216 goto err_disable_clk_tmds; 217 } 218 219 drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs); 220 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 221 222 sun8i_hdmi_phy_init(hdmi->phy); 223 224 plat_data->mode_valid = hdmi->quirks->mode_valid; 225 plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; 226 sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data); 227 228 platform_set_drvdata(pdev, hdmi); 229 230 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); 231 232 /* 233 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), 234 * which would have called the encoder cleanup. Do it manually. 235 */ 236 if (IS_ERR(hdmi->hdmi)) { 237 ret = PTR_ERR(hdmi->hdmi); 238 goto cleanup_encoder; 239 } 240 241 return 0; 242 243 cleanup_encoder: 244 drm_encoder_cleanup(encoder); 245 sun8i_hdmi_phy_remove(hdmi); 246 err_disable_clk_tmds: 247 clk_disable_unprepare(hdmi->clk_tmds); 248 err_assert_ctrl_reset: 249 reset_control_assert(hdmi->rst_ctrl); 250 err_disable_ddc_en: 251 gpiod_set_value(hdmi->ddc_en, 0); 252 regulator_disable(hdmi->regulator); 253 err_unref_ddc_en: 254 if (hdmi->ddc_en) 255 gpiod_put(hdmi->ddc_en); 256 257 return ret; 258 } 259 260 static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, 261 void *data) 262 { 263 struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); 264 265 dw_hdmi_unbind(hdmi->hdmi); 266 sun8i_hdmi_phy_remove(hdmi); 267 clk_disable_unprepare(hdmi->clk_tmds); 268 reset_control_assert(hdmi->rst_ctrl); 269 gpiod_set_value(hdmi->ddc_en, 0); 270 regulator_disable(hdmi->regulator); 271 272 if (hdmi->ddc_en) 273 gpiod_put(hdmi->ddc_en); 274 } 275 276 static const struct component_ops sun8i_dw_hdmi_ops = { 277 .bind = sun8i_dw_hdmi_bind, 278 .unbind = sun8i_dw_hdmi_unbind, 279 }; 280 281 static int sun8i_dw_hdmi_probe(struct platform_device *pdev) 282 { 283 return component_add(&pdev->dev, &sun8i_dw_hdmi_ops); 284 } 285 286 static int sun8i_dw_hdmi_remove(struct platform_device *pdev) 287 { 288 component_del(&pdev->dev, &sun8i_dw_hdmi_ops); 289 290 return 0; 291 } 292 293 static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = { 294 .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, 295 .set_rate = true, 296 }; 297 298 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { 299 .mode_valid = sun8i_dw_hdmi_mode_valid_h6, 300 .use_drm_infoframe = true, 301 }; 302 303 static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = { 304 { 305 .compatible = "allwinner,sun8i-a83t-dw-hdmi", 306 .data = &sun8i_a83t_quirks, 307 }, 308 { 309 .compatible = "allwinner,sun50i-h6-dw-hdmi", 310 .data = &sun50i_h6_quirks, 311 }, 312 { /* sentinel */ }, 313 }; 314 MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids); 315 316 static struct platform_driver sun8i_dw_hdmi_pltfm_driver = { 317 .probe = sun8i_dw_hdmi_probe, 318 .remove = sun8i_dw_hdmi_remove, 319 .driver = { 320 .name = "sun8i-dw-hdmi", 321 .of_match_table = sun8i_dw_hdmi_dt_ids, 322 }, 323 }; 324 module_platform_driver(sun8i_dw_hdmi_pltfm_driver); 325 326 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>"); 327 MODULE_DESCRIPTION("Allwinner DW HDMI bridge"); 328 MODULE_LICENSE("GPL"); 329