1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 51 /* 52 * r100,rv100,rs100,rv200,rs200 53 */ 54 struct r100_mc_save { 55 u32 GENMO_WT; 56 u32 CRTC_EXT_CNTL; 57 u32 CRTC_GEN_CNTL; 58 u32 CRTC2_GEN_CNTL; 59 u32 CUR_OFFSET; 60 u32 CUR2_OFFSET; 61 }; 62 int r100_init(struct radeon_device *rdev); 63 void r100_fini(struct radeon_device *rdev); 64 int r100_suspend(struct radeon_device *rdev); 65 int r100_resume(struct radeon_device *rdev); 66 void r100_vga_set_state(struct radeon_device *rdev, bool state); 67 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 68 int r100_asic_reset(struct radeon_device *rdev); 69 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 70 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 71 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 72 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 73 int r100_irq_set(struct radeon_device *rdev); 74 int r100_irq_process(struct radeon_device *rdev); 75 void r100_fence_ring_emit(struct radeon_device *rdev, 76 struct radeon_fence *fence); 77 void r100_semaphore_ring_emit(struct radeon_device *rdev, 78 struct radeon_ring *cp, 79 struct radeon_semaphore *semaphore, 80 bool emit_wait); 81 int r100_cs_parse(struct radeon_cs_parser *p); 82 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 83 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 84 int r100_copy_blit(struct radeon_device *rdev, 85 uint64_t src_offset, 86 uint64_t dst_offset, 87 unsigned num_gpu_pages, 88 struct radeon_fence **fence); 89 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 90 uint32_t tiling_flags, uint32_t pitch, 91 uint32_t offset, uint32_t obj_size); 92 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 93 void r100_bandwidth_update(struct radeon_device *rdev); 94 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 95 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 96 void r100_hpd_init(struct radeon_device *rdev); 97 void r100_hpd_fini(struct radeon_device *rdev); 98 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 99 void r100_hpd_set_polarity(struct radeon_device *rdev, 100 enum radeon_hpd_id hpd); 101 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 102 int r100_debugfs_cp_init(struct radeon_device *rdev); 103 void r100_cp_disable(struct radeon_device *rdev); 104 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 105 void r100_cp_fini(struct radeon_device *rdev); 106 int r100_pci_gart_init(struct radeon_device *rdev); 107 void r100_pci_gart_fini(struct radeon_device *rdev); 108 int r100_pci_gart_enable(struct radeon_device *rdev); 109 void r100_pci_gart_disable(struct radeon_device *rdev); 110 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 111 int r100_gui_wait_for_idle(struct radeon_device *rdev); 112 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 113 void r100_irq_disable(struct radeon_device *rdev); 114 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_vram_init_sizes(struct radeon_device *rdev); 117 int r100_cp_reset(struct radeon_device *rdev); 118 void r100_vga_render_disable(struct radeon_device *rdev); 119 void r100_restore_sanity(struct radeon_device *rdev); 120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127 int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130 void r100_enable_bm(struct radeon_device *rdev); 131 void r100_set_common_regs(struct radeon_device *rdev); 132 void r100_bm_disable(struct radeon_device *rdev); 133 extern bool r100_gui_idle(struct radeon_device *rdev); 134 extern void r100_pm_misc(struct radeon_device *rdev); 135 extern void r100_pm_prepare(struct radeon_device *rdev); 136 extern void r100_pm_finish(struct radeon_device *rdev); 137 extern void r100_pm_init_profile(struct radeon_device *rdev); 138 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 140 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 141 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 142 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 143 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 144 145 /* 146 * r200,rv250,rs300,rv280 147 */ 148 extern int r200_copy_dma(struct radeon_device *rdev, 149 uint64_t src_offset, 150 uint64_t dst_offset, 151 unsigned num_gpu_pages, 152 struct radeon_fence **fence); 153 void r200_set_safe_registers(struct radeon_device *rdev); 154 155 /* 156 * r300,r350,rv350,rv380 157 */ 158 extern int r300_init(struct radeon_device *rdev); 159 extern void r300_fini(struct radeon_device *rdev); 160 extern int r300_suspend(struct radeon_device *rdev); 161 extern int r300_resume(struct radeon_device *rdev); 162 extern int r300_asic_reset(struct radeon_device *rdev); 163 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 164 extern void r300_fence_ring_emit(struct radeon_device *rdev, 165 struct radeon_fence *fence); 166 extern int r300_cs_parse(struct radeon_cs_parser *p); 167 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 168 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 169 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 170 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 171 extern void r300_set_reg_safe(struct radeon_device *rdev); 172 extern void r300_mc_program(struct radeon_device *rdev); 173 extern void r300_mc_init(struct radeon_device *rdev); 174 extern void r300_clock_startup(struct radeon_device *rdev); 175 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 176 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 177 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 178 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 179 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 180 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 181 182 /* 183 * r420,r423,rv410 184 */ 185 extern int r420_init(struct radeon_device *rdev); 186 extern void r420_fini(struct radeon_device *rdev); 187 extern int r420_suspend(struct radeon_device *rdev); 188 extern int r420_resume(struct radeon_device *rdev); 189 extern void r420_pm_init_profile(struct radeon_device *rdev); 190 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 191 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 192 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 193 extern void r420_pipes_init(struct radeon_device *rdev); 194 195 /* 196 * rs400,rs480 197 */ 198 extern int rs400_init(struct radeon_device *rdev); 199 extern void rs400_fini(struct radeon_device *rdev); 200 extern int rs400_suspend(struct radeon_device *rdev); 201 extern int rs400_resume(struct radeon_device *rdev); 202 void rs400_gart_tlb_flush(struct radeon_device *rdev); 203 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 204 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 205 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 206 int rs400_gart_init(struct radeon_device *rdev); 207 int rs400_gart_enable(struct radeon_device *rdev); 208 void rs400_gart_adjust_size(struct radeon_device *rdev); 209 void rs400_gart_disable(struct radeon_device *rdev); 210 void rs400_gart_fini(struct radeon_device *rdev); 211 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 212 213 /* 214 * rs600. 215 */ 216 extern int rs600_asic_reset(struct radeon_device *rdev); 217 extern int rs600_init(struct radeon_device *rdev); 218 extern void rs600_fini(struct radeon_device *rdev); 219 extern int rs600_suspend(struct radeon_device *rdev); 220 extern int rs600_resume(struct radeon_device *rdev); 221 int rs600_irq_set(struct radeon_device *rdev); 222 int rs600_irq_process(struct radeon_device *rdev); 223 void rs600_irq_disable(struct radeon_device *rdev); 224 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 225 void rs600_gart_tlb_flush(struct radeon_device *rdev); 226 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 227 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 228 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 229 void rs600_bandwidth_update(struct radeon_device *rdev); 230 void rs600_hpd_init(struct radeon_device *rdev); 231 void rs600_hpd_fini(struct radeon_device *rdev); 232 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 233 void rs600_hpd_set_polarity(struct radeon_device *rdev, 234 enum radeon_hpd_id hpd); 235 extern void rs600_pm_misc(struct radeon_device *rdev); 236 extern void rs600_pm_prepare(struct radeon_device *rdev); 237 extern void rs600_pm_finish(struct radeon_device *rdev); 238 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 239 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 240 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 241 void rs600_set_safe_registers(struct radeon_device *rdev); 242 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 243 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 244 245 /* 246 * rs690,rs740 247 */ 248 int rs690_init(struct radeon_device *rdev); 249 void rs690_fini(struct radeon_device *rdev); 250 int rs690_resume(struct radeon_device *rdev); 251 int rs690_suspend(struct radeon_device *rdev); 252 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 253 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 254 void rs690_bandwidth_update(struct radeon_device *rdev); 255 void rs690_line_buffer_adjust(struct radeon_device *rdev, 256 struct drm_display_mode *mode1, 257 struct drm_display_mode *mode2); 258 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 259 260 /* 261 * rv515 262 */ 263 struct rv515_mc_save { 264 u32 vga_render_control; 265 u32 vga_hdp_control; 266 bool crtc_enabled[2]; 267 }; 268 269 int rv515_init(struct radeon_device *rdev); 270 void rv515_fini(struct radeon_device *rdev); 271 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 272 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 273 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 274 void rv515_bandwidth_update(struct radeon_device *rdev); 275 int rv515_resume(struct radeon_device *rdev); 276 int rv515_suspend(struct radeon_device *rdev); 277 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 278 void rv515_vga_render_disable(struct radeon_device *rdev); 279 void rv515_set_safe_registers(struct radeon_device *rdev); 280 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 281 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 282 void rv515_clock_startup(struct radeon_device *rdev); 283 void rv515_debugfs(struct radeon_device *rdev); 284 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 285 286 /* 287 * r520,rv530,rv560,rv570,r580 288 */ 289 int r520_init(struct radeon_device *rdev); 290 int r520_resume(struct radeon_device *rdev); 291 int r520_mc_wait_for_idle(struct radeon_device *rdev); 292 293 /* 294 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 295 */ 296 int r600_init(struct radeon_device *rdev); 297 void r600_fini(struct radeon_device *rdev); 298 int r600_suspend(struct radeon_device *rdev); 299 int r600_resume(struct radeon_device *rdev); 300 void r600_vga_set_state(struct radeon_device *rdev, bool state); 301 int r600_wb_init(struct radeon_device *rdev); 302 void r600_wb_fini(struct radeon_device *rdev); 303 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 304 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 305 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 306 int r600_cs_parse(struct radeon_cs_parser *p); 307 int r600_dma_cs_parse(struct radeon_cs_parser *p); 308 void r600_fence_ring_emit(struct radeon_device *rdev, 309 struct radeon_fence *fence); 310 void r600_semaphore_ring_emit(struct radeon_device *rdev, 311 struct radeon_ring *cp, 312 struct radeon_semaphore *semaphore, 313 bool emit_wait); 314 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 315 struct radeon_fence *fence); 316 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 317 struct radeon_ring *ring, 318 struct radeon_semaphore *semaphore, 319 bool emit_wait); 320 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 321 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 322 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 323 int r600_asic_reset(struct radeon_device *rdev); 324 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 325 uint32_t tiling_flags, uint32_t pitch, 326 uint32_t offset, uint32_t obj_size); 327 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 328 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 329 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 330 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 331 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 332 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 333 int r600_copy_blit(struct radeon_device *rdev, 334 uint64_t src_offset, uint64_t dst_offset, 335 unsigned num_gpu_pages, struct radeon_fence **fence); 336 int r600_copy_dma(struct radeon_device *rdev, 337 uint64_t src_offset, uint64_t dst_offset, 338 unsigned num_gpu_pages, struct radeon_fence **fence); 339 void r600_hpd_init(struct radeon_device *rdev); 340 void r600_hpd_fini(struct radeon_device *rdev); 341 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 342 void r600_hpd_set_polarity(struct radeon_device *rdev, 343 enum radeon_hpd_id hpd); 344 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 345 extern bool r600_gui_idle(struct radeon_device *rdev); 346 extern void r600_pm_misc(struct radeon_device *rdev); 347 extern void r600_pm_init_profile(struct radeon_device *rdev); 348 extern void rs780_pm_init_profile(struct radeon_device *rdev); 349 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 350 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 351 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 352 bool r600_card_posted(struct radeon_device *rdev); 353 void r600_cp_stop(struct radeon_device *rdev); 354 int r600_cp_start(struct radeon_device *rdev); 355 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 356 int r600_cp_resume(struct radeon_device *rdev); 357 void r600_cp_fini(struct radeon_device *rdev); 358 int r600_count_pipe_bits(uint32_t val); 359 int r600_mc_wait_for_idle(struct radeon_device *rdev); 360 int r600_pcie_gart_init(struct radeon_device *rdev); 361 void r600_scratch_init(struct radeon_device *rdev); 362 int r600_blit_init(struct radeon_device *rdev); 363 void r600_blit_fini(struct radeon_device *rdev); 364 int r600_init_microcode(struct radeon_device *rdev); 365 /* r600 irq */ 366 int r600_irq_process(struct radeon_device *rdev); 367 int r600_irq_init(struct radeon_device *rdev); 368 void r600_irq_fini(struct radeon_device *rdev); 369 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 370 int r600_irq_set(struct radeon_device *rdev); 371 void r600_irq_suspend(struct radeon_device *rdev); 372 void r600_disable_interrupts(struct radeon_device *rdev); 373 void r600_rlc_stop(struct radeon_device *rdev); 374 /* r600 audio */ 375 int r600_audio_init(struct radeon_device *rdev); 376 void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 377 struct r600_audio r600_audio_status(struct radeon_device *rdev); 378 void r600_audio_fini(struct radeon_device *rdev); 379 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 380 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 381 /* r600 blit */ 382 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 383 struct radeon_fence **fence, struct radeon_sa_bo **vb, 384 struct radeon_semaphore **sem); 385 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 386 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 387 void r600_kms_blit_copy(struct radeon_device *rdev, 388 u64 src_gpu_addr, u64 dst_gpu_addr, 389 unsigned num_gpu_pages, 390 struct radeon_sa_bo *vb); 391 int r600_mc_wait_for_idle(struct radeon_device *rdev); 392 u32 r600_get_xclk(struct radeon_device *rdev); 393 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 394 395 /* 396 * rv770,rv730,rv710,rv740 397 */ 398 int rv770_init(struct radeon_device *rdev); 399 void rv770_fini(struct radeon_device *rdev); 400 int rv770_suspend(struct radeon_device *rdev); 401 int rv770_resume(struct radeon_device *rdev); 402 void rv770_pm_misc(struct radeon_device *rdev); 403 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 404 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 405 void r700_cp_stop(struct radeon_device *rdev); 406 void r700_cp_fini(struct radeon_device *rdev); 407 int rv770_copy_dma(struct radeon_device *rdev, 408 uint64_t src_offset, uint64_t dst_offset, 409 unsigned num_gpu_pages, 410 struct radeon_fence **fence); 411 u32 rv770_get_xclk(struct radeon_device *rdev); 412 413 /* 414 * evergreen 415 */ 416 struct evergreen_mc_save { 417 u32 vga_render_control; 418 u32 vga_hdp_control; 419 bool crtc_enabled[RADEON_MAX_CRTCS]; 420 }; 421 422 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 423 int evergreen_init(struct radeon_device *rdev); 424 void evergreen_fini(struct radeon_device *rdev); 425 int evergreen_suspend(struct radeon_device *rdev); 426 int evergreen_resume(struct radeon_device *rdev); 427 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 428 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 429 int evergreen_asic_reset(struct radeon_device *rdev); 430 void evergreen_bandwidth_update(struct radeon_device *rdev); 431 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 432 void evergreen_hpd_init(struct radeon_device *rdev); 433 void evergreen_hpd_fini(struct radeon_device *rdev); 434 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 435 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 436 enum radeon_hpd_id hpd); 437 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 438 int evergreen_irq_set(struct radeon_device *rdev); 439 int evergreen_irq_process(struct radeon_device *rdev); 440 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 441 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 442 extern void evergreen_pm_misc(struct radeon_device *rdev); 443 extern void evergreen_pm_prepare(struct radeon_device *rdev); 444 extern void evergreen_pm_finish(struct radeon_device *rdev); 445 extern void sumo_pm_init_profile(struct radeon_device *rdev); 446 extern void btc_pm_init_profile(struct radeon_device *rdev); 447 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 448 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 449 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 450 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 451 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 452 int evergreen_blit_init(struct radeon_device *rdev); 453 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 454 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 455 struct radeon_fence *fence); 456 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 457 struct radeon_ib *ib); 458 int evergreen_copy_dma(struct radeon_device *rdev, 459 uint64_t src_offset, uint64_t dst_offset, 460 unsigned num_gpu_pages, 461 struct radeon_fence **fence); 462 463 /* 464 * cayman 465 */ 466 void cayman_fence_ring_emit(struct radeon_device *rdev, 467 struct radeon_fence *fence); 468 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 469 int cayman_init(struct radeon_device *rdev); 470 void cayman_fini(struct radeon_device *rdev); 471 int cayman_suspend(struct radeon_device *rdev); 472 int cayman_resume(struct radeon_device *rdev); 473 int cayman_asic_reset(struct radeon_device *rdev); 474 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 475 int cayman_vm_init(struct radeon_device *rdev); 476 void cayman_vm_fini(struct radeon_device *rdev); 477 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 478 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 479 void cayman_vm_set_page(struct radeon_device *rdev, 480 struct radeon_ib *ib, 481 uint64_t pe, 482 uint64_t addr, unsigned count, 483 uint32_t incr, uint32_t flags); 484 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 485 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 486 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 487 struct radeon_ib *ib); 488 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 489 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 490 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 491 492 /* DCE6 - SI */ 493 void dce6_bandwidth_update(struct radeon_device *rdev); 494 495 /* 496 * si 497 */ 498 void si_fence_ring_emit(struct radeon_device *rdev, 499 struct radeon_fence *fence); 500 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 501 int si_init(struct radeon_device *rdev); 502 void si_fini(struct radeon_device *rdev); 503 int si_suspend(struct radeon_device *rdev); 504 int si_resume(struct radeon_device *rdev); 505 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 506 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 507 int si_asic_reset(struct radeon_device *rdev); 508 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 509 int si_irq_set(struct radeon_device *rdev); 510 int si_irq_process(struct radeon_device *rdev); 511 int si_vm_init(struct radeon_device *rdev); 512 void si_vm_fini(struct radeon_device *rdev); 513 void si_vm_set_page(struct radeon_device *rdev, 514 struct radeon_ib *ib, 515 uint64_t pe, 516 uint64_t addr, unsigned count, 517 uint32_t incr, uint32_t flags); 518 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 519 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 520 int si_copy_dma(struct radeon_device *rdev, 521 uint64_t src_offset, uint64_t dst_offset, 522 unsigned num_gpu_pages, 523 struct radeon_fence **fence); 524 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 525 u32 si_get_xclk(struct radeon_device *rdev); 526 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 527 528 #endif 529