1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 #include <drm/drm_crtc_helper.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_drm.h" 37 #include "r100_track.h" 38 #include "r300d.h" 39 #include "rv350d.h" 40 #include "r300_reg_safe.h" 41 42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 43 * 44 * GPU Errata: 45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 47 * However, scheduling such write to the ring seems harmless, i suspect 48 * the CP read collide with the flush somehow, or maybe the MC, hard to 49 * tell. (Jerome Glisse) 50 */ 51 52 /* 53 * rv370,rv380 PCIE GART 54 */ 55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 56 57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 58 { 59 uint32_t tmp; 60 int i; 61 62 /* Workaround HW bug do flush 2 times */ 63 for (i = 0; i < 2; i++) { 64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 68 } 69 mb(); 70 } 71 72 #define R300_PTE_WRITEABLE (1 << 2) 73 #define R300_PTE_READABLE (1 << 3) 74 75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 76 { 77 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 78 79 if (i < 0 || i > rdev->gart.num_gpu_pages) { 80 return -EINVAL; 81 } 82 addr = (lower_32_bits(addr) >> 8) | 83 ((upper_32_bits(addr) & 0xff) << 24) | 84 R300_PTE_WRITEABLE | R300_PTE_READABLE; 85 /* on x86 we want this to be CPU endian, on powerpc 86 * on powerpc without HW swappers, it'll get swapped on way 87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 88 writel(addr, ((void __iomem *)ptr) + (i * 4)); 89 return 0; 90 } 91 92 int rv370_pcie_gart_init(struct radeon_device *rdev) 93 { 94 int r; 95 96 if (rdev->gart.table.vram.robj) { 97 WARN(1, "RV370 PCIE GART already initialized\n"); 98 return 0; 99 } 100 /* Initialize common gart structure */ 101 r = radeon_gart_init(rdev); 102 if (r) 103 return r; 104 r = rv370_debugfs_pcie_gart_info_init(rdev); 105 if (r) 106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 108 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 109 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 110 return radeon_gart_table_vram_alloc(rdev); 111 } 112 113 int rv370_pcie_gart_enable(struct radeon_device *rdev) 114 { 115 uint32_t table_addr; 116 uint32_t tmp; 117 int r; 118 119 if (rdev->gart.table.vram.robj == NULL) { 120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 121 return -EINVAL; 122 } 123 r = radeon_gart_table_vram_pin(rdev); 124 if (r) 125 return r; 126 radeon_gart_restore(rdev); 127 /* discard memory request outside of configured range */ 128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 135 table_addr = rdev->gart.table_addr; 136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 137 /* FIXME: setup default page */ 138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 140 /* Clear error */ 141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 143 tmp |= RADEON_PCIE_TX_GART_EN; 144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 146 rv370_pcie_gart_tlb_flush(rdev); 147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", 148 (unsigned)(rdev->mc.gtt_size >> 20), table_addr); 149 rdev->gart.ready = true; 150 return 0; 151 } 152 153 void rv370_pcie_gart_disable(struct radeon_device *rdev) 154 { 155 u32 tmp; 156 int r; 157 158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 165 if (rdev->gart.table.vram.robj) { 166 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 167 if (likely(r == 0)) { 168 radeon_bo_kunmap(rdev->gart.table.vram.robj); 169 radeon_bo_unpin(rdev->gart.table.vram.robj); 170 radeon_bo_unreserve(rdev->gart.table.vram.robj); 171 } 172 } 173 } 174 175 void rv370_pcie_gart_fini(struct radeon_device *rdev) 176 { 177 radeon_gart_fini(rdev); 178 rv370_pcie_gart_disable(rdev); 179 radeon_gart_table_vram_free(rdev); 180 } 181 182 void r300_fence_ring_emit(struct radeon_device *rdev, 183 struct radeon_fence *fence) 184 { 185 /* Who ever call radeon_fence_emit should call ring_lock and ask 186 * for enough space (today caller are ib schedule and buffer move) */ 187 /* Write SC register so SC & US assert idle */ 188 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); 189 radeon_ring_write(rdev, 0); 190 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); 191 radeon_ring_write(rdev, 0); 192 /* Flush 3D cache */ 193 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 194 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); 195 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 196 radeon_ring_write(rdev, R300_ZC_FLUSH); 197 /* Wait until IDLE & CLEAN */ 198 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 199 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | 200 RADEON_WAIT_2D_IDLECLEAN | 201 RADEON_WAIT_DMA_GUI_IDLE)); 202 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 203 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | 204 RADEON_HDP_READ_BUFFER_INVALIDATE); 205 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 206 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); 207 /* Emit fence sequence & fire IRQ */ 208 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 209 radeon_ring_write(rdev, fence->seq); 210 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 211 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 212 } 213 214 void r300_ring_start(struct radeon_device *rdev) 215 { 216 unsigned gb_tile_config; 217 int r; 218 219 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 220 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 221 switch(rdev->num_gb_pipes) { 222 case 2: 223 gb_tile_config |= R300_PIPE_COUNT_R300; 224 break; 225 case 3: 226 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 227 break; 228 case 4: 229 gb_tile_config |= R300_PIPE_COUNT_R420; 230 break; 231 case 1: 232 default: 233 gb_tile_config |= R300_PIPE_COUNT_RV350; 234 break; 235 } 236 237 r = radeon_ring_lock(rdev, 64); 238 if (r) { 239 return; 240 } 241 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 242 radeon_ring_write(rdev, 243 RADEON_ISYNC_ANY2D_IDLE3D | 244 RADEON_ISYNC_ANY3D_IDLE2D | 245 RADEON_ISYNC_WAIT_IDLEGUI | 246 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 247 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 248 radeon_ring_write(rdev, gb_tile_config); 249 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 250 radeon_ring_write(rdev, 251 RADEON_WAIT_2D_IDLECLEAN | 252 RADEON_WAIT_3D_IDLECLEAN); 253 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); 254 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); 255 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 256 radeon_ring_write(rdev, 0); 257 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 258 radeon_ring_write(rdev, 0); 259 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 260 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 261 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 262 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 263 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 264 radeon_ring_write(rdev, 265 RADEON_WAIT_2D_IDLECLEAN | 266 RADEON_WAIT_3D_IDLECLEAN); 267 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 268 radeon_ring_write(rdev, 0); 269 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 270 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 271 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 272 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 273 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 274 radeon_ring_write(rdev, 275 ((6 << R300_MS_X0_SHIFT) | 276 (6 << R300_MS_Y0_SHIFT) | 277 (6 << R300_MS_X1_SHIFT) | 278 (6 << R300_MS_Y1_SHIFT) | 279 (6 << R300_MS_X2_SHIFT) | 280 (6 << R300_MS_Y2_SHIFT) | 281 (6 << R300_MSBD0_Y_SHIFT) | 282 (6 << R300_MSBD0_X_SHIFT))); 283 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 284 radeon_ring_write(rdev, 285 ((6 << R300_MS_X3_SHIFT) | 286 (6 << R300_MS_Y3_SHIFT) | 287 (6 << R300_MS_X4_SHIFT) | 288 (6 << R300_MS_Y4_SHIFT) | 289 (6 << R300_MS_X5_SHIFT) | 290 (6 << R300_MS_Y5_SHIFT) | 291 (6 << R300_MSBD1_SHIFT))); 292 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 293 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 294 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 295 radeon_ring_write(rdev, 296 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 297 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 298 radeon_ring_write(rdev, 299 R300_GEOMETRY_ROUND_NEAREST | 300 R300_COLOR_ROUND_NEAREST); 301 radeon_ring_unlock_commit(rdev); 302 } 303 304 void r300_errata(struct radeon_device *rdev) 305 { 306 rdev->pll_errata = 0; 307 308 if (rdev->family == CHIP_R300 && 309 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 310 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 311 } 312 } 313 314 int r300_mc_wait_for_idle(struct radeon_device *rdev) 315 { 316 unsigned i; 317 uint32_t tmp; 318 319 for (i = 0; i < rdev->usec_timeout; i++) { 320 /* read MC_STATUS */ 321 tmp = RREG32(RADEON_MC_STATUS); 322 if (tmp & R300_MC_IDLE) { 323 return 0; 324 } 325 DRM_UDELAY(1); 326 } 327 return -1; 328 } 329 330 void r300_gpu_init(struct radeon_device *rdev) 331 { 332 uint32_t gb_tile_config, tmp; 333 334 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 335 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 336 /* r300,r350 */ 337 rdev->num_gb_pipes = 2; 338 } else { 339 /* rv350,rv370,rv380,r300 AD, r350 AH */ 340 rdev->num_gb_pipes = 1; 341 } 342 rdev->num_z_pipes = 1; 343 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 344 switch (rdev->num_gb_pipes) { 345 case 2: 346 gb_tile_config |= R300_PIPE_COUNT_R300; 347 break; 348 case 3: 349 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 350 break; 351 case 4: 352 gb_tile_config |= R300_PIPE_COUNT_R420; 353 break; 354 default: 355 case 1: 356 gb_tile_config |= R300_PIPE_COUNT_RV350; 357 break; 358 } 359 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 360 361 if (r100_gui_wait_for_idle(rdev)) { 362 printk(KERN_WARNING "Failed to wait GUI idle while " 363 "programming pipes. Bad things might happen.\n"); 364 } 365 366 tmp = RREG32(R300_DST_PIPE_CONFIG); 367 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 368 369 WREG32(R300_RB2D_DSTCACHE_MODE, 370 R300_DC_AUTOFLUSH_ENABLE | 371 R300_DC_DC_DISABLE_IGNORE_PE); 372 373 if (r100_gui_wait_for_idle(rdev)) { 374 printk(KERN_WARNING "Failed to wait GUI idle while " 375 "programming pipes. Bad things might happen.\n"); 376 } 377 if (r300_mc_wait_for_idle(rdev)) { 378 printk(KERN_WARNING "Failed to wait MC idle while " 379 "programming pipes. Bad things might happen.\n"); 380 } 381 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 382 rdev->num_gb_pipes, rdev->num_z_pipes); 383 } 384 385 bool r300_gpu_is_lockup(struct radeon_device *rdev) 386 { 387 u32 rbbm_status; 388 int r; 389 390 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 391 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 392 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 393 return false; 394 } 395 /* force CP activities */ 396 r = radeon_ring_lock(rdev, 2); 397 if (!r) { 398 /* PACKET2 NOP */ 399 radeon_ring_write(rdev, 0x80000000); 400 radeon_ring_write(rdev, 0x80000000); 401 radeon_ring_unlock_commit(rdev); 402 } 403 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 404 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 405 } 406 407 int r300_asic_reset(struct radeon_device *rdev) 408 { 409 struct r100_mc_save save; 410 u32 status, tmp; 411 int ret = 0; 412 413 status = RREG32(R_000E40_RBBM_STATUS); 414 if (!G_000E40_GUI_ACTIVE(status)) { 415 return 0; 416 } 417 r100_mc_stop(rdev, &save); 418 status = RREG32(R_000E40_RBBM_STATUS); 419 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 420 /* stop CP */ 421 WREG32(RADEON_CP_CSQ_CNTL, 0); 422 tmp = RREG32(RADEON_CP_RB_CNTL); 423 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 424 WREG32(RADEON_CP_RB_RPTR_WR, 0); 425 WREG32(RADEON_CP_RB_WPTR, 0); 426 WREG32(RADEON_CP_RB_CNTL, tmp); 427 /* save PCI state */ 428 pci_save_state(rdev->pdev); 429 /* disable bus mastering */ 430 r100_bm_disable(rdev); 431 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 432 S_0000F0_SOFT_RESET_GA(1)); 433 RREG32(R_0000F0_RBBM_SOFT_RESET); 434 mdelay(500); 435 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 436 mdelay(1); 437 status = RREG32(R_000E40_RBBM_STATUS); 438 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 439 /* resetting the CP seems to be problematic sometimes it end up 440 * hard locking the computer, but it's necessary for successfull 441 * reset more test & playing is needed on R3XX/R4XX to find a 442 * reliable (if any solution) 443 */ 444 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 445 RREG32(R_0000F0_RBBM_SOFT_RESET); 446 mdelay(500); 447 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 448 mdelay(1); 449 status = RREG32(R_000E40_RBBM_STATUS); 450 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 451 /* restore PCI & busmastering */ 452 pci_restore_state(rdev->pdev); 453 r100_enable_bm(rdev); 454 /* Check if GPU is idle */ 455 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 456 dev_err(rdev->dev, "failed to reset GPU\n"); 457 rdev->gpu_lockup = true; 458 ret = -1; 459 } else 460 dev_info(rdev->dev, "GPU reset succeed\n"); 461 r100_mc_resume(rdev, &save); 462 return ret; 463 } 464 465 /* 466 * r300,r350,rv350,rv380 VRAM info 467 */ 468 void r300_mc_init(struct radeon_device *rdev) 469 { 470 u64 base; 471 u32 tmp; 472 473 /* DDR for all card after R300 & IGP */ 474 rdev->mc.vram_is_ddr = true; 475 tmp = RREG32(RADEON_MEM_CNTL); 476 tmp &= R300_MEM_NUM_CHANNELS_MASK; 477 switch (tmp) { 478 case 0: rdev->mc.vram_width = 64; break; 479 case 1: rdev->mc.vram_width = 128; break; 480 case 2: rdev->mc.vram_width = 256; break; 481 default: rdev->mc.vram_width = 128; break; 482 } 483 r100_vram_init_sizes(rdev); 484 base = rdev->mc.aper_base; 485 if (rdev->flags & RADEON_IS_IGP) 486 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 487 radeon_vram_location(rdev, &rdev->mc, base); 488 rdev->mc.gtt_base_align = 0; 489 if (!(rdev->flags & RADEON_IS_AGP)) 490 radeon_gtt_location(rdev, &rdev->mc); 491 radeon_update_bandwidth_info(rdev); 492 } 493 494 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 495 { 496 uint32_t link_width_cntl, mask; 497 498 if (rdev->flags & RADEON_IS_IGP) 499 return; 500 501 if (!(rdev->flags & RADEON_IS_PCIE)) 502 return; 503 504 /* FIXME wait for idle */ 505 506 switch (lanes) { 507 case 0: 508 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 509 break; 510 case 1: 511 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 512 break; 513 case 2: 514 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 515 break; 516 case 4: 517 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 518 break; 519 case 8: 520 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 521 break; 522 case 12: 523 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 524 break; 525 case 16: 526 default: 527 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 528 break; 529 } 530 531 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 532 533 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 534 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 535 return; 536 537 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 538 RADEON_PCIE_LC_RECONFIG_NOW | 539 RADEON_PCIE_LC_RECONFIG_LATER | 540 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 541 link_width_cntl |= mask; 542 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 543 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 544 RADEON_PCIE_LC_RECONFIG_NOW)); 545 546 /* wait for lane set to complete */ 547 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 548 while (link_width_cntl == 0xffffffff) 549 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 550 551 } 552 553 int rv370_get_pcie_lanes(struct radeon_device *rdev) 554 { 555 u32 link_width_cntl; 556 557 if (rdev->flags & RADEON_IS_IGP) 558 return 0; 559 560 if (!(rdev->flags & RADEON_IS_PCIE)) 561 return 0; 562 563 /* FIXME wait for idle */ 564 565 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 566 567 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 568 case RADEON_PCIE_LC_LINK_WIDTH_X0: 569 return 0; 570 case RADEON_PCIE_LC_LINK_WIDTH_X1: 571 return 1; 572 case RADEON_PCIE_LC_LINK_WIDTH_X2: 573 return 2; 574 case RADEON_PCIE_LC_LINK_WIDTH_X4: 575 return 4; 576 case RADEON_PCIE_LC_LINK_WIDTH_X8: 577 return 8; 578 case RADEON_PCIE_LC_LINK_WIDTH_X16: 579 default: 580 return 16; 581 } 582 } 583 584 #if defined(CONFIG_DEBUG_FS) 585 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 586 { 587 struct drm_info_node *node = (struct drm_info_node *) m->private; 588 struct drm_device *dev = node->minor->dev; 589 struct radeon_device *rdev = dev->dev_private; 590 uint32_t tmp; 591 592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 593 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 595 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 597 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 599 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 601 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 603 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 604 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 605 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 606 return 0; 607 } 608 609 static struct drm_info_list rv370_pcie_gart_info_list[] = { 610 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 611 }; 612 #endif 613 614 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 615 { 616 #if defined(CONFIG_DEBUG_FS) 617 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 618 #else 619 return 0; 620 #endif 621 } 622 623 static int r300_packet0_check(struct radeon_cs_parser *p, 624 struct radeon_cs_packet *pkt, 625 unsigned idx, unsigned reg) 626 { 627 struct radeon_cs_reloc *reloc; 628 struct r100_cs_track *track; 629 volatile uint32_t *ib; 630 uint32_t tmp, tile_flags = 0; 631 unsigned i; 632 int r; 633 u32 idx_value; 634 635 ib = p->ib->ptr; 636 track = (struct r100_cs_track *)p->track; 637 idx_value = radeon_get_ib_value(p, idx); 638 639 switch(reg) { 640 case AVIVO_D1MODE_VLINE_START_END: 641 case RADEON_CRTC_GUI_TRIG_VLINE: 642 r = r100_cs_packet_parse_vline(p); 643 if (r) { 644 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 645 idx, reg); 646 r100_cs_dump_packet(p, pkt); 647 return r; 648 } 649 break; 650 case RADEON_DST_PITCH_OFFSET: 651 case RADEON_SRC_PITCH_OFFSET: 652 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 653 if (r) 654 return r; 655 break; 656 case R300_RB3D_COLOROFFSET0: 657 case R300_RB3D_COLOROFFSET1: 658 case R300_RB3D_COLOROFFSET2: 659 case R300_RB3D_COLOROFFSET3: 660 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 661 r = r100_cs_packet_next_reloc(p, &reloc); 662 if (r) { 663 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 664 idx, reg); 665 r100_cs_dump_packet(p, pkt); 666 return r; 667 } 668 track->cb[i].robj = reloc->robj; 669 track->cb[i].offset = idx_value; 670 track->cb_dirty = true; 671 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 672 break; 673 case R300_ZB_DEPTHOFFSET: 674 r = r100_cs_packet_next_reloc(p, &reloc); 675 if (r) { 676 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 677 idx, reg); 678 r100_cs_dump_packet(p, pkt); 679 return r; 680 } 681 track->zb.robj = reloc->robj; 682 track->zb.offset = idx_value; 683 track->zb_dirty = true; 684 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 685 break; 686 case R300_TX_OFFSET_0: 687 case R300_TX_OFFSET_0+4: 688 case R300_TX_OFFSET_0+8: 689 case R300_TX_OFFSET_0+12: 690 case R300_TX_OFFSET_0+16: 691 case R300_TX_OFFSET_0+20: 692 case R300_TX_OFFSET_0+24: 693 case R300_TX_OFFSET_0+28: 694 case R300_TX_OFFSET_0+32: 695 case R300_TX_OFFSET_0+36: 696 case R300_TX_OFFSET_0+40: 697 case R300_TX_OFFSET_0+44: 698 case R300_TX_OFFSET_0+48: 699 case R300_TX_OFFSET_0+52: 700 case R300_TX_OFFSET_0+56: 701 case R300_TX_OFFSET_0+60: 702 i = (reg - R300_TX_OFFSET_0) >> 2; 703 r = r100_cs_packet_next_reloc(p, &reloc); 704 if (r) { 705 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 706 idx, reg); 707 r100_cs_dump_packet(p, pkt); 708 return r; 709 } 710 711 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 712 tile_flags |= R300_TXO_MACRO_TILE; 713 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 714 tile_flags |= R300_TXO_MICRO_TILE; 715 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 716 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 717 718 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 719 tmp |= tile_flags; 720 ib[idx] = tmp; 721 track->textures[i].robj = reloc->robj; 722 track->tex_dirty = true; 723 break; 724 /* Tracked registers */ 725 case 0x2084: 726 /* VAP_VF_CNTL */ 727 track->vap_vf_cntl = idx_value; 728 break; 729 case 0x20B4: 730 /* VAP_VTX_SIZE */ 731 track->vtx_size = idx_value & 0x7F; 732 break; 733 case 0x2134: 734 /* VAP_VF_MAX_VTX_INDX */ 735 track->max_indx = idx_value & 0x00FFFFFFUL; 736 break; 737 case 0x2088: 738 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 739 if (p->rdev->family < CHIP_RV515) 740 goto fail; 741 track->vap_alt_nverts = idx_value & 0xFFFFFF; 742 break; 743 case 0x43E4: 744 /* SC_SCISSOR1 */ 745 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 746 if (p->rdev->family < CHIP_RV515) { 747 track->maxy -= 1440; 748 } 749 track->cb_dirty = true; 750 track->zb_dirty = true; 751 break; 752 case 0x4E00: 753 /* RB3D_CCTL */ 754 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 755 p->rdev->cmask_filp != p->filp) { 756 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 757 return -EINVAL; 758 } 759 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 760 track->cb_dirty = true; 761 break; 762 case 0x4E38: 763 case 0x4E3C: 764 case 0x4E40: 765 case 0x4E44: 766 /* RB3D_COLORPITCH0 */ 767 /* RB3D_COLORPITCH1 */ 768 /* RB3D_COLORPITCH2 */ 769 /* RB3D_COLORPITCH3 */ 770 r = r100_cs_packet_next_reloc(p, &reloc); 771 if (r) { 772 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 773 idx, reg); 774 r100_cs_dump_packet(p, pkt); 775 return r; 776 } 777 778 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 779 tile_flags |= R300_COLOR_TILE_ENABLE; 780 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 781 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 782 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 783 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 784 785 tmp = idx_value & ~(0x7 << 16); 786 tmp |= tile_flags; 787 ib[idx] = tmp; 788 i = (reg - 0x4E38) >> 2; 789 track->cb[i].pitch = idx_value & 0x3FFE; 790 switch (((idx_value >> 21) & 0xF)) { 791 case 9: 792 case 11: 793 case 12: 794 track->cb[i].cpp = 1; 795 break; 796 case 3: 797 case 4: 798 case 13: 799 case 15: 800 track->cb[i].cpp = 2; 801 break; 802 case 5: 803 if (p->rdev->family < CHIP_RV515) { 804 DRM_ERROR("Invalid color buffer format (%d)!\n", 805 ((idx_value >> 21) & 0xF)); 806 return -EINVAL; 807 } 808 /* Pass through. */ 809 case 6: 810 track->cb[i].cpp = 4; 811 break; 812 case 10: 813 track->cb[i].cpp = 8; 814 break; 815 case 7: 816 track->cb[i].cpp = 16; 817 break; 818 default: 819 DRM_ERROR("Invalid color buffer format (%d) !\n", 820 ((idx_value >> 21) & 0xF)); 821 return -EINVAL; 822 } 823 track->cb_dirty = true; 824 break; 825 case 0x4F00: 826 /* ZB_CNTL */ 827 if (idx_value & 2) { 828 track->z_enabled = true; 829 } else { 830 track->z_enabled = false; 831 } 832 track->zb_dirty = true; 833 break; 834 case 0x4F10: 835 /* ZB_FORMAT */ 836 switch ((idx_value & 0xF)) { 837 case 0: 838 case 1: 839 track->zb.cpp = 2; 840 break; 841 case 2: 842 track->zb.cpp = 4; 843 break; 844 default: 845 DRM_ERROR("Invalid z buffer format (%d) !\n", 846 (idx_value & 0xF)); 847 return -EINVAL; 848 } 849 track->zb_dirty = true; 850 break; 851 case 0x4F24: 852 /* ZB_DEPTHPITCH */ 853 r = r100_cs_packet_next_reloc(p, &reloc); 854 if (r) { 855 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 856 idx, reg); 857 r100_cs_dump_packet(p, pkt); 858 return r; 859 } 860 861 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 862 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 863 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 864 tile_flags |= R300_DEPTHMICROTILE_TILED; 865 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 866 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 867 868 tmp = idx_value & ~(0x7 << 16); 869 tmp |= tile_flags; 870 ib[idx] = tmp; 871 872 track->zb.pitch = idx_value & 0x3FFC; 873 track->zb_dirty = true; 874 break; 875 case 0x4104: 876 /* TX_ENABLE */ 877 for (i = 0; i < 16; i++) { 878 bool enabled; 879 880 enabled = !!(idx_value & (1 << i)); 881 track->textures[i].enabled = enabled; 882 } 883 track->tex_dirty = true; 884 break; 885 case 0x44C0: 886 case 0x44C4: 887 case 0x44C8: 888 case 0x44CC: 889 case 0x44D0: 890 case 0x44D4: 891 case 0x44D8: 892 case 0x44DC: 893 case 0x44E0: 894 case 0x44E4: 895 case 0x44E8: 896 case 0x44EC: 897 case 0x44F0: 898 case 0x44F4: 899 case 0x44F8: 900 case 0x44FC: 901 /* TX_FORMAT1_[0-15] */ 902 i = (reg - 0x44C0) >> 2; 903 tmp = (idx_value >> 25) & 0x3; 904 track->textures[i].tex_coord_type = tmp; 905 switch ((idx_value & 0x1F)) { 906 case R300_TX_FORMAT_X8: 907 case R300_TX_FORMAT_Y4X4: 908 case R300_TX_FORMAT_Z3Y3X2: 909 track->textures[i].cpp = 1; 910 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 911 break; 912 case R300_TX_FORMAT_X16: 913 case R300_TX_FORMAT_Y8X8: 914 case R300_TX_FORMAT_Z5Y6X5: 915 case R300_TX_FORMAT_Z6Y5X5: 916 case R300_TX_FORMAT_W4Z4Y4X4: 917 case R300_TX_FORMAT_W1Z5Y5X5: 918 case R300_TX_FORMAT_D3DMFT_CxV8U8: 919 case R300_TX_FORMAT_B8G8_B8G8: 920 case R300_TX_FORMAT_G8R8_G8B8: 921 track->textures[i].cpp = 2; 922 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 923 break; 924 case R300_TX_FORMAT_Y16X16: 925 case R300_TX_FORMAT_Z11Y11X10: 926 case R300_TX_FORMAT_Z10Y11X11: 927 case R300_TX_FORMAT_W8Z8Y8X8: 928 case R300_TX_FORMAT_W2Z10Y10X10: 929 case 0x17: 930 case R300_TX_FORMAT_FL_I32: 931 case 0x1e: 932 track->textures[i].cpp = 4; 933 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 934 break; 935 case R300_TX_FORMAT_W16Z16Y16X16: 936 case R300_TX_FORMAT_FL_R16G16B16A16: 937 case R300_TX_FORMAT_FL_I32A32: 938 track->textures[i].cpp = 8; 939 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 940 break; 941 case R300_TX_FORMAT_FL_R32G32B32A32: 942 track->textures[i].cpp = 16; 943 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 944 break; 945 case R300_TX_FORMAT_DXT1: 946 track->textures[i].cpp = 1; 947 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 948 break; 949 case R300_TX_FORMAT_ATI2N: 950 if (p->rdev->family < CHIP_R420) { 951 DRM_ERROR("Invalid texture format %u\n", 952 (idx_value & 0x1F)); 953 return -EINVAL; 954 } 955 /* The same rules apply as for DXT3/5. */ 956 /* Pass through. */ 957 case R300_TX_FORMAT_DXT3: 958 case R300_TX_FORMAT_DXT5: 959 track->textures[i].cpp = 1; 960 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 961 break; 962 default: 963 DRM_ERROR("Invalid texture format %u\n", 964 (idx_value & 0x1F)); 965 return -EINVAL; 966 } 967 track->tex_dirty = true; 968 break; 969 case 0x4400: 970 case 0x4404: 971 case 0x4408: 972 case 0x440C: 973 case 0x4410: 974 case 0x4414: 975 case 0x4418: 976 case 0x441C: 977 case 0x4420: 978 case 0x4424: 979 case 0x4428: 980 case 0x442C: 981 case 0x4430: 982 case 0x4434: 983 case 0x4438: 984 case 0x443C: 985 /* TX_FILTER0_[0-15] */ 986 i = (reg - 0x4400) >> 2; 987 tmp = idx_value & 0x7; 988 if (tmp == 2 || tmp == 4 || tmp == 6) { 989 track->textures[i].roundup_w = false; 990 } 991 tmp = (idx_value >> 3) & 0x7; 992 if (tmp == 2 || tmp == 4 || tmp == 6) { 993 track->textures[i].roundup_h = false; 994 } 995 track->tex_dirty = true; 996 break; 997 case 0x4500: 998 case 0x4504: 999 case 0x4508: 1000 case 0x450C: 1001 case 0x4510: 1002 case 0x4514: 1003 case 0x4518: 1004 case 0x451C: 1005 case 0x4520: 1006 case 0x4524: 1007 case 0x4528: 1008 case 0x452C: 1009 case 0x4530: 1010 case 0x4534: 1011 case 0x4538: 1012 case 0x453C: 1013 /* TX_FORMAT2_[0-15] */ 1014 i = (reg - 0x4500) >> 2; 1015 tmp = idx_value & 0x3FFF; 1016 track->textures[i].pitch = tmp + 1; 1017 if (p->rdev->family >= CHIP_RV515) { 1018 tmp = ((idx_value >> 15) & 1) << 11; 1019 track->textures[i].width_11 = tmp; 1020 tmp = ((idx_value >> 16) & 1) << 11; 1021 track->textures[i].height_11 = tmp; 1022 1023 /* ATI1N */ 1024 if (idx_value & (1 << 14)) { 1025 /* The same rules apply as for DXT1. */ 1026 track->textures[i].compress_format = 1027 R100_TRACK_COMP_DXT1; 1028 } 1029 } else if (idx_value & (1 << 14)) { 1030 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1031 return -EINVAL; 1032 } 1033 track->tex_dirty = true; 1034 break; 1035 case 0x4480: 1036 case 0x4484: 1037 case 0x4488: 1038 case 0x448C: 1039 case 0x4490: 1040 case 0x4494: 1041 case 0x4498: 1042 case 0x449C: 1043 case 0x44A0: 1044 case 0x44A4: 1045 case 0x44A8: 1046 case 0x44AC: 1047 case 0x44B0: 1048 case 0x44B4: 1049 case 0x44B8: 1050 case 0x44BC: 1051 /* TX_FORMAT0_[0-15] */ 1052 i = (reg - 0x4480) >> 2; 1053 tmp = idx_value & 0x7FF; 1054 track->textures[i].width = tmp + 1; 1055 tmp = (idx_value >> 11) & 0x7FF; 1056 track->textures[i].height = tmp + 1; 1057 tmp = (idx_value >> 26) & 0xF; 1058 track->textures[i].num_levels = tmp; 1059 tmp = idx_value & (1 << 31); 1060 track->textures[i].use_pitch = !!tmp; 1061 tmp = (idx_value >> 22) & 0xF; 1062 track->textures[i].txdepth = tmp; 1063 track->tex_dirty = true; 1064 break; 1065 case R300_ZB_ZPASS_ADDR: 1066 r = r100_cs_packet_next_reloc(p, &reloc); 1067 if (r) { 1068 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1069 idx, reg); 1070 r100_cs_dump_packet(p, pkt); 1071 return r; 1072 } 1073 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1074 break; 1075 case 0x4e0c: 1076 /* RB3D_COLOR_CHANNEL_MASK */ 1077 track->color_channel_mask = idx_value; 1078 track->cb_dirty = true; 1079 break; 1080 case 0x43a4: 1081 /* SC_HYPERZ_EN */ 1082 /* r300c emits this register - we need to disable hyperz for it 1083 * without complaining */ 1084 if (p->rdev->hyperz_filp != p->filp) { 1085 if (idx_value & 0x1) 1086 ib[idx] = idx_value & ~1; 1087 } 1088 break; 1089 case 0x4f1c: 1090 /* ZB_BW_CNTL */ 1091 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1092 track->cb_dirty = true; 1093 track->zb_dirty = true; 1094 if (p->rdev->hyperz_filp != p->filp) { 1095 if (idx_value & (R300_HIZ_ENABLE | 1096 R300_RD_COMP_ENABLE | 1097 R300_WR_COMP_ENABLE | 1098 R300_FAST_FILL_ENABLE)) 1099 goto fail; 1100 } 1101 break; 1102 case 0x4e04: 1103 /* RB3D_BLENDCNTL */ 1104 track->blend_read_enable = !!(idx_value & (1 << 2)); 1105 track->cb_dirty = true; 1106 break; 1107 case R300_RB3D_AARESOLVE_OFFSET: 1108 r = r100_cs_packet_next_reloc(p, &reloc); 1109 if (r) { 1110 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1111 idx, reg); 1112 r100_cs_dump_packet(p, pkt); 1113 return r; 1114 } 1115 track->aa.robj = reloc->robj; 1116 track->aa.offset = idx_value; 1117 track->aa_dirty = true; 1118 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1119 break; 1120 case R300_RB3D_AARESOLVE_PITCH: 1121 track->aa.pitch = idx_value & 0x3FFE; 1122 track->aa_dirty = true; 1123 break; 1124 case R300_RB3D_AARESOLVE_CTL: 1125 track->aaresolve = idx_value & 0x1; 1126 track->aa_dirty = true; 1127 break; 1128 case 0x4f30: /* ZB_MASK_OFFSET */ 1129 case 0x4f34: /* ZB_ZMASK_PITCH */ 1130 case 0x4f44: /* ZB_HIZ_OFFSET */ 1131 case 0x4f54: /* ZB_HIZ_PITCH */ 1132 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1133 goto fail; 1134 break; 1135 case 0x4028: 1136 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1137 goto fail; 1138 /* GB_Z_PEQ_CONFIG */ 1139 if (p->rdev->family >= CHIP_RV350) 1140 break; 1141 goto fail; 1142 break; 1143 case 0x4be8: 1144 /* valid register only on RV530 */ 1145 if (p->rdev->family == CHIP_RV530) 1146 break; 1147 /* fallthrough do not move */ 1148 default: 1149 goto fail; 1150 } 1151 return 0; 1152 fail: 1153 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1154 reg, idx, idx_value); 1155 return -EINVAL; 1156 } 1157 1158 static int r300_packet3_check(struct radeon_cs_parser *p, 1159 struct radeon_cs_packet *pkt) 1160 { 1161 struct radeon_cs_reloc *reloc; 1162 struct r100_cs_track *track; 1163 volatile uint32_t *ib; 1164 unsigned idx; 1165 int r; 1166 1167 ib = p->ib->ptr; 1168 idx = pkt->idx + 1; 1169 track = (struct r100_cs_track *)p->track; 1170 switch(pkt->opcode) { 1171 case PACKET3_3D_LOAD_VBPNTR: 1172 r = r100_packet3_load_vbpntr(p, pkt, idx); 1173 if (r) 1174 return r; 1175 break; 1176 case PACKET3_INDX_BUFFER: 1177 r = r100_cs_packet_next_reloc(p, &reloc); 1178 if (r) { 1179 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1180 r100_cs_dump_packet(p, pkt); 1181 return r; 1182 } 1183 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1184 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1185 if (r) { 1186 return r; 1187 } 1188 break; 1189 /* Draw packet */ 1190 case PACKET3_3D_DRAW_IMMD: 1191 /* Number of dwords is vtx_size * (num_vertices - 1) 1192 * PRIM_WALK must be equal to 3 vertex data in embedded 1193 * in cmd stream */ 1194 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1195 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1196 return -EINVAL; 1197 } 1198 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1199 track->immd_dwords = pkt->count - 1; 1200 r = r100_cs_track_check(p->rdev, track); 1201 if (r) { 1202 return r; 1203 } 1204 break; 1205 case PACKET3_3D_DRAW_IMMD_2: 1206 /* Number of dwords is vtx_size * (num_vertices - 1) 1207 * PRIM_WALK must be equal to 3 vertex data in embedded 1208 * in cmd stream */ 1209 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1210 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1211 return -EINVAL; 1212 } 1213 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1214 track->immd_dwords = pkt->count; 1215 r = r100_cs_track_check(p->rdev, track); 1216 if (r) { 1217 return r; 1218 } 1219 break; 1220 case PACKET3_3D_DRAW_VBUF: 1221 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1222 r = r100_cs_track_check(p->rdev, track); 1223 if (r) { 1224 return r; 1225 } 1226 break; 1227 case PACKET3_3D_DRAW_VBUF_2: 1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1229 r = r100_cs_track_check(p->rdev, track); 1230 if (r) { 1231 return r; 1232 } 1233 break; 1234 case PACKET3_3D_DRAW_INDX: 1235 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1236 r = r100_cs_track_check(p->rdev, track); 1237 if (r) { 1238 return r; 1239 } 1240 break; 1241 case PACKET3_3D_DRAW_INDX_2: 1242 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1243 r = r100_cs_track_check(p->rdev, track); 1244 if (r) { 1245 return r; 1246 } 1247 break; 1248 case PACKET3_3D_CLEAR_HIZ: 1249 case PACKET3_3D_CLEAR_ZMASK: 1250 if (p->rdev->hyperz_filp != p->filp) 1251 return -EINVAL; 1252 break; 1253 case PACKET3_3D_CLEAR_CMASK: 1254 if (p->rdev->cmask_filp != p->filp) 1255 return -EINVAL; 1256 break; 1257 case PACKET3_NOP: 1258 break; 1259 default: 1260 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1261 return -EINVAL; 1262 } 1263 return 0; 1264 } 1265 1266 int r300_cs_parse(struct radeon_cs_parser *p) 1267 { 1268 struct radeon_cs_packet pkt; 1269 struct r100_cs_track *track; 1270 int r; 1271 1272 track = kzalloc(sizeof(*track), GFP_KERNEL); 1273 if (track == NULL) 1274 return -ENOMEM; 1275 r100_cs_track_clear(p->rdev, track); 1276 p->track = track; 1277 do { 1278 r = r100_cs_packet_parse(p, &pkt, p->idx); 1279 if (r) { 1280 return r; 1281 } 1282 p->idx += pkt.count + 2; 1283 switch (pkt.type) { 1284 case PACKET_TYPE0: 1285 r = r100_cs_parse_packet0(p, &pkt, 1286 p->rdev->config.r300.reg_safe_bm, 1287 p->rdev->config.r300.reg_safe_bm_size, 1288 &r300_packet0_check); 1289 break; 1290 case PACKET_TYPE2: 1291 break; 1292 case PACKET_TYPE3: 1293 r = r300_packet3_check(p, &pkt); 1294 break; 1295 default: 1296 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1297 return -EINVAL; 1298 } 1299 if (r) { 1300 return r; 1301 } 1302 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1303 return 0; 1304 } 1305 1306 void r300_set_reg_safe(struct radeon_device *rdev) 1307 { 1308 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1309 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1310 } 1311 1312 void r300_mc_program(struct radeon_device *rdev) 1313 { 1314 struct r100_mc_save save; 1315 int r; 1316 1317 r = r100_debugfs_mc_info_init(rdev); 1318 if (r) { 1319 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1320 } 1321 1322 /* Stops all mc clients */ 1323 r100_mc_stop(rdev, &save); 1324 if (rdev->flags & RADEON_IS_AGP) { 1325 WREG32(R_00014C_MC_AGP_LOCATION, 1326 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1327 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1328 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1329 WREG32(R_00015C_AGP_BASE_2, 1330 upper_32_bits(rdev->mc.agp_base) & 0xff); 1331 } else { 1332 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1333 WREG32(R_000170_AGP_BASE, 0); 1334 WREG32(R_00015C_AGP_BASE_2, 0); 1335 } 1336 /* Wait for mc idle */ 1337 if (r300_mc_wait_for_idle(rdev)) 1338 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1339 /* Program MC, should be a 32bits limited address space */ 1340 WREG32(R_000148_MC_FB_LOCATION, 1341 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1342 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1343 r100_mc_resume(rdev, &save); 1344 } 1345 1346 void r300_clock_startup(struct radeon_device *rdev) 1347 { 1348 u32 tmp; 1349 1350 if (radeon_dynclks != -1 && radeon_dynclks) 1351 radeon_legacy_set_clock_gating(rdev, 1); 1352 /* We need to force on some of the block */ 1353 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1354 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1355 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1356 tmp |= S_00000D_FORCE_VAP(1); 1357 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1358 } 1359 1360 static int r300_startup(struct radeon_device *rdev) 1361 { 1362 int r; 1363 1364 /* set common regs */ 1365 r100_set_common_regs(rdev); 1366 /* program mc */ 1367 r300_mc_program(rdev); 1368 /* Resume clock */ 1369 r300_clock_startup(rdev); 1370 /* Initialize GPU configuration (# pipes, ...) */ 1371 r300_gpu_init(rdev); 1372 /* Initialize GART (initialize after TTM so we can allocate 1373 * memory through TTM but finalize after TTM) */ 1374 if (rdev->flags & RADEON_IS_PCIE) { 1375 r = rv370_pcie_gart_enable(rdev); 1376 if (r) 1377 return r; 1378 } 1379 1380 if (rdev->family == CHIP_R300 || 1381 rdev->family == CHIP_R350 || 1382 rdev->family == CHIP_RV350) 1383 r100_enable_bm(rdev); 1384 1385 if (rdev->flags & RADEON_IS_PCI) { 1386 r = r100_pci_gart_enable(rdev); 1387 if (r) 1388 return r; 1389 } 1390 1391 /* allocate wb buffer */ 1392 r = radeon_wb_init(rdev); 1393 if (r) 1394 return r; 1395 1396 /* Enable IRQ */ 1397 r100_irq_set(rdev); 1398 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1399 /* 1M ring buffer */ 1400 r = r100_cp_init(rdev, 1024 * 1024); 1401 if (r) { 1402 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 1403 return r; 1404 } 1405 r = r100_ib_init(rdev); 1406 if (r) { 1407 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 1408 return r; 1409 } 1410 return 0; 1411 } 1412 1413 int r300_resume(struct radeon_device *rdev) 1414 { 1415 /* Make sur GART are not working */ 1416 if (rdev->flags & RADEON_IS_PCIE) 1417 rv370_pcie_gart_disable(rdev); 1418 if (rdev->flags & RADEON_IS_PCI) 1419 r100_pci_gart_disable(rdev); 1420 /* Resume clock before doing reset */ 1421 r300_clock_startup(rdev); 1422 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1423 if (radeon_asic_reset(rdev)) { 1424 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1425 RREG32(R_000E40_RBBM_STATUS), 1426 RREG32(R_0007C0_CP_STAT)); 1427 } 1428 /* post */ 1429 radeon_combios_asic_init(rdev->ddev); 1430 /* Resume clock after posting */ 1431 r300_clock_startup(rdev); 1432 /* Initialize surface registers */ 1433 radeon_surface_init(rdev); 1434 return r300_startup(rdev); 1435 } 1436 1437 int r300_suspend(struct radeon_device *rdev) 1438 { 1439 r100_cp_disable(rdev); 1440 radeon_wb_disable(rdev); 1441 r100_irq_disable(rdev); 1442 if (rdev->flags & RADEON_IS_PCIE) 1443 rv370_pcie_gart_disable(rdev); 1444 if (rdev->flags & RADEON_IS_PCI) 1445 r100_pci_gart_disable(rdev); 1446 return 0; 1447 } 1448 1449 void r300_fini(struct radeon_device *rdev) 1450 { 1451 r100_cp_fini(rdev); 1452 radeon_wb_fini(rdev); 1453 r100_ib_fini(rdev); 1454 radeon_gem_fini(rdev); 1455 if (rdev->flags & RADEON_IS_PCIE) 1456 rv370_pcie_gart_fini(rdev); 1457 if (rdev->flags & RADEON_IS_PCI) 1458 r100_pci_gart_fini(rdev); 1459 radeon_agp_fini(rdev); 1460 radeon_irq_kms_fini(rdev); 1461 radeon_fence_driver_fini(rdev); 1462 radeon_bo_fini(rdev); 1463 radeon_atombios_fini(rdev); 1464 kfree(rdev->bios); 1465 rdev->bios = NULL; 1466 } 1467 1468 int r300_init(struct radeon_device *rdev) 1469 { 1470 int r; 1471 1472 /* Disable VGA */ 1473 r100_vga_render_disable(rdev); 1474 /* Initialize scratch registers */ 1475 radeon_scratch_init(rdev); 1476 /* Initialize surface registers */ 1477 radeon_surface_init(rdev); 1478 /* TODO: disable VGA need to use VGA request */ 1479 /* restore some register to sane defaults */ 1480 r100_restore_sanity(rdev); 1481 /* BIOS*/ 1482 if (!radeon_get_bios(rdev)) { 1483 if (ASIC_IS_AVIVO(rdev)) 1484 return -EINVAL; 1485 } 1486 if (rdev->is_atom_bios) { 1487 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1488 return -EINVAL; 1489 } else { 1490 r = radeon_combios_init(rdev); 1491 if (r) 1492 return r; 1493 } 1494 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1495 if (radeon_asic_reset(rdev)) { 1496 dev_warn(rdev->dev, 1497 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1498 RREG32(R_000E40_RBBM_STATUS), 1499 RREG32(R_0007C0_CP_STAT)); 1500 } 1501 /* check if cards are posted or not */ 1502 if (radeon_boot_test_post_card(rdev) == false) 1503 return -EINVAL; 1504 /* Set asic errata */ 1505 r300_errata(rdev); 1506 /* Initialize clocks */ 1507 radeon_get_clock_info(rdev->ddev); 1508 /* initialize AGP */ 1509 if (rdev->flags & RADEON_IS_AGP) { 1510 r = radeon_agp_init(rdev); 1511 if (r) { 1512 radeon_agp_disable(rdev); 1513 } 1514 } 1515 /* initialize memory controller */ 1516 r300_mc_init(rdev); 1517 /* Fence driver */ 1518 r = radeon_fence_driver_init(rdev); 1519 if (r) 1520 return r; 1521 r = radeon_irq_kms_init(rdev); 1522 if (r) 1523 return r; 1524 /* Memory manager */ 1525 r = radeon_bo_init(rdev); 1526 if (r) 1527 return r; 1528 if (rdev->flags & RADEON_IS_PCIE) { 1529 r = rv370_pcie_gart_init(rdev); 1530 if (r) 1531 return r; 1532 } 1533 if (rdev->flags & RADEON_IS_PCI) { 1534 r = r100_pci_gart_init(rdev); 1535 if (r) 1536 return r; 1537 } 1538 r300_set_reg_safe(rdev); 1539 rdev->accel_working = true; 1540 r = r300_startup(rdev); 1541 if (r) { 1542 /* Somethings want wront with the accel init stop accel */ 1543 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1544 r100_cp_fini(rdev); 1545 radeon_wb_fini(rdev); 1546 r100_ib_fini(rdev); 1547 radeon_irq_kms_fini(rdev); 1548 if (rdev->flags & RADEON_IS_PCIE) 1549 rv370_pcie_gart_fini(rdev); 1550 if (rdev->flags & RADEON_IS_PCI) 1551 r100_pci_gart_fini(rdev); 1552 radeon_agp_fini(rdev); 1553 rdev->accel_working = false; 1554 } 1555 return 0; 1556 } 1557