1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRV_H__ 26 #define __NOUVEAU_DRV_H__ 27 28 #define DRIVER_AUTHOR "Stephane Marchesin" 29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31 #define DRIVER_NAME "nouveau" 32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33 #define DRIVER_DATE "20090420" 34 35 #define DRIVER_MAJOR 0 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 16 38 39 #define NOUVEAU_FAMILY 0x0000FFFF 40 #define NOUVEAU_FLAGS 0xFFFF0000 41 42 #include "ttm/ttm_bo_api.h" 43 #include "ttm/ttm_bo_driver.h" 44 #include "ttm/ttm_placement.h" 45 #include "ttm/ttm_memory.h" 46 #include "ttm/ttm_module.h" 47 48 struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50 }; 51 52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54 #include "nouveau_drm.h" 55 #include "nouveau_reg.h" 56 #include "nouveau_bios.h" 57 #include "nouveau_util.h" 58 59 struct nouveau_grctx; 60 struct nouveau_mem; 61 #include "nouveau_vm.h" 62 63 #define MAX_NUM_DCB_ENTRIES 16 64 65 #define NOUVEAU_MAX_CHANNEL_NR 128 66 #define NOUVEAU_MAX_TILE_NR 15 67 68 struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81 }; 82 83 struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91 }; 92 93 struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118 }; 119 120 #define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123 static inline struct nouveau_bo * 124 nouveau_bo(struct ttm_buffer_object *bo) 125 { 126 return container_of(bo, struct nouveau_bo, bo); 127 } 128 129 static inline struct nouveau_bo * 130 nouveau_gem_object(struct drm_gem_object *gem) 131 { 132 return gem ? gem->driver_private : NULL; 133 } 134 135 /* TODO: submit equivalent to TTM generic API upstream? */ 136 static inline void __iomem * 137 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138 { 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144 } 145 146 enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149 }; 150 151 #define NVOBJ_ENGINE_SW 0 152 #define NVOBJ_ENGINE_GR 1 153 #define NVOBJ_ENGINE_CRYPT 2 154 #define NVOBJ_ENGINE_COPY0 3 155 #define NVOBJ_ENGINE_COPY1 4 156 #define NVOBJ_ENGINE_MPEG 5 157 #define NVOBJ_ENGINE_DISPLAY 15 158 #define NVOBJ_ENGINE_NR 16 159 160 #define NVOBJ_FLAG_DONT_MAP (1 << 0) 161 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 162 #define NVOBJ_FLAG_ZERO_FREE (1 << 2) 163 #define NVOBJ_FLAG_VM (1 << 3) 164 #define NVOBJ_FLAG_VM_USER (1 << 4) 165 166 #define NVOBJ_CINST_GLOBAL 0xdeadbeef 167 168 struct nouveau_gpuobj { 169 struct drm_device *dev; 170 struct kref refcount; 171 struct list_head list; 172 173 void *node; 174 u32 *suspend; 175 176 uint32_t flags; 177 178 u32 size; 179 u32 pinst; 180 u32 cinst; 181 u64 vinst; 182 183 uint32_t engine; 184 uint32_t class; 185 186 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 187 void *priv; 188 }; 189 190 struct nouveau_page_flip_state { 191 struct list_head head; 192 struct drm_pending_vblank_event *event; 193 int crtc, bpp, pitch, x, y; 194 uint64_t offset; 195 }; 196 197 enum nouveau_channel_mutex_class { 198 NOUVEAU_UCHANNEL_MUTEX, 199 NOUVEAU_KCHANNEL_MUTEX 200 }; 201 202 struct nouveau_channel { 203 struct drm_device *dev; 204 int id; 205 206 /* references to the channel data structure */ 207 struct kref ref; 208 /* users of the hardware channel resources, the hardware 209 * context will be kicked off when it reaches zero. */ 210 atomic_t users; 211 struct mutex mutex; 212 213 /* owner of this fifo */ 214 struct drm_file *file_priv; 215 /* mapping of the fifo itself */ 216 struct drm_local_map *map; 217 218 /* mapping of the regs controlling the fifo */ 219 void __iomem *user; 220 uint32_t user_get; 221 uint32_t user_put; 222 223 /* Fencing */ 224 struct { 225 /* lock protects the pending list only */ 226 spinlock_t lock; 227 struct list_head pending; 228 uint32_t sequence; 229 uint32_t sequence_ack; 230 atomic_t last_sequence_irq; 231 } fence; 232 233 /* DMA push buffer */ 234 struct nouveau_gpuobj *pushbuf; 235 struct nouveau_bo *pushbuf_bo; 236 uint32_t pushbuf_base; 237 238 /* Notifier memory */ 239 struct nouveau_bo *notifier_bo; 240 struct drm_mm notifier_heap; 241 242 /* PFIFO context */ 243 struct nouveau_gpuobj *ramfc; 244 struct nouveau_gpuobj *cache; 245 void *fifo_priv; 246 247 /* Execution engine contexts */ 248 void *engctx[NVOBJ_ENGINE_NR]; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295 }; 296 297 struct nouveau_exec_engine { 298 void (*destroy)(struct drm_device *, int engine); 299 int (*init)(struct drm_device *, int engine); 300 int (*fini)(struct drm_device *, int engine); 301 int (*context_new)(struct nouveau_channel *, int engine); 302 void (*context_del)(struct nouveau_channel *, int engine); 303 int (*object_new)(struct nouveau_channel *, int engine, 304 u32 handle, u16 class); 305 void (*set_tile_region)(struct drm_device *dev, int i); 306 void (*tlb_flush)(struct drm_device *, int engine); 307 }; 308 309 struct nouveau_instmem_engine { 310 void *priv; 311 312 int (*init)(struct drm_device *dev); 313 void (*takedown)(struct drm_device *dev); 314 int (*suspend)(struct drm_device *dev); 315 void (*resume)(struct drm_device *dev); 316 317 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 318 void (*put)(struct nouveau_gpuobj *); 319 int (*map)(struct nouveau_gpuobj *); 320 void (*unmap)(struct nouveau_gpuobj *); 321 322 void (*flush)(struct drm_device *); 323 }; 324 325 struct nouveau_mc_engine { 326 int (*init)(struct drm_device *dev); 327 void (*takedown)(struct drm_device *dev); 328 }; 329 330 struct nouveau_timer_engine { 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 uint64_t (*read)(struct drm_device *dev); 334 }; 335 336 struct nouveau_fb_engine { 337 int num_tiles; 338 struct drm_mm tag_heap; 339 void *priv; 340 341 int (*init)(struct drm_device *dev); 342 void (*takedown)(struct drm_device *dev); 343 344 void (*init_tile_region)(struct drm_device *dev, int i, 345 uint32_t addr, uint32_t size, 346 uint32_t pitch, uint32_t flags); 347 void (*set_tile_region)(struct drm_device *dev, int i); 348 void (*free_tile_region)(struct drm_device *dev, int i); 349 }; 350 351 struct nouveau_fifo_engine { 352 void *priv; 353 int channels; 354 355 struct nouveau_gpuobj *playlist[2]; 356 int cur_playlist; 357 358 int (*init)(struct drm_device *); 359 void (*takedown)(struct drm_device *); 360 361 void (*disable)(struct drm_device *); 362 void (*enable)(struct drm_device *); 363 bool (*reassign)(struct drm_device *, bool enable); 364 bool (*cache_pull)(struct drm_device *dev, bool enable); 365 366 int (*channel_id)(struct drm_device *); 367 368 int (*create_context)(struct nouveau_channel *); 369 void (*destroy_context)(struct nouveau_channel *); 370 int (*load_context)(struct nouveau_channel *); 371 int (*unload_context)(struct drm_device *); 372 void (*tlb_flush)(struct drm_device *dev); 373 }; 374 375 struct nouveau_display_engine { 376 void *priv; 377 int (*early_init)(struct drm_device *); 378 void (*late_takedown)(struct drm_device *); 379 int (*create)(struct drm_device *); 380 int (*init)(struct drm_device *); 381 void (*destroy)(struct drm_device *); 382 }; 383 384 struct nouveau_gpio_engine { 385 void *priv; 386 387 int (*init)(struct drm_device *); 388 void (*takedown)(struct drm_device *); 389 390 int (*get)(struct drm_device *, enum dcb_gpio_tag); 391 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 392 393 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 394 void (*)(void *, int), void *); 395 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 396 void (*)(void *, int), void *); 397 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 398 }; 399 400 struct nouveau_pm_voltage_level { 401 u8 voltage; 402 u8 vid; 403 }; 404 405 struct nouveau_pm_voltage { 406 bool supported; 407 u8 vid_mask; 408 409 struct nouveau_pm_voltage_level *level; 410 int nr_level; 411 }; 412 413 struct nouveau_pm_memtiming { 414 int id; 415 u32 reg_100220; 416 u32 reg_100224; 417 u32 reg_100228; 418 u32 reg_10022c; 419 u32 reg_100230; 420 u32 reg_100234; 421 u32 reg_100238; 422 u32 reg_10023c; 423 u32 reg_100240; 424 }; 425 426 #define NOUVEAU_PM_MAX_LEVEL 8 427 struct nouveau_pm_level { 428 struct device_attribute dev_attr; 429 char name[32]; 430 int id; 431 432 u32 core; 433 u32 memory; 434 u32 shader; 435 u32 unk05; 436 u32 unk0a; 437 438 u8 voltage; 439 u8 fanspeed; 440 441 u16 memscript; 442 struct nouveau_pm_memtiming *timing; 443 }; 444 445 struct nouveau_pm_temp_sensor_constants { 446 u16 offset_constant; 447 s16 offset_mult; 448 u16 offset_div; 449 u16 slope_mult; 450 u16 slope_div; 451 }; 452 453 struct nouveau_pm_threshold_temp { 454 s16 critical; 455 s16 down_clock; 456 s16 fan_boost; 457 }; 458 459 struct nouveau_pm_memtimings { 460 bool supported; 461 struct nouveau_pm_memtiming *timing; 462 int nr_timing; 463 }; 464 465 struct nouveau_pm_engine { 466 struct nouveau_pm_voltage voltage; 467 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 468 int nr_perflvl; 469 struct nouveau_pm_memtimings memtimings; 470 struct nouveau_pm_temp_sensor_constants sensor_constants; 471 struct nouveau_pm_threshold_temp threshold_temp; 472 473 struct nouveau_pm_level boot; 474 struct nouveau_pm_level *cur; 475 476 struct device *hwmon; 477 struct notifier_block acpi_nb; 478 479 int (*clock_get)(struct drm_device *, u32 id); 480 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 481 u32 id, int khz); 482 void (*clock_set)(struct drm_device *, void *); 483 int (*voltage_get)(struct drm_device *); 484 int (*voltage_set)(struct drm_device *, int voltage); 485 int (*fanspeed_get)(struct drm_device *); 486 int (*fanspeed_set)(struct drm_device *, int fanspeed); 487 int (*temp_get)(struct drm_device *); 488 }; 489 490 struct nouveau_vram_engine { 491 int (*init)(struct drm_device *); 492 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 493 u32 type, struct nouveau_mem **); 494 void (*put)(struct drm_device *, struct nouveau_mem **); 495 496 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 497 }; 498 499 struct nouveau_engine { 500 struct nouveau_instmem_engine instmem; 501 struct nouveau_mc_engine mc; 502 struct nouveau_timer_engine timer; 503 struct nouveau_fb_engine fb; 504 struct nouveau_fifo_engine fifo; 505 struct nouveau_display_engine display; 506 struct nouveau_gpio_engine gpio; 507 struct nouveau_pm_engine pm; 508 struct nouveau_vram_engine vram; 509 }; 510 511 struct nouveau_pll_vals { 512 union { 513 struct { 514 #ifdef __BIG_ENDIAN 515 uint8_t N1, M1, N2, M2; 516 #else 517 uint8_t M1, N1, M2, N2; 518 #endif 519 }; 520 struct { 521 uint16_t NM1, NM2; 522 } __attribute__((packed)); 523 }; 524 int log2P; 525 526 int refclk; 527 }; 528 529 enum nv04_fp_display_regs { 530 FP_DISPLAY_END, 531 FP_TOTAL, 532 FP_CRTC, 533 FP_SYNC_START, 534 FP_SYNC_END, 535 FP_VALID_START, 536 FP_VALID_END 537 }; 538 539 struct nv04_crtc_reg { 540 unsigned char MiscOutReg; 541 uint8_t CRTC[0xa0]; 542 uint8_t CR58[0x10]; 543 uint8_t Sequencer[5]; 544 uint8_t Graphics[9]; 545 uint8_t Attribute[21]; 546 unsigned char DAC[768]; 547 548 /* PCRTC regs */ 549 uint32_t fb_start; 550 uint32_t crtc_cfg; 551 uint32_t cursor_cfg; 552 uint32_t gpio_ext; 553 uint32_t crtc_830; 554 uint32_t crtc_834; 555 uint32_t crtc_850; 556 uint32_t crtc_eng_ctrl; 557 558 /* PRAMDAC regs */ 559 uint32_t nv10_cursync; 560 struct nouveau_pll_vals pllvals; 561 uint32_t ramdac_gen_ctrl; 562 uint32_t ramdac_630; 563 uint32_t ramdac_634; 564 uint32_t tv_setup; 565 uint32_t tv_vtotal; 566 uint32_t tv_vskew; 567 uint32_t tv_vsync_delay; 568 uint32_t tv_htotal; 569 uint32_t tv_hskew; 570 uint32_t tv_hsync_delay; 571 uint32_t tv_hsync_delay2; 572 uint32_t fp_horiz_regs[7]; 573 uint32_t fp_vert_regs[7]; 574 uint32_t dither; 575 uint32_t fp_control; 576 uint32_t dither_regs[6]; 577 uint32_t fp_debug_0; 578 uint32_t fp_debug_1; 579 uint32_t fp_debug_2; 580 uint32_t fp_margin_color; 581 uint32_t ramdac_8c0; 582 uint32_t ramdac_a20; 583 uint32_t ramdac_a24; 584 uint32_t ramdac_a34; 585 uint32_t ctv_regs[38]; 586 }; 587 588 struct nv04_output_reg { 589 uint32_t output; 590 int head; 591 }; 592 593 struct nv04_mode_state { 594 struct nv04_crtc_reg crtc_reg[2]; 595 uint32_t pllsel; 596 uint32_t sel_clk; 597 }; 598 599 enum nouveau_card_type { 600 NV_04 = 0x00, 601 NV_10 = 0x10, 602 NV_20 = 0x20, 603 NV_30 = 0x30, 604 NV_40 = 0x40, 605 NV_50 = 0x50, 606 NV_C0 = 0xc0, 607 }; 608 609 struct drm_nouveau_private { 610 struct drm_device *dev; 611 612 /* the card type, takes NV_* as values */ 613 enum nouveau_card_type card_type; 614 /* exact chipset, derived from NV_PMC_BOOT_0 */ 615 int chipset; 616 int stepping; 617 int flags; 618 619 void __iomem *mmio; 620 621 spinlock_t ramin_lock; 622 void __iomem *ramin; 623 u32 ramin_size; 624 u32 ramin_base; 625 bool ramin_available; 626 struct drm_mm ramin_heap; 627 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 628 struct list_head gpuobj_list; 629 struct list_head classes; 630 631 struct nouveau_bo *vga_ram; 632 633 /* interrupt handling */ 634 void (*irq_handler[32])(struct drm_device *); 635 bool msi_enabled; 636 637 struct list_head vbl_waiting; 638 639 struct { 640 struct drm_global_reference mem_global_ref; 641 struct ttm_bo_global_ref bo_global_ref; 642 struct ttm_bo_device bdev; 643 atomic_t validate_sequence; 644 } ttm; 645 646 struct { 647 spinlock_t lock; 648 struct drm_mm heap; 649 struct nouveau_bo *bo; 650 } fence; 651 652 struct { 653 spinlock_t lock; 654 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 655 } channels; 656 657 struct nouveau_engine engine; 658 struct nouveau_channel *channel; 659 660 /* For PFIFO and PGRAPH. */ 661 spinlock_t context_switch_lock; 662 663 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 664 spinlock_t vm_lock; 665 666 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 667 struct nouveau_ramht *ramht; 668 struct nouveau_gpuobj *ramfc; 669 struct nouveau_gpuobj *ramro; 670 671 uint32_t ramin_rsvd_vram; 672 673 struct { 674 enum { 675 NOUVEAU_GART_NONE = 0, 676 NOUVEAU_GART_AGP, /* AGP */ 677 NOUVEAU_GART_PDMA, /* paged dma object */ 678 NOUVEAU_GART_HW /* on-chip gart/vm */ 679 } type; 680 uint64_t aper_base; 681 uint64_t aper_size; 682 uint64_t aper_free; 683 684 struct ttm_backend_func *func; 685 686 struct { 687 struct page *page; 688 dma_addr_t addr; 689 } dummy; 690 691 struct nouveau_gpuobj *sg_ctxdma; 692 } gart_info; 693 694 /* nv10-nv40 tiling regions */ 695 struct { 696 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 697 spinlock_t lock; 698 } tile; 699 700 /* VRAM/fb configuration */ 701 uint64_t vram_size; 702 uint64_t vram_sys_base; 703 u32 vram_rblock_size; 704 705 uint64_t fb_phys; 706 uint64_t fb_available_size; 707 uint64_t fb_mappable_pages; 708 uint64_t fb_aper_free; 709 int fb_mtrr; 710 711 /* BAR control (NV50-) */ 712 struct nouveau_vm *bar1_vm; 713 struct nouveau_vm *bar3_vm; 714 715 /* G8x/G9x virtual address space */ 716 struct nouveau_vm *chan_vm; 717 718 struct nvbios vbios; 719 720 struct nv04_mode_state mode_reg; 721 struct nv04_mode_state saved_reg; 722 uint32_t saved_vga_font[4][16384]; 723 uint32_t crtc_owner; 724 uint32_t dac_users[4]; 725 726 struct backlight_device *backlight; 727 728 struct { 729 struct dentry *channel_root; 730 } debugfs; 731 732 struct nouveau_fbdev *nfbdev; 733 struct apertures_struct *apertures; 734 }; 735 736 static inline struct drm_nouveau_private * 737 nouveau_private(struct drm_device *dev) 738 { 739 return dev->dev_private; 740 } 741 742 static inline struct drm_nouveau_private * 743 nouveau_bdev(struct ttm_bo_device *bd) 744 { 745 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 746 } 747 748 static inline int 749 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 750 { 751 struct nouveau_bo *prev; 752 753 if (!pnvbo) 754 return -EINVAL; 755 prev = *pnvbo; 756 757 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 758 if (prev) { 759 struct ttm_buffer_object *bo = &prev->bo; 760 761 ttm_bo_unref(&bo); 762 } 763 764 return 0; 765 } 766 767 /* nouveau_drv.c */ 768 extern int nouveau_agpmode; 769 extern int nouveau_duallink; 770 extern int nouveau_uscript_lvds; 771 extern int nouveau_uscript_tmds; 772 extern int nouveau_vram_pushbuf; 773 extern int nouveau_vram_notify; 774 extern int nouveau_fbpercrtc; 775 extern int nouveau_tv_disable; 776 extern char *nouveau_tv_norm; 777 extern int nouveau_reg_debug; 778 extern char *nouveau_vbios; 779 extern int nouveau_ignorelid; 780 extern int nouveau_nofbaccel; 781 extern int nouveau_noaccel; 782 extern int nouveau_force_post; 783 extern int nouveau_override_conntype; 784 extern char *nouveau_perflvl; 785 extern int nouveau_perflvl_wr; 786 extern int nouveau_msi; 787 788 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 789 extern int nouveau_pci_resume(struct pci_dev *pdev); 790 791 /* nouveau_state.c */ 792 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 793 extern int nouveau_load(struct drm_device *, unsigned long flags); 794 extern int nouveau_firstopen(struct drm_device *); 795 extern void nouveau_lastclose(struct drm_device *); 796 extern int nouveau_unload(struct drm_device *); 797 extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 798 struct drm_file *); 799 extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 800 struct drm_file *); 801 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 802 uint32_t reg, uint32_t mask, uint32_t val); 803 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 804 uint32_t reg, uint32_t mask, uint32_t val); 805 extern bool nouveau_wait_for_idle(struct drm_device *); 806 extern int nouveau_card_init(struct drm_device *); 807 808 /* nouveau_mem.c */ 809 extern int nouveau_mem_vram_init(struct drm_device *); 810 extern void nouveau_mem_vram_fini(struct drm_device *); 811 extern int nouveau_mem_gart_init(struct drm_device *); 812 extern void nouveau_mem_gart_fini(struct drm_device *); 813 extern int nouveau_mem_init_agp(struct drm_device *); 814 extern int nouveau_mem_reset_agp(struct drm_device *); 815 extern void nouveau_mem_close(struct drm_device *); 816 extern int nouveau_mem_detect(struct drm_device *); 817 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 818 extern struct nouveau_tile_reg *nv10_mem_set_tiling( 819 struct drm_device *dev, uint32_t addr, uint32_t size, 820 uint32_t pitch, uint32_t flags); 821 extern void nv10_mem_put_tile_region(struct drm_device *dev, 822 struct nouveau_tile_reg *tile, 823 struct nouveau_fence *fence); 824 extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 825 extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 826 827 /* nouveau_notifier.c */ 828 extern int nouveau_notifier_init_channel(struct nouveau_channel *); 829 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 830 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 831 int cout, uint32_t start, uint32_t end, 832 uint32_t *offset); 833 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 834 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 835 struct drm_file *); 836 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 837 struct drm_file *); 838 839 /* nouveau_channel.c */ 840 extern struct drm_ioctl_desc nouveau_ioctls[]; 841 extern int nouveau_max_ioctl; 842 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 843 extern int nouveau_channel_alloc(struct drm_device *dev, 844 struct nouveau_channel **chan, 845 struct drm_file *file_priv, 846 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 847 extern struct nouveau_channel * 848 nouveau_channel_get_unlocked(struct nouveau_channel *); 849 extern struct nouveau_channel * 850 nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 851 extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 852 extern void nouveau_channel_put(struct nouveau_channel **); 853 extern void nouveau_channel_ref(struct nouveau_channel *chan, 854 struct nouveau_channel **pchan); 855 extern void nouveau_channel_idle(struct nouveau_channel *chan); 856 857 /* nouveau_object.c */ 858 #define NVOBJ_ENGINE_ADD(d, e, p) do { \ 859 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 860 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 861 } while (0) 862 863 #define NVOBJ_ENGINE_DEL(d, e) do { \ 864 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 865 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 866 } while (0) 867 868 #define NVOBJ_CLASS(d, c, e) do { \ 869 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 870 if (ret) \ 871 return ret; \ 872 } while (0) 873 874 #define NVOBJ_MTHD(d, c, m, e) do { \ 875 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 876 if (ret) \ 877 return ret; \ 878 } while (0) 879 880 extern int nouveau_gpuobj_early_init(struct drm_device *); 881 extern int nouveau_gpuobj_init(struct drm_device *); 882 extern void nouveau_gpuobj_takedown(struct drm_device *); 883 extern int nouveau_gpuobj_suspend(struct drm_device *dev); 884 extern void nouveau_gpuobj_resume(struct drm_device *dev); 885 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 886 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 887 int (*exec)(struct nouveau_channel *, 888 u32 class, u32 mthd, u32 data)); 889 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 890 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 891 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 892 uint32_t vram_h, uint32_t tt_h); 893 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 894 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 895 uint32_t size, int align, uint32_t flags, 896 struct nouveau_gpuobj **); 897 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 898 struct nouveau_gpuobj **); 899 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 900 u32 size, u32 flags, 901 struct nouveau_gpuobj **); 902 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 903 uint64_t offset, uint64_t size, int access, 904 int target, struct nouveau_gpuobj **); 905 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 906 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 907 u64 size, int target, int access, u32 type, 908 u32 comp, struct nouveau_gpuobj **pobj); 909 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 910 int class, u64 base, u64 size, int target, 911 int access, u32 type, u32 comp); 912 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 913 struct drm_file *); 914 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 915 struct drm_file *); 916 917 /* nouveau_irq.c */ 918 extern int nouveau_irq_init(struct drm_device *); 919 extern void nouveau_irq_fini(struct drm_device *); 920 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 921 extern void nouveau_irq_register(struct drm_device *, int status_bit, 922 void (*)(struct drm_device *)); 923 extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 924 extern void nouveau_irq_preinstall(struct drm_device *); 925 extern int nouveau_irq_postinstall(struct drm_device *); 926 extern void nouveau_irq_uninstall(struct drm_device *); 927 928 /* nouveau_sgdma.c */ 929 extern int nouveau_sgdma_init(struct drm_device *); 930 extern void nouveau_sgdma_takedown(struct drm_device *); 931 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 932 uint32_t offset); 933 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 934 935 /* nouveau_debugfs.c */ 936 #if defined(CONFIG_DRM_NOUVEAU_DEBUG) 937 extern int nouveau_debugfs_init(struct drm_minor *); 938 extern void nouveau_debugfs_takedown(struct drm_minor *); 939 extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 940 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 941 #else 942 static inline int 943 nouveau_debugfs_init(struct drm_minor *minor) 944 { 945 return 0; 946 } 947 948 static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 949 { 950 } 951 952 static inline int 953 nouveau_debugfs_channel_init(struct nouveau_channel *chan) 954 { 955 return 0; 956 } 957 958 static inline void 959 nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 960 { 961 } 962 #endif 963 964 /* nouveau_dma.c */ 965 extern void nouveau_dma_pre_init(struct nouveau_channel *); 966 extern int nouveau_dma_init(struct nouveau_channel *); 967 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 968 969 /* nouveau_acpi.c */ 970 #define ROM_BIOS_PAGE 4096 971 #if defined(CONFIG_ACPI) 972 void nouveau_register_dsm_handler(void); 973 void nouveau_unregister_dsm_handler(void); 974 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 975 bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 976 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 977 #else 978 static inline void nouveau_register_dsm_handler(void) {} 979 static inline void nouveau_unregister_dsm_handler(void) {} 980 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 981 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 982 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 983 #endif 984 985 /* nouveau_backlight.c */ 986 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 987 extern int nouveau_backlight_init(struct drm_connector *); 988 extern void nouveau_backlight_exit(struct drm_connector *); 989 #else 990 static inline int nouveau_backlight_init(struct drm_connector *dev) 991 { 992 return 0; 993 } 994 995 static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 996 #endif 997 998 /* nouveau_bios.c */ 999 extern int nouveau_bios_init(struct drm_device *); 1000 extern void nouveau_bios_takedown(struct drm_device *dev); 1001 extern int nouveau_run_vbios_init(struct drm_device *); 1002 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1003 struct dcb_entry *); 1004 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1005 enum dcb_gpio_tag); 1006 extern struct dcb_connector_table_entry * 1007 nouveau_bios_connector_entry(struct drm_device *, int index); 1008 extern u32 get_pll_register(struct drm_device *, enum pll_types); 1009 extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1010 struct pll_lims *); 1011 extern int nouveau_bios_run_display_table(struct drm_device *, 1012 struct dcb_entry *, 1013 uint32_t script, int pxclk); 1014 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1015 int *length); 1016 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1017 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1018 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1019 bool *dl, bool *if_is_24bit); 1020 extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1021 int head, int pxclk); 1022 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1023 enum LVDS_script, int pxclk); 1024 1025 /* nouveau_ttm.c */ 1026 int nouveau_ttm_global_init(struct drm_nouveau_private *); 1027 void nouveau_ttm_global_release(struct drm_nouveau_private *); 1028 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1029 1030 /* nouveau_dp.c */ 1031 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1032 uint8_t *data, int data_nr); 1033 bool nouveau_dp_detect(struct drm_encoder *); 1034 bool nouveau_dp_link_train(struct drm_encoder *); 1035 1036 /* nv04_fb.c */ 1037 extern int nv04_fb_init(struct drm_device *); 1038 extern void nv04_fb_takedown(struct drm_device *); 1039 1040 /* nv10_fb.c */ 1041 extern int nv10_fb_init(struct drm_device *); 1042 extern void nv10_fb_takedown(struct drm_device *); 1043 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1044 uint32_t addr, uint32_t size, 1045 uint32_t pitch, uint32_t flags); 1046 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1047 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1048 1049 /* nv30_fb.c */ 1050 extern int nv30_fb_init(struct drm_device *); 1051 extern void nv30_fb_takedown(struct drm_device *); 1052 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1053 uint32_t addr, uint32_t size, 1054 uint32_t pitch, uint32_t flags); 1055 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1056 1057 /* nv40_fb.c */ 1058 extern int nv40_fb_init(struct drm_device *); 1059 extern void nv40_fb_takedown(struct drm_device *); 1060 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1061 1062 /* nv50_fb.c */ 1063 extern int nv50_fb_init(struct drm_device *); 1064 extern void nv50_fb_takedown(struct drm_device *); 1065 extern void nv50_fb_vm_trap(struct drm_device *, int display); 1066 1067 /* nvc0_fb.c */ 1068 extern int nvc0_fb_init(struct drm_device *); 1069 extern void nvc0_fb_takedown(struct drm_device *); 1070 1071 /* nv04_fifo.c */ 1072 extern int nv04_fifo_init(struct drm_device *); 1073 extern void nv04_fifo_fini(struct drm_device *); 1074 extern void nv04_fifo_disable(struct drm_device *); 1075 extern void nv04_fifo_enable(struct drm_device *); 1076 extern bool nv04_fifo_reassign(struct drm_device *, bool); 1077 extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1078 extern int nv04_fifo_channel_id(struct drm_device *); 1079 extern int nv04_fifo_create_context(struct nouveau_channel *); 1080 extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1081 extern int nv04_fifo_load_context(struct nouveau_channel *); 1082 extern int nv04_fifo_unload_context(struct drm_device *); 1083 extern void nv04_fifo_isr(struct drm_device *); 1084 1085 /* nv10_fifo.c */ 1086 extern int nv10_fifo_init(struct drm_device *); 1087 extern int nv10_fifo_channel_id(struct drm_device *); 1088 extern int nv10_fifo_create_context(struct nouveau_channel *); 1089 extern int nv10_fifo_load_context(struct nouveau_channel *); 1090 extern int nv10_fifo_unload_context(struct drm_device *); 1091 1092 /* nv40_fifo.c */ 1093 extern int nv40_fifo_init(struct drm_device *); 1094 extern int nv40_fifo_create_context(struct nouveau_channel *); 1095 extern int nv40_fifo_load_context(struct nouveau_channel *); 1096 extern int nv40_fifo_unload_context(struct drm_device *); 1097 1098 /* nv50_fifo.c */ 1099 extern int nv50_fifo_init(struct drm_device *); 1100 extern void nv50_fifo_takedown(struct drm_device *); 1101 extern int nv50_fifo_channel_id(struct drm_device *); 1102 extern int nv50_fifo_create_context(struct nouveau_channel *); 1103 extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1104 extern int nv50_fifo_load_context(struct nouveau_channel *); 1105 extern int nv50_fifo_unload_context(struct drm_device *); 1106 extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1107 1108 /* nvc0_fifo.c */ 1109 extern int nvc0_fifo_init(struct drm_device *); 1110 extern void nvc0_fifo_takedown(struct drm_device *); 1111 extern void nvc0_fifo_disable(struct drm_device *); 1112 extern void nvc0_fifo_enable(struct drm_device *); 1113 extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1114 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1115 extern int nvc0_fifo_channel_id(struct drm_device *); 1116 extern int nvc0_fifo_create_context(struct nouveau_channel *); 1117 extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1118 extern int nvc0_fifo_load_context(struct nouveau_channel *); 1119 extern int nvc0_fifo_unload_context(struct drm_device *); 1120 1121 /* nv04_graph.c */ 1122 extern int nv04_graph_create(struct drm_device *); 1123 extern void nv04_graph_fifo_access(struct drm_device *, bool); 1124 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1125 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1126 u32 class, u32 mthd, u32 data); 1127 extern struct nouveau_bitfield nv04_graph_nsource[]; 1128 1129 /* nv10_graph.c */ 1130 extern int nv10_graph_create(struct drm_device *); 1131 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1132 extern struct nouveau_bitfield nv10_graph_intr[]; 1133 extern struct nouveau_bitfield nv10_graph_nstatus[]; 1134 1135 /* nv20_graph.c */ 1136 extern int nv20_graph_create(struct drm_device *); 1137 1138 /* nv40_graph.c */ 1139 extern int nv40_graph_create(struct drm_device *); 1140 extern void nv40_grctx_init(struct nouveau_grctx *); 1141 1142 /* nv50_graph.c */ 1143 extern int nv50_graph_create(struct drm_device *); 1144 extern int nv50_grctx_init(struct nouveau_grctx *); 1145 extern struct nouveau_enum nv50_data_error_names[]; 1146 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1147 1148 /* nvc0_graph.c */ 1149 extern int nvc0_graph_create(struct drm_device *); 1150 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1151 1152 /* nv84_crypt.c */ 1153 extern int nv84_crypt_create(struct drm_device *); 1154 1155 /* nva3_copy.c */ 1156 extern int nva3_copy_create(struct drm_device *dev); 1157 1158 /* nvc0_copy.c */ 1159 extern int nvc0_copy_create(struct drm_device *dev, int engine); 1160 1161 /* nv40_mpeg.c */ 1162 extern int nv40_mpeg_create(struct drm_device *dev); 1163 1164 /* nv50_mpeg.c */ 1165 extern int nv50_mpeg_create(struct drm_device *dev); 1166 1167 /* nv04_instmem.c */ 1168 extern int nv04_instmem_init(struct drm_device *); 1169 extern void nv04_instmem_takedown(struct drm_device *); 1170 extern int nv04_instmem_suspend(struct drm_device *); 1171 extern void nv04_instmem_resume(struct drm_device *); 1172 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1173 extern void nv04_instmem_put(struct nouveau_gpuobj *); 1174 extern int nv04_instmem_map(struct nouveau_gpuobj *); 1175 extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1176 extern void nv04_instmem_flush(struct drm_device *); 1177 1178 /* nv50_instmem.c */ 1179 extern int nv50_instmem_init(struct drm_device *); 1180 extern void nv50_instmem_takedown(struct drm_device *); 1181 extern int nv50_instmem_suspend(struct drm_device *); 1182 extern void nv50_instmem_resume(struct drm_device *); 1183 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1184 extern void nv50_instmem_put(struct nouveau_gpuobj *); 1185 extern int nv50_instmem_map(struct nouveau_gpuobj *); 1186 extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1187 extern void nv50_instmem_flush(struct drm_device *); 1188 extern void nv84_instmem_flush(struct drm_device *); 1189 1190 /* nvc0_instmem.c */ 1191 extern int nvc0_instmem_init(struct drm_device *); 1192 extern void nvc0_instmem_takedown(struct drm_device *); 1193 extern int nvc0_instmem_suspend(struct drm_device *); 1194 extern void nvc0_instmem_resume(struct drm_device *); 1195 1196 /* nv04_mc.c */ 1197 extern int nv04_mc_init(struct drm_device *); 1198 extern void nv04_mc_takedown(struct drm_device *); 1199 1200 /* nv40_mc.c */ 1201 extern int nv40_mc_init(struct drm_device *); 1202 extern void nv40_mc_takedown(struct drm_device *); 1203 1204 /* nv50_mc.c */ 1205 extern int nv50_mc_init(struct drm_device *); 1206 extern void nv50_mc_takedown(struct drm_device *); 1207 1208 /* nv04_timer.c */ 1209 extern int nv04_timer_init(struct drm_device *); 1210 extern uint64_t nv04_timer_read(struct drm_device *); 1211 extern void nv04_timer_takedown(struct drm_device *); 1212 1213 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1214 unsigned long arg); 1215 1216 /* nv04_dac.c */ 1217 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1218 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1219 extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1220 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1221 extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1222 1223 /* nv04_dfp.c */ 1224 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1225 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1226 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1227 int head, bool dl); 1228 extern void nv04_dfp_disable(struct drm_device *dev, int head); 1229 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1230 1231 /* nv04_tv.c */ 1232 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1233 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1234 1235 /* nv17_tv.c */ 1236 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1237 1238 /* nv04_display.c */ 1239 extern int nv04_display_early_init(struct drm_device *); 1240 extern void nv04_display_late_takedown(struct drm_device *); 1241 extern int nv04_display_create(struct drm_device *); 1242 extern int nv04_display_init(struct drm_device *); 1243 extern void nv04_display_destroy(struct drm_device *); 1244 1245 /* nv04_crtc.c */ 1246 extern int nv04_crtc_create(struct drm_device *, int index); 1247 1248 /* nouveau_bo.c */ 1249 extern struct ttm_bo_driver nouveau_bo_driver; 1250 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1251 int size, int align, uint32_t flags, 1252 uint32_t tile_mode, uint32_t tile_flags, 1253 struct nouveau_bo **); 1254 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1255 extern int nouveau_bo_unpin(struct nouveau_bo *); 1256 extern int nouveau_bo_map(struct nouveau_bo *); 1257 extern void nouveau_bo_unmap(struct nouveau_bo *); 1258 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1259 uint32_t busy); 1260 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1261 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1262 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1263 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1264 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1265 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1266 bool no_wait_reserve, bool no_wait_gpu); 1267 1268 /* nouveau_fence.c */ 1269 struct nouveau_fence; 1270 extern int nouveau_fence_init(struct drm_device *); 1271 extern void nouveau_fence_fini(struct drm_device *); 1272 extern int nouveau_fence_channel_init(struct nouveau_channel *); 1273 extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1274 extern void nouveau_fence_update(struct nouveau_channel *); 1275 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1276 bool emit); 1277 extern int nouveau_fence_emit(struct nouveau_fence *); 1278 extern void nouveau_fence_work(struct nouveau_fence *fence, 1279 void (*work)(void *priv, bool signalled), 1280 void *priv); 1281 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1282 1283 extern bool __nouveau_fence_signalled(void *obj, void *arg); 1284 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1285 extern int __nouveau_fence_flush(void *obj, void *arg); 1286 extern void __nouveau_fence_unref(void **obj); 1287 extern void *__nouveau_fence_ref(void *obj); 1288 1289 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1290 { 1291 return __nouveau_fence_signalled(obj, NULL); 1292 } 1293 static inline int 1294 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1295 { 1296 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1297 } 1298 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1299 static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1300 { 1301 return __nouveau_fence_flush(obj, NULL); 1302 } 1303 static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1304 { 1305 __nouveau_fence_unref((void **)obj); 1306 } 1307 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1308 { 1309 return __nouveau_fence_ref(obj); 1310 } 1311 1312 /* nouveau_gem.c */ 1313 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1314 int size, int align, uint32_t domain, 1315 uint32_t tile_mode, uint32_t tile_flags, 1316 struct nouveau_bo **); 1317 extern int nouveau_gem_object_new(struct drm_gem_object *); 1318 extern void nouveau_gem_object_del(struct drm_gem_object *); 1319 extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1320 struct drm_file *); 1321 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1322 struct drm_file *); 1323 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1324 struct drm_file *); 1325 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1326 struct drm_file *); 1327 extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1328 struct drm_file *); 1329 1330 /* nouveau_display.c */ 1331 int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1332 void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1333 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1334 struct drm_pending_vblank_event *event); 1335 int nouveau_finish_page_flip(struct nouveau_channel *, 1336 struct nouveau_page_flip_state *); 1337 1338 /* nv10_gpio.c */ 1339 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1340 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1341 1342 /* nv50_gpio.c */ 1343 int nv50_gpio_init(struct drm_device *dev); 1344 void nv50_gpio_fini(struct drm_device *dev); 1345 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1346 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1347 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1348 void (*)(void *, int), void *); 1349 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1350 void (*)(void *, int), void *); 1351 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1352 1353 /* nv50_calc. */ 1354 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1355 int *N1, int *M1, int *N2, int *M2, int *P); 1356 int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1357 int clk, int *N, int *fN, int *M, int *P); 1358 1359 #ifndef ioread32_native 1360 #ifdef __BIG_ENDIAN 1361 #define ioread16_native ioread16be 1362 #define iowrite16_native iowrite16be 1363 #define ioread32_native ioread32be 1364 #define iowrite32_native iowrite32be 1365 #else /* def __BIG_ENDIAN */ 1366 #define ioread16_native ioread16 1367 #define iowrite16_native iowrite16 1368 #define ioread32_native ioread32 1369 #define iowrite32_native iowrite32 1370 #endif /* def __BIG_ENDIAN else */ 1371 #endif /* !ioread32_native */ 1372 1373 /* channel control reg access */ 1374 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1375 { 1376 return ioread32_native(chan->user + reg); 1377 } 1378 1379 static inline void nvchan_wr32(struct nouveau_channel *chan, 1380 unsigned reg, u32 val) 1381 { 1382 iowrite32_native(val, chan->user + reg); 1383 } 1384 1385 /* register access */ 1386 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1387 { 1388 struct drm_nouveau_private *dev_priv = dev->dev_private; 1389 return ioread32_native(dev_priv->mmio + reg); 1390 } 1391 1392 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1393 { 1394 struct drm_nouveau_private *dev_priv = dev->dev_private; 1395 iowrite32_native(val, dev_priv->mmio + reg); 1396 } 1397 1398 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1399 { 1400 u32 tmp = nv_rd32(dev, reg); 1401 nv_wr32(dev, reg, (tmp & ~mask) | val); 1402 return tmp; 1403 } 1404 1405 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1406 { 1407 struct drm_nouveau_private *dev_priv = dev->dev_private; 1408 return ioread8(dev_priv->mmio + reg); 1409 } 1410 1411 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1412 { 1413 struct drm_nouveau_private *dev_priv = dev->dev_private; 1414 iowrite8(val, dev_priv->mmio + reg); 1415 } 1416 1417 #define nv_wait(dev, reg, mask, val) \ 1418 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1419 #define nv_wait_ne(dev, reg, mask, val) \ 1420 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1421 1422 /* PRAMIN access */ 1423 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1424 { 1425 struct drm_nouveau_private *dev_priv = dev->dev_private; 1426 return ioread32_native(dev_priv->ramin + offset); 1427 } 1428 1429 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1430 { 1431 struct drm_nouveau_private *dev_priv = dev->dev_private; 1432 iowrite32_native(val, dev_priv->ramin + offset); 1433 } 1434 1435 /* object access */ 1436 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1437 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1438 1439 /* 1440 * Logging 1441 * Argument d is (struct drm_device *). 1442 */ 1443 #define NV_PRINTK(level, d, fmt, arg...) \ 1444 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1445 pci_name(d->pdev), ##arg) 1446 #ifndef NV_DEBUG_NOTRACE 1447 #define NV_DEBUG(d, fmt, arg...) do { \ 1448 if (drm_debug & DRM_UT_DRIVER) { \ 1449 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1450 __LINE__, ##arg); \ 1451 } \ 1452 } while (0) 1453 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1454 if (drm_debug & DRM_UT_KMS) { \ 1455 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1456 __LINE__, ##arg); \ 1457 } \ 1458 } while (0) 1459 #else 1460 #define NV_DEBUG(d, fmt, arg...) do { \ 1461 if (drm_debug & DRM_UT_DRIVER) \ 1462 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1463 } while (0) 1464 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1465 if (drm_debug & DRM_UT_KMS) \ 1466 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1467 } while (0) 1468 #endif 1469 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1470 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1471 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1472 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1473 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1474 1475 /* nouveau_reg_debug bitmask */ 1476 enum { 1477 NOUVEAU_REG_DEBUG_MC = 0x1, 1478 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1479 NOUVEAU_REG_DEBUG_FB = 0x4, 1480 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1481 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1482 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1483 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1484 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1485 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1486 NOUVEAU_REG_DEBUG_EVO = 0x200, 1487 }; 1488 1489 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1490 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1491 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1492 } while (0) 1493 1494 static inline bool 1495 nv_two_heads(struct drm_device *dev) 1496 { 1497 struct drm_nouveau_private *dev_priv = dev->dev_private; 1498 const int impl = dev->pci_device & 0x0ff0; 1499 1500 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1501 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1502 return true; 1503 1504 return false; 1505 } 1506 1507 static inline bool 1508 nv_gf4_disp_arch(struct drm_device *dev) 1509 { 1510 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1511 } 1512 1513 static inline bool 1514 nv_two_reg_pll(struct drm_device *dev) 1515 { 1516 struct drm_nouveau_private *dev_priv = dev->dev_private; 1517 const int impl = dev->pci_device & 0x0ff0; 1518 1519 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1520 return true; 1521 return false; 1522 } 1523 1524 static inline bool 1525 nv_match_device(struct drm_device *dev, unsigned device, 1526 unsigned sub_vendor, unsigned sub_device) 1527 { 1528 return dev->pdev->device == device && 1529 dev->pdev->subsystem_vendor == sub_vendor && 1530 dev->pdev->subsystem_device == sub_device; 1531 } 1532 1533 static inline void * 1534 nv_engine(struct drm_device *dev, int engine) 1535 { 1536 struct drm_nouveau_private *dev_priv = dev->dev_private; 1537 return (void *)dev_priv->eng[engine]; 1538 } 1539 1540 /* returns 1 if device is one of the nv4x using the 0x4497 object class, 1541 * helpful to determine a number of other hardware features 1542 */ 1543 static inline int 1544 nv44_graph_class(struct drm_device *dev) 1545 { 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 1548 if ((dev_priv->chipset & 0xf0) == 0x60) 1549 return 1; 1550 1551 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1552 } 1553 1554 /* memory type/access flags, do not match hardware values */ 1555 #define NV_MEM_ACCESS_RO 1 1556 #define NV_MEM_ACCESS_WO 2 1557 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1558 #define NV_MEM_ACCESS_SYS 4 1559 #define NV_MEM_ACCESS_VM 8 1560 1561 #define NV_MEM_TARGET_VRAM 0 1562 #define NV_MEM_TARGET_PCI 1 1563 #define NV_MEM_TARGET_PCI_NOSNOOP 2 1564 #define NV_MEM_TARGET_VM 3 1565 #define NV_MEM_TARGET_GART 4 1566 1567 #define NV_MEM_TYPE_VM 0x7f 1568 #define NV_MEM_COMP_VM 0x03 1569 1570 /* NV_SW object class */ 1571 #define NV_SW 0x0000506e 1572 #define NV_SW_DMA_SEMAPHORE 0x00000060 1573 #define NV_SW_SEMAPHORE_OFFSET 0x00000064 1574 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1575 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1576 #define NV_SW_YIELD 0x00000080 1577 #define NV_SW_DMA_VBLSEM 0x0000018c 1578 #define NV_SW_VBLSEM_OFFSET 0x00000400 1579 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1580 #define NV_SW_VBLSEM_RELEASE 0x00000408 1581 #define NV_SW_PAGE_FLIP 0x00000500 1582 1583 #endif /* __NOUVEAU_DRV_H__ */ 1584