1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved 4 */ 5 6 #include "dpu_hw_mdss.h" 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_wb.h" 10 #include "dpu_formats.h" 11 #include "dpu_kms.h" 12 13 #define WB_DST_FORMAT 0x000 14 #define WB_DST_OP_MODE 0x004 15 #define WB_DST_PACK_PATTERN 0x008 16 #define WB_DST0_ADDR 0x00C 17 #define WB_DST1_ADDR 0x010 18 #define WB_DST2_ADDR 0x014 19 #define WB_DST3_ADDR 0x018 20 #define WB_DST_YSTRIDE0 0x01C 21 #define WB_DST_YSTRIDE1 0x020 22 #define WB_DST_YSTRIDE1 0x020 23 #define WB_DST_DITHER_BITDEPTH 0x024 24 #define WB_DST_MATRIX_ROW0 0x030 25 #define WB_DST_MATRIX_ROW1 0x034 26 #define WB_DST_MATRIX_ROW2 0x038 27 #define WB_DST_MATRIX_ROW3 0x03C 28 #define WB_DST_WRITE_CONFIG 0x048 29 #define WB_ROTATION_DNSCALER 0x050 30 #define WB_ROTATOR_PIPE_DOWNSCALER 0x054 31 #define WB_N16_INIT_PHASE_X_C03 0x060 32 #define WB_N16_INIT_PHASE_X_C12 0x064 33 #define WB_N16_INIT_PHASE_Y_C03 0x068 34 #define WB_N16_INIT_PHASE_Y_C12 0x06C 35 #define WB_OUT_SIZE 0x074 36 #define WB_ALPHA_X_VALUE 0x078 37 #define WB_DANGER_LUT 0x084 38 #define WB_SAFE_LUT 0x088 39 #define WB_QOS_CTRL 0x090 40 #define WB_CREQ_LUT_0 0x098 41 #define WB_CREQ_LUT_1 0x09C 42 #define WB_UBWC_STATIC_CTRL 0x144 43 #define WB_MUX 0x150 44 #define WB_CROP_CTRL 0x154 45 #define WB_CROP_OFFSET 0x158 46 #define WB_CLK_CTRL 0x178 47 #define WB_CSC_BASE 0x260 48 #define WB_DST_ADDR_SW_STATUS 0x2B0 49 #define WB_CDP_CNTL 0x2B4 50 #define WB_OUT_IMAGE_SIZE 0x2C0 51 #define WB_OUT_XY 0x2C4 52 53 static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx, 54 struct dpu_hw_wb_cfg *data) 55 { 56 struct dpu_hw_blk_reg_map *c = &ctx->hw; 57 58 DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]); 59 DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]); 60 DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]); 61 DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]); 62 } 63 64 static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, 65 struct dpu_hw_wb_cfg *data) 66 { 67 struct dpu_hw_blk_reg_map *c = &ctx->hw; 68 const struct dpu_format *fmt = data->dest.format; 69 u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp; 70 u32 write_config = 0; 71 u32 opmode = 0; 72 u32 dst_addr_sw = 0; 73 74 chroma_samp = fmt->chroma_sample; 75 76 dst_format = (chroma_samp << 23) | 77 (fmt->fetch_planes << 19) | 78 (fmt->bits[C3_ALPHA] << 6) | 79 (fmt->bits[C2_R_Cr] << 4) | 80 (fmt->bits[C1_B_Cb] << 2) | 81 (fmt->bits[C0_G_Y] << 0); 82 83 if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) { 84 dst_format |= BIT(8); /* DSTC3_EN */ 85 if (!fmt->alpha_enable || 86 !(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA))) 87 dst_format |= BIT(14); /* DST_ALPHA_X */ 88 } 89 90 pattern = (fmt->element[3] << 24) | 91 (fmt->element[2] << 16) | 92 (fmt->element[1] << 8) | 93 (fmt->element[0] << 0); 94 95 dst_format |= (fmt->unpack_align_msb << 18) | 96 (fmt->unpack_tight << 17) | 97 ((fmt->unpack_count - 1) << 12) | 98 ((fmt->bpp - 1) << 9); 99 100 ystride0 = data->dest.plane_pitch[0] | 101 (data->dest.plane_pitch[1] << 16); 102 ystride1 = data->dest.plane_pitch[2] | 103 (data->dest.plane_pitch[3] << 16); 104 105 if (drm_rect_height(&data->roi) && drm_rect_width(&data->roi)) 106 outsize = (drm_rect_height(&data->roi) << 16) | drm_rect_width(&data->roi); 107 else 108 outsize = (data->dest.height << 16) | data->dest.width; 109 110 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); 111 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); 112 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); 113 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern); 114 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); 115 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); 116 DPU_REG_WRITE(c, WB_OUT_SIZE, outsize); 117 DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config); 118 DPU_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw); 119 } 120 121 static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb) 122 { 123 struct dpu_hw_blk_reg_map *c = &ctx->hw; 124 u32 image_size, out_size, out_xy; 125 126 image_size = (wb->dest.height << 16) | wb->dest.width; 127 out_xy = 0; 128 out_size = (drm_rect_height(&wb->roi) << 16) | drm_rect_width(&wb->roi); 129 130 DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size); 131 DPU_REG_WRITE(c, WB_OUT_XY, out_xy); 132 DPU_REG_WRITE(c, WB_OUT_SIZE, out_size); 133 } 134 135 static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, 136 struct dpu_hw_qos_cfg *cfg) 137 { 138 if (!ctx || !cfg) 139 return; 140 141 _dpu_hw_setup_qos_lut(&ctx->hw, WB_DANGER_LUT, 142 test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features), 143 cfg); 144 } 145 146 static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, 147 const struct dpu_format *fmt, 148 bool enable) 149 { 150 if (!ctx) 151 return; 152 153 dpu_setup_cdp(&ctx->hw, WB_CDP_CNTL, fmt, enable); 154 } 155 156 static void dpu_hw_wb_bind_pingpong_blk( 157 struct dpu_hw_wb *ctx, 158 const enum dpu_pingpong pp) 159 { 160 struct dpu_hw_blk_reg_map *c; 161 int mux_cfg; 162 163 if (!ctx) 164 return; 165 166 c = &ctx->hw; 167 168 mux_cfg = DPU_REG_READ(c, WB_MUX); 169 mux_cfg &= ~0xf; 170 171 if (pp) 172 mux_cfg |= (pp - PINGPONG_0) & 0x7; 173 else 174 mux_cfg |= 0xf; 175 176 DPU_REG_WRITE(c, WB_MUX, mux_cfg); 177 } 178 179 static bool dpu_hw_wb_setup_clk_force_ctrl(struct dpu_hw_wb *ctx, bool enable) 180 { 181 static const struct dpu_clk_ctrl_reg wb_clk_ctrl = { 182 .reg_off = WB_CLK_CTRL, 183 .bit_off = 0 184 }; 185 186 return dpu_hw_clk_force_ctrl(&ctx->hw, &wb_clk_ctrl, enable); 187 } 188 189 static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, 190 unsigned long features, const struct dpu_mdss_version *mdss_rev) 191 { 192 ops->setup_outaddress = dpu_hw_wb_setup_outaddress; 193 ops->setup_outformat = dpu_hw_wb_setup_format; 194 195 if (test_bit(DPU_WB_XY_ROI_OFFSET, &features)) 196 ops->setup_roi = dpu_hw_wb_roi; 197 198 if (test_bit(DPU_WB_QOS, &features)) 199 ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut; 200 201 if (test_bit(DPU_WB_CDP, &features)) 202 ops->setup_cdp = dpu_hw_wb_setup_cdp; 203 204 if (test_bit(DPU_WB_INPUT_CTRL, &features)) 205 ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk; 206 207 if (mdss_rev->core_major_ver >= 9) 208 ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl; 209 } 210 211 struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg, 212 void __iomem *addr, const struct dpu_mdss_version *mdss_rev) 213 { 214 struct dpu_hw_wb *c; 215 216 if (!addr) 217 return ERR_PTR(-EINVAL); 218 219 c = kzalloc(sizeof(*c), GFP_KERNEL); 220 if (!c) 221 return ERR_PTR(-ENOMEM); 222 223 c->hw.blk_addr = addr + cfg->base; 224 c->hw.log_mask = DPU_DBG_MASK_WB; 225 226 /* Assign ops */ 227 c->idx = cfg->id; 228 c->caps = cfg; 229 _setup_wb_ops(&c->ops, c->caps->features, mdss_rev); 230 231 return c; 232 } 233 234 void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb) 235 { 236 kfree(hw_wb); 237 } 238