1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #include "dpu_hwio.h" 14 #include "dpu_hw_catalog.h" 15 #include "dpu_hw_lm.h" 16 #include "dpu_hw_sspp.h" 17 #include "dpu_dbg.h" 18 #include "dpu_kms.h" 19 20 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 21 22 /* DPU_SSPP_SRC */ 23 #define SSPP_SRC_SIZE 0x00 24 #define SSPP_SRC_XY 0x08 25 #define SSPP_OUT_SIZE 0x0c 26 #define SSPP_OUT_XY 0x10 27 #define SSPP_SRC0_ADDR 0x14 28 #define SSPP_SRC1_ADDR 0x18 29 #define SSPP_SRC2_ADDR 0x1C 30 #define SSPP_SRC3_ADDR 0x20 31 #define SSPP_SRC_YSTRIDE0 0x24 32 #define SSPP_SRC_YSTRIDE1 0x28 33 #define SSPP_SRC_FORMAT 0x30 34 #define SSPP_SRC_UNPACK_PATTERN 0x34 35 #define SSPP_SRC_OP_MODE 0x38 36 37 /* SSPP_MULTIRECT*/ 38 #define SSPP_SRC_SIZE_REC1 0x16C 39 #define SSPP_SRC_XY_REC1 0x168 40 #define SSPP_OUT_SIZE_REC1 0x160 41 #define SSPP_OUT_XY_REC1 0x164 42 #define SSPP_SRC_FORMAT_REC1 0x174 43 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 44 #define SSPP_SRC_OP_MODE_REC1 0x17C 45 #define SSPP_MULTIRECT_OPMODE 0x170 46 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 47 #define SSPP_EXCL_REC_SIZE_REC1 0x184 48 #define SSPP_EXCL_REC_XY_REC1 0x188 49 50 #define MDSS_MDP_OP_DEINTERLACE BIT(22) 51 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) 52 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) 53 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) 54 #define MDSS_MDP_OP_IGC_EN BIT(16) 55 #define MDSS_MDP_OP_FLIP_UD BIT(14) 56 #define MDSS_MDP_OP_FLIP_LR BIT(13) 57 #define MDSS_MDP_OP_BWC_EN BIT(0) 58 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) 59 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) 60 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) 61 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) 62 63 #define SSPP_SRC_CONSTANT_COLOR 0x3c 64 #define SSPP_EXCL_REC_CTL 0x40 65 #define SSPP_UBWC_STATIC_CTRL 0x44 66 #define SSPP_FETCH_CONFIG 0x048 67 #define SSPP_DANGER_LUT 0x60 68 #define SSPP_SAFE_LUT 0x64 69 #define SSPP_CREQ_LUT 0x68 70 #define SSPP_QOS_CTRL 0x6C 71 #define SSPP_DECIMATION_CONFIG 0xB4 72 #define SSPP_SRC_ADDR_SW_STATUS 0x70 73 #define SSPP_CREQ_LUT_0 0x74 74 #define SSPP_CREQ_LUT_1 0x78 75 #define SSPP_SW_PIX_EXT_C0_LR 0x100 76 #define SSPP_SW_PIX_EXT_C0_TB 0x104 77 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 78 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 79 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 80 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 81 #define SSPP_SW_PIX_EXT_C3_LR 0x120 82 #define SSPP_SW_PIX_EXT_C3_TB 0x124 83 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 84 #define SSPP_TRAFFIC_SHAPER 0x130 85 #define SSPP_CDP_CNTL 0x134 86 #define SSPP_UBWC_ERROR_STATUS 0x138 87 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 88 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 89 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 90 #define SSPP_EXCL_REC_SIZE 0x1B4 91 #define SSPP_EXCL_REC_XY 0x1B8 92 #define SSPP_VIG_OP_MODE 0x0 93 #define SSPP_VIG_CSC_10_OP_MODE 0x0 94 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF 95 96 /* SSPP_QOS_CTRL */ 97 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) 98 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) 99 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 100 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 101 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 102 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 103 104 /* DPU_SSPP_SCALER_QSEED2 */ 105 #define SCALE_CONFIG 0x04 106 #define COMP0_3_PHASE_STEP_X 0x10 107 #define COMP0_3_PHASE_STEP_Y 0x14 108 #define COMP1_2_PHASE_STEP_X 0x18 109 #define COMP1_2_PHASE_STEP_Y 0x1c 110 #define COMP0_3_INIT_PHASE_X 0x20 111 #define COMP0_3_INIT_PHASE_Y 0x24 112 #define COMP1_2_INIT_PHASE_X 0x28 113 #define COMP1_2_INIT_PHASE_Y 0x2C 114 #define VIG_0_QSEED2_SHARP 0x30 115 116 /* 117 * Definitions for ViG op modes 118 */ 119 #define VIG_OP_CSC_DST_DATAFMT BIT(19) 120 #define VIG_OP_CSC_SRC_DATAFMT BIT(18) 121 #define VIG_OP_CSC_EN BIT(17) 122 #define VIG_OP_MEM_PROT_CONT BIT(15) 123 #define VIG_OP_MEM_PROT_VAL BIT(14) 124 #define VIG_OP_MEM_PROT_SAT BIT(13) 125 #define VIG_OP_MEM_PROT_HUE BIT(12) 126 #define VIG_OP_HIST BIT(8) 127 #define VIG_OP_SKY_COL BIT(7) 128 #define VIG_OP_FOIL BIT(6) 129 #define VIG_OP_SKIN_COL BIT(5) 130 #define VIG_OP_PA_EN BIT(4) 131 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) 132 #define VIG_OP_MEM_PROT_BLEND BIT(1) 133 134 /* 135 * Definitions for CSC 10 op modes 136 */ 137 #define VIG_CSC_10_SRC_DATAFMT BIT(1) 138 #define VIG_CSC_10_EN BIT(0) 139 #define CSC_10BIT_OFFSET 4 140 141 /* traffic shaper clock in Hz */ 142 #define TS_CLK 19200000 143 144 static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, 145 int s_id, 146 u32 *idx) 147 { 148 int rc = 0; 149 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; 150 151 if (!ctx) 152 return -EINVAL; 153 154 switch (s_id) { 155 case DPU_SSPP_SRC: 156 *idx = sblk->src_blk.base; 157 break; 158 case DPU_SSPP_SCALER_QSEED2: 159 case DPU_SSPP_SCALER_QSEED3: 160 case DPU_SSPP_SCALER_RGB: 161 *idx = sblk->scaler_blk.base; 162 break; 163 case DPU_SSPP_CSC: 164 case DPU_SSPP_CSC_10BIT: 165 *idx = sblk->csc_blk.base; 166 break; 167 default: 168 rc = -EINVAL; 169 } 170 171 return rc; 172 } 173 174 static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, 175 enum dpu_sspp_multirect_index index, 176 enum dpu_sspp_multirect_mode mode) 177 { 178 u32 mode_mask; 179 u32 idx; 180 181 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 182 return; 183 184 if (index == DPU_SSPP_RECT_SOLO) { 185 /** 186 * if rect index is RECT_SOLO, we cannot expect a 187 * virtual plane sharing the same SSPP id. So we go 188 * and disable multirect 189 */ 190 mode_mask = 0; 191 } else { 192 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); 193 mode_mask |= index; 194 if (mode == DPU_SSPP_MULTIRECT_TIME_MX) 195 mode_mask |= BIT(2); 196 else 197 mode_mask &= ~BIT(2); 198 } 199 200 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); 201 } 202 203 static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, 204 u32 mask, u8 en) 205 { 206 u32 idx; 207 u32 opmode; 208 209 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || 210 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || 211 !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 212 return; 213 214 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); 215 216 if (en) 217 opmode |= mask; 218 else 219 opmode &= ~mask; 220 221 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); 222 } 223 224 static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, 225 u32 mask, u8 en) 226 { 227 u32 idx; 228 u32 opmode; 229 230 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) 231 return; 232 233 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); 234 if (en) 235 opmode |= mask; 236 else 237 opmode &= ~mask; 238 239 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); 240 } 241 242 /** 243 * Setup source pixel format, flip, 244 */ 245 static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, 246 const struct dpu_format *fmt, u32 flags, 247 enum dpu_sspp_multirect_index rect_mode) 248 { 249 struct dpu_hw_blk_reg_map *c; 250 u32 chroma_samp, unpack, src_format; 251 u32 opmode = 0; 252 u32 fast_clear = 0; 253 u32 op_mode_off, unpack_pat_off, format_off; 254 u32 idx; 255 256 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) 257 return; 258 259 if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { 260 op_mode_off = SSPP_SRC_OP_MODE; 261 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; 262 format_off = SSPP_SRC_FORMAT; 263 } else { 264 op_mode_off = SSPP_SRC_OP_MODE_REC1; 265 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; 266 format_off = SSPP_SRC_FORMAT_REC1; 267 } 268 269 c = &ctx->hw; 270 opmode = DPU_REG_READ(c, op_mode_off + idx); 271 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | 272 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); 273 274 if (flags & DPU_SSPP_FLIP_LR) 275 opmode |= MDSS_MDP_OP_FLIP_LR; 276 if (flags & DPU_SSPP_FLIP_UD) 277 opmode |= MDSS_MDP_OP_FLIP_UD; 278 279 chroma_samp = fmt->chroma_sample; 280 if (flags & DPU_SSPP_SOURCE_ROTATED_90) { 281 if (chroma_samp == DPU_CHROMA_H2V1) 282 chroma_samp = DPU_CHROMA_H1V2; 283 else if (chroma_samp == DPU_CHROMA_H1V2) 284 chroma_samp = DPU_CHROMA_H2V1; 285 } 286 287 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | 288 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | 289 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); 290 291 if (flags & DPU_SSPP_ROT_90) 292 src_format |= BIT(11); /* ROT90 */ 293 294 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) 295 src_format |= BIT(8); /* SRCC3_EN */ 296 297 if (flags & DPU_SSPP_SOLID_FILL) 298 src_format |= BIT(22); 299 300 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | 301 (fmt->element[1] << 8) | (fmt->element[0] << 0); 302 src_format |= ((fmt->unpack_count - 1) << 12) | 303 (fmt->unpack_tight << 17) | 304 (fmt->unpack_align_msb << 18) | 305 ((fmt->bpp - 1) << 9); 306 307 if (fmt->fetch_mode != DPU_FETCH_LINEAR) { 308 if (DPU_FORMAT_IS_UBWC(fmt)) 309 opmode |= MDSS_MDP_OP_BWC_EN; 310 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 311 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 312 DPU_FETCH_CONFIG_RESET_VALUE | 313 ctx->mdp->highest_bank_bit << 18); 314 if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) { 315 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 316 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 317 fast_clear | (ctx->mdp->ubwc_swizzle) | 318 (ctx->mdp->highest_bank_bit << 4)); 319 } 320 } 321 322 opmode |= MDSS_MDP_OP_PE_OVERRIDE; 323 324 /* if this is YUV pixel format, enable CSC */ 325 if (DPU_FORMAT_IS_YUV(fmt)) 326 src_format |= BIT(15); 327 328 if (DPU_FORMAT_IS_DX(fmt)) 329 src_format |= BIT(14); 330 331 /* update scaler opmode, if appropriate */ 332 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 333 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, 334 DPU_FORMAT_IS_YUV(fmt)); 335 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) 336 _sspp_setup_csc10_opmode(ctx, 337 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, 338 DPU_FORMAT_IS_YUV(fmt)); 339 340 DPU_REG_WRITE(c, format_off + idx, src_format); 341 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); 342 DPU_REG_WRITE(c, op_mode_off + idx, opmode); 343 344 /* clear previous UBWC error */ 345 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); 346 } 347 348 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, 349 struct dpu_hw_pixel_ext *pe_ext) 350 { 351 struct dpu_hw_blk_reg_map *c; 352 u8 color; 353 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; 354 const u32 bytemask = 0xff; 355 const u32 shortmask = 0xffff; 356 u32 idx; 357 358 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) 359 return; 360 361 c = &ctx->hw; 362 363 /* program SW pixel extension override for all pipes*/ 364 for (color = 0; color < DPU_MAX_PLANES; color++) { 365 /* color 2 has the same set of registers as color 1 */ 366 if (color == 2) 367 continue; 368 369 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| 370 ((pe_ext->right_rpt[color] & bytemask) << 16)| 371 ((pe_ext->left_ftch[color] & bytemask) << 8)| 372 (pe_ext->left_rpt[color] & bytemask); 373 374 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| 375 ((pe_ext->btm_rpt[color] & bytemask) << 16)| 376 ((pe_ext->top_ftch[color] & bytemask) << 8)| 377 (pe_ext->top_rpt[color] & bytemask); 378 379 tot_req_pixels[color] = (((pe_ext->roi_h[color] + 380 pe_ext->num_ext_pxls_top[color] + 381 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | 382 ((pe_ext->roi_w[color] + 383 pe_ext->num_ext_pxls_left[color] + 384 pe_ext->num_ext_pxls_right[color]) & shortmask); 385 } 386 387 /* color 0 */ 388 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); 389 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); 390 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, 391 tot_req_pixels[0]); 392 393 /* color 1 and color 2 */ 394 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); 395 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); 396 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, 397 tot_req_pixels[1]); 398 399 /* color 3 */ 400 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); 401 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); 402 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, 403 tot_req_pixels[3]); 404 } 405 406 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, 407 struct dpu_hw_pipe_cfg *sspp, 408 struct dpu_hw_pixel_ext *pe, 409 void *scaler_cfg) 410 { 411 u32 idx; 412 struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; 413 414 (void)pe; 415 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp 416 || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk) 417 return; 418 419 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, 420 ctx->cap->sblk->scaler_blk.version, 421 sspp->layout.format); 422 } 423 424 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) 425 { 426 u32 idx; 427 428 if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) 429 return 0; 430 431 return dpu_hw_get_scaler3_ver(&ctx->hw, idx); 432 } 433 434 /** 435 * dpu_hw_sspp_setup_rects() 436 */ 437 static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, 438 struct dpu_hw_pipe_cfg *cfg, 439 enum dpu_sspp_multirect_index rect_index) 440 { 441 struct dpu_hw_blk_reg_map *c; 442 u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; 443 u32 src_size_off, src_xy_off, out_size_off, out_xy_off; 444 u32 idx; 445 446 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) 447 return; 448 449 c = &ctx->hw; 450 451 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { 452 src_size_off = SSPP_SRC_SIZE; 453 src_xy_off = SSPP_SRC_XY; 454 out_size_off = SSPP_OUT_SIZE; 455 out_xy_off = SSPP_OUT_XY; 456 } else { 457 src_size_off = SSPP_SRC_SIZE_REC1; 458 src_xy_off = SSPP_SRC_XY_REC1; 459 out_size_off = SSPP_OUT_SIZE_REC1; 460 out_xy_off = SSPP_OUT_XY_REC1; 461 } 462 463 464 /* src and dest rect programming */ 465 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 466 src_size = (drm_rect_height(&cfg->src_rect) << 16) | 467 drm_rect_width(&cfg->src_rect); 468 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; 469 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | 470 drm_rect_width(&cfg->dst_rect); 471 472 if (rect_index == DPU_SSPP_RECT_SOLO) { 473 ystride0 = (cfg->layout.plane_pitch[0]) | 474 (cfg->layout.plane_pitch[1] << 16); 475 ystride1 = (cfg->layout.plane_pitch[2]) | 476 (cfg->layout.plane_pitch[3] << 16); 477 } else { 478 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); 479 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); 480 481 if (rect_index == DPU_SSPP_RECT_0) { 482 ystride0 = (ystride0 & 0xFFFF0000) | 483 (cfg->layout.plane_pitch[0] & 0x0000FFFF); 484 ystride1 = (ystride1 & 0xFFFF0000)| 485 (cfg->layout.plane_pitch[2] & 0x0000FFFF); 486 } else { 487 ystride0 = (ystride0 & 0x0000FFFF) | 488 ((cfg->layout.plane_pitch[0] << 16) & 489 0xFFFF0000); 490 ystride1 = (ystride1 & 0x0000FFFF) | 491 ((cfg->layout.plane_pitch[2] << 16) & 492 0xFFFF0000); 493 } 494 } 495 496 /* rectangle register programming */ 497 DPU_REG_WRITE(c, src_size_off + idx, src_size); 498 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); 499 DPU_REG_WRITE(c, out_size_off + idx, dst_size); 500 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); 501 502 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); 503 DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); 504 } 505 506 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, 507 struct dpu_hw_pipe_cfg *cfg, 508 enum dpu_sspp_multirect_index rect_mode) 509 { 510 int i; 511 u32 idx; 512 513 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 514 return; 515 516 if (rect_mode == DPU_SSPP_RECT_SOLO) { 517 for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) 518 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, 519 cfg->layout.plane_addr[i]); 520 } else if (rect_mode == DPU_SSPP_RECT_0) { 521 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, 522 cfg->layout.plane_addr[0]); 523 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, 524 cfg->layout.plane_addr[2]); 525 } else { 526 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, 527 cfg->layout.plane_addr[0]); 528 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, 529 cfg->layout.plane_addr[2]); 530 } 531 } 532 533 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, 534 struct dpu_csc_cfg *data) 535 { 536 u32 idx; 537 bool csc10 = false; 538 539 if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) 540 return; 541 542 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { 543 idx += CSC_10BIT_OFFSET; 544 csc10 = true; 545 } 546 547 dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); 548 } 549 550 static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum 551 dpu_sspp_multirect_index rect_index) 552 { 553 u32 idx; 554 555 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 556 return; 557 558 if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) 559 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); 560 else 561 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, 562 color); 563 } 564 565 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, 566 struct dpu_hw_pipe_qos_cfg *cfg) 567 { 568 u32 idx; 569 570 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 571 return; 572 573 DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); 574 DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); 575 } 576 577 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, 578 struct dpu_hw_pipe_qos_cfg *cfg) 579 { 580 u32 idx; 581 582 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 583 return; 584 585 if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { 586 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); 587 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, 588 cfg->creq_lut >> 32); 589 } else { 590 DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); 591 } 592 } 593 594 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, 595 struct dpu_hw_pipe_qos_cfg *cfg) 596 { 597 u32 idx; 598 u32 qos_ctrl = 0; 599 600 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 601 return; 602 603 if (cfg->vblank_en) { 604 qos_ctrl |= ((cfg->creq_vblank & 605 SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << 606 SSPP_QOS_CTRL_CREQ_VBLANK_OFF); 607 qos_ctrl |= ((cfg->danger_vblank & 608 SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << 609 SSPP_QOS_CTRL_DANGER_VBLANK_OFF); 610 qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; 611 } 612 613 if (cfg->danger_safe_en) 614 qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; 615 616 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); 617 } 618 619 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, 620 struct dpu_hw_pipe_cdp_cfg *cfg) 621 { 622 u32 idx; 623 u32 cdp_cntl = 0; 624 625 if (!ctx || !cfg) 626 return; 627 628 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) 629 return; 630 631 if (cfg->enable) 632 cdp_cntl |= BIT(0); 633 if (cfg->ubwc_meta_enable) 634 cdp_cntl |= BIT(1); 635 if (cfg->tile_amortize_enable) 636 cdp_cntl |= BIT(2); 637 if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64) 638 cdp_cntl |= BIT(3); 639 640 DPU_REG_WRITE(&ctx->hw, SSPP_CDP_CNTL, cdp_cntl); 641 } 642 643 static void _setup_layer_ops(struct dpu_hw_pipe *c, 644 unsigned long features) 645 { 646 if (test_bit(DPU_SSPP_SRC, &features)) { 647 c->ops.setup_format = dpu_hw_sspp_setup_format; 648 c->ops.setup_rects = dpu_hw_sspp_setup_rects; 649 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; 650 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; 651 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; 652 } 653 654 if (test_bit(DPU_SSPP_QOS, &features)) { 655 c->ops.setup_danger_safe_lut = 656 dpu_hw_sspp_setup_danger_safe_lut; 657 c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut; 658 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; 659 } 660 661 if (test_bit(DPU_SSPP_CSC, &features) || 662 test_bit(DPU_SSPP_CSC_10BIT, &features)) 663 c->ops.setup_csc = dpu_hw_sspp_setup_csc; 664 665 if (dpu_hw_sspp_multirect_enabled(c->cap)) 666 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 667 668 if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) { 669 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 670 c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; 671 } 672 673 if (test_bit(DPU_SSPP_CDP, &features)) 674 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; 675 } 676 677 static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, 678 void __iomem *addr, 679 struct dpu_mdss_cfg *catalog, 680 struct dpu_hw_blk_reg_map *b) 681 { 682 int i; 683 684 if ((sspp < SSPP_MAX) && catalog && addr && b) { 685 for (i = 0; i < catalog->sspp_count; i++) { 686 if (sspp == catalog->sspp[i].id) { 687 b->base_off = addr; 688 b->blk_off = catalog->sspp[i].base; 689 b->length = catalog->sspp[i].len; 690 b->hwversion = catalog->hwversion; 691 b->log_mask = DPU_DBG_MASK_SSPP; 692 return &catalog->sspp[i]; 693 } 694 } 695 } 696 697 return ERR_PTR(-ENOMEM); 698 } 699 700 static struct dpu_hw_blk_ops dpu_hw_ops = { 701 .start = NULL, 702 .stop = NULL, 703 }; 704 705 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, 706 void __iomem *addr, struct dpu_mdss_cfg *catalog, 707 bool is_virtual_pipe) 708 { 709 struct dpu_hw_pipe *hw_pipe; 710 struct dpu_sspp_cfg *cfg; 711 int rc; 712 713 if (!addr || !catalog) 714 return ERR_PTR(-EINVAL); 715 716 hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); 717 if (!hw_pipe) 718 return ERR_PTR(-ENOMEM); 719 720 cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); 721 if (IS_ERR_OR_NULL(cfg)) { 722 kfree(hw_pipe); 723 return ERR_PTR(-EINVAL); 724 } 725 726 /* Assign ops */ 727 hw_pipe->catalog = catalog; 728 hw_pipe->mdp = &catalog->mdp[0]; 729 hw_pipe->idx = idx; 730 hw_pipe->cap = cfg; 731 _setup_layer_ops(hw_pipe, hw_pipe->cap->features); 732 733 rc = dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); 734 if (rc) { 735 DPU_ERROR("failed to init hw blk %d\n", rc); 736 goto blk_init_error; 737 } 738 739 return hw_pipe; 740 741 blk_init_error: 742 kzfree(hw_pipe); 743 744 return ERR_PTR(rc); 745 } 746 747 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) 748 { 749 if (ctx) 750 dpu_hw_blk_destroy(&ctx->base); 751 kfree(ctx); 752 } 753 754