1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define MAX_IMG_WIDTH 0x3fff 25 #define MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_DUAL_MIXERS 2 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * Supported UBWC feature versions 33 */ 34 enum { 35 DPU_HW_UBWC_VER_10 = 0x100, 36 DPU_HW_UBWC_VER_20 = 0x200, 37 DPU_HW_UBWC_VER_30 = 0x300, 38 DPU_HW_UBWC_VER_40 = 0x400, 39 }; 40 41 /** 42 * MDP TOP BLOCK features 43 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 44 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 45 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 46 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 47 * compression initial revision 48 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 49 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 50 * in a failure 51 * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register 52 * (moved into INTF block since DPU 5.0.0) 53 * @DPU_MDP_MAX Maximum value 54 55 */ 56 enum { 57 DPU_MDP_PANIC_PER_PIPE = 0x1, 58 DPU_MDP_10BIT_SUPPORT, 59 DPU_MDP_BWC, 60 DPU_MDP_UBWC_1_0, 61 DPU_MDP_UBWC_1_5, 62 DPU_MDP_AUDIO_SELECT, 63 DPU_MDP_PERIPH_0_REMOVED, 64 DPU_MDP_VSYNC_SEL, 65 DPU_MDP_MAX 66 }; 67 68 /** 69 * SSPP sub-blocks/features 70 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 71 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 72 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 73 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 74 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 75 * @DPU_SSPP_CSC, Support of Color space converion 76 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 77 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 78 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 79 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 80 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 81 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 82 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 83 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 84 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 85 * @DPU_SSPP_CDP Supports client driven prefetch 86 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 87 * @DPU_SSPP_MAX maximum value 88 */ 89 enum { 90 DPU_SSPP_SCALER_QSEED2 = 0x1, 91 DPU_SSPP_SCALER_QSEED3, 92 DPU_SSPP_SCALER_QSEED3LITE, 93 DPU_SSPP_SCALER_QSEED4, 94 DPU_SSPP_SCALER_RGB, 95 DPU_SSPP_CSC, 96 DPU_SSPP_CSC_10BIT, 97 DPU_SSPP_CURSOR, 98 DPU_SSPP_QOS, 99 DPU_SSPP_QOS_8LVL, 100 DPU_SSPP_EXCL_RECT, 101 DPU_SSPP_SMART_DMA_V1, 102 DPU_SSPP_SMART_DMA_V2, 103 DPU_SSPP_TS_PREFILL, 104 DPU_SSPP_TS_PREFILL_REC1, 105 DPU_SSPP_CDP, 106 DPU_SSPP_INLINE_ROTATION, 107 DPU_SSPP_MAX 108 }; 109 110 /* 111 * MIXER sub-blocks/features 112 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 113 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 114 * @DPU_MIXER_GC Gamma correction block 115 * @DPU_DIM_LAYER Layer mixer supports dim layer 116 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 117 * @DPU_MIXER_MAX maximum value 118 */ 119 enum { 120 DPU_MIXER_LAYER = 0x1, 121 DPU_MIXER_SOURCESPLIT, 122 DPU_MIXER_GC, 123 DPU_DIM_LAYER, 124 DPU_MIXER_COMBINED_ALPHA, 125 DPU_MIXER_MAX 126 }; 127 128 /** 129 * DSPP sub-blocks 130 * @DPU_DSPP_PCC Panel color correction block 131 */ 132 enum { 133 DPU_DSPP_PCC = 0x1, 134 DPU_DSPP_MAX 135 }; 136 137 /** 138 * PINGPONG sub-blocks 139 * @DPU_PINGPONG_TE Tear check block 140 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 141 * @DPU_PINGPONG_SPLIT PP block supports split fifo 142 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 143 * @DPU_PINGPONG_DITHER Dither blocks 144 * @DPU_PINGPONG_DSC PP block supports DSC 145 * @DPU_PINGPONG_MAX 146 */ 147 enum { 148 DPU_PINGPONG_TE = 0x1, 149 DPU_PINGPONG_TE2, 150 DPU_PINGPONG_SPLIT, 151 DPU_PINGPONG_SLAVE, 152 DPU_PINGPONG_DITHER, 153 DPU_PINGPONG_DSC, 154 DPU_PINGPONG_MAX 155 }; 156 157 /** 158 * CTL sub-blocks 159 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 160 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 161 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 162 * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register 163 * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 164 * @DPU_CTL_MAX 165 */ 166 enum { 167 DPU_CTL_SPLIT_DISPLAY = 0x1, 168 DPU_CTL_ACTIVE_CFG, 169 DPU_CTL_FETCH_ACTIVE, 170 DPU_CTL_VM_CFG, 171 DPU_CTL_HAS_LAYER_EXT4, 172 DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 173 DPU_CTL_MAX 174 }; 175 176 /** 177 * INTF sub-blocks 178 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 179 * pixel data arrives to this INTF 180 * @DPU_INTF_TE INTF block has TE configuration support 181 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 182 * than video timing 183 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 184 * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register 185 * @DPU_INTF_MAX 186 */ 187 enum { 188 DPU_INTF_INPUT_CTRL = 0x1, 189 DPU_INTF_TE, 190 DPU_DATA_HCTL_EN, 191 DPU_INTF_STATUS_SUPPORTED, 192 DPU_INTF_DATA_COMPRESS, 193 DPU_INTF_MAX 194 }; 195 196 /** 197 * WB sub-blocks and features 198 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 199 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 200 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 201 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 202 * @DPU_WB_DITHER, Dither block 203 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 204 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 205 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 206 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 207 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 208 * the destination image 209 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 210 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 211 * @DPU_WB_CDP Writeback supports client driven prefetch 212 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 213 * data arrives. 214 * @DPU_WB_CROP CWB supports cropping 215 * @DPU_WB_MAX maximum value 216 */ 217 enum { 218 DPU_WB_LINE_MODE = 0x1, 219 DPU_WB_BLOCK_MODE, 220 DPU_WB_UBWC, 221 DPU_WB_YUV_CONFIG, 222 DPU_WB_PIPE_ALPHA, 223 DPU_WB_XY_ROI_OFFSET, 224 DPU_WB_QOS, 225 DPU_WB_QOS_8LVL, 226 DPU_WB_CDP, 227 DPU_WB_INPUT_CTRL, 228 DPU_WB_CROP, 229 DPU_WB_MAX 230 }; 231 232 /** 233 * VBIF sub-blocks and features 234 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 235 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 236 * @DPU_VBIF_MAX maximum value 237 */ 238 enum { 239 DPU_VBIF_QOS_OTLIM = 0x1, 240 DPU_VBIF_QOS_REMAP, 241 DPU_VBIF_MAX 242 }; 243 244 /** 245 * DSC sub-blocks/features 246 * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 247 * the pixel output from this DSC. 248 * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 249 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 250 * @DPU_DSC_MAX 251 */ 252 enum { 253 DPU_DSC_OUTPUT_CTRL = 0x1, 254 DPU_DSC_HW_REV_1_2, 255 DPU_DSC_NATIVE_42x_EN, 256 DPU_DSC_MAX 257 }; 258 259 /** 260 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 261 * @name: string name for debug purposes 262 * @id: enum identifying this block 263 * @base: register base offset to mdss 264 * @len: length of hardware block 265 * @features bit mask identifying sub-blocks/features 266 */ 267 #define DPU_HW_BLK_INFO \ 268 char name[DPU_HW_BLK_NAME_LEN]; \ 269 u32 id; \ 270 u32 base; \ 271 u32 len; \ 272 unsigned long features 273 274 /** 275 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 276 * @name: string name for debug purposes 277 * @id: enum identifying this sub-block 278 * @base: offset of this sub-block relative to the block 279 * offset 280 * @len register block length of this sub-block 281 */ 282 #define DPU_HW_SUBBLK_INFO \ 283 char name[DPU_HW_BLK_NAME_LEN]; \ 284 u32 id; \ 285 u32 base; \ 286 u32 len 287 288 /** 289 * struct dpu_scaler_blk: Scaler information 290 * @info: HW register and features supported by this sub-blk 291 * @version: qseed block revision 292 */ 293 struct dpu_scaler_blk { 294 DPU_HW_SUBBLK_INFO; 295 u32 version; 296 }; 297 298 struct dpu_csc_blk { 299 DPU_HW_SUBBLK_INFO; 300 }; 301 302 /** 303 * struct dpu_pp_blk : Pixel processing sub-blk information 304 * @info: HW register and features supported by this sub-blk 305 * @version: HW Algorithm version 306 */ 307 struct dpu_pp_blk { 308 DPU_HW_SUBBLK_INFO; 309 u32 version; 310 }; 311 312 /** 313 * struct dpu_dsc_blk - DSC Encoder sub-blk information 314 * @info: HW register and features supported by this sub-blk 315 */ 316 struct dpu_dsc_blk { 317 DPU_HW_SUBBLK_INFO; 318 }; 319 320 /** 321 * enum dpu_qos_lut_usage - define QoS LUT use cases 322 */ 323 enum dpu_qos_lut_usage { 324 DPU_QOS_LUT_USAGE_LINEAR, 325 DPU_QOS_LUT_USAGE_MACROTILE, 326 DPU_QOS_LUT_USAGE_NRT, 327 DPU_QOS_LUT_USAGE_MAX, 328 }; 329 330 /** 331 * struct dpu_qos_lut_entry - define QoS LUT table entry 332 * @fl: fill level, or zero on last entry to indicate default lut 333 * @lut: lut to use if equal to or less than fill level 334 */ 335 struct dpu_qos_lut_entry { 336 u32 fl; 337 u64 lut; 338 }; 339 340 /** 341 * struct dpu_qos_lut_tbl - define QoS LUT table 342 * @nentry: number of entry in this table 343 * @entries: Pointer to table entries 344 */ 345 struct dpu_qos_lut_tbl { 346 u32 nentry; 347 const struct dpu_qos_lut_entry *entries; 348 }; 349 350 /** 351 * struct dpu_rotation_cfg - define inline rotation config 352 * @rot_maxheight: max pre rotated height allowed for rotation 353 * @rot_num_formats: number of elements in @rot_format_list 354 * @rot_format_list: list of supported rotator formats 355 */ 356 struct dpu_rotation_cfg { 357 u32 rot_maxheight; 358 size_t rot_num_formats; 359 const u32 *rot_format_list; 360 }; 361 362 /** 363 * struct dpu_caps - define DPU capabilities 364 * @max_mixer_width max layer mixer line width support. 365 * @max_mixer_blendstages max layer mixer blend stages or 366 * supported z order 367 * @qseed_type qseed2 or qseed3 support. 368 * @has_src_split source split feature status 369 * @has_dim_layer dim layer feature status 370 * @has_idle_pc indicate if idle power collapse feature is supported 371 * @has_3d_merge indicate if 3D merge is supported 372 * @max_linewidth max linewidth for sspp 373 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 374 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 375 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 376 */ 377 struct dpu_caps { 378 u32 max_mixer_width; 379 u32 max_mixer_blendstages; 380 u32 qseed_type; 381 bool has_src_split; 382 bool has_dim_layer; 383 bool has_idle_pc; 384 bool has_3d_merge; 385 /* SSPP limits */ 386 u32 max_linewidth; 387 u32 pixel_ram_size; 388 u32 max_hdeci_exp; 389 u32 max_vdeci_exp; 390 }; 391 392 /** 393 * struct dpu_sspp_sub_blks : SSPP sub-blocks 394 * common: Pointer to common configurations shared by sub blocks 395 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 396 * @maxupscale: maxupscale ratio supported 397 * @smart_dma_priority: hw priority of rect1 of multirect pipe 398 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 399 * @qseed_ver: qseed version 400 * @scaler_blk: 401 * @csc_blk: 402 * @format_list: Pointer to list of supported formats 403 * @num_formats: Number of supported formats 404 * @virt_format_list: Pointer to list of supported formats for virtual planes 405 * @virt_num_formats: Number of supported formats for virtual planes 406 * @dpu_rotation_cfg: inline rotation configuration 407 */ 408 struct dpu_sspp_sub_blks { 409 u32 maxdwnscale; 410 u32 maxupscale; 411 u32 smart_dma_priority; 412 u32 max_per_pipe_bw; 413 u32 qseed_ver; 414 struct dpu_scaler_blk scaler_blk; 415 struct dpu_pp_blk csc_blk; 416 417 const u32 *format_list; 418 u32 num_formats; 419 const u32 *virt_format_list; 420 u32 virt_num_formats; 421 const struct dpu_rotation_cfg *rotation_cfg; 422 }; 423 424 /** 425 * struct dpu_lm_sub_blks: information of mixer block 426 * @maxwidth: Max pixel width supported by this mixer 427 * @maxblendstages: Max number of blend-stages supported 428 * @blendstage_base: Blend-stage register base offset 429 */ 430 struct dpu_lm_sub_blks { 431 u32 maxwidth; 432 u32 maxblendstages; 433 u32 blendstage_base[MAX_BLOCKS]; 434 }; 435 436 /** 437 * struct dpu_dspp_sub_blks: Information of DSPP block 438 * @pcc: pixel color correction block 439 */ 440 struct dpu_dspp_sub_blks { 441 struct dpu_pp_blk pcc; 442 }; 443 444 struct dpu_pingpong_sub_blks { 445 struct dpu_pp_blk te; 446 struct dpu_pp_blk te2; 447 struct dpu_pp_blk dither; 448 }; 449 450 /** 451 * struct dpu_dsc_sub_blks - DSC sub-blks 452 * @enc: DSC encoder sub-block 453 * @ctl: DSC controller sub-block 454 */ 455 struct dpu_dsc_sub_blks { 456 struct dpu_dsc_blk enc; 457 struct dpu_dsc_blk ctl; 458 }; 459 460 /** 461 * dpu_clk_ctrl_type - Defines top level clock control signals 462 */ 463 enum dpu_clk_ctrl_type { 464 DPU_CLK_CTRL_NONE, 465 DPU_CLK_CTRL_VIG0, 466 DPU_CLK_CTRL_VIG1, 467 DPU_CLK_CTRL_VIG2, 468 DPU_CLK_CTRL_VIG3, 469 DPU_CLK_CTRL_VIG4, 470 DPU_CLK_CTRL_RGB0, 471 DPU_CLK_CTRL_RGB1, 472 DPU_CLK_CTRL_RGB2, 473 DPU_CLK_CTRL_RGB3, 474 DPU_CLK_CTRL_DMA0, 475 DPU_CLK_CTRL_DMA1, 476 DPU_CLK_CTRL_DMA2, 477 DPU_CLK_CTRL_DMA3, 478 DPU_CLK_CTRL_DMA4, 479 DPU_CLK_CTRL_DMA5, 480 DPU_CLK_CTRL_CURSOR0, 481 DPU_CLK_CTRL_CURSOR1, 482 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 483 DPU_CLK_CTRL_REG_DMA, 484 DPU_CLK_CTRL_WB2, 485 DPU_CLK_CTRL_MAX, 486 }; 487 488 /* struct dpu_clk_ctrl_reg : Clock control register 489 * @reg_off: register offset 490 * @bit_off: bit offset 491 */ 492 struct dpu_clk_ctrl_reg { 493 u32 reg_off; 494 u32 bit_off; 495 }; 496 497 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 498 * @id: index identifying this block 499 * @base: register base offset to mdss 500 * @features bit mask identifying sub-blocks/features 501 * @clk_ctrls clock control register definition 502 */ 503 struct dpu_mdp_cfg { 504 DPU_HW_BLK_INFO; 505 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 506 }; 507 508 /** 509 * struct dpu_ubwc_cfg - UBWC and memory configuration 510 * 511 * @ubwc_version UBWC feature version (0x0 for not supported) 512 * @highest_bank_bit: UBWC parameter 513 * @ubwc_swizzle: ubwc default swizzle setting 514 */ 515 struct dpu_ubwc_cfg { 516 u32 ubwc_version; 517 u32 highest_bank_bit; 518 u32 ubwc_swizzle; 519 }; 520 521 /* struct dpu_ctl_cfg : MDP CTL instance info 522 * @id: index identifying this block 523 * @base: register base offset to mdss 524 * @features bit mask identifying sub-blocks/features 525 * @intr_start: interrupt index for CTL_START 526 */ 527 struct dpu_ctl_cfg { 528 DPU_HW_BLK_INFO; 529 s32 intr_start; 530 }; 531 532 /** 533 * struct dpu_sspp_cfg - information of source pipes 534 * @id: index identifying this block 535 * @base register offset of this block 536 * @features bit mask identifying sub-blocks/features 537 * @sblk: SSPP sub-blocks information 538 * @xin_id: bus client identifier 539 * @clk_ctrl clock control identifier 540 * @type sspp type identifier 541 */ 542 struct dpu_sspp_cfg { 543 DPU_HW_BLK_INFO; 544 const struct dpu_sspp_sub_blks *sblk; 545 u32 xin_id; 546 enum dpu_clk_ctrl_type clk_ctrl; 547 u32 type; 548 }; 549 550 /** 551 * struct dpu_lm_cfg - information of layer mixer blocks 552 * @id: index identifying this block 553 * @base register offset of this block 554 * @features bit mask identifying sub-blocks/features 555 * @sblk: LM Sub-blocks information 556 * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported 557 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 558 */ 559 struct dpu_lm_cfg { 560 DPU_HW_BLK_INFO; 561 const struct dpu_lm_sub_blks *sblk; 562 u32 pingpong; 563 u32 dspp; 564 unsigned long lm_pair_mask; 565 }; 566 567 /** 568 * struct dpu_dspp_cfg - information of DSPP blocks 569 * @id enum identifying this block 570 * @base register offset of this block 571 * @features bit mask identifying sub-blocks/features 572 * supported by this block 573 * @sblk sub-blocks information 574 */ 575 struct dpu_dspp_cfg { 576 DPU_HW_BLK_INFO; 577 const struct dpu_dspp_sub_blks *sblk; 578 }; 579 580 /** 581 * struct dpu_pingpong_cfg - information of PING-PONG blocks 582 * @id enum identifying this block 583 * @base register offset of this block 584 * @features bit mask identifying sub-blocks/features 585 * @intr_done: index for PINGPONG done interrupt 586 * @intr_rdptr: index for PINGPONG readpointer done interrupt 587 * @sblk sub-blocks information 588 */ 589 struct dpu_pingpong_cfg { 590 DPU_HW_BLK_INFO; 591 u32 merge_3d; 592 s32 intr_done; 593 s32 intr_rdptr; 594 const struct dpu_pingpong_sub_blks *sblk; 595 }; 596 597 /** 598 * struct dpu_merge_3d_cfg - information of DSPP blocks 599 * @id enum identifying this block 600 * @base register offset of this block 601 * @features bit mask identifying sub-blocks/features 602 * supported by this block 603 * @sblk sub-blocks information 604 */ 605 struct dpu_merge_3d_cfg { 606 DPU_HW_BLK_INFO; 607 const struct dpu_merge_3d_sub_blks *sblk; 608 }; 609 610 /** 611 * struct dpu_dsc_cfg - information of DSC blocks 612 * @id enum identifying this block 613 * @base register offset of this block 614 * @len: length of hardware block 615 * @features bit mask identifying sub-blocks/features 616 * @sblk: sub-blocks information 617 */ 618 struct dpu_dsc_cfg { 619 DPU_HW_BLK_INFO; 620 const struct dpu_dsc_sub_blks *sblk; 621 }; 622 623 /** 624 * struct dpu_intf_cfg - information of timing engine blocks 625 * @id enum identifying this block 626 * @base register offset of this block 627 * @features bit mask identifying sub-blocks/features 628 * @type: Interface type(DSI, DP, HDMI) 629 * @controller_id: Controller Instance ID in case of multiple of intf type 630 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 631 * @intr_underrun: index for INTF underrun interrupt 632 * @intr_vsync: index for INTF VSYNC interrupt 633 * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt 634 */ 635 struct dpu_intf_cfg { 636 DPU_HW_BLK_INFO; 637 u32 type; /* interface type*/ 638 u32 controller_id; 639 u32 prog_fetch_lines_worst_case; 640 s32 intr_underrun; 641 s32 intr_vsync; 642 s32 intr_tear_rd_ptr; 643 }; 644 645 /** 646 * struct dpu_wb_cfg - information of writeback blocks 647 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 648 * @vbif_idx: vbif client index 649 * @maxlinewidth: max line width supported by writeback block 650 * @xin_id: bus client identifier 651 * @intr_wb_done: interrupt index for WB_DONE 652 * @format_list: list of formats supported by this writeback block 653 * @num_formats: number of formats supported by this writeback block 654 * @clk_ctrl: clock control identifier 655 */ 656 struct dpu_wb_cfg { 657 DPU_HW_BLK_INFO; 658 u8 vbif_idx; 659 u32 maxlinewidth; 660 u32 xin_id; 661 s32 intr_wb_done; 662 const u32 *format_list; 663 u32 num_formats; 664 enum dpu_clk_ctrl_type clk_ctrl; 665 }; 666 667 /** 668 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 669 * @pps pixel per seconds 670 * @ot_limit OT limit to use up to specified pixel per second 671 */ 672 struct dpu_vbif_dynamic_ot_cfg { 673 u64 pps; 674 u32 ot_limit; 675 }; 676 677 /** 678 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 679 * @count length of cfg 680 * @cfg pointer to array of configuration settings with 681 * ascending requirements 682 */ 683 struct dpu_vbif_dynamic_ot_tbl { 684 u32 count; 685 const struct dpu_vbif_dynamic_ot_cfg *cfg; 686 }; 687 688 /** 689 * struct dpu_vbif_qos_tbl - QoS priority table 690 * @npriority_lvl num of priority level 691 * @priority_lvl pointer to array of priority level in ascending order 692 */ 693 struct dpu_vbif_qos_tbl { 694 u32 npriority_lvl; 695 const u32 *priority_lvl; 696 }; 697 698 /** 699 * struct dpu_vbif_cfg - information of VBIF blocks 700 * @id enum identifying this block 701 * @base register offset of this block 702 * @features bit mask identifying sub-blocks/features 703 * @ot_rd_limit default OT read limit 704 * @ot_wr_limit default OT write limit 705 * @xin_halt_timeout maximum time (in usec) for xin to halt 706 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 707 * @dynamic_ot_rd_tbl dynamic OT read configuration table 708 * @dynamic_ot_wr_tbl dynamic OT write configuration table 709 * @qos_rt_tbl real-time QoS priority table 710 * @qos_nrt_tbl non-real-time QoS priority table 711 * @memtype_count number of defined memtypes 712 * @memtype array of xin memtype definitions 713 */ 714 struct dpu_vbif_cfg { 715 DPU_HW_BLK_INFO; 716 u32 default_ot_rd_limit; 717 u32 default_ot_wr_limit; 718 u32 xin_halt_timeout; 719 u32 qos_rp_remap_size; 720 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 721 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 722 struct dpu_vbif_qos_tbl qos_rt_tbl; 723 struct dpu_vbif_qos_tbl qos_nrt_tbl; 724 u32 memtype_count; 725 u32 memtype[MAX_XIN_COUNT]; 726 }; 727 728 /** 729 * Define CDP use cases 730 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 731 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 732 */ 733 enum { 734 DPU_PERF_CDP_USAGE_RT, 735 DPU_PERF_CDP_USAGE_NRT, 736 DPU_PERF_CDP_USAGE_MAX 737 }; 738 739 /** 740 * struct dpu_perf_cdp_cfg - define CDP use case configuration 741 * @rd_enable: true if read pipe CDP is enabled 742 * @wr_enable: true if write pipe CDP is enabled 743 */ 744 struct dpu_perf_cdp_cfg { 745 bool rd_enable; 746 bool wr_enable; 747 }; 748 749 /** 750 * struct dpu_perf_cfg - performance control settings 751 * @max_bw_low low threshold of maximum bandwidth (kbps) 752 * @max_bw_high high threshold of maximum bandwidth (kbps) 753 * @min_core_ib minimum bandwidth for core (kbps) 754 * @min_core_ib minimum mnoc ib vote in kbps 755 * @min_llcc_ib minimum llcc ib vote in kbps 756 * @min_dram_ib minimum dram ib vote in kbps 757 * @undersized_prefill_lines undersized prefill in lines 758 * @xtra_prefill_lines extra prefill latency in lines 759 * @dest_scale_prefill_lines destination scaler latency in lines 760 * @macrotile_perfill_lines macrotile latency in lines 761 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 762 * @linear_prefill_lines linear latency in lines 763 * @downscaling_prefill_lines downscaling latency in lines 764 * @amortizable_theshold minimum y position for traffic shaping prefill 765 * @min_prefill_lines minimum pipeline latency in lines 766 * @clk_inefficiency_factor DPU src clock inefficiency factor 767 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 768 * @safe_lut_tbl: LUT tables for safe signals 769 * @danger_lut_tbl: LUT tables for danger signals 770 * @qos_lut_tbl: LUT tables for QoS signals 771 * @cdp_cfg cdp use case configurations 772 */ 773 struct dpu_perf_cfg { 774 u32 max_bw_low; 775 u32 max_bw_high; 776 u32 min_core_ib; 777 u32 min_llcc_ib; 778 u32 min_dram_ib; 779 u32 undersized_prefill_lines; 780 u32 xtra_prefill_lines; 781 u32 dest_scale_prefill_lines; 782 u32 macrotile_prefill_lines; 783 u32 yuv_nv12_prefill_lines; 784 u32 linear_prefill_lines; 785 u32 downscaling_prefill_lines; 786 u32 amortizable_threshold; 787 u32 min_prefill_lines; 788 u32 clk_inefficiency_factor; 789 u32 bw_inefficiency_factor; 790 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 791 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 792 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 793 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 794 }; 795 796 /** 797 * struct dpu_mdss_cfg - information of MDSS HW 798 * This is the main catalog data structure representing 799 * this HW version. Contains number of instances, 800 * register offsets, capabilities of the all MDSS HW sub-blocks. 801 * 802 * @dma_formats Supported formats for dma pipe 803 * @cursor_formats Supported formats for cursor pipe 804 * @vig_formats Supported formats for vig pipe 805 * @mdss_irqs: Bitmap with the irqs supported by the target 806 */ 807 struct dpu_mdss_cfg { 808 const struct dpu_caps *caps; 809 810 const struct dpu_ubwc_cfg *ubwc; 811 812 u32 mdp_count; 813 const struct dpu_mdp_cfg *mdp; 814 815 u32 ctl_count; 816 const struct dpu_ctl_cfg *ctl; 817 818 u32 sspp_count; 819 const struct dpu_sspp_cfg *sspp; 820 821 u32 mixer_count; 822 const struct dpu_lm_cfg *mixer; 823 824 u32 pingpong_count; 825 const struct dpu_pingpong_cfg *pingpong; 826 827 u32 merge_3d_count; 828 const struct dpu_merge_3d_cfg *merge_3d; 829 830 u32 dsc_count; 831 const struct dpu_dsc_cfg *dsc; 832 833 u32 intf_count; 834 const struct dpu_intf_cfg *intf; 835 836 u32 vbif_count; 837 const struct dpu_vbif_cfg *vbif; 838 839 u32 wb_count; 840 const struct dpu_wb_cfg *wb; 841 842 u32 ad_count; 843 844 u32 dspp_count; 845 const struct dpu_dspp_cfg *dspp; 846 847 /* Add additional block data structures here */ 848 849 const struct dpu_perf_cfg *perf; 850 const struct dpu_format_extended *dma_formats; 851 const struct dpu_format_extended *cursor_formats; 852 const struct dpu_format_extended *vig_formats; 853 854 unsigned long mdss_irqs; 855 }; 856 857 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 858 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 859 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 860 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 861 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 862 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 863 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 864 extern const struct dpu_mdss_cfg dpu_sm6350_cfg; 865 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 866 extern const struct dpu_mdss_cfg dpu_sm6375_cfg; 867 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 868 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 869 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 870 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 871 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 872 873 #endif /* _DPU_HW_CATALOG_H */ 874