1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 8 #include <linux/debugfs.h> 9 10 #include <drm/drm_framebuffer.h> 11 12 #include "dpu_encoder_phys.h" 13 #include "dpu_formats.h" 14 #include "dpu_hw_top.h" 15 #include "dpu_hw_wb.h" 16 #include "dpu_hw_lm.h" 17 #include "dpu_hw_merge3d.h" 18 #include "dpu_hw_interrupts.h" 19 #include "dpu_core_irq.h" 20 #include "dpu_vbif.h" 21 #include "dpu_crtc.h" 22 #include "disp/msm_disp_snapshot.h" 23 24 #define to_dpu_encoder_phys_wb(x) \ 25 container_of(x, struct dpu_encoder_phys_wb, base) 26 27 /** 28 * dpu_encoder_phys_wb_is_master - report wb always as master encoder 29 * @phys_enc: Pointer to physical encoder 30 */ 31 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc) 32 { 33 /* there is only one physical enc for dpu_writeback */ 34 return true; 35 } 36 37 /** 38 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface 39 * @phys_enc: Pointer to physical encoder 40 */ 41 static void dpu_encoder_phys_wb_set_ot_limit( 42 struct dpu_encoder_phys *phys_enc) 43 { 44 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; 45 struct dpu_vbif_set_ot_params ot_params; 46 47 memset(&ot_params, 0, sizeof(ot_params)); 48 ot_params.xin_id = hw_wb->caps->xin_id; 49 ot_params.num = hw_wb->idx - WB_0; 50 ot_params.width = phys_enc->cached_mode.hdisplay; 51 ot_params.height = phys_enc->cached_mode.vdisplay; 52 ot_params.is_wfd = true; 53 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); 54 ot_params.vbif_idx = hw_wb->caps->vbif_idx; 55 ot_params.clk_ctrl = hw_wb->caps->clk_ctrl; 56 ot_params.rd = false; 57 58 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params); 59 } 60 61 /** 62 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback 63 * @phys_enc: Pointer to physical encoder 64 */ 65 static void dpu_encoder_phys_wb_set_qos_remap( 66 struct dpu_encoder_phys *phys_enc) 67 { 68 struct dpu_hw_wb *hw_wb; 69 struct dpu_vbif_set_qos_params qos_params; 70 71 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) { 72 DPU_ERROR("invalid arguments\n"); 73 return; 74 } 75 76 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) { 77 DPU_ERROR("invalid writeback hardware\n"); 78 return; 79 } 80 81 hw_wb = phys_enc->hw_wb; 82 83 memset(&qos_params, 0, sizeof(qos_params)); 84 qos_params.vbif_idx = hw_wb->caps->vbif_idx; 85 qos_params.xin_id = hw_wb->caps->xin_id; 86 qos_params.clk_ctrl = hw_wb->caps->clk_ctrl; 87 qos_params.num = hw_wb->idx - WB_0; 88 qos_params.is_rt = false; 89 90 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n", 91 qos_params.num, 92 qos_params.vbif_idx, 93 qos_params.xin_id, qos_params.is_rt); 94 95 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params); 96 } 97 98 /** 99 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback 100 * @phys_enc: Pointer to physical encoder 101 */ 102 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) 103 { 104 struct dpu_hw_wb *hw_wb; 105 struct dpu_hw_qos_cfg qos_cfg; 106 const struct dpu_mdss_cfg *catalog; 107 const struct dpu_qos_lut_tbl *qos_lut_tb; 108 109 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { 110 DPU_ERROR("invalid parameter(s)\n"); 111 return; 112 } 113 114 catalog = phys_enc->dpu_kms->catalog; 115 116 hw_wb = phys_enc->hw_wb; 117 118 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg)); 119 qos_cfg.danger_safe_en = true; 120 qos_cfg.danger_lut = 121 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; 122 123 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; 124 125 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; 126 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0); 127 128 if (hw_wb->ops.setup_qos_lut) 129 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg); 130 } 131 132 /** 133 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer 134 * @phys_enc: Pointer to physical encoder 135 * @fb: Pointer to output framebuffer 136 */ 137 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, 138 struct drm_framebuffer *fb) 139 { 140 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 141 struct dpu_hw_wb *hw_wb; 142 struct dpu_hw_wb_cfg *wb_cfg; 143 144 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { 145 DPU_ERROR("invalid encoder\n"); 146 return; 147 } 148 149 hw_wb = phys_enc->hw_wb; 150 wb_cfg = &wb_enc->wb_cfg; 151 152 wb_cfg->intf_mode = phys_enc->intf_mode; 153 wb_cfg->roi.x1 = 0; 154 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay; 155 wb_cfg->roi.y1 = 0; 156 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay; 157 158 if (hw_wb->ops.setup_roi) 159 hw_wb->ops.setup_roi(hw_wb, wb_cfg); 160 161 if (hw_wb->ops.setup_outformat) 162 hw_wb->ops.setup_outformat(hw_wb, wb_cfg); 163 164 if (hw_wb->ops.setup_cdp) { 165 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf; 166 167 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format, 168 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable); 169 } 170 171 if (hw_wb->ops.setup_outaddress) 172 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg); 173 } 174 175 /** 176 * dpu_encoder_phys_wb_setup_cdp - setup chroma down prefetch block 177 * @phys_enc:Pointer to physical encoder 178 */ 179 static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) 180 { 181 struct dpu_hw_wb *hw_wb; 182 struct dpu_hw_ctl *ctl; 183 184 if (!phys_enc) { 185 DPU_ERROR("invalid encoder\n"); 186 return; 187 } 188 189 hw_wb = phys_enc->hw_wb; 190 ctl = phys_enc->hw_ctl; 191 192 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && 193 (phys_enc->hw_ctl && 194 phys_enc->hw_ctl->ops.setup_intf_cfg)) { 195 struct dpu_hw_intf_cfg intf_cfg = {0}; 196 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; 197 enum dpu_3d_blend_mode mode_3d; 198 199 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 200 201 intf_cfg.intf = DPU_NONE; 202 intf_cfg.wb = hw_wb->idx; 203 204 if (mode_3d && hw_pp && hw_pp->merge_3d) 205 intf_cfg.merge_3d = hw_pp->merge_3d->idx; 206 207 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode) 208 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 209 mode_3d); 210 211 /* setup which pp blk will connect to this wb */ 212 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk) 213 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, 214 phys_enc->hw_pp->idx); 215 216 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 217 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { 218 struct dpu_hw_intf_cfg intf_cfg = {0}; 219 220 intf_cfg.intf = DPU_NONE; 221 intf_cfg.wb = hw_wb->idx; 222 intf_cfg.mode_3d = 223 dpu_encoder_helper_get_3d_blend_mode(phys_enc); 224 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 225 } 226 } 227 228 /** 229 * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states 230 * @phys_enc: Pointer to physical encoder 231 * @crtc_state: Pointer to CRTC atomic state 232 * @conn_state: Pointer to connector atomic state 233 */ 234 static int dpu_encoder_phys_wb_atomic_check( 235 struct dpu_encoder_phys *phys_enc, 236 struct drm_crtc_state *crtc_state, 237 struct drm_connector_state *conn_state) 238 { 239 struct drm_framebuffer *fb; 240 const struct drm_display_mode *mode = &crtc_state->mode; 241 242 DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n", 243 phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay); 244 245 if (!conn_state || !conn_state->connector) { 246 DPU_ERROR("invalid connector state\n"); 247 return -EINVAL; 248 } else if (conn_state->connector->status != 249 connector_status_connected) { 250 DPU_ERROR("connector not connected %d\n", 251 conn_state->connector->status); 252 return -EINVAL; 253 } 254 255 if (!conn_state->writeback_job || !conn_state->writeback_job->fb) 256 return 0; 257 258 fb = conn_state->writeback_job->fb; 259 260 DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id, 261 fb->width, fb->height); 262 263 if (fb->width != mode->hdisplay) { 264 DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width, 265 mode->hdisplay); 266 return -EINVAL; 267 } else if (fb->height != mode->vdisplay) { 268 DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height, 269 mode->vdisplay); 270 return -EINVAL; 271 } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) { 272 DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n", 273 fb->width, phys_enc->hw_wb->caps->maxlinewidth); 274 return -EINVAL; 275 } 276 277 return 0; 278 } 279 280 281 /** 282 * _dpu_encoder_phys_wb_update_flush - flush hardware update 283 * @phys_enc: Pointer to physical encoder 284 */ 285 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc) 286 { 287 struct dpu_hw_wb *hw_wb; 288 struct dpu_hw_ctl *hw_ctl; 289 struct dpu_hw_pingpong *hw_pp; 290 u32 pending_flush = 0; 291 292 if (!phys_enc) 293 return; 294 295 hw_wb = phys_enc->hw_wb; 296 hw_pp = phys_enc->hw_pp; 297 hw_ctl = phys_enc->hw_ctl; 298 299 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); 300 301 if (!hw_ctl) { 302 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0); 303 return; 304 } 305 306 if (hw_ctl->ops.update_pending_flush_wb) 307 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx); 308 309 if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d) 310 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl, 311 hw_pp->merge_3d->idx); 312 313 if (hw_ctl->ops.get_pending_flush) 314 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl); 315 316 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n", 317 hw_ctl->idx - CTL_0, pending_flush, 318 hw_wb->idx - WB_0); 319 } 320 321 /** 322 * dpu_encoder_phys_wb_setup - setup writeback encoder 323 * @phys_enc: Pointer to physical encoder 324 */ 325 static void dpu_encoder_phys_wb_setup( 326 struct dpu_encoder_phys *phys_enc) 327 { 328 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; 329 struct drm_display_mode mode = phys_enc->cached_mode; 330 struct drm_framebuffer *fb = NULL; 331 332 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n", 333 hw_wb->idx - WB_0, mode.name, 334 mode.hdisplay, mode.vdisplay); 335 336 dpu_encoder_phys_wb_set_ot_limit(phys_enc); 337 338 dpu_encoder_phys_wb_set_qos_remap(phys_enc); 339 340 dpu_encoder_phys_wb_set_qos(phys_enc); 341 342 dpu_encoder_phys_wb_setup_fb(phys_enc, fb); 343 344 dpu_encoder_phys_wb_setup_cdp(phys_enc); 345 346 } 347 348 static void _dpu_encoder_phys_wb_frame_done_helper(void *arg) 349 { 350 struct dpu_encoder_phys *phys_enc = arg; 351 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 352 353 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; 354 unsigned long lock_flags; 355 u32 event = DPU_ENCODER_FRAME_EVENT_DONE; 356 357 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); 358 359 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event); 360 361 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc); 362 363 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 364 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); 365 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 366 367 if (wb_enc->wb_conn) 368 drm_writeback_signal_completion(wb_enc->wb_conn, 0); 369 370 /* Signal any waiting atomic commit thread */ 371 wake_up_all(&phys_enc->pending_kickoff_wq); 372 } 373 374 /** 375 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler 376 * @arg: Pointer to writeback encoder 377 * @irq_idx: interrupt index 378 */ 379 static void dpu_encoder_phys_wb_done_irq(void *arg, int irq_idx) 380 { 381 _dpu_encoder_phys_wb_frame_done_helper(arg); 382 } 383 384 /** 385 * dpu_encoder_phys_wb_irq_ctrl - irq control of WB 386 * @phys: Pointer to physical encoder 387 * @enable: indicates enable or disable interrupts 388 */ 389 static void dpu_encoder_phys_wb_irq_ctrl( 390 struct dpu_encoder_phys *phys, bool enable) 391 { 392 393 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); 394 395 if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1) 396 dpu_core_irq_register_callback(phys->dpu_kms, 397 phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys); 398 else if (!enable && 399 atomic_dec_return(&wb_enc->wbirq_refcount) == 0) 400 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); 401 } 402 403 static void dpu_encoder_phys_wb_atomic_mode_set( 404 struct dpu_encoder_phys *phys_enc, 405 struct drm_crtc_state *crtc_state, 406 struct drm_connector_state *conn_state) 407 { 408 409 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; 410 } 411 412 static void _dpu_encoder_phys_wb_handle_wbdone_timeout( 413 struct dpu_encoder_phys *phys_enc) 414 { 415 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 416 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; 417 418 wb_enc->wb_done_timeout_cnt++; 419 420 if (wb_enc->wb_done_timeout_cnt == 1) 421 msm_disp_snapshot_state(phys_enc->parent->dev); 422 423 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); 424 425 /* request a ctl reset before the next kickoff */ 426 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET; 427 428 if (wb_enc->wb_conn) 429 drm_writeback_signal_completion(wb_enc->wb_conn, 0); 430 431 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event); 432 } 433 434 /** 435 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed 436 * @phys_enc: Pointer to physical encoder 437 */ 438 static int dpu_encoder_phys_wb_wait_for_commit_done( 439 struct dpu_encoder_phys *phys_enc) 440 { 441 unsigned long ret; 442 struct dpu_encoder_wait_info wait_info; 443 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 444 445 wait_info.wq = &phys_enc->pending_kickoff_wq; 446 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; 447 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; 448 449 ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE, 450 dpu_encoder_phys_wb_done_irq, &wait_info); 451 if (ret == -ETIMEDOUT) 452 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc); 453 else if (!ret) 454 wb_enc->wb_done_timeout_cnt = 0; 455 456 return ret; 457 } 458 459 /** 460 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing 461 * @phys_enc: Pointer to physical encoder 462 * Returns: Zero on success 463 */ 464 static void dpu_encoder_phys_wb_prepare_for_kickoff( 465 struct dpu_encoder_phys *phys_enc) 466 { 467 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 468 struct drm_connector *drm_conn; 469 struct drm_connector_state *state; 470 471 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); 472 473 if (!wb_enc->wb_conn || !wb_enc->wb_job) { 474 DPU_ERROR("invalid wb_conn or wb_job\n"); 475 return; 476 } 477 478 drm_conn = &wb_enc->wb_conn->base; 479 state = drm_conn->state; 480 481 if (wb_enc->wb_conn && wb_enc->wb_job) 482 drm_writeback_queue_job(wb_enc->wb_conn, state); 483 484 dpu_encoder_phys_wb_setup(phys_enc); 485 486 _dpu_encoder_phys_wb_update_flush(phys_enc); 487 } 488 489 /** 490 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing 491 * @phys_enc: Pointer to physical encoder 492 */ 493 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc) 494 { 495 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); 496 return false; 497 } 498 499 /** 500 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing 501 * @phys_enc: Pointer to physical encoder 502 */ 503 static void dpu_encoder_phys_wb_handle_post_kickoff( 504 struct dpu_encoder_phys *phys_enc) 505 { 506 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); 507 508 } 509 510 /** 511 * dpu_encoder_phys_wb_enable - enable writeback encoder 512 * @phys_enc: Pointer to physical encoder 513 */ 514 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc) 515 { 516 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); 517 phys_enc->enable_state = DPU_ENC_ENABLED; 518 } 519 /** 520 * dpu_encoder_phys_wb_disable - disable writeback encoder 521 * @phys_enc: Pointer to physical encoder 522 */ 523 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) 524 { 525 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; 526 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; 527 528 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); 529 530 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 531 DPU_ERROR("encoder is already disabled\n"); 532 return; 533 } 534 535 /* reset h/w before final flush */ 536 if (phys_enc->hw_ctl->ops.clear_pending_flush) 537 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl); 538 539 /* 540 * New CTL reset sequence from 5.0 MDP onwards. 541 * If has_3d_merge_reset is not set, legacy reset 542 * sequence is executed. 543 * 544 * Legacy reset sequence has not been implemented yet. 545 * Any target earlier than SM8150 will need it and when 546 * WB support is added to those targets will need to add 547 * the legacy teardown sequence as well. 548 */ 549 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) 550 dpu_encoder_helper_phys_cleanup(phys_enc); 551 552 phys_enc->enable_state = DPU_ENC_DISABLED; 553 } 554 555 /** 556 * dpu_encoder_phys_wb_destroy - destroy writeback encoder 557 * @phys_enc: Pointer to physical encoder 558 */ 559 static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc) 560 { 561 if (!phys_enc) 562 return; 563 564 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); 565 566 kfree(phys_enc); 567 } 568 569 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc, 570 struct drm_writeback_job *job) 571 { 572 const struct msm_format *format; 573 struct msm_gem_address_space *aspace; 574 struct dpu_hw_wb_cfg *wb_cfg; 575 int ret; 576 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 577 578 if (!job->fb) 579 return; 580 581 wb_enc->wb_job = job; 582 wb_enc->wb_conn = job->connector; 583 aspace = phys_enc->dpu_kms->base.aspace; 584 585 wb_cfg = &wb_enc->wb_cfg; 586 587 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg)); 588 589 ret = msm_framebuffer_prepare(job->fb, aspace, false); 590 if (ret) { 591 DPU_ERROR("prep fb failed, %d\n", ret); 592 return; 593 } 594 595 format = msm_framebuffer_format(job->fb); 596 597 wb_cfg->dest.format = dpu_get_dpu_format_ext( 598 format->pixel_format, job->fb->modifier); 599 if (!wb_cfg->dest.format) { 600 /* this error should be detected during atomic_check */ 601 DPU_ERROR("failed to get format %x\n", format->pixel_format); 602 return; 603 } 604 605 ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest); 606 if (ret) { 607 DPU_DEBUG("failed to populate layout %d\n", ret); 608 return; 609 } 610 611 wb_cfg->dest.width = job->fb->width; 612 wb_cfg->dest.height = job->fb->height; 613 wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes; 614 615 if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) && 616 (wb_cfg->dest.format->element[0] == C1_B_Cb)) 617 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]); 618 619 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n", 620 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1], 621 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]); 622 623 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n", 624 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1], 625 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]); 626 } 627 628 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc, 629 struct drm_writeback_job *job) 630 { 631 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 632 struct msm_gem_address_space *aspace; 633 634 if (!job->fb) 635 return; 636 637 aspace = phys_enc->dpu_kms->base.aspace; 638 639 msm_framebuffer_cleanup(job->fb, aspace, false); 640 wb_enc->wb_job = NULL; 641 wb_enc->wb_conn = NULL; 642 } 643 644 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc) 645 { 646 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 647 648 if (wb_enc->wb_job) 649 return true; 650 else 651 return false; 652 } 653 654 /** 655 * dpu_encoder_phys_wb_init_ops - initialize writeback operations 656 * @ops: Pointer to encoder operation table 657 */ 658 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) 659 { 660 ops->is_master = dpu_encoder_phys_wb_is_master; 661 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; 662 ops->enable = dpu_encoder_phys_wb_enable; 663 ops->disable = dpu_encoder_phys_wb_disable; 664 ops->destroy = dpu_encoder_phys_wb_destroy; 665 ops->atomic_check = dpu_encoder_phys_wb_atomic_check; 666 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done; 667 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff; 668 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff; 669 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush; 670 ops->trigger_start = dpu_encoder_helper_trigger_start; 671 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job; 672 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job; 673 ops->irq_control = dpu_encoder_phys_wb_irq_ctrl; 674 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit; 675 676 } 677 678 /** 679 * dpu_encoder_phys_wb_init - initialize writeback encoder 680 * @p: Pointer to init info structure with initialization params 681 */ 682 struct dpu_encoder_phys *dpu_encoder_phys_wb_init( 683 struct dpu_enc_phys_init_params *p) 684 { 685 struct dpu_encoder_phys *phys_enc = NULL; 686 struct dpu_encoder_phys_wb *wb_enc = NULL; 687 688 DPU_DEBUG("\n"); 689 690 if (!p || !p->parent) { 691 DPU_ERROR("invalid params\n"); 692 return ERR_PTR(-EINVAL); 693 } 694 695 wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL); 696 if (!wb_enc) { 697 DPU_ERROR("failed to allocate wb phys_enc enc\n"); 698 return ERR_PTR(-ENOMEM); 699 } 700 701 phys_enc = &wb_enc->base; 702 703 dpu_encoder_phys_init(phys_enc, p); 704 705 dpu_encoder_phys_wb_init_ops(&phys_enc->ops); 706 phys_enc->intf_mode = INTF_MODE_WB_LINE; 707 708 atomic_set(&wb_enc->wbirq_refcount, 0); 709 710 wb_enc->wb_done_timeout_cnt = 0; 711 712 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx); 713 714 return phys_enc; 715 } 716