1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_5_QCM2290_H 8 #define _DPU_6_5_QCM2290_H 9 10 static const struct dpu_caps qcm2290_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 12 .max_mixer_blendstages = 0x4, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .max_linewidth = 2160, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17 }; 18 19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { 20 .highest_bank_bit = 0x2, 21 }; 22 23 static const struct dpu_mdp_cfg qcm2290_mdp[] = { 24 { 25 .name = "top_0", .id = MDP_TOP, 26 .base = 0x0, .len = 0x494, 27 .features = 0, 28 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg qcm2290_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x1dc, 37 .features = BIT(DPU_CTL_ACTIVE_CFG), 38 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 39 }, 40 }; 41 42 static const struct dpu_sspp_cfg qcm2290_sspp[] = { 43 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK, 44 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 45 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 46 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 47 }; 48 49 static const struct dpu_lm_cfg qcm2290_lm[] = { 50 LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, 51 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), 52 }; 53 54 static const struct dpu_dspp_cfg qcm2290_dspp[] = { 55 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 56 &sm8150_dspp_sblk), 57 }; 58 59 static const struct dpu_pingpong_cfg qcm2290_pp[] = { 60 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 61 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 62 -1), 63 }; 64 65 static const struct dpu_intf_cfg qcm2290_intf[] = { 66 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, 67 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 68 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 69 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 70 }; 71 72 static const struct dpu_perf_cfg qcm2290_perf_data = { 73 .max_bw_low = 2700000, 74 .max_bw_high = 2700000, 75 .min_core_ib = 1300000, 76 .min_llcc_ib = 0, 77 .min_dram_ib = 1600000, 78 .min_prefill_lines = 24, 79 .danger_lut_tbl = {0xff, 0x0, 0x0}, 80 .safe_lut_tbl = {0xfff0, 0x0, 0x0}, 81 .qos_lut_tbl = { 82 {.nentry = ARRAY_SIZE(qcm2290_qos_linear), 83 .entries = qcm2290_qos_linear 84 }, 85 }, 86 .cdp_cfg = { 87 {.rd_enable = 1, .wr_enable = 1}, 88 {.rd_enable = 1, .wr_enable = 0} 89 }, 90 .clk_inefficiency_factor = 105, 91 .bw_inefficiency_factor = 120, 92 }; 93 94 const struct dpu_mdss_cfg dpu_qcm2290_cfg = { 95 .caps = &qcm2290_dpu_caps, 96 .ubwc = &qcm2290_ubwc_cfg, 97 .mdp_count = ARRAY_SIZE(qcm2290_mdp), 98 .mdp = qcm2290_mdp, 99 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 100 .ctl = qcm2290_ctl, 101 .sspp_count = ARRAY_SIZE(qcm2290_sspp), 102 .sspp = qcm2290_sspp, 103 .mixer_count = ARRAY_SIZE(qcm2290_lm), 104 .mixer = qcm2290_lm, 105 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 106 .dspp = qcm2290_dspp, 107 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 108 .pingpong = qcm2290_pp, 109 .intf_count = ARRAY_SIZE(qcm2290_intf), 110 .intf = qcm2290_intf, 111 .vbif_count = ARRAY_SIZE(sdm845_vbif), 112 .vbif = sdm845_vbif, 113 .perf = &qcm2290_perf_data, 114 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 115 BIT(MDP_SSPP_TOP0_INTR2) | \ 116 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 117 BIT(MDP_INTF1_INTR) | \ 118 BIT(MDP_INTF1_TEAR_INTR), 119 }; 120 121 #endif 122