1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_2_SC7180_H 8 #define _DPU_6_2_SC7180_H 9 10 static const struct dpu_caps sc7180_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x9, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg sc7180_mdp = { 21 .name = "top_0", 22 .base = 0x0, .len = 0x494, 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 29 }, 30 }; 31 32 static const struct dpu_ctl_cfg sc7180_ctl[] = { 33 { 34 .name = "ctl_0", .id = CTL_0, 35 .base = 0x1000, .len = 0x1dc, 36 .features = BIT(DPU_CTL_ACTIVE_CFG), 37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 38 }, { 39 .name = "ctl_1", .id = CTL_1, 40 .base = 0x1200, .len = 0x1dc, 41 .features = BIT(DPU_CTL_ACTIVE_CFG), 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 43 }, { 44 .name = "ctl_2", .id = CTL_2, 45 .base = 0x1400, .len = 0x1dc, 46 .features = BIT(DPU_CTL_ACTIVE_CFG), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 48 }, 49 }; 50 51 static const struct dpu_sspp_cfg sc7180_sspp[] = { 52 { 53 .name = "sspp_0", .id = SSPP_VIG0, 54 .base = 0x4000, .len = 0x1f8, 55 .features = VIG_SC7180_MASK, 56 .sblk = &sc7180_vig_sblk_0, 57 .xin_id = 0, 58 .type = SSPP_TYPE_VIG, 59 .clk_ctrl = DPU_CLK_CTRL_VIG0, 60 }, { 61 .name = "sspp_8", .id = SSPP_DMA0, 62 .base = 0x24000, .len = 0x1f8, 63 .features = DMA_SDM845_MASK, 64 .sblk = &sdm845_dma_sblk_0, 65 .xin_id = 1, 66 .type = SSPP_TYPE_DMA, 67 .clk_ctrl = DPU_CLK_CTRL_DMA0, 68 }, { 69 .name = "sspp_9", .id = SSPP_DMA1, 70 .base = 0x26000, .len = 0x1f8, 71 .features = DMA_CURSOR_SDM845_MASK, 72 .sblk = &sdm845_dma_sblk_1, 73 .xin_id = 5, 74 .type = SSPP_TYPE_DMA, 75 .clk_ctrl = DPU_CLK_CTRL_DMA1, 76 }, { 77 .name = "sspp_10", .id = SSPP_DMA2, 78 .base = 0x28000, .len = 0x1f8, 79 .features = DMA_CURSOR_SDM845_MASK, 80 .sblk = &sdm845_dma_sblk_2, 81 .xin_id = 9, 82 .type = SSPP_TYPE_DMA, 83 .clk_ctrl = DPU_CLK_CTRL_DMA2, 84 }, 85 }; 86 87 static const struct dpu_lm_cfg sc7180_lm[] = { 88 { 89 .name = "lm_0", .id = LM_0, 90 .base = 0x44000, .len = 0x320, 91 .features = MIXER_SDM845_MASK, 92 .sblk = &sc7180_lm_sblk, 93 .lm_pair = LM_1, 94 .pingpong = PINGPONG_0, 95 .dspp = DSPP_0, 96 }, { 97 .name = "lm_1", .id = LM_1, 98 .base = 0x45000, .len = 0x320, 99 .features = MIXER_SDM845_MASK, 100 .sblk = &sc7180_lm_sblk, 101 .lm_pair = LM_0, 102 .pingpong = PINGPONG_1, 103 }, 104 }; 105 106 static const struct dpu_dspp_cfg sc7180_dspp[] = { 107 { 108 .name = "dspp_0", .id = DSPP_0, 109 .base = 0x54000, .len = 0x1800, 110 .features = DSPP_SC7180_MASK, 111 .sblk = &sdm845_dspp_sblk, 112 }, 113 }; 114 115 static const struct dpu_pingpong_cfg sc7180_pp[] = { 116 { 117 .name = "pingpong_0", .id = PINGPONG_0, 118 .base = 0x70000, .len = 0xd4, 119 .features = PINGPONG_SM8150_MASK, 120 .sblk = &sdm845_pp_sblk, 121 .merge_3d = 0, 122 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 123 .intr_rdptr = -1, 124 }, { 125 .name = "pingpong_1", .id = PINGPONG_1, 126 .base = 0x70800, .len = 0xd4, 127 .features = PINGPONG_SM8150_MASK, 128 .sblk = &sdm845_pp_sblk, 129 .merge_3d = 0, 130 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 131 .intr_rdptr = -1, 132 }, 133 }; 134 135 static const struct dpu_intf_cfg sc7180_intf[] = { 136 { 137 .name = "intf_0", .id = INTF_0, 138 .base = 0x6a000, .len = 0x280, 139 .features = INTF_SC7180_MASK, 140 .type = INTF_DP, 141 .controller_id = MSM_DP_CONTROLLER_0, 142 .prog_fetch_lines_worst_case = 24, 143 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 144 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 145 .intr_tear_rd_ptr = -1, 146 }, { 147 .name = "intf_1", .id = INTF_1, 148 .base = 0x6a800, .len = 0x2c0, 149 .features = INTF_SC7180_MASK, 150 .type = INTF_DSI, 151 .controller_id = MSM_DSI_CONTROLLER_0, 152 .prog_fetch_lines_worst_case = 24, 153 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 154 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 155 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 156 }, 157 }; 158 159 static const struct dpu_wb_cfg sc7180_wb[] = { 160 { 161 .name = "wb_2", .id = WB_2, 162 .base = 0x65000, .len = 0x2c8, 163 .features = WB_SM8250_MASK, 164 .format_list = wb2_formats, 165 .num_formats = ARRAY_SIZE(wb2_formats), 166 .clk_ctrl = DPU_CLK_CTRL_WB2, 167 .xin_id = 6, 168 .vbif_idx = VBIF_RT, 169 .maxlinewidth = 4096, 170 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 171 }, 172 }; 173 174 static const struct dpu_perf_cfg sc7180_perf_data = { 175 .max_bw_low = 6800000, 176 .max_bw_high = 6800000, 177 .min_core_ib = 2400000, 178 .min_llcc_ib = 800000, 179 .min_dram_ib = 1600000, 180 .min_prefill_lines = 24, 181 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 182 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 183 .qos_lut_tbl = { 184 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 185 .entries = sc7180_qos_linear 186 }, 187 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 188 .entries = sc7180_qos_macrotile 189 }, 190 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 191 .entries = sc7180_qos_nrt 192 }, 193 }, 194 .cdp_cfg = { 195 {.rd_enable = 1, .wr_enable = 1}, 196 {.rd_enable = 1, .wr_enable = 0} 197 }, 198 .clk_inefficiency_factor = 105, 199 .bw_inefficiency_factor = 120, 200 }; 201 202 static const struct dpu_mdss_version sc7180_mdss_ver = { 203 .core_major_ver = 6, 204 .core_minor_ver = 2, 205 }; 206 207 const struct dpu_mdss_cfg dpu_sc7180_cfg = { 208 .mdss_ver = &sc7180_mdss_ver, 209 .caps = &sc7180_dpu_caps, 210 .mdp = &sc7180_mdp, 211 .ctl_count = ARRAY_SIZE(sc7180_ctl), 212 .ctl = sc7180_ctl, 213 .sspp_count = ARRAY_SIZE(sc7180_sspp), 214 .sspp = sc7180_sspp, 215 .mixer_count = ARRAY_SIZE(sc7180_lm), 216 .mixer = sc7180_lm, 217 .dspp_count = ARRAY_SIZE(sc7180_dspp), 218 .dspp = sc7180_dspp, 219 .pingpong_count = ARRAY_SIZE(sc7180_pp), 220 .pingpong = sc7180_pp, 221 .intf_count = ARRAY_SIZE(sc7180_intf), 222 .intf = sc7180_intf, 223 .wb_count = ARRAY_SIZE(sc7180_wb), 224 .wb = sc7180_wb, 225 .vbif_count = ARRAY_SIZE(sdm845_vbif), 226 .vbif = sdm845_vbif, 227 .perf = &sc7180_perf_data, 228 }; 229 230 #endif 231