1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 53 enum i915_power_well_id power_well_id); 54 55 static struct i915_power_well * 56 lookup_power_well(struct drm_i915_private *dev_priv, 57 enum i915_power_well_id power_well_id); 58 59 const char * 60 intel_display_power_domain_str(enum intel_display_power_domain domain) 61 { 62 switch (domain) { 63 case POWER_DOMAIN_PIPE_A: 64 return "PIPE_A"; 65 case POWER_DOMAIN_PIPE_B: 66 return "PIPE_B"; 67 case POWER_DOMAIN_PIPE_C: 68 return "PIPE_C"; 69 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 70 return "PIPE_A_PANEL_FITTER"; 71 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 72 return "PIPE_B_PANEL_FITTER"; 73 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 74 return "PIPE_C_PANEL_FITTER"; 75 case POWER_DOMAIN_TRANSCODER_A: 76 return "TRANSCODER_A"; 77 case POWER_DOMAIN_TRANSCODER_B: 78 return "TRANSCODER_B"; 79 case POWER_DOMAIN_TRANSCODER_C: 80 return "TRANSCODER_C"; 81 case POWER_DOMAIN_TRANSCODER_EDP: 82 return "TRANSCODER_EDP"; 83 case POWER_DOMAIN_TRANSCODER_DSI_A: 84 return "TRANSCODER_DSI_A"; 85 case POWER_DOMAIN_TRANSCODER_DSI_C: 86 return "TRANSCODER_DSI_C"; 87 case POWER_DOMAIN_PORT_DDI_A_LANES: 88 return "PORT_DDI_A_LANES"; 89 case POWER_DOMAIN_PORT_DDI_B_LANES: 90 return "PORT_DDI_B_LANES"; 91 case POWER_DOMAIN_PORT_DDI_C_LANES: 92 return "PORT_DDI_C_LANES"; 93 case POWER_DOMAIN_PORT_DDI_D_LANES: 94 return "PORT_DDI_D_LANES"; 95 case POWER_DOMAIN_PORT_DDI_E_LANES: 96 return "PORT_DDI_E_LANES"; 97 case POWER_DOMAIN_PORT_DDI_F_LANES: 98 return "PORT_DDI_F_LANES"; 99 case POWER_DOMAIN_PORT_DDI_A_IO: 100 return "PORT_DDI_A_IO"; 101 case POWER_DOMAIN_PORT_DDI_B_IO: 102 return "PORT_DDI_B_IO"; 103 case POWER_DOMAIN_PORT_DDI_C_IO: 104 return "PORT_DDI_C_IO"; 105 case POWER_DOMAIN_PORT_DDI_D_IO: 106 return "PORT_DDI_D_IO"; 107 case POWER_DOMAIN_PORT_DDI_E_IO: 108 return "PORT_DDI_E_IO"; 109 case POWER_DOMAIN_PORT_DDI_F_IO: 110 return "PORT_DDI_F_IO"; 111 case POWER_DOMAIN_PORT_DSI: 112 return "PORT_DSI"; 113 case POWER_DOMAIN_PORT_CRT: 114 return "PORT_CRT"; 115 case POWER_DOMAIN_PORT_OTHER: 116 return "PORT_OTHER"; 117 case POWER_DOMAIN_VGA: 118 return "VGA"; 119 case POWER_DOMAIN_AUDIO: 120 return "AUDIO"; 121 case POWER_DOMAIN_PLLS: 122 return "PLLS"; 123 case POWER_DOMAIN_AUX_A: 124 return "AUX_A"; 125 case POWER_DOMAIN_AUX_B: 126 return "AUX_B"; 127 case POWER_DOMAIN_AUX_C: 128 return "AUX_C"; 129 case POWER_DOMAIN_AUX_D: 130 return "AUX_D"; 131 case POWER_DOMAIN_AUX_F: 132 return "AUX_F"; 133 case POWER_DOMAIN_AUX_IO_A: 134 return "AUX_IO_A"; 135 case POWER_DOMAIN_GMBUS: 136 return "GMBUS"; 137 case POWER_DOMAIN_INIT: 138 return "INIT"; 139 case POWER_DOMAIN_MODESET: 140 return "MODESET"; 141 case POWER_DOMAIN_GT_IRQ: 142 return "GT_IRQ"; 143 default: 144 MISSING_CASE(domain); 145 return "?"; 146 } 147 } 148 149 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 150 struct i915_power_well *power_well) 151 { 152 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 153 power_well->ops->enable(dev_priv, power_well); 154 power_well->hw_enabled = true; 155 } 156 157 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 158 struct i915_power_well *power_well) 159 { 160 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 161 power_well->hw_enabled = false; 162 power_well->ops->disable(dev_priv, power_well); 163 } 164 165 static void intel_power_well_get(struct drm_i915_private *dev_priv, 166 struct i915_power_well *power_well) 167 { 168 if (!power_well->count++) 169 intel_power_well_enable(dev_priv, power_well); 170 } 171 172 static void intel_power_well_put(struct drm_i915_private *dev_priv, 173 struct i915_power_well *power_well) 174 { 175 WARN(!power_well->count, "Use count on power well %s is already zero", 176 power_well->name); 177 178 if (!--power_well->count) 179 intel_power_well_disable(dev_priv, power_well); 180 } 181 182 /** 183 * __intel_display_power_is_enabled - unlocked check for a power domain 184 * @dev_priv: i915 device instance 185 * @domain: power domain to check 186 * 187 * This is the unlocked version of intel_display_power_is_enabled() and should 188 * only be used from error capture and recovery code where deadlocks are 189 * possible. 190 * 191 * Returns: 192 * True when the power domain is enabled, false otherwise. 193 */ 194 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 195 enum intel_display_power_domain domain) 196 { 197 struct i915_power_well *power_well; 198 bool is_enabled; 199 200 if (dev_priv->runtime_pm.suspended) 201 return false; 202 203 is_enabled = true; 204 205 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { 206 if (power_well->always_on) 207 continue; 208 209 if (!power_well->hw_enabled) { 210 is_enabled = false; 211 break; 212 } 213 } 214 215 return is_enabled; 216 } 217 218 /** 219 * intel_display_power_is_enabled - check for a power domain 220 * @dev_priv: i915 device instance 221 * @domain: power domain to check 222 * 223 * This function can be used to check the hw power domain state. It is mostly 224 * used in hardware state readout functions. Everywhere else code should rely 225 * upon explicit power domain reference counting to ensure that the hardware 226 * block is powered up before accessing it. 227 * 228 * Callers must hold the relevant modesetting locks to ensure that concurrent 229 * threads can't disable the power well while the caller tries to read a few 230 * registers. 231 * 232 * Returns: 233 * True when the power domain is enabled, false otherwise. 234 */ 235 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 236 enum intel_display_power_domain domain) 237 { 238 struct i915_power_domains *power_domains; 239 bool ret; 240 241 power_domains = &dev_priv->power_domains; 242 243 mutex_lock(&power_domains->lock); 244 ret = __intel_display_power_is_enabled(dev_priv, domain); 245 mutex_unlock(&power_domains->lock); 246 247 return ret; 248 } 249 250 /** 251 * intel_display_set_init_power - set the initial power domain state 252 * @dev_priv: i915 device instance 253 * @enable: whether to enable or disable the initial power domain state 254 * 255 * For simplicity our driver load/unload and system suspend/resume code assumes 256 * that all power domains are always enabled. This functions controls the state 257 * of this little hack. While the initial power domain state is enabled runtime 258 * pm is effectively disabled. 259 */ 260 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 261 bool enable) 262 { 263 if (dev_priv->power_domains.init_power_on == enable) 264 return; 265 266 if (enable) 267 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 268 else 269 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 270 271 dev_priv->power_domains.init_power_on = enable; 272 } 273 274 /* 275 * Starting with Haswell, we have a "Power Down Well" that can be turned off 276 * when not needed anymore. We have 4 registers that can request the power well 277 * to be enabled, and it will only be disabled if none of the registers is 278 * requesting it to be enabled. 279 */ 280 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 281 u8 irq_pipe_mask, bool has_vga) 282 { 283 struct pci_dev *pdev = dev_priv->drm.pdev; 284 285 /* 286 * After we re-enable the power well, if we touch VGA register 0x3d5 287 * we'll get unclaimed register interrupts. This stops after we write 288 * anything to the VGA MSR register. The vgacon module uses this 289 * register all the time, so if we unbind our driver and, as a 290 * consequence, bind vgacon, we'll get stuck in an infinite loop at 291 * console_unlock(). So make here we touch the VGA MSR register, making 292 * sure vgacon can keep working normally without triggering interrupts 293 * and error messages. 294 */ 295 if (has_vga) { 296 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 297 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 298 vga_put(pdev, VGA_RSRC_LEGACY_IO); 299 } 300 301 if (irq_pipe_mask) 302 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 303 } 304 305 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 306 u8 irq_pipe_mask) 307 { 308 if (irq_pipe_mask) 309 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 310 } 311 312 313 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 314 struct i915_power_well *power_well) 315 { 316 enum i915_power_well_id id = power_well->id; 317 318 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 319 WARN_ON(intel_wait_for_register(dev_priv, 320 HSW_PWR_WELL_CTL_DRIVER(id), 321 HSW_PWR_WELL_CTL_STATE(id), 322 HSW_PWR_WELL_CTL_STATE(id), 323 1)); 324 } 325 326 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 327 enum i915_power_well_id id) 328 { 329 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); 330 u32 ret; 331 332 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; 333 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; 334 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; 335 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; 336 337 return ret; 338 } 339 340 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 341 struct i915_power_well *power_well) 342 { 343 enum i915_power_well_id id = power_well->id; 344 bool disabled; 345 u32 reqs; 346 347 /* 348 * Bspec doesn't require waiting for PWs to get disabled, but still do 349 * this for paranoia. The known cases where a PW will be forced on: 350 * - a KVMR request on any power well via the KVMR request register 351 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 352 * DEBUG request registers 353 * Skip the wait in case any of the request bits are set and print a 354 * diagnostic message. 355 */ 356 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 357 HSW_PWR_WELL_CTL_STATE(id))) || 358 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); 359 if (disabled) 360 return; 361 362 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 363 power_well->name, 364 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 365 } 366 367 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 368 enum skl_power_gate pg) 369 { 370 /* Timeout 5us for PG#0, for other PGs 1us */ 371 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, 372 SKL_FUSE_PG_DIST_STATUS(pg), 373 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 374 } 375 376 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 377 struct i915_power_well *power_well) 378 { 379 enum i915_power_well_id id = power_well->id; 380 bool wait_fuses = power_well->hsw.has_fuses; 381 enum skl_power_gate uninitialized_var(pg); 382 u32 val; 383 384 if (wait_fuses) { 385 pg = SKL_PW_TO_PG(id); 386 /* 387 * For PW1 we have to wait both for the PW0/PG0 fuse state 388 * before enabling the power well and PW1/PG1's own fuse 389 * state after the enabling. For all other power wells with 390 * fuses we only have to wait for that PW/PG's fuse state 391 * after the enabling. 392 */ 393 if (pg == SKL_PG1) 394 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 395 } 396 397 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 398 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 399 hsw_wait_for_power_well_enable(dev_priv, power_well); 400 401 /* Display WA #1178: cnl */ 402 if (IS_CANNONLAKE(dev_priv) && 403 (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C || 404 id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) { 405 val = I915_READ(CNL_AUX_ANAOVRD1(id)); 406 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; 407 I915_WRITE(CNL_AUX_ANAOVRD1(id), val); 408 } 409 410 if (wait_fuses) 411 gen9_wait_for_power_well_fuses(dev_priv, pg); 412 413 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, 414 power_well->hsw.has_vga); 415 } 416 417 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 418 struct i915_power_well *power_well) 419 { 420 enum i915_power_well_id id = power_well->id; 421 u32 val; 422 423 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); 424 425 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 426 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 427 val & ~HSW_PWR_WELL_CTL_REQ(id)); 428 hsw_wait_for_power_well_disable(dev_priv, power_well); 429 } 430 431 /* 432 * We should only use the power well if we explicitly asked the hardware to 433 * enable it, so check if it's enabled and also check if we've requested it to 434 * be enabled. 435 */ 436 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 437 struct i915_power_well *power_well) 438 { 439 enum i915_power_well_id id = power_well->id; 440 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); 441 442 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; 443 } 444 445 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 446 { 447 enum i915_power_well_id id = SKL_DISP_PW_2; 448 449 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 450 "DC9 already programmed to be enabled.\n"); 451 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 452 "DC5 still not disabled to enable DC9.\n"); 453 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 454 HSW_PWR_WELL_CTL_REQ(id), 455 "Power well 2 on.\n"); 456 WARN_ONCE(intel_irqs_enabled(dev_priv), 457 "Interrupts not disabled yet.\n"); 458 459 /* 460 * TODO: check for the following to verify the conditions to enter DC9 461 * state are satisfied: 462 * 1] Check relevant display engine registers to verify if mode set 463 * disable sequence was followed. 464 * 2] Check if display uninitialize sequence is initialized. 465 */ 466 } 467 468 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 469 { 470 WARN_ONCE(intel_irqs_enabled(dev_priv), 471 "Interrupts not disabled yet.\n"); 472 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 473 "DC5 still not disabled.\n"); 474 475 /* 476 * TODO: check for the following to verify DC9 state was indeed 477 * entered before programming to disable it: 478 * 1] Check relevant display engine registers to verify if mode 479 * set disable sequence was followed. 480 * 2] Check if display uninitialize sequence is initialized. 481 */ 482 } 483 484 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 485 u32 state) 486 { 487 int rewrites = 0; 488 int rereads = 0; 489 u32 v; 490 491 I915_WRITE(DC_STATE_EN, state); 492 493 /* It has been observed that disabling the dc6 state sometimes 494 * doesn't stick and dmc keeps returning old value. Make sure 495 * the write really sticks enough times and also force rewrite until 496 * we are confident that state is exactly what we want. 497 */ 498 do { 499 v = I915_READ(DC_STATE_EN); 500 501 if (v != state) { 502 I915_WRITE(DC_STATE_EN, state); 503 rewrites++; 504 rereads = 0; 505 } else if (rereads++ > 5) { 506 break; 507 } 508 509 } while (rewrites < 100); 510 511 if (v != state) 512 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 513 state, v); 514 515 /* Most of the times we need one retry, avoid spam */ 516 if (rewrites > 1) 517 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 518 state, rewrites); 519 } 520 521 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 522 { 523 u32 mask; 524 525 mask = DC_STATE_EN_UPTO_DC5; 526 if (IS_GEN9_LP(dev_priv)) 527 mask |= DC_STATE_EN_DC9; 528 else 529 mask |= DC_STATE_EN_UPTO_DC6; 530 531 return mask; 532 } 533 534 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 535 { 536 u32 val; 537 538 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 539 540 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 541 dev_priv->csr.dc_state, val); 542 dev_priv->csr.dc_state = val; 543 } 544 545 /** 546 * gen9_set_dc_state - set target display C power state 547 * @dev_priv: i915 device instance 548 * @state: target DC power state 549 * - DC_STATE_DISABLE 550 * - DC_STATE_EN_UPTO_DC5 551 * - DC_STATE_EN_UPTO_DC6 552 * - DC_STATE_EN_DC9 553 * 554 * Signal to DMC firmware/HW the target DC power state passed in @state. 555 * DMC/HW can turn off individual display clocks and power rails when entering 556 * a deeper DC power state (higher in number) and turns these back when exiting 557 * that state to a shallower power state (lower in number). The HW will decide 558 * when to actually enter a given state on an on-demand basis, for instance 559 * depending on the active state of display pipes. The state of display 560 * registers backed by affected power rails are saved/restored as needed. 561 * 562 * Based on the above enabling a deeper DC power state is asynchronous wrt. 563 * enabling it. Disabling a deeper power state is synchronous: for instance 564 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 565 * back on and register state is restored. This is guaranteed by the MMIO write 566 * to DC_STATE_EN blocking until the state is restored. 567 */ 568 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 569 { 570 uint32_t val; 571 uint32_t mask; 572 573 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 574 state &= dev_priv->csr.allowed_dc_mask; 575 576 val = I915_READ(DC_STATE_EN); 577 mask = gen9_dc_mask(dev_priv); 578 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 579 val & mask, state); 580 581 /* Check if DMC is ignoring our DC state requests */ 582 if ((val & mask) != dev_priv->csr.dc_state) 583 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 584 dev_priv->csr.dc_state, val & mask); 585 586 val &= ~mask; 587 val |= state; 588 589 gen9_write_dc_state(dev_priv, val); 590 591 dev_priv->csr.dc_state = val & mask; 592 } 593 594 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 595 { 596 assert_can_enable_dc9(dev_priv); 597 598 DRM_DEBUG_KMS("Enabling DC9\n"); 599 600 intel_power_sequencer_reset(dev_priv); 601 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 602 } 603 604 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 605 { 606 assert_can_disable_dc9(dev_priv); 607 608 DRM_DEBUG_KMS("Disabling DC9\n"); 609 610 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 611 612 intel_pps_unlock_regs_wa(dev_priv); 613 } 614 615 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 616 { 617 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 618 "CSR program storage start is NULL\n"); 619 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 620 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 621 } 622 623 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 624 { 625 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 626 SKL_DISP_PW_2); 627 628 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 629 630 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 631 "DC5 already programmed to be enabled.\n"); 632 assert_rpm_wakelock_held(dev_priv); 633 634 assert_csr_loaded(dev_priv); 635 } 636 637 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 638 { 639 assert_can_enable_dc5(dev_priv); 640 641 DRM_DEBUG_KMS("Enabling DC5\n"); 642 643 /* Wa Display #1183: skl,kbl,cfl */ 644 if (IS_GEN9_BC(dev_priv)) 645 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 646 SKL_SELECT_ALTERNATE_DC_EXIT); 647 648 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 649 } 650 651 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 652 { 653 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 654 "Backlight is not disabled.\n"); 655 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 656 "DC6 already programmed to be enabled.\n"); 657 658 assert_csr_loaded(dev_priv); 659 } 660 661 static void skl_enable_dc6(struct drm_i915_private *dev_priv) 662 { 663 assert_can_enable_dc6(dev_priv); 664 665 DRM_DEBUG_KMS("Enabling DC6\n"); 666 667 /* Wa Display #1183: skl,kbl,cfl */ 668 if (IS_GEN9_BC(dev_priv)) 669 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 670 SKL_SELECT_ALTERNATE_DC_EXIT); 671 672 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 673 } 674 675 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 676 struct i915_power_well *power_well) 677 { 678 enum i915_power_well_id id = power_well->id; 679 u32 mask = HSW_PWR_WELL_CTL_REQ(id); 680 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); 681 682 /* Take over the request bit if set by BIOS. */ 683 if (bios_req & mask) { 684 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 685 686 if (!(drv_req & mask)) 687 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); 688 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); 689 } 690 } 691 692 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 693 struct i915_power_well *power_well) 694 { 695 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); 696 } 697 698 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 699 struct i915_power_well *power_well) 700 { 701 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); 702 } 703 704 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 705 struct i915_power_well *power_well) 706 { 707 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); 708 } 709 710 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 711 { 712 struct i915_power_well *power_well; 713 714 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 715 if (power_well->count > 0) 716 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 717 718 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 719 if (power_well->count > 0) 720 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 721 722 if (IS_GEMINILAKE(dev_priv)) { 723 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); 724 if (power_well->count > 0) 725 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 726 } 727 } 728 729 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 730 struct i915_power_well *power_well) 731 { 732 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 733 } 734 735 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 736 { 737 u32 tmp = I915_READ(DBUF_CTL); 738 739 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 740 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 741 "Unexpected DBuf power power state (0x%08x)\n", tmp); 742 } 743 744 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 745 struct i915_power_well *power_well) 746 { 747 struct intel_cdclk_state cdclk_state = {}; 748 749 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 750 751 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); 752 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 753 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); 754 755 gen9_assert_dbuf_enabled(dev_priv); 756 757 if (IS_GEN9_LP(dev_priv)) 758 bxt_verify_ddi_phy_power_wells(dev_priv); 759 } 760 761 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 762 struct i915_power_well *power_well) 763 { 764 if (!dev_priv->csr.dmc_payload) 765 return; 766 767 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 768 skl_enable_dc6(dev_priv); 769 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 770 gen9_enable_dc5(dev_priv); 771 } 772 773 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 774 struct i915_power_well *power_well) 775 { 776 } 777 778 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 779 struct i915_power_well *power_well) 780 { 781 } 782 783 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 784 struct i915_power_well *power_well) 785 { 786 return true; 787 } 788 789 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 790 struct i915_power_well *power_well) 791 { 792 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 793 i830_enable_pipe(dev_priv, PIPE_A); 794 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 795 i830_enable_pipe(dev_priv, PIPE_B); 796 } 797 798 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 799 struct i915_power_well *power_well) 800 { 801 i830_disable_pipe(dev_priv, PIPE_B); 802 i830_disable_pipe(dev_priv, PIPE_A); 803 } 804 805 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 806 struct i915_power_well *power_well) 807 { 808 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 809 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 810 } 811 812 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 813 struct i915_power_well *power_well) 814 { 815 if (power_well->count > 0) 816 i830_pipes_power_well_enable(dev_priv, power_well); 817 else 818 i830_pipes_power_well_disable(dev_priv, power_well); 819 } 820 821 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 822 struct i915_power_well *power_well, bool enable) 823 { 824 enum i915_power_well_id power_well_id = power_well->id; 825 u32 mask; 826 u32 state; 827 u32 ctrl; 828 829 mask = PUNIT_PWRGT_MASK(power_well_id); 830 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 831 PUNIT_PWRGT_PWR_GATE(power_well_id); 832 833 mutex_lock(&dev_priv->pcu_lock); 834 835 #define COND \ 836 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 837 838 if (COND) 839 goto out; 840 841 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 842 ctrl &= ~mask; 843 ctrl |= state; 844 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 845 846 if (wait_for(COND, 100)) 847 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 848 state, 849 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 850 851 #undef COND 852 853 out: 854 mutex_unlock(&dev_priv->pcu_lock); 855 } 856 857 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 858 struct i915_power_well *power_well) 859 { 860 vlv_set_power_well(dev_priv, power_well, true); 861 } 862 863 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 864 struct i915_power_well *power_well) 865 { 866 vlv_set_power_well(dev_priv, power_well, false); 867 } 868 869 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 870 struct i915_power_well *power_well) 871 { 872 enum i915_power_well_id power_well_id = power_well->id; 873 bool enabled = false; 874 u32 mask; 875 u32 state; 876 u32 ctrl; 877 878 mask = PUNIT_PWRGT_MASK(power_well_id); 879 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 880 881 mutex_lock(&dev_priv->pcu_lock); 882 883 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 884 /* 885 * We only ever set the power-on and power-gate states, anything 886 * else is unexpected. 887 */ 888 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 889 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 890 if (state == ctrl) 891 enabled = true; 892 893 /* 894 * A transient state at this point would mean some unexpected party 895 * is poking at the power controls too. 896 */ 897 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 898 WARN_ON(ctrl != state); 899 900 mutex_unlock(&dev_priv->pcu_lock); 901 902 return enabled; 903 } 904 905 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 906 { 907 u32 val; 908 909 /* 910 * On driver load, a pipe may be active and driving a DSI display. 911 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 912 * (and never recovering) in this case. intel_dsi_post_disable() will 913 * clear it when we turn off the display. 914 */ 915 val = I915_READ(DSPCLK_GATE_D); 916 val &= DPOUNIT_CLOCK_GATE_DISABLE; 917 val |= VRHUNIT_CLOCK_GATE_DISABLE; 918 I915_WRITE(DSPCLK_GATE_D, val); 919 920 /* 921 * Disable trickle feed and enable pnd deadline calculation 922 */ 923 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 924 I915_WRITE(CBR1_VLV, 0); 925 926 WARN_ON(dev_priv->rawclk_freq == 0); 927 928 I915_WRITE(RAWCLK_FREQ_VLV, 929 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 930 } 931 932 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 933 { 934 struct intel_encoder *encoder; 935 enum pipe pipe; 936 937 /* 938 * Enable the CRI clock source so we can get at the 939 * display and the reference clock for VGA 940 * hotplug / manual detection. Supposedly DSI also 941 * needs the ref clock up and running. 942 * 943 * CHV DPLL B/C have some issues if VGA mode is enabled. 944 */ 945 for_each_pipe(dev_priv, pipe) { 946 u32 val = I915_READ(DPLL(pipe)); 947 948 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 949 if (pipe != PIPE_A) 950 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 951 952 I915_WRITE(DPLL(pipe), val); 953 } 954 955 vlv_init_display_clock_gating(dev_priv); 956 957 spin_lock_irq(&dev_priv->irq_lock); 958 valleyview_enable_display_irqs(dev_priv); 959 spin_unlock_irq(&dev_priv->irq_lock); 960 961 /* 962 * During driver initialization/resume we can avoid restoring the 963 * part of the HW/SW state that will be inited anyway explicitly. 964 */ 965 if (dev_priv->power_domains.initializing) 966 return; 967 968 intel_hpd_init(dev_priv); 969 970 /* Re-enable the ADPA, if we have one */ 971 for_each_intel_encoder(&dev_priv->drm, encoder) { 972 if (encoder->type == INTEL_OUTPUT_ANALOG) 973 intel_crt_reset(&encoder->base); 974 } 975 976 i915_redisable_vga_power_on(dev_priv); 977 978 intel_pps_unlock_regs_wa(dev_priv); 979 } 980 981 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 982 { 983 spin_lock_irq(&dev_priv->irq_lock); 984 valleyview_disable_display_irqs(dev_priv); 985 spin_unlock_irq(&dev_priv->irq_lock); 986 987 /* make sure we're done processing display irqs */ 988 synchronize_irq(dev_priv->drm.irq); 989 990 intel_power_sequencer_reset(dev_priv); 991 992 /* Prevent us from re-enabling polling on accident in late suspend */ 993 if (!dev_priv->drm.dev->power.is_suspended) 994 intel_hpd_poll_init(dev_priv); 995 } 996 997 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 998 struct i915_power_well *power_well) 999 { 1000 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 1001 1002 vlv_set_power_well(dev_priv, power_well, true); 1003 1004 vlv_display_power_well_init(dev_priv); 1005 } 1006 1007 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1008 struct i915_power_well *power_well) 1009 { 1010 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 1011 1012 vlv_display_power_well_deinit(dev_priv); 1013 1014 vlv_set_power_well(dev_priv, power_well, false); 1015 } 1016 1017 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1018 struct i915_power_well *power_well) 1019 { 1020 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1021 1022 /* since ref/cri clock was enabled */ 1023 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1024 1025 vlv_set_power_well(dev_priv, power_well, true); 1026 1027 /* 1028 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1029 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1030 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1031 * b. The other bits such as sfr settings / modesel may all 1032 * be set to 0. 1033 * 1034 * This should only be done on init and resume from S3 with 1035 * both PLLs disabled, or we risk losing DPIO and PLL 1036 * synchronization. 1037 */ 1038 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1039 } 1040 1041 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1042 struct i915_power_well *power_well) 1043 { 1044 enum pipe pipe; 1045 1046 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1047 1048 for_each_pipe(dev_priv, pipe) 1049 assert_pll_disabled(dev_priv, pipe); 1050 1051 /* Assert common reset */ 1052 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1053 1054 vlv_set_power_well(dev_priv, power_well, false); 1055 } 1056 1057 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 1058 1059 static struct i915_power_well * 1060 lookup_power_well(struct drm_i915_private *dev_priv, 1061 enum i915_power_well_id power_well_id) 1062 { 1063 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1064 int i; 1065 1066 for (i = 0; i < power_domains->power_well_count; i++) { 1067 struct i915_power_well *power_well; 1068 1069 power_well = &power_domains->power_wells[i]; 1070 if (power_well->id == power_well_id) 1071 return power_well; 1072 } 1073 1074 return NULL; 1075 } 1076 1077 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1078 1079 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1080 { 1081 struct i915_power_well *cmn_bc = 1082 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1083 struct i915_power_well *cmn_d = 1084 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1085 u32 phy_control = dev_priv->chv_phy_control; 1086 u32 phy_status = 0; 1087 u32 phy_status_mask = 0xffffffff; 1088 1089 /* 1090 * The BIOS can leave the PHY is some weird state 1091 * where it doesn't fully power down some parts. 1092 * Disable the asserts until the PHY has been fully 1093 * reset (ie. the power well has been disabled at 1094 * least once). 1095 */ 1096 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1097 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1098 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1099 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1100 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1101 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1102 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1103 1104 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1105 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1106 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1107 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1108 1109 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1110 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1111 1112 /* this assumes override is only used to enable lanes */ 1113 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1114 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1115 1116 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1117 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1118 1119 /* CL1 is on whenever anything is on in either channel */ 1120 if (BITS_SET(phy_control, 1121 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1122 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1123 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1124 1125 /* 1126 * The DPLLB check accounts for the pipe B + port A usage 1127 * with CL2 powered up but all the lanes in the second channel 1128 * powered down. 1129 */ 1130 if (BITS_SET(phy_control, 1131 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1132 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1133 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1134 1135 if (BITS_SET(phy_control, 1136 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1137 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1138 if (BITS_SET(phy_control, 1139 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1140 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1141 1142 if (BITS_SET(phy_control, 1143 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1144 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1145 if (BITS_SET(phy_control, 1146 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1147 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1148 } 1149 1150 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1151 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1152 1153 /* this assumes override is only used to enable lanes */ 1154 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1155 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1156 1157 if (BITS_SET(phy_control, 1158 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1159 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1160 1161 if (BITS_SET(phy_control, 1162 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1163 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1164 if (BITS_SET(phy_control, 1165 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1166 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1167 } 1168 1169 phy_status &= phy_status_mask; 1170 1171 /* 1172 * The PHY may be busy with some initial calibration and whatnot, 1173 * so the power state can take a while to actually change. 1174 */ 1175 if (intel_wait_for_register(dev_priv, 1176 DISPLAY_PHY_STATUS, 1177 phy_status_mask, 1178 phy_status, 1179 10)) 1180 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1181 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1182 phy_status, dev_priv->chv_phy_control); 1183 } 1184 1185 #undef BITS_SET 1186 1187 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1188 struct i915_power_well *power_well) 1189 { 1190 enum dpio_phy phy; 1191 enum pipe pipe; 1192 uint32_t tmp; 1193 1194 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1195 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1196 1197 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1198 pipe = PIPE_A; 1199 phy = DPIO_PHY0; 1200 } else { 1201 pipe = PIPE_C; 1202 phy = DPIO_PHY1; 1203 } 1204 1205 /* since ref/cri clock was enabled */ 1206 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1207 vlv_set_power_well(dev_priv, power_well, true); 1208 1209 /* Poll for phypwrgood signal */ 1210 if (intel_wait_for_register(dev_priv, 1211 DISPLAY_PHY_STATUS, 1212 PHY_POWERGOOD(phy), 1213 PHY_POWERGOOD(phy), 1214 1)) 1215 DRM_ERROR("Display PHY %d is not power up\n", phy); 1216 1217 mutex_lock(&dev_priv->sb_lock); 1218 1219 /* Enable dynamic power down */ 1220 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1221 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1222 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1223 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1224 1225 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1226 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1227 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1228 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1229 } else { 1230 /* 1231 * Force the non-existing CL2 off. BXT does this 1232 * too, so maybe it saves some power even though 1233 * CL2 doesn't exist? 1234 */ 1235 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1236 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1237 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1238 } 1239 1240 mutex_unlock(&dev_priv->sb_lock); 1241 1242 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1243 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1244 1245 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1246 phy, dev_priv->chv_phy_control); 1247 1248 assert_chv_phy_status(dev_priv); 1249 } 1250 1251 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1252 struct i915_power_well *power_well) 1253 { 1254 enum dpio_phy phy; 1255 1256 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1257 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1258 1259 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1260 phy = DPIO_PHY0; 1261 assert_pll_disabled(dev_priv, PIPE_A); 1262 assert_pll_disabled(dev_priv, PIPE_B); 1263 } else { 1264 phy = DPIO_PHY1; 1265 assert_pll_disabled(dev_priv, PIPE_C); 1266 } 1267 1268 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1269 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1270 1271 vlv_set_power_well(dev_priv, power_well, false); 1272 1273 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1274 phy, dev_priv->chv_phy_control); 1275 1276 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1277 dev_priv->chv_phy_assert[phy] = true; 1278 1279 assert_chv_phy_status(dev_priv); 1280 } 1281 1282 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1283 enum dpio_channel ch, bool override, unsigned int mask) 1284 { 1285 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1286 u32 reg, val, expected, actual; 1287 1288 /* 1289 * The BIOS can leave the PHY is some weird state 1290 * where it doesn't fully power down some parts. 1291 * Disable the asserts until the PHY has been fully 1292 * reset (ie. the power well has been disabled at 1293 * least once). 1294 */ 1295 if (!dev_priv->chv_phy_assert[phy]) 1296 return; 1297 1298 if (ch == DPIO_CH0) 1299 reg = _CHV_CMN_DW0_CH0; 1300 else 1301 reg = _CHV_CMN_DW6_CH1; 1302 1303 mutex_lock(&dev_priv->sb_lock); 1304 val = vlv_dpio_read(dev_priv, pipe, reg); 1305 mutex_unlock(&dev_priv->sb_lock); 1306 1307 /* 1308 * This assumes !override is only used when the port is disabled. 1309 * All lanes should power down even without the override when 1310 * the port is disabled. 1311 */ 1312 if (!override || mask == 0xf) { 1313 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1314 /* 1315 * If CH1 common lane is not active anymore 1316 * (eg. for pipe B DPLL) the entire channel will 1317 * shut down, which causes the common lane registers 1318 * to read as 0. That means we can't actually check 1319 * the lane power down status bits, but as the entire 1320 * register reads as 0 it's a good indication that the 1321 * channel is indeed entirely powered down. 1322 */ 1323 if (ch == DPIO_CH1 && val == 0) 1324 expected = 0; 1325 } else if (mask != 0x0) { 1326 expected = DPIO_ANYDL_POWERDOWN; 1327 } else { 1328 expected = 0; 1329 } 1330 1331 if (ch == DPIO_CH0) 1332 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1333 else 1334 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1335 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1336 1337 WARN(actual != expected, 1338 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1339 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1340 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1341 reg, val); 1342 } 1343 1344 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1345 enum dpio_channel ch, bool override) 1346 { 1347 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1348 bool was_override; 1349 1350 mutex_lock(&power_domains->lock); 1351 1352 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1353 1354 if (override == was_override) 1355 goto out; 1356 1357 if (override) 1358 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1359 else 1360 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1361 1362 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1363 1364 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1365 phy, ch, dev_priv->chv_phy_control); 1366 1367 assert_chv_phy_status(dev_priv); 1368 1369 out: 1370 mutex_unlock(&power_domains->lock); 1371 1372 return was_override; 1373 } 1374 1375 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1376 bool override, unsigned int mask) 1377 { 1378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1379 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1380 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1381 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1382 1383 mutex_lock(&power_domains->lock); 1384 1385 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1386 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1387 1388 if (override) 1389 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1390 else 1391 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1392 1393 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1394 1395 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1396 phy, ch, mask, dev_priv->chv_phy_control); 1397 1398 assert_chv_phy_status(dev_priv); 1399 1400 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1401 1402 mutex_unlock(&power_domains->lock); 1403 } 1404 1405 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1406 struct i915_power_well *power_well) 1407 { 1408 enum pipe pipe = PIPE_A; 1409 bool enabled; 1410 u32 state, ctrl; 1411 1412 mutex_lock(&dev_priv->pcu_lock); 1413 1414 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1415 /* 1416 * We only ever set the power-on and power-gate states, anything 1417 * else is unexpected. 1418 */ 1419 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1420 enabled = state == DP_SSS_PWR_ON(pipe); 1421 1422 /* 1423 * A transient state at this point would mean some unexpected party 1424 * is poking at the power controls too. 1425 */ 1426 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1427 WARN_ON(ctrl << 16 != state); 1428 1429 mutex_unlock(&dev_priv->pcu_lock); 1430 1431 return enabled; 1432 } 1433 1434 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1435 struct i915_power_well *power_well, 1436 bool enable) 1437 { 1438 enum pipe pipe = PIPE_A; 1439 u32 state; 1440 u32 ctrl; 1441 1442 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1443 1444 mutex_lock(&dev_priv->pcu_lock); 1445 1446 #define COND \ 1447 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1448 1449 if (COND) 1450 goto out; 1451 1452 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1453 ctrl &= ~DP_SSC_MASK(pipe); 1454 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1455 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1456 1457 if (wait_for(COND, 100)) 1458 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1459 state, 1460 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1461 1462 #undef COND 1463 1464 out: 1465 mutex_unlock(&dev_priv->pcu_lock); 1466 } 1467 1468 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1469 struct i915_power_well *power_well) 1470 { 1471 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1472 1473 chv_set_pipe_power_well(dev_priv, power_well, true); 1474 1475 vlv_display_power_well_init(dev_priv); 1476 } 1477 1478 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1479 struct i915_power_well *power_well) 1480 { 1481 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1482 1483 vlv_display_power_well_deinit(dev_priv); 1484 1485 chv_set_pipe_power_well(dev_priv, power_well, false); 1486 } 1487 1488 static void 1489 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1490 enum intel_display_power_domain domain) 1491 { 1492 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1493 struct i915_power_well *power_well; 1494 1495 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) 1496 intel_power_well_get(dev_priv, power_well); 1497 1498 power_domains->domain_use_count[domain]++; 1499 } 1500 1501 /** 1502 * intel_display_power_get - grab a power domain reference 1503 * @dev_priv: i915 device instance 1504 * @domain: power domain to reference 1505 * 1506 * This function grabs a power domain reference for @domain and ensures that the 1507 * power domain and all its parents are powered up. Therefore users should only 1508 * grab a reference to the innermost power domain they need. 1509 * 1510 * Any power domain reference obtained by this function must have a symmetric 1511 * call to intel_display_power_put() to release the reference again. 1512 */ 1513 void intel_display_power_get(struct drm_i915_private *dev_priv, 1514 enum intel_display_power_domain domain) 1515 { 1516 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1517 1518 intel_runtime_pm_get(dev_priv); 1519 1520 mutex_lock(&power_domains->lock); 1521 1522 __intel_display_power_get_domain(dev_priv, domain); 1523 1524 mutex_unlock(&power_domains->lock); 1525 } 1526 1527 /** 1528 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1529 * @dev_priv: i915 device instance 1530 * @domain: power domain to reference 1531 * 1532 * This function grabs a power domain reference for @domain and ensures that the 1533 * power domain and all its parents are powered up. Therefore users should only 1534 * grab a reference to the innermost power domain they need. 1535 * 1536 * Any power domain reference obtained by this function must have a symmetric 1537 * call to intel_display_power_put() to release the reference again. 1538 */ 1539 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1540 enum intel_display_power_domain domain) 1541 { 1542 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1543 bool is_enabled; 1544 1545 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1546 return false; 1547 1548 mutex_lock(&power_domains->lock); 1549 1550 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1551 __intel_display_power_get_domain(dev_priv, domain); 1552 is_enabled = true; 1553 } else { 1554 is_enabled = false; 1555 } 1556 1557 mutex_unlock(&power_domains->lock); 1558 1559 if (!is_enabled) 1560 intel_runtime_pm_put(dev_priv); 1561 1562 return is_enabled; 1563 } 1564 1565 /** 1566 * intel_display_power_put - release a power domain reference 1567 * @dev_priv: i915 device instance 1568 * @domain: power domain to reference 1569 * 1570 * This function drops the power domain reference obtained by 1571 * intel_display_power_get() and might power down the corresponding hardware 1572 * block right away if this is the last reference. 1573 */ 1574 void intel_display_power_put(struct drm_i915_private *dev_priv, 1575 enum intel_display_power_domain domain) 1576 { 1577 struct i915_power_domains *power_domains; 1578 struct i915_power_well *power_well; 1579 1580 power_domains = &dev_priv->power_domains; 1581 1582 mutex_lock(&power_domains->lock); 1583 1584 WARN(!power_domains->domain_use_count[domain], 1585 "Use count on domain %s is already zero\n", 1586 intel_display_power_domain_str(domain)); 1587 power_domains->domain_use_count[domain]--; 1588 1589 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) 1590 intel_power_well_put(dev_priv, power_well); 1591 1592 mutex_unlock(&power_domains->lock); 1593 1594 intel_runtime_pm_put(dev_priv); 1595 } 1596 1597 #define I830_PIPES_POWER_DOMAINS ( \ 1598 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1599 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1600 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1601 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1602 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1603 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1604 BIT_ULL(POWER_DOMAIN_INIT)) 1605 1606 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1607 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1608 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1609 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1610 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1611 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1612 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1613 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1614 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1615 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1616 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1617 BIT_ULL(POWER_DOMAIN_VGA) | \ 1618 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1619 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1620 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1621 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1622 BIT_ULL(POWER_DOMAIN_INIT)) 1623 1624 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1625 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1626 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1627 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1628 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1629 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1630 BIT_ULL(POWER_DOMAIN_INIT)) 1631 1632 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1633 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1634 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1635 BIT_ULL(POWER_DOMAIN_INIT)) 1636 1637 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1638 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1639 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1640 BIT_ULL(POWER_DOMAIN_INIT)) 1641 1642 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1643 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1644 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1645 BIT_ULL(POWER_DOMAIN_INIT)) 1646 1647 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1648 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1649 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1650 BIT_ULL(POWER_DOMAIN_INIT)) 1651 1652 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1653 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1654 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1655 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1656 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1657 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1658 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1659 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1660 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1661 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1662 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1663 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1664 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1665 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1666 BIT_ULL(POWER_DOMAIN_VGA) | \ 1667 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1668 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1669 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1670 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1671 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1672 BIT_ULL(POWER_DOMAIN_INIT)) 1673 1674 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1675 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1676 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1677 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1678 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1679 BIT_ULL(POWER_DOMAIN_INIT)) 1680 1681 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1682 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1683 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1684 BIT_ULL(POWER_DOMAIN_INIT)) 1685 1686 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1687 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1688 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1689 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1690 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1691 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1692 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1693 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1694 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1695 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1696 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1697 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1698 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1699 BIT_ULL(POWER_DOMAIN_VGA) | \ 1700 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1701 BIT_ULL(POWER_DOMAIN_INIT)) 1702 1703 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1704 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1705 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1706 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1707 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1708 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1709 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1710 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1711 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1712 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1713 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1714 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1715 BIT_ULL(POWER_DOMAIN_VGA) | \ 1716 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1717 BIT_ULL(POWER_DOMAIN_INIT)) 1718 1719 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1720 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1721 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1722 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1723 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1724 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1725 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1726 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1727 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1728 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1729 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1730 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1731 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1732 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1733 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1734 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1735 BIT_ULL(POWER_DOMAIN_VGA) | \ 1736 BIT_ULL(POWER_DOMAIN_INIT)) 1737 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ 1738 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1739 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1740 BIT_ULL(POWER_DOMAIN_INIT)) 1741 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1742 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1743 BIT_ULL(POWER_DOMAIN_INIT)) 1744 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1745 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1746 BIT_ULL(POWER_DOMAIN_INIT)) 1747 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ 1748 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1749 BIT_ULL(POWER_DOMAIN_INIT)) 1750 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1751 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1752 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1753 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1754 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1755 BIT_ULL(POWER_DOMAIN_INIT)) 1756 1757 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1758 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1759 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1760 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1761 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1762 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1763 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1764 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1765 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1766 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1767 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1768 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1769 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1770 BIT_ULL(POWER_DOMAIN_VGA) | \ 1771 BIT_ULL(POWER_DOMAIN_INIT)) 1772 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1773 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1774 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1775 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1776 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1777 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1778 BIT_ULL(POWER_DOMAIN_INIT)) 1779 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 1780 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1781 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1782 BIT_ULL(POWER_DOMAIN_INIT)) 1783 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 1784 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1785 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1786 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1787 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1788 BIT_ULL(POWER_DOMAIN_INIT)) 1789 1790 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1791 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1792 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1793 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1794 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1795 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1796 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1797 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1798 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1799 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1800 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1801 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1802 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1803 BIT_ULL(POWER_DOMAIN_VGA) | \ 1804 BIT_ULL(POWER_DOMAIN_INIT)) 1805 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ 1806 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1807 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1808 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1809 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1810 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1811 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ 1812 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1813 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1814 BIT_ULL(POWER_DOMAIN_INIT)) 1815 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ 1816 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1817 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1818 BIT_ULL(POWER_DOMAIN_INIT)) 1819 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ 1820 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1821 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1822 BIT_ULL(POWER_DOMAIN_INIT)) 1823 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1824 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1825 BIT_ULL(POWER_DOMAIN_INIT)) 1826 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1827 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1828 BIT_ULL(POWER_DOMAIN_INIT)) 1829 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1830 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1831 BIT_ULL(POWER_DOMAIN_INIT)) 1832 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1833 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1834 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1835 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1836 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1837 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1838 BIT_ULL(POWER_DOMAIN_INIT)) 1839 1840 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1841 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1842 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1843 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1844 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1845 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1846 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1847 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1848 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1849 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1850 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1851 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \ 1852 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1853 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1854 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1855 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1856 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1857 BIT_ULL(POWER_DOMAIN_VGA) | \ 1858 BIT_ULL(POWER_DOMAIN_INIT)) 1859 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ 1860 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1861 BIT_ULL(POWER_DOMAIN_INIT)) 1862 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ 1863 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1864 BIT_ULL(POWER_DOMAIN_INIT)) 1865 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ 1866 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1867 BIT_ULL(POWER_DOMAIN_INIT)) 1868 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ 1869 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1870 BIT_ULL(POWER_DOMAIN_INIT)) 1871 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1872 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1873 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \ 1874 BIT_ULL(POWER_DOMAIN_INIT)) 1875 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1876 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1877 BIT_ULL(POWER_DOMAIN_INIT)) 1878 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1879 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1880 BIT_ULL(POWER_DOMAIN_INIT)) 1881 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ 1882 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1883 BIT_ULL(POWER_DOMAIN_INIT)) 1884 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \ 1885 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1886 BIT_ULL(POWER_DOMAIN_INIT)) 1887 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \ 1888 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \ 1889 BIT_ULL(POWER_DOMAIN_INIT)) 1890 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1891 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1892 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1893 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1894 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1895 BIT_ULL(POWER_DOMAIN_INIT)) 1896 1897 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1898 .sync_hw = i9xx_power_well_sync_hw_noop, 1899 .enable = i9xx_always_on_power_well_noop, 1900 .disable = i9xx_always_on_power_well_noop, 1901 .is_enabled = i9xx_always_on_power_well_enabled, 1902 }; 1903 1904 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1905 .sync_hw = i9xx_power_well_sync_hw_noop, 1906 .enable = chv_pipe_power_well_enable, 1907 .disable = chv_pipe_power_well_disable, 1908 .is_enabled = chv_pipe_power_well_enabled, 1909 }; 1910 1911 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1912 .sync_hw = i9xx_power_well_sync_hw_noop, 1913 .enable = chv_dpio_cmn_power_well_enable, 1914 .disable = chv_dpio_cmn_power_well_disable, 1915 .is_enabled = vlv_power_well_enabled, 1916 }; 1917 1918 static struct i915_power_well i9xx_always_on_power_well[] = { 1919 { 1920 .name = "always-on", 1921 .always_on = 1, 1922 .domains = POWER_DOMAIN_MASK, 1923 .ops = &i9xx_always_on_power_well_ops, 1924 .id = I915_DISP_PW_ALWAYS_ON, 1925 }, 1926 }; 1927 1928 static const struct i915_power_well_ops i830_pipes_power_well_ops = { 1929 .sync_hw = i830_pipes_power_well_sync_hw, 1930 .enable = i830_pipes_power_well_enable, 1931 .disable = i830_pipes_power_well_disable, 1932 .is_enabled = i830_pipes_power_well_enabled, 1933 }; 1934 1935 static struct i915_power_well i830_power_wells[] = { 1936 { 1937 .name = "always-on", 1938 .always_on = 1, 1939 .domains = POWER_DOMAIN_MASK, 1940 .ops = &i9xx_always_on_power_well_ops, 1941 .id = I915_DISP_PW_ALWAYS_ON, 1942 }, 1943 { 1944 .name = "pipes", 1945 .domains = I830_PIPES_POWER_DOMAINS, 1946 .ops = &i830_pipes_power_well_ops, 1947 .id = I830_DISP_PW_PIPES, 1948 }, 1949 }; 1950 1951 static const struct i915_power_well_ops hsw_power_well_ops = { 1952 .sync_hw = hsw_power_well_sync_hw, 1953 .enable = hsw_power_well_enable, 1954 .disable = hsw_power_well_disable, 1955 .is_enabled = hsw_power_well_enabled, 1956 }; 1957 1958 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1959 .sync_hw = i9xx_power_well_sync_hw_noop, 1960 .enable = gen9_dc_off_power_well_enable, 1961 .disable = gen9_dc_off_power_well_disable, 1962 .is_enabled = gen9_dc_off_power_well_enabled, 1963 }; 1964 1965 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1966 .sync_hw = i9xx_power_well_sync_hw_noop, 1967 .enable = bxt_dpio_cmn_power_well_enable, 1968 .disable = bxt_dpio_cmn_power_well_disable, 1969 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1970 }; 1971 1972 static struct i915_power_well hsw_power_wells[] = { 1973 { 1974 .name = "always-on", 1975 .always_on = 1, 1976 .domains = POWER_DOMAIN_MASK, 1977 .ops = &i9xx_always_on_power_well_ops, 1978 .id = I915_DISP_PW_ALWAYS_ON, 1979 }, 1980 { 1981 .name = "display", 1982 .domains = HSW_DISPLAY_POWER_DOMAINS, 1983 .ops = &hsw_power_well_ops, 1984 .id = HSW_DISP_PW_GLOBAL, 1985 { 1986 .hsw.has_vga = true, 1987 }, 1988 }, 1989 }; 1990 1991 static struct i915_power_well bdw_power_wells[] = { 1992 { 1993 .name = "always-on", 1994 .always_on = 1, 1995 .domains = POWER_DOMAIN_MASK, 1996 .ops = &i9xx_always_on_power_well_ops, 1997 .id = I915_DISP_PW_ALWAYS_ON, 1998 }, 1999 { 2000 .name = "display", 2001 .domains = BDW_DISPLAY_POWER_DOMAINS, 2002 .ops = &hsw_power_well_ops, 2003 .id = HSW_DISP_PW_GLOBAL, 2004 { 2005 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2006 .hsw.has_vga = true, 2007 }, 2008 }, 2009 }; 2010 2011 static const struct i915_power_well_ops vlv_display_power_well_ops = { 2012 .sync_hw = i9xx_power_well_sync_hw_noop, 2013 .enable = vlv_display_power_well_enable, 2014 .disable = vlv_display_power_well_disable, 2015 .is_enabled = vlv_power_well_enabled, 2016 }; 2017 2018 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2019 .sync_hw = i9xx_power_well_sync_hw_noop, 2020 .enable = vlv_dpio_cmn_power_well_enable, 2021 .disable = vlv_dpio_cmn_power_well_disable, 2022 .is_enabled = vlv_power_well_enabled, 2023 }; 2024 2025 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2026 .sync_hw = i9xx_power_well_sync_hw_noop, 2027 .enable = vlv_power_well_enable, 2028 .disable = vlv_power_well_disable, 2029 .is_enabled = vlv_power_well_enabled, 2030 }; 2031 2032 static struct i915_power_well vlv_power_wells[] = { 2033 { 2034 .name = "always-on", 2035 .always_on = 1, 2036 .domains = POWER_DOMAIN_MASK, 2037 .ops = &i9xx_always_on_power_well_ops, 2038 .id = I915_DISP_PW_ALWAYS_ON, 2039 }, 2040 { 2041 .name = "display", 2042 .domains = VLV_DISPLAY_POWER_DOMAINS, 2043 .id = PUNIT_POWER_WELL_DISP2D, 2044 .ops = &vlv_display_power_well_ops, 2045 }, 2046 { 2047 .name = "dpio-tx-b-01", 2048 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2049 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2050 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2051 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2052 .ops = &vlv_dpio_power_well_ops, 2053 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 2054 }, 2055 { 2056 .name = "dpio-tx-b-23", 2057 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2058 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2059 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2060 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2061 .ops = &vlv_dpio_power_well_ops, 2062 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2063 }, 2064 { 2065 .name = "dpio-tx-c-01", 2066 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2067 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2068 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2069 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2070 .ops = &vlv_dpio_power_well_ops, 2071 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2072 }, 2073 { 2074 .name = "dpio-tx-c-23", 2075 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2076 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2077 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2078 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2079 .ops = &vlv_dpio_power_well_ops, 2080 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2081 }, 2082 { 2083 .name = "dpio-common", 2084 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2085 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2086 .ops = &vlv_dpio_cmn_power_well_ops, 2087 }, 2088 }; 2089 2090 static struct i915_power_well chv_power_wells[] = { 2091 { 2092 .name = "always-on", 2093 .always_on = 1, 2094 .domains = POWER_DOMAIN_MASK, 2095 .ops = &i9xx_always_on_power_well_ops, 2096 .id = I915_DISP_PW_ALWAYS_ON, 2097 }, 2098 { 2099 .name = "display", 2100 /* 2101 * Pipe A power well is the new disp2d well. Pipe B and C 2102 * power wells don't actually exist. Pipe A power well is 2103 * required for any pipe to work. 2104 */ 2105 .domains = CHV_DISPLAY_POWER_DOMAINS, 2106 .id = CHV_DISP_PW_PIPE_A, 2107 .ops = &chv_pipe_power_well_ops, 2108 }, 2109 { 2110 .name = "dpio-common-bc", 2111 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2112 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2113 .ops = &chv_dpio_cmn_power_well_ops, 2114 }, 2115 { 2116 .name = "dpio-common-d", 2117 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2118 .id = PUNIT_POWER_WELL_DPIO_CMN_D, 2119 .ops = &chv_dpio_cmn_power_well_ops, 2120 }, 2121 }; 2122 2123 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2124 enum i915_power_well_id power_well_id) 2125 { 2126 struct i915_power_well *power_well; 2127 bool ret; 2128 2129 power_well = lookup_power_well(dev_priv, power_well_id); 2130 ret = power_well->ops->is_enabled(dev_priv, power_well); 2131 2132 return ret; 2133 } 2134 2135 static struct i915_power_well skl_power_wells[] = { 2136 { 2137 .name = "always-on", 2138 .always_on = 1, 2139 .domains = POWER_DOMAIN_MASK, 2140 .ops = &i9xx_always_on_power_well_ops, 2141 .id = I915_DISP_PW_ALWAYS_ON, 2142 }, 2143 { 2144 .name = "power well 1", 2145 /* Handled by the DMC firmware */ 2146 .domains = 0, 2147 .ops = &hsw_power_well_ops, 2148 .id = SKL_DISP_PW_1, 2149 { 2150 .hsw.has_fuses = true, 2151 }, 2152 }, 2153 { 2154 .name = "MISC IO power well", 2155 /* Handled by the DMC firmware */ 2156 .domains = 0, 2157 .ops = &hsw_power_well_ops, 2158 .id = SKL_DISP_PW_MISC_IO, 2159 }, 2160 { 2161 .name = "DC off", 2162 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2163 .ops = &gen9_dc_off_power_well_ops, 2164 .id = SKL_DISP_PW_DC_OFF, 2165 }, 2166 { 2167 .name = "power well 2", 2168 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2169 .ops = &hsw_power_well_ops, 2170 .id = SKL_DISP_PW_2, 2171 { 2172 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2173 .hsw.has_vga = true, 2174 .hsw.has_fuses = true, 2175 }, 2176 }, 2177 { 2178 .name = "DDI A/E IO power well", 2179 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2180 .ops = &hsw_power_well_ops, 2181 .id = SKL_DISP_PW_DDI_A_E, 2182 }, 2183 { 2184 .name = "DDI B IO power well", 2185 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2186 .ops = &hsw_power_well_ops, 2187 .id = SKL_DISP_PW_DDI_B, 2188 }, 2189 { 2190 .name = "DDI C IO power well", 2191 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2192 .ops = &hsw_power_well_ops, 2193 .id = SKL_DISP_PW_DDI_C, 2194 }, 2195 { 2196 .name = "DDI D IO power well", 2197 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2198 .ops = &hsw_power_well_ops, 2199 .id = SKL_DISP_PW_DDI_D, 2200 }, 2201 }; 2202 2203 static struct i915_power_well bxt_power_wells[] = { 2204 { 2205 .name = "always-on", 2206 .always_on = 1, 2207 .domains = POWER_DOMAIN_MASK, 2208 .ops = &i9xx_always_on_power_well_ops, 2209 .id = I915_DISP_PW_ALWAYS_ON, 2210 }, 2211 { 2212 .name = "power well 1", 2213 .domains = 0, 2214 .ops = &hsw_power_well_ops, 2215 .id = SKL_DISP_PW_1, 2216 { 2217 .hsw.has_fuses = true, 2218 }, 2219 }, 2220 { 2221 .name = "DC off", 2222 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2223 .ops = &gen9_dc_off_power_well_ops, 2224 .id = SKL_DISP_PW_DC_OFF, 2225 }, 2226 { 2227 .name = "power well 2", 2228 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2229 .ops = &hsw_power_well_ops, 2230 .id = SKL_DISP_PW_2, 2231 { 2232 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2233 .hsw.has_vga = true, 2234 .hsw.has_fuses = true, 2235 }, 2236 }, 2237 { 2238 .name = "dpio-common-a", 2239 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2240 .ops = &bxt_dpio_cmn_power_well_ops, 2241 .id = BXT_DPIO_CMN_A, 2242 { 2243 .bxt.phy = DPIO_PHY1, 2244 }, 2245 }, 2246 { 2247 .name = "dpio-common-bc", 2248 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2249 .ops = &bxt_dpio_cmn_power_well_ops, 2250 .id = BXT_DPIO_CMN_BC, 2251 { 2252 .bxt.phy = DPIO_PHY0, 2253 }, 2254 }, 2255 }; 2256 2257 static struct i915_power_well glk_power_wells[] = { 2258 { 2259 .name = "always-on", 2260 .always_on = 1, 2261 .domains = POWER_DOMAIN_MASK, 2262 .ops = &i9xx_always_on_power_well_ops, 2263 .id = I915_DISP_PW_ALWAYS_ON, 2264 }, 2265 { 2266 .name = "power well 1", 2267 /* Handled by the DMC firmware */ 2268 .domains = 0, 2269 .ops = &hsw_power_well_ops, 2270 .id = SKL_DISP_PW_1, 2271 { 2272 .hsw.has_fuses = true, 2273 }, 2274 }, 2275 { 2276 .name = "DC off", 2277 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, 2278 .ops = &gen9_dc_off_power_well_ops, 2279 .id = SKL_DISP_PW_DC_OFF, 2280 }, 2281 { 2282 .name = "power well 2", 2283 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2284 .ops = &hsw_power_well_ops, 2285 .id = SKL_DISP_PW_2, 2286 { 2287 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2288 .hsw.has_vga = true, 2289 .hsw.has_fuses = true, 2290 }, 2291 }, 2292 { 2293 .name = "dpio-common-a", 2294 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, 2295 .ops = &bxt_dpio_cmn_power_well_ops, 2296 .id = BXT_DPIO_CMN_A, 2297 { 2298 .bxt.phy = DPIO_PHY1, 2299 }, 2300 }, 2301 { 2302 .name = "dpio-common-b", 2303 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, 2304 .ops = &bxt_dpio_cmn_power_well_ops, 2305 .id = BXT_DPIO_CMN_BC, 2306 { 2307 .bxt.phy = DPIO_PHY0, 2308 }, 2309 }, 2310 { 2311 .name = "dpio-common-c", 2312 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, 2313 .ops = &bxt_dpio_cmn_power_well_ops, 2314 .id = GLK_DPIO_CMN_C, 2315 { 2316 .bxt.phy = DPIO_PHY2, 2317 }, 2318 }, 2319 { 2320 .name = "AUX A", 2321 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2322 .ops = &hsw_power_well_ops, 2323 .id = GLK_DISP_PW_AUX_A, 2324 }, 2325 { 2326 .name = "AUX B", 2327 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2328 .ops = &hsw_power_well_ops, 2329 .id = GLK_DISP_PW_AUX_B, 2330 }, 2331 { 2332 .name = "AUX C", 2333 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2334 .ops = &hsw_power_well_ops, 2335 .id = GLK_DISP_PW_AUX_C, 2336 }, 2337 { 2338 .name = "DDI A IO power well", 2339 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2340 .ops = &hsw_power_well_ops, 2341 .id = GLK_DISP_PW_DDI_A, 2342 }, 2343 { 2344 .name = "DDI B IO power well", 2345 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2346 .ops = &hsw_power_well_ops, 2347 .id = SKL_DISP_PW_DDI_B, 2348 }, 2349 { 2350 .name = "DDI C IO power well", 2351 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2352 .ops = &hsw_power_well_ops, 2353 .id = SKL_DISP_PW_DDI_C, 2354 }, 2355 }; 2356 2357 static struct i915_power_well cnl_power_wells[] = { 2358 { 2359 .name = "always-on", 2360 .always_on = 1, 2361 .domains = POWER_DOMAIN_MASK, 2362 .ops = &i9xx_always_on_power_well_ops, 2363 .id = I915_DISP_PW_ALWAYS_ON, 2364 }, 2365 { 2366 .name = "power well 1", 2367 /* Handled by the DMC firmware */ 2368 .domains = 0, 2369 .ops = &hsw_power_well_ops, 2370 .id = SKL_DISP_PW_1, 2371 { 2372 .hsw.has_fuses = true, 2373 }, 2374 }, 2375 { 2376 .name = "AUX A", 2377 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2378 .ops = &hsw_power_well_ops, 2379 .id = CNL_DISP_PW_AUX_A, 2380 }, 2381 { 2382 .name = "AUX B", 2383 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2384 .ops = &hsw_power_well_ops, 2385 .id = CNL_DISP_PW_AUX_B, 2386 }, 2387 { 2388 .name = "AUX C", 2389 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2390 .ops = &hsw_power_well_ops, 2391 .id = CNL_DISP_PW_AUX_C, 2392 }, 2393 { 2394 .name = "AUX D", 2395 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2396 .ops = &hsw_power_well_ops, 2397 .id = CNL_DISP_PW_AUX_D, 2398 }, 2399 { 2400 .name = "DC off", 2401 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, 2402 .ops = &gen9_dc_off_power_well_ops, 2403 .id = SKL_DISP_PW_DC_OFF, 2404 }, 2405 { 2406 .name = "power well 2", 2407 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2408 .ops = &hsw_power_well_ops, 2409 .id = SKL_DISP_PW_2, 2410 { 2411 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2412 .hsw.has_vga = true, 2413 .hsw.has_fuses = true, 2414 }, 2415 }, 2416 { 2417 .name = "DDI A IO power well", 2418 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2419 .ops = &hsw_power_well_ops, 2420 .id = CNL_DISP_PW_DDI_A, 2421 }, 2422 { 2423 .name = "DDI B IO power well", 2424 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2425 .ops = &hsw_power_well_ops, 2426 .id = SKL_DISP_PW_DDI_B, 2427 }, 2428 { 2429 .name = "DDI C IO power well", 2430 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2431 .ops = &hsw_power_well_ops, 2432 .id = SKL_DISP_PW_DDI_C, 2433 }, 2434 { 2435 .name = "DDI D IO power well", 2436 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2437 .ops = &hsw_power_well_ops, 2438 .id = SKL_DISP_PW_DDI_D, 2439 }, 2440 { 2441 .name = "DDI F IO power well", 2442 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, 2443 .ops = &hsw_power_well_ops, 2444 .id = CNL_DISP_PW_DDI_F, 2445 }, 2446 { 2447 .name = "AUX F", 2448 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, 2449 .ops = &hsw_power_well_ops, 2450 .id = CNL_DISP_PW_AUX_F, 2451 }, 2452 }; 2453 2454 static int 2455 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2456 int disable_power_well) 2457 { 2458 if (disable_power_well >= 0) 2459 return !!disable_power_well; 2460 2461 return 1; 2462 } 2463 2464 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2465 int enable_dc) 2466 { 2467 uint32_t mask; 2468 int requested_dc; 2469 int max_dc; 2470 2471 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { 2472 max_dc = 2; 2473 mask = 0; 2474 } else if (IS_GEN9_LP(dev_priv)) { 2475 max_dc = 1; 2476 /* 2477 * DC9 has a separate HW flow from the rest of the DC states, 2478 * not depending on the DMC firmware. It's needed by system 2479 * suspend/resume, so allow it unconditionally. 2480 */ 2481 mask = DC_STATE_EN_DC9; 2482 } else { 2483 max_dc = 0; 2484 mask = 0; 2485 } 2486 2487 if (!i915_modparams.disable_power_well) 2488 max_dc = 0; 2489 2490 if (enable_dc >= 0 && enable_dc <= max_dc) { 2491 requested_dc = enable_dc; 2492 } else if (enable_dc == -1) { 2493 requested_dc = max_dc; 2494 } else if (enable_dc > max_dc && enable_dc <= 2) { 2495 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2496 enable_dc, max_dc); 2497 requested_dc = max_dc; 2498 } else { 2499 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2500 requested_dc = max_dc; 2501 } 2502 2503 if (requested_dc > 1) 2504 mask |= DC_STATE_EN_UPTO_DC6; 2505 if (requested_dc > 0) 2506 mask |= DC_STATE_EN_UPTO_DC5; 2507 2508 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2509 2510 return mask; 2511 } 2512 2513 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) 2514 { 2515 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2516 u64 power_well_ids; 2517 int i; 2518 2519 power_well_ids = 0; 2520 for (i = 0; i < power_domains->power_well_count; i++) { 2521 enum i915_power_well_id id = power_domains->power_wells[i].id; 2522 2523 WARN_ON(id >= sizeof(power_well_ids) * 8); 2524 WARN_ON(power_well_ids & BIT_ULL(id)); 2525 power_well_ids |= BIT_ULL(id); 2526 } 2527 } 2528 2529 #define set_power_wells(power_domains, __power_wells) ({ \ 2530 (power_domains)->power_wells = (__power_wells); \ 2531 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2532 }) 2533 2534 /** 2535 * intel_power_domains_init - initializes the power domain structures 2536 * @dev_priv: i915 device instance 2537 * 2538 * Initializes the power domain structures for @dev_priv depending upon the 2539 * supported platform. 2540 */ 2541 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2542 { 2543 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2544 2545 i915_modparams.disable_power_well = 2546 sanitize_disable_power_well_option(dev_priv, 2547 i915_modparams.disable_power_well); 2548 dev_priv->csr.allowed_dc_mask = 2549 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); 2550 2551 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); 2552 2553 mutex_init(&power_domains->lock); 2554 2555 /* 2556 * The enabling order will be from lower to higher indexed wells, 2557 * the disabling order is reversed. 2558 */ 2559 if (IS_HASWELL(dev_priv)) { 2560 set_power_wells(power_domains, hsw_power_wells); 2561 } else if (IS_BROADWELL(dev_priv)) { 2562 set_power_wells(power_domains, bdw_power_wells); 2563 } else if (IS_GEN9_BC(dev_priv)) { 2564 set_power_wells(power_domains, skl_power_wells); 2565 } else if (IS_CANNONLAKE(dev_priv)) { 2566 set_power_wells(power_domains, cnl_power_wells); 2567 2568 /* 2569 * DDI and Aux IO are getting enabled for all ports 2570 * regardless the presence or use. So, in order to avoid 2571 * timeouts, lets remove them from the list 2572 * for the SKUs without port F. 2573 */ 2574 if (!IS_CNL_WITH_PORT_F(dev_priv)) 2575 power_domains->power_well_count -= 2; 2576 2577 } else if (IS_BROXTON(dev_priv)) { 2578 set_power_wells(power_domains, bxt_power_wells); 2579 } else if (IS_GEMINILAKE(dev_priv)) { 2580 set_power_wells(power_domains, glk_power_wells); 2581 } else if (IS_CHERRYVIEW(dev_priv)) { 2582 set_power_wells(power_domains, chv_power_wells); 2583 } else if (IS_VALLEYVIEW(dev_priv)) { 2584 set_power_wells(power_domains, vlv_power_wells); 2585 } else if (IS_I830(dev_priv)) { 2586 set_power_wells(power_domains, i830_power_wells); 2587 } else { 2588 set_power_wells(power_domains, i9xx_always_on_power_well); 2589 } 2590 2591 assert_power_well_ids_unique(dev_priv); 2592 2593 return 0; 2594 } 2595 2596 /** 2597 * intel_power_domains_fini - finalizes the power domain structures 2598 * @dev_priv: i915 device instance 2599 * 2600 * Finalizes the power domain structures for @dev_priv depending upon the 2601 * supported platform. This function also disables runtime pm and ensures that 2602 * the device stays powered up so that the driver can be reloaded. 2603 */ 2604 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2605 { 2606 struct device *kdev = &dev_priv->drm.pdev->dev; 2607 2608 /* 2609 * The i915.ko module is still not prepared to be loaded when 2610 * the power well is not enabled, so just enable it in case 2611 * we're going to unload/reload. 2612 * The following also reacquires the RPM reference the core passed 2613 * to the driver during loading, which is dropped in 2614 * intel_runtime_pm_enable(). We have to hand back the control of the 2615 * device to the core with this reference held. 2616 */ 2617 intel_display_set_init_power(dev_priv, true); 2618 2619 /* Remove the refcount we took to keep power well support disabled. */ 2620 if (!i915_modparams.disable_power_well) 2621 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2622 2623 /* 2624 * Remove the refcount we took in intel_runtime_pm_enable() in case 2625 * the platform doesn't support runtime PM. 2626 */ 2627 if (!HAS_RUNTIME_PM(dev_priv)) 2628 pm_runtime_put(kdev); 2629 } 2630 2631 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2632 { 2633 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2634 struct i915_power_well *power_well; 2635 2636 mutex_lock(&power_domains->lock); 2637 for_each_power_well(dev_priv, power_well) { 2638 power_well->ops->sync_hw(dev_priv, power_well); 2639 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2640 power_well); 2641 } 2642 mutex_unlock(&power_domains->lock); 2643 } 2644 2645 static inline 2646 bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, 2647 i915_reg_t reg, bool enable) 2648 { 2649 u32 val, status; 2650 2651 val = I915_READ(reg); 2652 val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST); 2653 I915_WRITE(reg, val); 2654 POSTING_READ(reg); 2655 udelay(10); 2656 2657 status = I915_READ(reg) & DBUF_POWER_STATE; 2658 if ((enable && !status) || (!enable && status)) { 2659 DRM_ERROR("DBus power %s timeout!\n", 2660 enable ? "enable" : "disable"); 2661 return false; 2662 } 2663 return true; 2664 } 2665 2666 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2667 { 2668 intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); 2669 } 2670 2671 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2672 { 2673 intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); 2674 } 2675 2676 static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) 2677 { 2678 if (INTEL_GEN(dev_priv) < 11) 2679 return 1; 2680 return 2; 2681 } 2682 2683 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 2684 u8 req_slices) 2685 { 2686 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; 2687 u32 val; 2688 bool ret; 2689 2690 if (req_slices > intel_dbuf_max_slices(dev_priv)) { 2691 DRM_ERROR("Invalid number of dbuf slices requested\n"); 2692 return; 2693 } 2694 2695 if (req_slices == hw_enabled_slices || req_slices == 0) 2696 return; 2697 2698 val = I915_READ(DBUF_CTL_S2); 2699 if (req_slices > hw_enabled_slices) 2700 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); 2701 else 2702 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); 2703 2704 if (ret) 2705 dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; 2706 } 2707 2708 static void icl_dbuf_enable(struct drm_i915_private *dev_priv) 2709 { 2710 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); 2711 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); 2712 POSTING_READ(DBUF_CTL_S2); 2713 2714 udelay(10); 2715 2716 if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 2717 !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 2718 DRM_ERROR("DBuf power enable timeout\n"); 2719 else 2720 dev_priv->wm.skl_hw.ddb.enabled_slices = 2; 2721 } 2722 2723 static void icl_dbuf_disable(struct drm_i915_private *dev_priv) 2724 { 2725 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); 2726 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); 2727 POSTING_READ(DBUF_CTL_S2); 2728 2729 udelay(10); 2730 2731 if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 2732 (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 2733 DRM_ERROR("DBuf power disable timeout!\n"); 2734 else 2735 dev_priv->wm.skl_hw.ddb.enabled_slices = 0; 2736 } 2737 2738 static void icl_mbus_init(struct drm_i915_private *dev_priv) 2739 { 2740 uint32_t val; 2741 2742 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 2743 MBUS_ABOX_BT_CREDIT_POOL2(16) | 2744 MBUS_ABOX_B_CREDIT(1) | 2745 MBUS_ABOX_BW_CREDIT(1); 2746 2747 I915_WRITE(MBUS_ABOX_CTL, val); 2748 } 2749 2750 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2751 bool resume) 2752 { 2753 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2754 struct i915_power_well *well; 2755 uint32_t val; 2756 2757 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2758 2759 /* enable PCH reset handshake */ 2760 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2761 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2762 2763 /* enable PG1 and Misc I/O */ 2764 mutex_lock(&power_domains->lock); 2765 2766 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2767 intel_power_well_enable(dev_priv, well); 2768 2769 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2770 intel_power_well_enable(dev_priv, well); 2771 2772 mutex_unlock(&power_domains->lock); 2773 2774 skl_init_cdclk(dev_priv); 2775 2776 gen9_dbuf_enable(dev_priv); 2777 2778 if (resume && dev_priv->csr.dmc_payload) 2779 intel_csr_load_program(dev_priv); 2780 } 2781 2782 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2783 { 2784 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2785 struct i915_power_well *well; 2786 2787 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2788 2789 gen9_dbuf_disable(dev_priv); 2790 2791 skl_uninit_cdclk(dev_priv); 2792 2793 /* The spec doesn't call for removing the reset handshake flag */ 2794 /* disable PG1 and Misc I/O */ 2795 2796 mutex_lock(&power_domains->lock); 2797 2798 /* 2799 * BSpec says to keep the MISC IO power well enabled here, only 2800 * remove our request for power well 1. 2801 * Note that even though the driver's request is removed power well 1 2802 * may stay enabled after this due to DMC's own request on it. 2803 */ 2804 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2805 intel_power_well_disable(dev_priv, well); 2806 2807 mutex_unlock(&power_domains->lock); 2808 2809 usleep_range(10, 30); /* 10 us delay per Bspec */ 2810 } 2811 2812 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2813 bool resume) 2814 { 2815 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2816 struct i915_power_well *well; 2817 uint32_t val; 2818 2819 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2820 2821 /* 2822 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2823 * or else the reset will hang because there is no PCH to respond. 2824 * Move the handshake programming to initialization sequence. 2825 * Previously was left up to BIOS. 2826 */ 2827 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2828 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2829 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2830 2831 /* Enable PG1 */ 2832 mutex_lock(&power_domains->lock); 2833 2834 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2835 intel_power_well_enable(dev_priv, well); 2836 2837 mutex_unlock(&power_domains->lock); 2838 2839 bxt_init_cdclk(dev_priv); 2840 2841 gen9_dbuf_enable(dev_priv); 2842 2843 if (resume && dev_priv->csr.dmc_payload) 2844 intel_csr_load_program(dev_priv); 2845 } 2846 2847 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2848 { 2849 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2850 struct i915_power_well *well; 2851 2852 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2853 2854 gen9_dbuf_disable(dev_priv); 2855 2856 bxt_uninit_cdclk(dev_priv); 2857 2858 /* The spec doesn't call for removing the reset handshake flag */ 2859 2860 /* 2861 * Disable PW1 (PG1). 2862 * Note that even though the driver's request is removed power well 1 2863 * may stay enabled after this due to DMC's own request on it. 2864 */ 2865 mutex_lock(&power_domains->lock); 2866 2867 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2868 intel_power_well_disable(dev_priv, well); 2869 2870 mutex_unlock(&power_domains->lock); 2871 2872 usleep_range(10, 30); /* 10 us delay per Bspec */ 2873 } 2874 2875 enum { 2876 PROCMON_0_85V_DOT_0, 2877 PROCMON_0_95V_DOT_0, 2878 PROCMON_0_95V_DOT_1, 2879 PROCMON_1_05V_DOT_0, 2880 PROCMON_1_05V_DOT_1, 2881 }; 2882 2883 static const struct cnl_procmon { 2884 u32 dw1, dw9, dw10; 2885 } cnl_procmon_values[] = { 2886 [PROCMON_0_85V_DOT_0] = 2887 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 2888 [PROCMON_0_95V_DOT_0] = 2889 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 2890 [PROCMON_0_95V_DOT_1] = 2891 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 2892 [PROCMON_1_05V_DOT_0] = 2893 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 2894 [PROCMON_1_05V_DOT_1] = 2895 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 2896 }; 2897 2898 /* 2899 * CNL has just one set of registers, while ICL has two sets: one for port A and 2900 * the other for port B. The CNL registers are equivalent to the ICL port A 2901 * registers, that's why we call the ICL macros even though the function has CNL 2902 * on its name. 2903 */ 2904 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 2905 enum port port) 2906 { 2907 const struct cnl_procmon *procmon; 2908 u32 val; 2909 2910 val = I915_READ(ICL_PORT_COMP_DW3(port)); 2911 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 2912 default: 2913 MISSING_CASE(val); 2914 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 2915 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 2916 break; 2917 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 2918 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 2919 break; 2920 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 2921 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 2922 break; 2923 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 2924 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 2925 break; 2926 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 2927 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 2928 break; 2929 } 2930 2931 val = I915_READ(ICL_PORT_COMP_DW1(port)); 2932 val &= ~((0xff << 16) | 0xff); 2933 val |= procmon->dw1; 2934 I915_WRITE(ICL_PORT_COMP_DW1(port), val); 2935 2936 I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); 2937 I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); 2938 } 2939 2940 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 2941 { 2942 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2943 struct i915_power_well *well; 2944 u32 val; 2945 2946 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2947 2948 /* 1. Enable PCH Reset Handshake */ 2949 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2950 val |= RESET_PCH_HANDSHAKE_ENABLE; 2951 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2952 2953 /* 2. Enable Comp */ 2954 val = I915_READ(CHICKEN_MISC_2); 2955 val &= ~CNL_COMP_PWR_DOWN; 2956 I915_WRITE(CHICKEN_MISC_2, val); 2957 2958 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 2959 cnl_set_procmon_ref_values(dev_priv, PORT_A); 2960 2961 val = I915_READ(CNL_PORT_COMP_DW0); 2962 val |= COMP_INIT; 2963 I915_WRITE(CNL_PORT_COMP_DW0, val); 2964 2965 /* 3. */ 2966 val = I915_READ(CNL_PORT_CL1CM_DW5); 2967 val |= CL_POWER_DOWN_ENABLE; 2968 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2969 2970 /* 2971 * 4. Enable Power Well 1 (PG1). 2972 * The AUX IO power wells will be enabled on demand. 2973 */ 2974 mutex_lock(&power_domains->lock); 2975 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2976 intel_power_well_enable(dev_priv, well); 2977 mutex_unlock(&power_domains->lock); 2978 2979 /* 5. Enable CD clock */ 2980 cnl_init_cdclk(dev_priv); 2981 2982 /* 6. Enable DBUF */ 2983 gen9_dbuf_enable(dev_priv); 2984 2985 if (resume && dev_priv->csr.dmc_payload) 2986 intel_csr_load_program(dev_priv); 2987 } 2988 2989 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 2990 { 2991 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2992 struct i915_power_well *well; 2993 u32 val; 2994 2995 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2996 2997 /* 1. Disable all display engine functions -> aready done */ 2998 2999 /* 2. Disable DBUF */ 3000 gen9_dbuf_disable(dev_priv); 3001 3002 /* 3. Disable CD clock */ 3003 cnl_uninit_cdclk(dev_priv); 3004 3005 /* 3006 * 4. Disable Power Well 1 (PG1). 3007 * The AUX IO power wells are toggled on demand, so they are already 3008 * disabled at this point. 3009 */ 3010 mutex_lock(&power_domains->lock); 3011 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3012 intel_power_well_disable(dev_priv, well); 3013 mutex_unlock(&power_domains->lock); 3014 3015 usleep_range(10, 30); /* 10 us delay per Bspec */ 3016 3017 /* 5. Disable Comp */ 3018 val = I915_READ(CHICKEN_MISC_2); 3019 val |= CNL_COMP_PWR_DOWN; 3020 I915_WRITE(CHICKEN_MISC_2, val); 3021 } 3022 3023 static void icl_display_core_init(struct drm_i915_private *dev_priv, 3024 bool resume) 3025 { 3026 enum port port; 3027 u32 val; 3028 3029 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3030 3031 /* 1. Enable PCH reset handshake. */ 3032 val = I915_READ(HSW_NDE_RSTWRN_OPT); 3033 val |= RESET_PCH_HANDSHAKE_ENABLE; 3034 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 3035 3036 for (port = PORT_A; port <= PORT_B; port++) { 3037 /* 2. Enable DDI combo PHY comp. */ 3038 val = I915_READ(ICL_PHY_MISC(port)); 3039 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 3040 I915_WRITE(ICL_PHY_MISC(port), val); 3041 3042 cnl_set_procmon_ref_values(dev_priv, port); 3043 3044 val = I915_READ(ICL_PORT_COMP_DW0(port)); 3045 val |= COMP_INIT; 3046 I915_WRITE(ICL_PORT_COMP_DW0(port), val); 3047 3048 /* 3. Set power down enable. */ 3049 val = I915_READ(ICL_PORT_CL_DW5(port)); 3050 val |= CL_POWER_DOWN_ENABLE; 3051 I915_WRITE(ICL_PORT_CL_DW5(port), val); 3052 } 3053 3054 /* 4. Enable power well 1 (PG1) and aux IO power. */ 3055 /* FIXME: ICL power wells code not here yet. */ 3056 3057 /* 5. Enable CDCLK. */ 3058 icl_init_cdclk(dev_priv); 3059 3060 /* 6. Enable DBUF. */ 3061 icl_dbuf_enable(dev_priv); 3062 3063 /* 7. Setup MBUS. */ 3064 icl_mbus_init(dev_priv); 3065 3066 /* 8. CHICKEN_DCPR_1 */ 3067 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 3068 CNL_DDI_CLOCK_REG_ACCESS_ON); 3069 } 3070 3071 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 3072 { 3073 enum port port; 3074 u32 val; 3075 3076 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3077 3078 /* 1. Disable all display engine functions -> aready done */ 3079 3080 /* 2. Disable DBUF */ 3081 icl_dbuf_disable(dev_priv); 3082 3083 /* 3. Disable CD clock */ 3084 icl_uninit_cdclk(dev_priv); 3085 3086 /* 4. Disable Power Well 1 (PG1) and Aux IO Power */ 3087 /* FIXME: ICL power wells code not here yet. */ 3088 3089 /* 5. Disable Comp */ 3090 for (port = PORT_A; port <= PORT_B; port++) { 3091 val = I915_READ(ICL_PHY_MISC(port)); 3092 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 3093 I915_WRITE(ICL_PHY_MISC(port), val); 3094 } 3095 } 3096 3097 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 3098 { 3099 struct i915_power_well *cmn_bc = 3100 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 3101 struct i915_power_well *cmn_d = 3102 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 3103 3104 /* 3105 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 3106 * workaround never ever read DISPLAY_PHY_CONTROL, and 3107 * instead maintain a shadow copy ourselves. Use the actual 3108 * power well state and lane status to reconstruct the 3109 * expected initial value. 3110 */ 3111 dev_priv->chv_phy_control = 3112 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 3113 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 3114 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 3115 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 3116 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 3117 3118 /* 3119 * If all lanes are disabled we leave the override disabled 3120 * with all power down bits cleared to match the state we 3121 * would use after disabling the port. Otherwise enable the 3122 * override and set the lane powerdown bits accding to the 3123 * current lane status. 3124 */ 3125 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 3126 uint32_t status = I915_READ(DPLL(PIPE_A)); 3127 unsigned int mask; 3128 3129 mask = status & DPLL_PORTB_READY_MASK; 3130 if (mask == 0xf) 3131 mask = 0x0; 3132 else 3133 dev_priv->chv_phy_control |= 3134 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 3135 3136 dev_priv->chv_phy_control |= 3137 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 3138 3139 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 3140 if (mask == 0xf) 3141 mask = 0x0; 3142 else 3143 dev_priv->chv_phy_control |= 3144 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 3145 3146 dev_priv->chv_phy_control |= 3147 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 3148 3149 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 3150 3151 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 3152 } else { 3153 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 3154 } 3155 3156 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 3157 uint32_t status = I915_READ(DPIO_PHY_STATUS); 3158 unsigned int mask; 3159 3160 mask = status & DPLL_PORTD_READY_MASK; 3161 3162 if (mask == 0xf) 3163 mask = 0x0; 3164 else 3165 dev_priv->chv_phy_control |= 3166 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 3167 3168 dev_priv->chv_phy_control |= 3169 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 3170 3171 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 3172 3173 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 3174 } else { 3175 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 3176 } 3177 3178 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 3179 3180 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 3181 dev_priv->chv_phy_control); 3182 } 3183 3184 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 3185 { 3186 struct i915_power_well *cmn = 3187 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 3188 struct i915_power_well *disp2d = 3189 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 3190 3191 /* If the display might be already active skip this */ 3192 if (cmn->ops->is_enabled(dev_priv, cmn) && 3193 disp2d->ops->is_enabled(dev_priv, disp2d) && 3194 I915_READ(DPIO_CTL) & DPIO_CMNRST) 3195 return; 3196 3197 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 3198 3199 /* cmnlane needs DPLL registers */ 3200 disp2d->ops->enable(dev_priv, disp2d); 3201 3202 /* 3203 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 3204 * Need to assert and de-assert PHY SB reset by gating the 3205 * common lane power, then un-gating it. 3206 * Simply ungating isn't enough to reset the PHY enough to get 3207 * ports and lanes running. 3208 */ 3209 cmn->ops->disable(dev_priv, cmn); 3210 } 3211 3212 /** 3213 * intel_power_domains_init_hw - initialize hardware power domain state 3214 * @dev_priv: i915 device instance 3215 * @resume: Called from resume code paths or not 3216 * 3217 * This function initializes the hardware power domain state and enables all 3218 * power wells belonging to the INIT power domain. Power wells in other 3219 * domains (and not in the INIT domain) are referenced or disabled during the 3220 * modeset state HW readout. After that the reference count of each power well 3221 * must match its HW enabled state, see intel_power_domains_verify_state(). 3222 */ 3223 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 3224 { 3225 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3226 3227 power_domains->initializing = true; 3228 3229 if (IS_ICELAKE(dev_priv)) { 3230 icl_display_core_init(dev_priv, resume); 3231 } else if (IS_CANNONLAKE(dev_priv)) { 3232 cnl_display_core_init(dev_priv, resume); 3233 } else if (IS_GEN9_BC(dev_priv)) { 3234 skl_display_core_init(dev_priv, resume); 3235 } else if (IS_GEN9_LP(dev_priv)) { 3236 bxt_display_core_init(dev_priv, resume); 3237 } else if (IS_CHERRYVIEW(dev_priv)) { 3238 mutex_lock(&power_domains->lock); 3239 chv_phy_control_init(dev_priv); 3240 mutex_unlock(&power_domains->lock); 3241 } else if (IS_VALLEYVIEW(dev_priv)) { 3242 mutex_lock(&power_domains->lock); 3243 vlv_cmnlane_wa(dev_priv); 3244 mutex_unlock(&power_domains->lock); 3245 } 3246 3247 /* For now, we need the power well to be always enabled. */ 3248 intel_display_set_init_power(dev_priv, true); 3249 /* Disable power support if the user asked so. */ 3250 if (!i915_modparams.disable_power_well) 3251 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3252 intel_power_domains_sync_hw(dev_priv); 3253 power_domains->initializing = false; 3254 } 3255 3256 /** 3257 * intel_power_domains_suspend - suspend power domain state 3258 * @dev_priv: i915 device instance 3259 * 3260 * This function prepares the hardware power domain state before entering 3261 * system suspend. It must be paired with intel_power_domains_init_hw(). 3262 */ 3263 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 3264 { 3265 /* 3266 * Even if power well support was disabled we still want to disable 3267 * power wells while we are system suspended. 3268 */ 3269 if (!i915_modparams.disable_power_well) 3270 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3271 3272 if (IS_ICELAKE(dev_priv)) 3273 icl_display_core_uninit(dev_priv); 3274 else if (IS_CANNONLAKE(dev_priv)) 3275 cnl_display_core_uninit(dev_priv); 3276 else if (IS_GEN9_BC(dev_priv)) 3277 skl_display_core_uninit(dev_priv); 3278 else if (IS_GEN9_LP(dev_priv)) 3279 bxt_display_core_uninit(dev_priv); 3280 } 3281 3282 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) 3283 { 3284 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3285 struct i915_power_well *power_well; 3286 3287 for_each_power_well(dev_priv, power_well) { 3288 enum intel_display_power_domain domain; 3289 3290 DRM_DEBUG_DRIVER("%-25s %d\n", 3291 power_well->name, power_well->count); 3292 3293 for_each_power_domain(domain, power_well->domains) 3294 DRM_DEBUG_DRIVER(" %-23s %d\n", 3295 intel_display_power_domain_str(domain), 3296 power_domains->domain_use_count[domain]); 3297 } 3298 } 3299 3300 /** 3301 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 3302 * @dev_priv: i915 device instance 3303 * 3304 * Verify if the reference count of each power well matches its HW enabled 3305 * state and the total refcount of the domains it belongs to. This must be 3306 * called after modeset HW state sanitization, which is responsible for 3307 * acquiring reference counts for any power wells in use and disabling the 3308 * ones left on by BIOS but not required by any active output. 3309 */ 3310 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3311 { 3312 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3313 struct i915_power_well *power_well; 3314 bool dump_domain_info; 3315 3316 mutex_lock(&power_domains->lock); 3317 3318 dump_domain_info = false; 3319 for_each_power_well(dev_priv, power_well) { 3320 enum intel_display_power_domain domain; 3321 int domains_count; 3322 bool enabled; 3323 3324 /* 3325 * Power wells not belonging to any domain (like the MISC_IO 3326 * and PW1 power wells) are under FW control, so ignore them, 3327 * since their state can change asynchronously. 3328 */ 3329 if (!power_well->domains) 3330 continue; 3331 3332 enabled = power_well->ops->is_enabled(dev_priv, power_well); 3333 if ((power_well->count || power_well->always_on) != enabled) 3334 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", 3335 power_well->name, power_well->count, enabled); 3336 3337 domains_count = 0; 3338 for_each_power_domain(domain, power_well->domains) 3339 domains_count += power_domains->domain_use_count[domain]; 3340 3341 if (power_well->count != domains_count) { 3342 DRM_ERROR("power well %s refcount/domain refcount mismatch " 3343 "(refcount %d/domains refcount %d)\n", 3344 power_well->name, power_well->count, 3345 domains_count); 3346 dump_domain_info = true; 3347 } 3348 } 3349 3350 if (dump_domain_info) { 3351 static bool dumped; 3352 3353 if (!dumped) { 3354 intel_power_domains_dump_info(dev_priv); 3355 dumped = true; 3356 } 3357 } 3358 3359 mutex_unlock(&power_domains->lock); 3360 } 3361 3362 /** 3363 * intel_runtime_pm_get - grab a runtime pm reference 3364 * @dev_priv: i915 device instance 3365 * 3366 * This function grabs a device-level runtime pm reference (mostly used for GEM 3367 * code to ensure the GTT or GT is on) and ensures that it is powered up. 3368 * 3369 * Any runtime pm reference obtained by this function must have a symmetric 3370 * call to intel_runtime_pm_put() to release the reference again. 3371 */ 3372 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 3373 { 3374 struct pci_dev *pdev = dev_priv->drm.pdev; 3375 struct device *kdev = &pdev->dev; 3376 int ret; 3377 3378 ret = pm_runtime_get_sync(kdev); 3379 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3380 3381 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3382 assert_rpm_wakelock_held(dev_priv); 3383 } 3384 3385 /** 3386 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 3387 * @dev_priv: i915 device instance 3388 * 3389 * This function grabs a device-level runtime pm reference if the device is 3390 * already in use and ensures that it is powered up. It is illegal to try 3391 * and access the HW should intel_runtime_pm_get_if_in_use() report failure. 3392 * 3393 * Any runtime pm reference obtained by this function must have a symmetric 3394 * call to intel_runtime_pm_put() to release the reference again. 3395 * 3396 * Returns: True if the wakeref was acquired, or False otherwise. 3397 */ 3398 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 3399 { 3400 if (IS_ENABLED(CONFIG_PM)) { 3401 struct pci_dev *pdev = dev_priv->drm.pdev; 3402 struct device *kdev = &pdev->dev; 3403 3404 /* 3405 * In cases runtime PM is disabled by the RPM core and we get 3406 * an -EINVAL return value we are not supposed to call this 3407 * function, since the power state is undefined. This applies 3408 * atm to the late/early system suspend/resume handlers. 3409 */ 3410 if (pm_runtime_get_if_in_use(kdev) <= 0) 3411 return false; 3412 } 3413 3414 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3415 assert_rpm_wakelock_held(dev_priv); 3416 3417 return true; 3418 } 3419 3420 /** 3421 * intel_runtime_pm_get_noresume - grab a runtime pm reference 3422 * @dev_priv: i915 device instance 3423 * 3424 * This function grabs a device-level runtime pm reference (mostly used for GEM 3425 * code to ensure the GTT or GT is on). 3426 * 3427 * It will _not_ power up the device but instead only check that it's powered 3428 * on. Therefore it is only valid to call this functions from contexts where 3429 * the device is known to be powered up and where trying to power it up would 3430 * result in hilarity and deadlocks. That pretty much means only the system 3431 * suspend/resume code where this is used to grab runtime pm references for 3432 * delayed setup down in work items. 3433 * 3434 * Any runtime pm reference obtained by this function must have a symmetric 3435 * call to intel_runtime_pm_put() to release the reference again. 3436 */ 3437 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 3438 { 3439 struct pci_dev *pdev = dev_priv->drm.pdev; 3440 struct device *kdev = &pdev->dev; 3441 3442 assert_rpm_wakelock_held(dev_priv); 3443 pm_runtime_get_noresume(kdev); 3444 3445 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3446 } 3447 3448 /** 3449 * intel_runtime_pm_put - release a runtime pm reference 3450 * @dev_priv: i915 device instance 3451 * 3452 * This function drops the device-level runtime pm reference obtained by 3453 * intel_runtime_pm_get() and might power down the corresponding 3454 * hardware block right away if this is the last reference. 3455 */ 3456 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 3457 { 3458 struct pci_dev *pdev = dev_priv->drm.pdev; 3459 struct device *kdev = &pdev->dev; 3460 3461 assert_rpm_wakelock_held(dev_priv); 3462 atomic_dec(&dev_priv->runtime_pm.wakeref_count); 3463 3464 pm_runtime_mark_last_busy(kdev); 3465 pm_runtime_put_autosuspend(kdev); 3466 } 3467 3468 /** 3469 * intel_runtime_pm_enable - enable runtime pm 3470 * @dev_priv: i915 device instance 3471 * 3472 * This function enables runtime pm at the end of the driver load sequence. 3473 * 3474 * Note that this function does currently not enable runtime pm for the 3475 * subordinate display power domains. That is only done on the first modeset 3476 * using intel_display_set_init_power(). 3477 */ 3478 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 3479 { 3480 struct pci_dev *pdev = dev_priv->drm.pdev; 3481 struct device *kdev = &pdev->dev; 3482 3483 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */ 3484 pm_runtime_mark_last_busy(kdev); 3485 3486 /* 3487 * Take a permanent reference to disable the RPM functionality and drop 3488 * it only when unloading the driver. Use the low level get/put helpers, 3489 * so the driver's own RPM reference tracking asserts also work on 3490 * platforms without RPM support. 3491 */ 3492 if (!HAS_RUNTIME_PM(dev_priv)) { 3493 int ret; 3494 3495 pm_runtime_dont_use_autosuspend(kdev); 3496 ret = pm_runtime_get_sync(kdev); 3497 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3498 } else { 3499 pm_runtime_use_autosuspend(kdev); 3500 } 3501 3502 /* 3503 * The core calls the driver load handler with an RPM reference held. 3504 * We drop that here and will reacquire it during unloading in 3505 * intel_power_domains_fini(). 3506 */ 3507 pm_runtime_put_autosuspend(kdev); 3508 } 3509