1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "mmio_context.h" 48 #include "cmd_parser.h" 49 #include "fb_decoder.h" 50 #include "dmabuf.h" 51 #include "page_track.h" 52 53 #define GVT_MAX_VGPU 8 54 55 struct intel_gvt_host { 56 struct device *dev; 57 bool initialized; 58 int hypervisor_type; 59 struct intel_gvt_mpt *mpt; 60 }; 61 62 extern struct intel_gvt_host intel_gvt_host; 63 64 /* Describe per-platform limitations. */ 65 struct intel_gvt_device_info { 66 u32 max_support_vgpus; 67 u32 cfg_space_size; 68 u32 mmio_size; 69 u32 mmio_bar; 70 unsigned long msi_cap_offset; 71 u32 gtt_start_offset; 72 u32 gtt_entry_size; 73 u32 gtt_entry_size_shift; 74 int gmadr_bytes_in_cmd; 75 u32 max_surface_size; 76 }; 77 78 /* GM resources owned by a vGPU */ 79 struct intel_vgpu_gm { 80 u64 aperture_sz; 81 u64 hidden_sz; 82 struct drm_mm_node low_gm_node; 83 struct drm_mm_node high_gm_node; 84 }; 85 86 #define INTEL_GVT_MAX_NUM_FENCES 32 87 88 /* Fences owned by a vGPU */ 89 struct intel_vgpu_fence { 90 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 91 u32 base; 92 u32 size; 93 }; 94 95 struct intel_vgpu_mmio { 96 void *vreg; 97 }; 98 99 #define INTEL_GVT_MAX_BAR_NUM 4 100 101 struct intel_vgpu_pci_bar { 102 u64 size; 103 bool tracked; 104 }; 105 106 struct intel_vgpu_cfg_space { 107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 109 }; 110 111 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 112 113 struct intel_vgpu_irq { 114 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 115 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 116 INTEL_GVT_EVENT_MAX); 117 }; 118 119 struct intel_vgpu_opregion { 120 bool mapped; 121 void *va; 122 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 123 }; 124 125 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 126 127 struct intel_vgpu_display { 128 struct intel_vgpu_i2c_edid i2c_edid; 129 struct intel_vgpu_port ports[I915_MAX_PORTS]; 130 struct intel_vgpu_sbi sbi; 131 }; 132 133 struct vgpu_sched_ctl { 134 int weight; 135 }; 136 137 enum { 138 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 139 INTEL_VGPU_GUC_SUBMISSION, 140 }; 141 142 struct intel_vgpu_submission_ops { 143 const char *name; 144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 147 }; 148 149 struct intel_vgpu_submission { 150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 151 struct list_head workload_q_head[I915_NUM_ENGINES]; 152 struct intel_context *shadow[I915_NUM_ENGINES]; 153 struct kmem_cache *workloads; 154 atomic_t running_workload_num; 155 union { 156 u64 i915_context_pml4; 157 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 158 }; 159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 161 void *ring_scan_buffer[I915_NUM_ENGINES]; 162 int ring_scan_buffer_size[I915_NUM_ENGINES]; 163 const struct intel_vgpu_submission_ops *ops; 164 int virtual_submission_interface; 165 bool active; 166 struct { 167 u32 lrca; 168 bool valid; 169 u64 ring_context_gpa; 170 } last_ctx[I915_NUM_ENGINES]; 171 }; 172 173 struct intel_vgpu { 174 struct intel_gvt *gvt; 175 struct mutex vgpu_lock; 176 int id; 177 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 178 bool active; 179 bool pv_notified; 180 bool failsafe; 181 unsigned int resetting_eng; 182 183 /* Both sched_data and sched_ctl can be seen a part of the global gvt 184 * scheduler structure. So below 2 vgpu data are protected 185 * by sched_lock, not vgpu_lock. 186 */ 187 void *sched_data; 188 struct vgpu_sched_ctl sched_ctl; 189 190 struct intel_vgpu_fence fence; 191 struct intel_vgpu_gm gm; 192 struct intel_vgpu_cfg_space cfg_space; 193 struct intel_vgpu_mmio mmio; 194 struct intel_vgpu_irq irq; 195 struct intel_vgpu_gtt gtt; 196 struct intel_vgpu_opregion opregion; 197 struct intel_vgpu_display display; 198 struct intel_vgpu_submission submission; 199 struct radix_tree_root page_track_tree; 200 u32 hws_pga[I915_NUM_ENGINES]; 201 202 struct dentry *debugfs; 203 204 /* Hypervisor-specific device state. */ 205 void *vdev; 206 207 struct list_head dmabuf_obj_list_head; 208 struct mutex dmabuf_lock; 209 struct idr object_idr; 210 211 u32 scan_nonprivbb; 212 }; 213 214 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu) 215 { 216 return vgpu->vdev; 217 } 218 219 /* validating GM healthy status*/ 220 #define vgpu_is_vm_unhealthy(ret_val) \ 221 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 222 223 struct intel_gvt_gm { 224 unsigned long vgpu_allocated_low_gm_size; 225 unsigned long vgpu_allocated_high_gm_size; 226 }; 227 228 struct intel_gvt_fence { 229 unsigned long vgpu_allocated_fence_num; 230 }; 231 232 /* Special MMIO blocks. */ 233 struct gvt_mmio_block { 234 unsigned int device; 235 i915_reg_t offset; 236 unsigned int size; 237 gvt_mmio_func read; 238 gvt_mmio_func write; 239 }; 240 241 #define INTEL_GVT_MMIO_HASH_BITS 11 242 243 struct intel_gvt_mmio { 244 u8 *mmio_attribute; 245 /* Register contains RO bits */ 246 #define F_RO (1 << 0) 247 /* Register contains graphics address */ 248 #define F_GMADR (1 << 1) 249 /* Mode mask registers with high 16 bits as the mask bits */ 250 #define F_MODE_MASK (1 << 2) 251 /* This reg can be accessed by GPU commands */ 252 #define F_CMD_ACCESS (1 << 3) 253 /* This reg has been accessed by a VM */ 254 #define F_ACCESSED (1 << 4) 255 /* This reg has been accessed through GPU commands */ 256 #define F_CMD_ACCESSED (1 << 5) 257 /* This reg could be accessed by unaligned address */ 258 #define F_UNALIGN (1 << 6) 259 /* This reg is saved/restored in context */ 260 #define F_IN_CTX (1 << 7) 261 262 struct gvt_mmio_block *mmio_block; 263 unsigned int num_mmio_block; 264 265 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 266 unsigned long num_tracked_mmio; 267 }; 268 269 struct intel_gvt_firmware { 270 void *cfg_space; 271 void *mmio; 272 bool firmware_loaded; 273 }; 274 275 #define NR_MAX_INTEL_VGPU_TYPES 20 276 struct intel_vgpu_type { 277 char name[16]; 278 unsigned int avail_instance; 279 unsigned int low_gm_size; 280 unsigned int high_gm_size; 281 unsigned int fence; 282 unsigned int weight; 283 enum intel_vgpu_edid resolution; 284 }; 285 286 struct intel_gvt { 287 /* GVT scope lock, protect GVT itself, and all resource currently 288 * not yet protected by special locks(vgpu and scheduler lock). 289 */ 290 struct mutex lock; 291 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 292 struct mutex sched_lock; 293 294 struct intel_gt *gt; 295 struct idr vgpu_idr; /* vGPU IDR pool */ 296 297 struct intel_gvt_device_info device_info; 298 struct intel_gvt_gm gm; 299 struct intel_gvt_fence fence; 300 struct intel_gvt_mmio mmio; 301 struct intel_gvt_firmware firmware; 302 struct intel_gvt_irq irq; 303 struct intel_gvt_gtt gtt; 304 struct intel_gvt_workload_scheduler scheduler; 305 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 306 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 307 struct intel_vgpu_type *types; 308 unsigned int num_types; 309 struct intel_vgpu *idle_vgpu; 310 311 struct task_struct *service_thread; 312 wait_queue_head_t service_thread_wq; 313 314 /* service_request is always used in bit operation, we should always 315 * use it with atomic bit ops so that no need to use gvt big lock. 316 */ 317 unsigned long service_request; 318 319 struct { 320 struct engine_mmio *mmio; 321 int ctx_mmio_count[I915_NUM_ENGINES]; 322 u32 *tlb_mmio_offset_list; 323 u32 tlb_mmio_offset_list_cnt; 324 u32 *mocs_mmio_offset_list; 325 u32 mocs_mmio_offset_list_cnt; 326 } engine_mmio_list; 327 328 struct dentry *debugfs_root; 329 }; 330 331 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 332 { 333 return i915->gvt; 334 } 335 336 enum { 337 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 338 339 /* Scheduling trigger by timer */ 340 INTEL_GVT_REQUEST_SCHED = 1, 341 342 /* Scheduling trigger by event */ 343 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 344 }; 345 346 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 347 int service) 348 { 349 set_bit(service, (void *)&gvt->service_request); 350 wake_up(&gvt->service_thread_wq); 351 } 352 353 void intel_gvt_free_firmware(struct intel_gvt *gvt); 354 int intel_gvt_load_firmware(struct intel_gvt *gvt); 355 356 /* Aperture/GM space definitions for GVT device */ 357 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 358 #define BYTES_TO_MB(b) ((b) >> 20ULL) 359 360 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 361 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 362 #define HOST_FENCE 4 363 364 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 365 366 /* Aperture/GM space definitions for GVT device */ 367 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 368 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 369 370 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 371 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 372 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 373 374 #define gvt_aperture_gmadr_base(gvt) (0) 375 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 376 + gvt_aperture_sz(gvt) - 1) 377 378 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 379 + gvt_aperture_sz(gvt)) 380 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 381 + gvt_hidden_sz(gvt) - 1) 382 383 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 384 385 /* Aperture/GM space definitions for vGPU */ 386 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 387 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 388 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 389 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 390 391 #define vgpu_aperture_pa_base(vgpu) \ 392 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 393 394 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 395 396 #define vgpu_aperture_pa_end(vgpu) \ 397 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 398 399 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 400 #define vgpu_aperture_gmadr_end(vgpu) \ 401 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 402 403 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 404 #define vgpu_hidden_gmadr_end(vgpu) \ 405 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 406 407 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 408 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 409 410 struct intel_vgpu_creation_params { 411 __u64 handle; 412 __u64 low_gm_sz; /* in MB */ 413 __u64 high_gm_sz; /* in MB */ 414 __u64 fence_sz; 415 __u64 resolution; 416 __s32 primary; 417 __u64 vgpu_id; 418 419 __u32 weight; 420 }; 421 422 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 423 struct intel_vgpu_creation_params *param); 424 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 425 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 426 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 427 u32 fence, u64 value); 428 429 /* Macros for easily accessing vGPU virtual/shadow register. 430 Explicitly seperate use for typed MMIO reg or real offset.*/ 431 #define vgpu_vreg_t(vgpu, reg) \ 432 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 433 #define vgpu_vreg(vgpu, offset) \ 434 (*(u32 *)(vgpu->mmio.vreg + (offset))) 435 #define vgpu_vreg64_t(vgpu, reg) \ 436 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 437 #define vgpu_vreg64(vgpu, offset) \ 438 (*(u64 *)(vgpu->mmio.vreg + (offset))) 439 440 #define for_each_active_vgpu(gvt, vgpu, id) \ 441 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 442 for_each_if(vgpu->active) 443 444 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 445 u32 offset, u32 val, bool low) 446 { 447 u32 *pval; 448 449 /* BAR offset should be 32 bits algiend */ 450 offset = rounddown(offset, 4); 451 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 452 453 if (low) { 454 /* 455 * only update bit 31 - bit 4, 456 * leave the bit 3 - bit 0 unchanged. 457 */ 458 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 459 } else { 460 *pval = val; 461 } 462 } 463 464 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 465 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 466 467 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 468 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 469 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 470 struct intel_vgpu_type *type); 471 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 472 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 473 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 474 intel_engine_mask_t engine_mask); 475 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 476 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 477 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 478 479 /* validating GM functions */ 480 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 481 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 482 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 483 484 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 485 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 486 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 487 488 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 489 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 490 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 491 492 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 493 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 494 (gmadr <= gvt_aperture_gmadr_end(gvt))) 495 496 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 497 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 498 (gmadr <= gvt_hidden_gmadr_end(gvt))) 499 500 #define gvt_gmadr_is_valid(gvt, gmadr) \ 501 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 502 gvt_gmadr_is_hidden(gvt, gmadr)) 503 504 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 505 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 506 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 507 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 508 unsigned long *h_index); 509 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 510 unsigned long *g_index); 511 512 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 513 bool primary); 514 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 515 516 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 517 void *p_data, unsigned int bytes); 518 519 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 520 void *p_data, unsigned int bytes); 521 522 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 523 524 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 525 { 526 /* We are 64bit bar. */ 527 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 528 PCI_BASE_ADDRESS_MEM_MASK; 529 } 530 531 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 532 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 533 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 534 535 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 536 void populate_pvinfo_page(struct intel_vgpu *vgpu); 537 538 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 539 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 540 541 struct intel_gvt_ops { 542 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 543 unsigned int); 544 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 545 unsigned int); 546 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 547 unsigned int); 548 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 549 unsigned int); 550 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 551 struct intel_vgpu_type *); 552 void (*vgpu_destroy)(struct intel_vgpu *vgpu); 553 void (*vgpu_release)(struct intel_vgpu *vgpu); 554 void (*vgpu_reset)(struct intel_vgpu *); 555 void (*vgpu_activate)(struct intel_vgpu *); 556 void (*vgpu_deactivate)(struct intel_vgpu *); 557 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 558 const char *name); 559 bool (*get_gvt_attrs)(struct attribute_group ***intel_vgpu_type_groups); 560 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 561 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 562 int (*write_protect_handler)(struct intel_vgpu *, u64, void *, 563 unsigned int); 564 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected); 565 }; 566 567 568 enum { 569 GVT_FAILSAFE_UNSUPPORTED_GUEST, 570 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 571 GVT_FAILSAFE_GUEST_ERR, 572 }; 573 574 static inline void mmio_hw_access_pre(struct intel_gt *gt) 575 { 576 intel_runtime_pm_get(gt->uncore->rpm); 577 } 578 579 static inline void mmio_hw_access_post(struct intel_gt *gt) 580 { 581 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 582 } 583 584 /** 585 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 586 * @gvt: a GVT device 587 * @offset: register offset 588 * 589 */ 590 static inline void intel_gvt_mmio_set_accessed( 591 struct intel_gvt *gvt, unsigned int offset) 592 { 593 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 594 } 595 596 /** 597 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 598 * @gvt: a GVT device 599 * @offset: register offset 600 * 601 */ 602 static inline bool intel_gvt_mmio_is_cmd_access( 603 struct intel_gvt *gvt, unsigned int offset) 604 { 605 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 606 } 607 608 /** 609 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 610 * @gvt: a GVT device 611 * @offset: register offset 612 * 613 */ 614 static inline bool intel_gvt_mmio_is_unalign( 615 struct intel_gvt *gvt, unsigned int offset) 616 { 617 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 618 } 619 620 /** 621 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 622 * @gvt: a GVT device 623 * @offset: register offset 624 * 625 */ 626 static inline void intel_gvt_mmio_set_cmd_accessed( 627 struct intel_gvt *gvt, unsigned int offset) 628 { 629 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 630 } 631 632 /** 633 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 634 * @gvt: a GVT device 635 * @offset: register offset 636 * 637 * Returns: 638 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 639 * 640 */ 641 static inline bool intel_gvt_mmio_has_mode_mask( 642 struct intel_gvt *gvt, unsigned int offset) 643 { 644 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 645 } 646 647 /** 648 * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask 649 * @gvt: a GVT device 650 * @offset: register offset 651 * 652 * Returns: 653 * True if a MMIO has a in-context mask, false if it isn't. 654 * 655 */ 656 static inline bool intel_gvt_mmio_is_in_ctx( 657 struct intel_gvt *gvt, unsigned int offset) 658 { 659 return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX; 660 } 661 662 /** 663 * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context 664 * @gvt: a GVT device 665 * @offset: register offset 666 * 667 */ 668 static inline void intel_gvt_mmio_set_in_ctx( 669 struct intel_gvt *gvt, unsigned int offset) 670 { 671 gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX; 672 } 673 674 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 675 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 676 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 677 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 678 679 680 #include "trace.h" 681 #include "mpt.h" 682 683 #endif 684