1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_blend.h> 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_de.h" 15 #include "intel_display_irq.h" 16 #include "intel_display_types.h" 17 #include "intel_fb.h" 18 #include "intel_fbc.h" 19 #include "intel_frontbuffer.h" 20 #include "intel_psr.h" 21 #include "intel_psr_regs.h" 22 #include "skl_scaler.h" 23 #include "skl_universal_plane.h" 24 #include "skl_watermark.h" 25 #include "pxp/intel_pxp.h" 26 27 static const u32 skl_plane_formats[] = { 28 DRM_FORMAT_C8, 29 DRM_FORMAT_RGB565, 30 DRM_FORMAT_XRGB8888, 31 DRM_FORMAT_XBGR8888, 32 DRM_FORMAT_ARGB8888, 33 DRM_FORMAT_ABGR8888, 34 DRM_FORMAT_XRGB2101010, 35 DRM_FORMAT_XBGR2101010, 36 DRM_FORMAT_XRGB16161616F, 37 DRM_FORMAT_XBGR16161616F, 38 DRM_FORMAT_YUYV, 39 DRM_FORMAT_YVYU, 40 DRM_FORMAT_UYVY, 41 DRM_FORMAT_VYUY, 42 DRM_FORMAT_XYUV8888, 43 }; 44 45 static const u32 skl_planar_formats[] = { 46 DRM_FORMAT_C8, 47 DRM_FORMAT_RGB565, 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_XBGR8888, 50 DRM_FORMAT_ARGB8888, 51 DRM_FORMAT_ABGR8888, 52 DRM_FORMAT_XRGB2101010, 53 DRM_FORMAT_XBGR2101010, 54 DRM_FORMAT_XRGB16161616F, 55 DRM_FORMAT_XBGR16161616F, 56 DRM_FORMAT_YUYV, 57 DRM_FORMAT_YVYU, 58 DRM_FORMAT_UYVY, 59 DRM_FORMAT_VYUY, 60 DRM_FORMAT_NV12, 61 DRM_FORMAT_XYUV8888, 62 }; 63 64 static const u32 glk_planar_formats[] = { 65 DRM_FORMAT_C8, 66 DRM_FORMAT_RGB565, 67 DRM_FORMAT_XRGB8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ARGB8888, 70 DRM_FORMAT_ABGR8888, 71 DRM_FORMAT_XRGB2101010, 72 DRM_FORMAT_XBGR2101010, 73 DRM_FORMAT_XRGB16161616F, 74 DRM_FORMAT_XBGR16161616F, 75 DRM_FORMAT_YUYV, 76 DRM_FORMAT_YVYU, 77 DRM_FORMAT_UYVY, 78 DRM_FORMAT_VYUY, 79 DRM_FORMAT_NV12, 80 DRM_FORMAT_XYUV8888, 81 DRM_FORMAT_P010, 82 DRM_FORMAT_P012, 83 DRM_FORMAT_P016, 84 }; 85 86 static const u32 icl_sdr_y_plane_formats[] = { 87 DRM_FORMAT_C8, 88 DRM_FORMAT_RGB565, 89 DRM_FORMAT_XRGB8888, 90 DRM_FORMAT_XBGR8888, 91 DRM_FORMAT_ARGB8888, 92 DRM_FORMAT_ABGR8888, 93 DRM_FORMAT_XRGB2101010, 94 DRM_FORMAT_XBGR2101010, 95 DRM_FORMAT_ARGB2101010, 96 DRM_FORMAT_ABGR2101010, 97 DRM_FORMAT_YUYV, 98 DRM_FORMAT_YVYU, 99 DRM_FORMAT_UYVY, 100 DRM_FORMAT_VYUY, 101 DRM_FORMAT_Y210, 102 DRM_FORMAT_Y212, 103 DRM_FORMAT_Y216, 104 DRM_FORMAT_XYUV8888, 105 DRM_FORMAT_XVYU2101010, 106 DRM_FORMAT_XVYU12_16161616, 107 DRM_FORMAT_XVYU16161616, 108 }; 109 110 static const u32 icl_sdr_uv_plane_formats[] = { 111 DRM_FORMAT_C8, 112 DRM_FORMAT_RGB565, 113 DRM_FORMAT_XRGB8888, 114 DRM_FORMAT_XBGR8888, 115 DRM_FORMAT_ARGB8888, 116 DRM_FORMAT_ABGR8888, 117 DRM_FORMAT_XRGB2101010, 118 DRM_FORMAT_XBGR2101010, 119 DRM_FORMAT_ARGB2101010, 120 DRM_FORMAT_ABGR2101010, 121 DRM_FORMAT_YUYV, 122 DRM_FORMAT_YVYU, 123 DRM_FORMAT_UYVY, 124 DRM_FORMAT_VYUY, 125 DRM_FORMAT_NV12, 126 DRM_FORMAT_P010, 127 DRM_FORMAT_P012, 128 DRM_FORMAT_P016, 129 DRM_FORMAT_Y210, 130 DRM_FORMAT_Y212, 131 DRM_FORMAT_Y216, 132 DRM_FORMAT_XYUV8888, 133 DRM_FORMAT_XVYU2101010, 134 DRM_FORMAT_XVYU12_16161616, 135 DRM_FORMAT_XVYU16161616, 136 }; 137 138 static const u32 icl_hdr_plane_formats[] = { 139 DRM_FORMAT_C8, 140 DRM_FORMAT_RGB565, 141 DRM_FORMAT_XRGB8888, 142 DRM_FORMAT_XBGR8888, 143 DRM_FORMAT_ARGB8888, 144 DRM_FORMAT_ABGR8888, 145 DRM_FORMAT_XRGB2101010, 146 DRM_FORMAT_XBGR2101010, 147 DRM_FORMAT_ARGB2101010, 148 DRM_FORMAT_ABGR2101010, 149 DRM_FORMAT_XRGB16161616F, 150 DRM_FORMAT_XBGR16161616F, 151 DRM_FORMAT_ARGB16161616F, 152 DRM_FORMAT_ABGR16161616F, 153 DRM_FORMAT_YUYV, 154 DRM_FORMAT_YVYU, 155 DRM_FORMAT_UYVY, 156 DRM_FORMAT_VYUY, 157 DRM_FORMAT_NV12, 158 DRM_FORMAT_P010, 159 DRM_FORMAT_P012, 160 DRM_FORMAT_P016, 161 DRM_FORMAT_Y210, 162 DRM_FORMAT_Y212, 163 DRM_FORMAT_Y216, 164 DRM_FORMAT_XYUV8888, 165 DRM_FORMAT_XVYU2101010, 166 DRM_FORMAT_XVYU12_16161616, 167 DRM_FORMAT_XVYU16161616, 168 }; 169 170 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 171 { 172 switch (format) { 173 case PLANE_CTL_FORMAT_RGB_565: 174 return DRM_FORMAT_RGB565; 175 case PLANE_CTL_FORMAT_NV12: 176 return DRM_FORMAT_NV12; 177 case PLANE_CTL_FORMAT_XYUV: 178 return DRM_FORMAT_XYUV8888; 179 case PLANE_CTL_FORMAT_P010: 180 return DRM_FORMAT_P010; 181 case PLANE_CTL_FORMAT_P012: 182 return DRM_FORMAT_P012; 183 case PLANE_CTL_FORMAT_P016: 184 return DRM_FORMAT_P016; 185 case PLANE_CTL_FORMAT_Y210: 186 return DRM_FORMAT_Y210; 187 case PLANE_CTL_FORMAT_Y212: 188 return DRM_FORMAT_Y212; 189 case PLANE_CTL_FORMAT_Y216: 190 return DRM_FORMAT_Y216; 191 case PLANE_CTL_FORMAT_Y410: 192 return DRM_FORMAT_XVYU2101010; 193 case PLANE_CTL_FORMAT_Y412: 194 return DRM_FORMAT_XVYU12_16161616; 195 case PLANE_CTL_FORMAT_Y416: 196 return DRM_FORMAT_XVYU16161616; 197 default: 198 case PLANE_CTL_FORMAT_XRGB_8888: 199 if (rgb_order) { 200 if (alpha) 201 return DRM_FORMAT_ABGR8888; 202 else 203 return DRM_FORMAT_XBGR8888; 204 } else { 205 if (alpha) 206 return DRM_FORMAT_ARGB8888; 207 else 208 return DRM_FORMAT_XRGB8888; 209 } 210 case PLANE_CTL_FORMAT_XRGB_2101010: 211 if (rgb_order) { 212 if (alpha) 213 return DRM_FORMAT_ABGR2101010; 214 else 215 return DRM_FORMAT_XBGR2101010; 216 } else { 217 if (alpha) 218 return DRM_FORMAT_ARGB2101010; 219 else 220 return DRM_FORMAT_XRGB2101010; 221 } 222 case PLANE_CTL_FORMAT_XRGB_16161616F: 223 if (rgb_order) { 224 if (alpha) 225 return DRM_FORMAT_ABGR16161616F; 226 else 227 return DRM_FORMAT_XBGR16161616F; 228 } else { 229 if (alpha) 230 return DRM_FORMAT_ARGB16161616F; 231 else 232 return DRM_FORMAT_XRGB16161616F; 233 } 234 } 235 } 236 237 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 238 { 239 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 240 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); 241 else 242 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); 243 } 244 245 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 246 enum plane_id plane_id) 247 { 248 return DISPLAY_VER(dev_priv) >= 11 && 249 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 250 } 251 252 u8 icl_hdr_plane_mask(void) 253 { 254 return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1); 255 } 256 257 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 258 { 259 return DISPLAY_VER(dev_priv) >= 11 && 260 icl_hdr_plane_mask() & BIT(plane_id); 261 } 262 263 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 264 const struct intel_plane_state *plane_state) 265 { 266 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 267 268 /* two pixels per clock */ 269 return DIV_ROUND_UP(pixel_rate, 2); 270 } 271 272 static void 273 glk_plane_ratio(const struct intel_plane_state *plane_state, 274 unsigned int *num, unsigned int *den) 275 { 276 const struct drm_framebuffer *fb = plane_state->hw.fb; 277 278 if (fb->format->cpp[0] == 8) { 279 *num = 10; 280 *den = 8; 281 } else { 282 *num = 1; 283 *den = 1; 284 } 285 } 286 287 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 288 const struct intel_plane_state *plane_state) 289 { 290 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 291 unsigned int num, den; 292 293 glk_plane_ratio(plane_state, &num, &den); 294 295 /* two pixels per clock */ 296 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 297 } 298 299 static void 300 skl_plane_ratio(const struct intel_plane_state *plane_state, 301 unsigned int *num, unsigned int *den) 302 { 303 const struct drm_framebuffer *fb = plane_state->hw.fb; 304 305 if (fb->format->cpp[0] == 8) { 306 *num = 9; 307 *den = 8; 308 } else { 309 *num = 1; 310 *den = 1; 311 } 312 } 313 314 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 315 const struct intel_plane_state *plane_state) 316 { 317 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 318 unsigned int num, den; 319 320 skl_plane_ratio(plane_state, &num, &den); 321 322 return DIV_ROUND_UP(pixel_rate * num, den); 323 } 324 325 static int skl_plane_max_width(const struct drm_framebuffer *fb, 326 int color_plane, 327 unsigned int rotation) 328 { 329 int cpp = fb->format->cpp[color_plane]; 330 331 switch (fb->modifier) { 332 case DRM_FORMAT_MOD_LINEAR: 333 case I915_FORMAT_MOD_X_TILED: 334 /* 335 * Validated limit is 4k, but has 5k should 336 * work apart from the following features: 337 * - Ytile (already limited to 4k) 338 * - FP16 (already limited to 4k) 339 * - render compression (already limited to 4k) 340 * - KVMR sprite and cursor (don't care) 341 * - horizontal panning (TODO verify this) 342 * - pipe and plane scaling (TODO verify this) 343 */ 344 if (cpp == 8) 345 return 4096; 346 else 347 return 5120; 348 case I915_FORMAT_MOD_Y_TILED_CCS: 349 case I915_FORMAT_MOD_Yf_TILED_CCS: 350 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 351 /* FIXME AUX plane? */ 352 case I915_FORMAT_MOD_Y_TILED: 353 case I915_FORMAT_MOD_Yf_TILED: 354 if (cpp == 8) 355 return 2048; 356 else 357 return 4096; 358 default: 359 MISSING_CASE(fb->modifier); 360 return 2048; 361 } 362 } 363 364 static int glk_plane_max_width(const struct drm_framebuffer *fb, 365 int color_plane, 366 unsigned int rotation) 367 { 368 int cpp = fb->format->cpp[color_plane]; 369 370 switch (fb->modifier) { 371 case DRM_FORMAT_MOD_LINEAR: 372 case I915_FORMAT_MOD_X_TILED: 373 if (cpp == 8) 374 return 4096; 375 else 376 return 5120; 377 case I915_FORMAT_MOD_Y_TILED_CCS: 378 case I915_FORMAT_MOD_Yf_TILED_CCS: 379 /* FIXME AUX plane? */ 380 case I915_FORMAT_MOD_Y_TILED: 381 case I915_FORMAT_MOD_Yf_TILED: 382 if (cpp == 8) 383 return 2048; 384 else 385 return 5120; 386 default: 387 MISSING_CASE(fb->modifier); 388 return 2048; 389 } 390 } 391 392 static int icl_plane_min_width(const struct drm_framebuffer *fb, 393 int color_plane, 394 unsigned int rotation) 395 { 396 /* Wa_14011264657, Wa_14011050563: gen11+ */ 397 switch (fb->format->format) { 398 case DRM_FORMAT_C8: 399 return 18; 400 case DRM_FORMAT_RGB565: 401 return 10; 402 case DRM_FORMAT_XRGB8888: 403 case DRM_FORMAT_XBGR8888: 404 case DRM_FORMAT_ARGB8888: 405 case DRM_FORMAT_ABGR8888: 406 case DRM_FORMAT_XRGB2101010: 407 case DRM_FORMAT_XBGR2101010: 408 case DRM_FORMAT_ARGB2101010: 409 case DRM_FORMAT_ABGR2101010: 410 case DRM_FORMAT_XVYU2101010: 411 case DRM_FORMAT_Y212: 412 case DRM_FORMAT_Y216: 413 return 6; 414 case DRM_FORMAT_NV12: 415 return 20; 416 case DRM_FORMAT_P010: 417 case DRM_FORMAT_P012: 418 case DRM_FORMAT_P016: 419 return 12; 420 case DRM_FORMAT_XRGB16161616F: 421 case DRM_FORMAT_XBGR16161616F: 422 case DRM_FORMAT_ARGB16161616F: 423 case DRM_FORMAT_ABGR16161616F: 424 case DRM_FORMAT_XVYU12_16161616: 425 case DRM_FORMAT_XVYU16161616: 426 return 4; 427 default: 428 return 1; 429 } 430 } 431 432 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 433 int color_plane, 434 unsigned int rotation) 435 { 436 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 437 return 4096; 438 else 439 return 5120; 440 } 441 442 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 443 int color_plane, 444 unsigned int rotation) 445 { 446 return 5120; 447 } 448 449 static int skl_plane_max_height(const struct drm_framebuffer *fb, 450 int color_plane, 451 unsigned int rotation) 452 { 453 return 4096; 454 } 455 456 static int icl_plane_max_height(const struct drm_framebuffer *fb, 457 int color_plane, 458 unsigned int rotation) 459 { 460 return 4320; 461 } 462 463 static unsigned int 464 skl_plane_max_stride(struct intel_plane *plane, 465 u32 pixel_format, u64 modifier, 466 unsigned int rotation) 467 { 468 struct drm_i915_private *i915 = to_i915(plane->base.dev); 469 const struct drm_format_info *info = drm_format_info(pixel_format); 470 int cpp = info->cpp[0]; 471 int max_horizontal_pixels = 8192; 472 int max_stride_bytes; 473 474 if (DISPLAY_VER(i915) >= 13) { 475 /* 476 * The stride in bytes must not exceed of the size 477 * of 128K bytes. For pixel formats of 64bpp will allow 478 * for a 16K pixel surface. 479 */ 480 max_stride_bytes = 131072; 481 if (cpp == 8) 482 max_horizontal_pixels = 16384; 483 else 484 max_horizontal_pixels = 65536; 485 } else { 486 /* 487 * "The stride in bytes must not exceed the 488 * of the size of 8K pixels and 32K bytes." 489 */ 490 max_stride_bytes = 32768; 491 } 492 493 if (drm_rotation_90_or_270(rotation)) 494 return min(max_horizontal_pixels, max_stride_bytes / cpp); 495 else 496 return min(max_horizontal_pixels * cpp, max_stride_bytes); 497 } 498 499 500 /* Preoffset values for YUV to RGB Conversion */ 501 #define PREOFF_YUV_TO_RGB_HI 0x1800 502 #define PREOFF_YUV_TO_RGB_ME 0x0000 503 #define PREOFF_YUV_TO_RGB_LO 0x1800 504 505 #define ROFF(x) (((x) & 0xffff) << 16) 506 #define GOFF(x) (((x) & 0xffff) << 0) 507 #define BOFF(x) (((x) & 0xffff) << 16) 508 509 /* 510 * Programs the input color space conversion stage for ICL HDR planes. 511 * Note that it is assumed that this stage always happens after YUV 512 * range correction. Thus, the input to this stage is assumed to be 513 * in full-range YCbCr. 514 */ 515 static void 516 icl_program_input_csc(struct intel_plane *plane, 517 const struct intel_crtc_state *crtc_state, 518 const struct intel_plane_state *plane_state) 519 { 520 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 521 enum pipe pipe = plane->pipe; 522 enum plane_id plane_id = plane->id; 523 524 static const u16 input_csc_matrix[][9] = { 525 /* 526 * BT.601 full range YCbCr -> full range RGB 527 * The matrix required is : 528 * [1.000, 0.000, 1.371, 529 * 1.000, -0.336, -0.698, 530 * 1.000, 1.732, 0.0000] 531 */ 532 [DRM_COLOR_YCBCR_BT601] = { 533 0x7AF8, 0x7800, 0x0, 534 0x8B28, 0x7800, 0x9AC0, 535 0x0, 0x7800, 0x7DD8, 536 }, 537 /* 538 * BT.709 full range YCbCr -> full range RGB 539 * The matrix required is : 540 * [1.000, 0.000, 1.574, 541 * 1.000, -0.187, -0.468, 542 * 1.000, 1.855, 0.0000] 543 */ 544 [DRM_COLOR_YCBCR_BT709] = { 545 0x7C98, 0x7800, 0x0, 546 0x9EF8, 0x7800, 0xAC00, 547 0x0, 0x7800, 0x7ED8, 548 }, 549 /* 550 * BT.2020 full range YCbCr -> full range RGB 551 * The matrix required is : 552 * [1.000, 0.000, 1.474, 553 * 1.000, -0.1645, -0.5713, 554 * 1.000, 1.8814, 0.0000] 555 */ 556 [DRM_COLOR_YCBCR_BT2020] = { 557 0x7BC8, 0x7800, 0x0, 558 0x8928, 0x7800, 0xAA88, 559 0x0, 0x7800, 0x7F10, 560 }, 561 }; 562 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 563 564 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 565 ROFF(csc[0]) | GOFF(csc[1])); 566 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 567 BOFF(csc[2])); 568 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 569 ROFF(csc[3]) | GOFF(csc[4])); 570 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 571 BOFF(csc[5])); 572 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 573 ROFF(csc[6]) | GOFF(csc[7])); 574 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 575 BOFF(csc[8])); 576 577 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 578 PREOFF_YUV_TO_RGB_HI); 579 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 580 PREOFF_YUV_TO_RGB_ME); 581 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 582 PREOFF_YUV_TO_RGB_LO); 583 intel_de_write_fw(dev_priv, 584 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 585 intel_de_write_fw(dev_priv, 586 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 587 intel_de_write_fw(dev_priv, 588 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 589 } 590 591 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 592 int color_plane, unsigned int rotation) 593 { 594 /* 595 * The stride is either expressed as a multiple of 64 bytes chunks for 596 * linear buffers or in number of tiles for tiled buffers. 597 */ 598 if (is_surface_linear(fb, color_plane)) 599 return 64; 600 else if (drm_rotation_90_or_270(rotation)) 601 return intel_tile_height(fb, color_plane); 602 else 603 return intel_tile_width_bytes(fb, color_plane); 604 } 605 606 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 607 int color_plane) 608 { 609 const struct drm_framebuffer *fb = plane_state->hw.fb; 610 unsigned int rotation = plane_state->hw.rotation; 611 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 612 613 if (color_plane >= fb->format->num_planes) 614 return 0; 615 616 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 617 } 618 619 static void 620 skl_plane_disable_arm(struct intel_plane *plane, 621 const struct intel_crtc_state *crtc_state) 622 { 623 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 624 enum plane_id plane_id = plane->id; 625 enum pipe pipe = plane->pipe; 626 627 skl_write_plane_wm(plane, crtc_state); 628 629 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 630 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 631 } 632 633 static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane, 634 const struct intel_crtc_state *crtc_state) 635 { 636 struct drm_i915_private *i915 = to_i915(plane->base.dev); 637 enum pipe pipe = plane->pipe; 638 639 if (!crtc_state->enable_psr2_sel_fetch) 640 return; 641 642 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 643 } 644 645 static void 646 icl_plane_disable_arm(struct intel_plane *plane, 647 const struct intel_crtc_state *crtc_state) 648 { 649 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 650 enum plane_id plane_id = plane->id; 651 enum pipe pipe = plane->pipe; 652 653 if (icl_is_hdr_plane(dev_priv, plane_id)) 654 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 655 656 skl_write_plane_wm(plane, crtc_state); 657 658 icl_plane_disable_sel_fetch_arm(plane, crtc_state); 659 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 660 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 661 } 662 663 static bool 664 skl_plane_get_hw_state(struct intel_plane *plane, 665 enum pipe *pipe) 666 { 667 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 668 enum intel_display_power_domain power_domain; 669 enum plane_id plane_id = plane->id; 670 intel_wakeref_t wakeref; 671 bool ret; 672 673 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 674 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 675 if (!wakeref) 676 return false; 677 678 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 679 680 *pipe = plane->pipe; 681 682 intel_display_power_put(dev_priv, power_domain, wakeref); 683 684 return ret; 685 } 686 687 static u32 skl_plane_ctl_format(u32 pixel_format) 688 { 689 switch (pixel_format) { 690 case DRM_FORMAT_C8: 691 return PLANE_CTL_FORMAT_INDEXED; 692 case DRM_FORMAT_RGB565: 693 return PLANE_CTL_FORMAT_RGB_565; 694 case DRM_FORMAT_XBGR8888: 695 case DRM_FORMAT_ABGR8888: 696 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 697 case DRM_FORMAT_XRGB8888: 698 case DRM_FORMAT_ARGB8888: 699 return PLANE_CTL_FORMAT_XRGB_8888; 700 case DRM_FORMAT_XBGR2101010: 701 case DRM_FORMAT_ABGR2101010: 702 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 703 case DRM_FORMAT_XRGB2101010: 704 case DRM_FORMAT_ARGB2101010: 705 return PLANE_CTL_FORMAT_XRGB_2101010; 706 case DRM_FORMAT_XBGR16161616F: 707 case DRM_FORMAT_ABGR16161616F: 708 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 709 case DRM_FORMAT_XRGB16161616F: 710 case DRM_FORMAT_ARGB16161616F: 711 return PLANE_CTL_FORMAT_XRGB_16161616F; 712 case DRM_FORMAT_XYUV8888: 713 return PLANE_CTL_FORMAT_XYUV; 714 case DRM_FORMAT_YUYV: 715 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 716 case DRM_FORMAT_YVYU: 717 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 718 case DRM_FORMAT_UYVY: 719 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 720 case DRM_FORMAT_VYUY: 721 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 722 case DRM_FORMAT_NV12: 723 return PLANE_CTL_FORMAT_NV12; 724 case DRM_FORMAT_P010: 725 return PLANE_CTL_FORMAT_P010; 726 case DRM_FORMAT_P012: 727 return PLANE_CTL_FORMAT_P012; 728 case DRM_FORMAT_P016: 729 return PLANE_CTL_FORMAT_P016; 730 case DRM_FORMAT_Y210: 731 return PLANE_CTL_FORMAT_Y210; 732 case DRM_FORMAT_Y212: 733 return PLANE_CTL_FORMAT_Y212; 734 case DRM_FORMAT_Y216: 735 return PLANE_CTL_FORMAT_Y216; 736 case DRM_FORMAT_XVYU2101010: 737 return PLANE_CTL_FORMAT_Y410; 738 case DRM_FORMAT_XVYU12_16161616: 739 return PLANE_CTL_FORMAT_Y412; 740 case DRM_FORMAT_XVYU16161616: 741 return PLANE_CTL_FORMAT_Y416; 742 default: 743 MISSING_CASE(pixel_format); 744 } 745 746 return 0; 747 } 748 749 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 750 { 751 if (!plane_state->hw.fb->format->has_alpha) 752 return PLANE_CTL_ALPHA_DISABLE; 753 754 switch (plane_state->hw.pixel_blend_mode) { 755 case DRM_MODE_BLEND_PIXEL_NONE: 756 return PLANE_CTL_ALPHA_DISABLE; 757 case DRM_MODE_BLEND_PREMULTI: 758 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 759 case DRM_MODE_BLEND_COVERAGE: 760 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 761 default: 762 MISSING_CASE(plane_state->hw.pixel_blend_mode); 763 return PLANE_CTL_ALPHA_DISABLE; 764 } 765 } 766 767 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 768 { 769 if (!plane_state->hw.fb->format->has_alpha) 770 return PLANE_COLOR_ALPHA_DISABLE; 771 772 switch (plane_state->hw.pixel_blend_mode) { 773 case DRM_MODE_BLEND_PIXEL_NONE: 774 return PLANE_COLOR_ALPHA_DISABLE; 775 case DRM_MODE_BLEND_PREMULTI: 776 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 777 case DRM_MODE_BLEND_COVERAGE: 778 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 779 default: 780 MISSING_CASE(plane_state->hw.pixel_blend_mode); 781 return PLANE_COLOR_ALPHA_DISABLE; 782 } 783 } 784 785 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 786 { 787 switch (fb_modifier) { 788 case DRM_FORMAT_MOD_LINEAR: 789 break; 790 case I915_FORMAT_MOD_X_TILED: 791 return PLANE_CTL_TILED_X; 792 case I915_FORMAT_MOD_Y_TILED: 793 return PLANE_CTL_TILED_Y; 794 case I915_FORMAT_MOD_4_TILED: 795 return PLANE_CTL_TILED_4; 796 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 797 return PLANE_CTL_TILED_4 | 798 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 799 PLANE_CTL_CLEAR_COLOR_DISABLE; 800 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 801 return PLANE_CTL_TILED_4 | 802 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE | 803 PLANE_CTL_CLEAR_COLOR_DISABLE; 804 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 805 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 806 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 807 return PLANE_CTL_TILED_4 | 808 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 809 PLANE_CTL_CLEAR_COLOR_DISABLE; 810 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 811 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 812 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 813 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 814 case I915_FORMAT_MOD_Y_TILED_CCS: 815 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 816 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 817 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 818 return PLANE_CTL_TILED_Y | 819 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 820 PLANE_CTL_CLEAR_COLOR_DISABLE; 821 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 822 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 823 case I915_FORMAT_MOD_Yf_TILED: 824 return PLANE_CTL_TILED_YF; 825 case I915_FORMAT_MOD_Yf_TILED_CCS: 826 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 827 default: 828 MISSING_CASE(fb_modifier); 829 } 830 831 return 0; 832 } 833 834 static u32 skl_plane_ctl_rotate(unsigned int rotate) 835 { 836 switch (rotate) { 837 case DRM_MODE_ROTATE_0: 838 break; 839 /* 840 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 841 * while i915 HW rotation is clockwise, thats why this swapping. 842 */ 843 case DRM_MODE_ROTATE_90: 844 return PLANE_CTL_ROTATE_270; 845 case DRM_MODE_ROTATE_180: 846 return PLANE_CTL_ROTATE_180; 847 case DRM_MODE_ROTATE_270: 848 return PLANE_CTL_ROTATE_90; 849 default: 850 MISSING_CASE(rotate); 851 } 852 853 return 0; 854 } 855 856 static u32 icl_plane_ctl_flip(unsigned int reflect) 857 { 858 switch (reflect) { 859 case 0: 860 break; 861 case DRM_MODE_REFLECT_X: 862 return PLANE_CTL_FLIP_HORIZONTAL; 863 case DRM_MODE_REFLECT_Y: 864 default: 865 MISSING_CASE(reflect); 866 } 867 868 return 0; 869 } 870 871 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 872 { 873 const struct drm_framebuffer *fb = plane_state->hw.fb; 874 875 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 876 switch (fb->format->cpp[0]) { 877 case 2: 878 return PLANE_CTL_ARB_SLOTS(1); 879 default: 880 return PLANE_CTL_ARB_SLOTS(0); 881 } 882 } else { 883 switch (fb->format->cpp[0]) { 884 case 8: 885 return PLANE_CTL_ARB_SLOTS(3); 886 case 4: 887 return PLANE_CTL_ARB_SLOTS(1); 888 default: 889 return PLANE_CTL_ARB_SLOTS(0); 890 } 891 } 892 } 893 894 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 895 { 896 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 897 u32 plane_ctl = 0; 898 899 if (DISPLAY_VER(dev_priv) >= 10) 900 return plane_ctl; 901 902 if (crtc_state->gamma_enable) 903 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 904 905 if (crtc_state->csc_enable) 906 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 907 908 return plane_ctl; 909 } 910 911 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 912 const struct intel_plane_state *plane_state) 913 { 914 struct drm_i915_private *dev_priv = 915 to_i915(plane_state->uapi.plane->dev); 916 const struct drm_framebuffer *fb = plane_state->hw.fb; 917 unsigned int rotation = plane_state->hw.rotation; 918 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 919 u32 plane_ctl; 920 921 plane_ctl = PLANE_CTL_ENABLE; 922 923 if (DISPLAY_VER(dev_priv) < 10) { 924 plane_ctl |= skl_plane_ctl_alpha(plane_state); 925 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 926 927 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 928 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 929 930 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 931 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 932 } 933 934 plane_ctl |= skl_plane_ctl_format(fb->format->format); 935 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 936 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 937 938 if (DISPLAY_VER(dev_priv) >= 11) 939 plane_ctl |= icl_plane_ctl_flip(rotation & 940 DRM_MODE_REFLECT_MASK); 941 942 if (key->flags & I915_SET_COLORKEY_DESTINATION) 943 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 944 else if (key->flags & I915_SET_COLORKEY_SOURCE) 945 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 946 947 /* Wa_22012358565:adl-p */ 948 if (DISPLAY_VER(dev_priv) == 13) 949 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 950 951 return plane_ctl; 952 } 953 954 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 955 { 956 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 957 u32 plane_color_ctl = 0; 958 959 if (DISPLAY_VER(dev_priv) >= 11) 960 return plane_color_ctl; 961 962 if (crtc_state->gamma_enable) 963 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 964 965 if (crtc_state->csc_enable) 966 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 967 968 return plane_color_ctl; 969 } 970 971 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 972 const struct intel_plane_state *plane_state) 973 { 974 struct drm_i915_private *dev_priv = 975 to_i915(plane_state->uapi.plane->dev); 976 const struct drm_framebuffer *fb = plane_state->hw.fb; 977 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 978 u32 plane_color_ctl = 0; 979 980 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 981 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 982 983 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 984 switch (plane_state->hw.color_encoding) { 985 case DRM_COLOR_YCBCR_BT709: 986 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 987 break; 988 case DRM_COLOR_YCBCR_BT2020: 989 plane_color_ctl |= 990 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 991 break; 992 default: 993 plane_color_ctl |= 994 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 995 } 996 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 997 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 998 } else if (fb->format->is_yuv) { 999 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 1000 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1001 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 1002 } 1003 1004 if (plane_state->force_black) 1005 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 1006 1007 return plane_color_ctl; 1008 } 1009 1010 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 1011 int color_plane) 1012 { 1013 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1014 const struct drm_framebuffer *fb = plane_state->hw.fb; 1015 u32 offset = plane_state->view.color_plane[color_plane].offset; 1016 1017 if (intel_fb_uses_dpt(fb)) { 1018 /* 1019 * The DPT object contains only one vma, so the VMA's offset 1020 * within the DPT is always 0. 1021 */ 1022 drm_WARN_ON(&i915->drm, plane_state->dpt_vma && 1023 plane_state->dpt_vma->node.start); 1024 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 1025 return offset >> 9; 1026 } else { 1027 drm_WARN_ON(&i915->drm, offset & 0xfff); 1028 return offset; 1029 } 1030 } 1031 1032 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 1033 int color_plane) 1034 { 1035 u32 plane_surf; 1036 1037 plane_surf = intel_plane_ggtt_offset(plane_state) + 1038 skl_surf_address(plane_state, color_plane); 1039 1040 if (plane_state->decrypt) 1041 plane_surf |= PLANE_SURF_DECRYPT; 1042 1043 return plane_surf; 1044 } 1045 1046 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 1047 int color_plane) 1048 { 1049 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1050 const struct drm_framebuffer *fb = plane_state->hw.fb; 1051 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1052 u32 aux_dist; 1053 1054 if (!aux_plane) 1055 return 0; 1056 1057 aux_dist = skl_surf_address(plane_state, aux_plane) - 1058 skl_surf_address(plane_state, color_plane); 1059 1060 if (DISPLAY_VER(i915) < 12) 1061 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1062 1063 return aux_dist; 1064 } 1065 1066 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1067 { 1068 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1069 1070 return key->min_value; 1071 } 1072 1073 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1074 { 1075 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1076 u8 alpha = plane_state->hw.alpha >> 8; 1077 1078 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1079 } 1080 1081 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1082 { 1083 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1084 u8 alpha = plane_state->hw.alpha >> 8; 1085 u32 keymsk; 1086 1087 keymsk = key->channel_mask & 0x7ffffff; 1088 if (alpha < 0xff) 1089 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1090 1091 return keymsk; 1092 } 1093 1094 static void icl_plane_csc_load_black(struct intel_plane *plane) 1095 { 1096 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1097 enum plane_id plane_id = plane->id; 1098 enum pipe pipe = plane->pipe; 1099 1100 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1101 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1102 1103 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1104 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1105 1106 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1107 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1108 1109 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1110 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1111 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1112 1113 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1114 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1115 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1116 } 1117 1118 static int icl_plane_color_plane(const struct intel_plane_state *plane_state) 1119 { 1120 /* Program the UV plane on planar master */ 1121 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1122 return 1; 1123 else 1124 return 0; 1125 } 1126 1127 static void 1128 skl_plane_update_noarm(struct intel_plane *plane, 1129 const struct intel_crtc_state *crtc_state, 1130 const struct intel_plane_state *plane_state) 1131 { 1132 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1133 enum plane_id plane_id = plane->id; 1134 enum pipe pipe = plane->pipe; 1135 u32 stride = skl_plane_stride(plane_state, 0); 1136 int crtc_x = plane_state->uapi.dst.x1; 1137 int crtc_y = plane_state->uapi.dst.y1; 1138 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1139 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1140 1141 /* The scaler will handle the output position */ 1142 if (plane_state->scaler_id >= 0) { 1143 crtc_x = 0; 1144 crtc_y = 0; 1145 } 1146 1147 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1148 PLANE_STRIDE_(stride)); 1149 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1150 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1151 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1152 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1153 1154 skl_write_plane_wm(plane, crtc_state); 1155 } 1156 1157 static void 1158 skl_plane_update_arm(struct intel_plane *plane, 1159 const struct intel_crtc_state *crtc_state, 1160 const struct intel_plane_state *plane_state) 1161 { 1162 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1163 enum plane_id plane_id = plane->id; 1164 enum pipe pipe = plane->pipe; 1165 u32 x = plane_state->view.color_plane[0].x; 1166 u32 y = plane_state->view.color_plane[0].y; 1167 u32 plane_ctl, plane_color_ctl = 0; 1168 1169 plane_ctl = plane_state->ctl | 1170 skl_plane_ctl_crtc(crtc_state); 1171 1172 if (DISPLAY_VER(dev_priv) >= 10) 1173 plane_color_ctl = plane_state->color_ctl | 1174 glk_plane_color_ctl_crtc(crtc_state); 1175 1176 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1177 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1178 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1179 1180 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1181 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1182 1183 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1184 skl_plane_aux_dist(plane_state, 0)); 1185 1186 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 1187 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1188 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1189 1190 if (DISPLAY_VER(dev_priv) >= 10) 1191 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1192 1193 /* 1194 * Enable the scaler before the plane so that we don't 1195 * get a catastrophic underrun even if the two operations 1196 * end up happening in two different frames. 1197 * 1198 * TODO: split into noarm+arm pair 1199 */ 1200 if (plane_state->scaler_id >= 0) 1201 skl_program_plane_scaler(plane, crtc_state, plane_state); 1202 1203 /* 1204 * The control register self-arms if the plane was previously 1205 * disabled. Try to make the plane enable atomic by writing 1206 * the control register just before the surface register. 1207 */ 1208 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1209 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1210 skl_plane_surf(plane_state, 0)); 1211 } 1212 1213 static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, 1214 const struct intel_crtc_state *crtc_state, 1215 const struct intel_plane_state *plane_state, 1216 int color_plane) 1217 { 1218 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1219 enum pipe pipe = plane->pipe; 1220 const struct drm_rect *clip; 1221 u32 val; 1222 int x, y; 1223 1224 if (!crtc_state->enable_psr2_sel_fetch) 1225 return; 1226 1227 clip = &plane_state->psr2_sel_fetch_area; 1228 1229 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1230 val |= plane_state->uapi.dst.x1; 1231 intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1232 1233 x = plane_state->view.color_plane[color_plane].x; 1234 1235 /* 1236 * From Bspec: UV surface Start Y Position = half of Y plane Y 1237 * start position. 1238 */ 1239 if (!color_plane) 1240 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1241 else 1242 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1243 1244 val = y << 16 | x; 1245 1246 intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1247 val); 1248 1249 /* Sizes are 0 based */ 1250 val = (drm_rect_height(clip) - 1) << 16; 1251 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1252 intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1253 } 1254 1255 static void 1256 icl_plane_update_noarm(struct intel_plane *plane, 1257 const struct intel_crtc_state *crtc_state, 1258 const struct intel_plane_state *plane_state) 1259 { 1260 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1261 enum plane_id plane_id = plane->id; 1262 enum pipe pipe = plane->pipe; 1263 int color_plane = icl_plane_color_plane(plane_state); 1264 u32 stride = skl_plane_stride(plane_state, color_plane); 1265 const struct drm_framebuffer *fb = plane_state->hw.fb; 1266 int crtc_x = plane_state->uapi.dst.x1; 1267 int crtc_y = plane_state->uapi.dst.y1; 1268 int x = plane_state->view.color_plane[color_plane].x; 1269 int y = plane_state->view.color_plane[color_plane].y; 1270 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1271 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1272 u32 plane_color_ctl; 1273 1274 plane_color_ctl = plane_state->color_ctl | 1275 glk_plane_color_ctl_crtc(crtc_state); 1276 1277 /* The scaler will handle the output position */ 1278 if (plane_state->scaler_id >= 0) { 1279 crtc_x = 0; 1280 crtc_y = 0; 1281 } 1282 1283 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1284 PLANE_STRIDE_(stride)); 1285 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1286 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1287 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1288 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1289 1290 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1291 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1292 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1293 1294 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1295 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1296 1297 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1298 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), 1299 lower_32_bits(plane_state->ccval)); 1300 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), 1301 upper_32_bits(plane_state->ccval)); 1302 } 1303 1304 /* FLAT CCS doesn't need to program AUX_DIST */ 1305 if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) 1306 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1307 skl_plane_aux_dist(plane_state, color_plane)); 1308 1309 if (icl_is_hdr_plane(dev_priv, plane_id)) 1310 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 1311 plane_state->cus_ctl); 1312 1313 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1314 1315 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1316 icl_program_input_csc(plane, crtc_state, plane_state); 1317 1318 skl_write_plane_wm(plane, crtc_state); 1319 1320 /* 1321 * FIXME: pxp session invalidation can hit any time even at time of commit 1322 * or after the commit, display content will be garbage. 1323 */ 1324 if (plane_state->force_black) 1325 icl_plane_csc_load_black(plane); 1326 1327 icl_plane_update_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); 1328 } 1329 1330 static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane, 1331 const struct intel_crtc_state *crtc_state, 1332 const struct intel_plane_state *plane_state) 1333 { 1334 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1335 enum pipe pipe = plane->pipe; 1336 1337 if (!crtc_state->enable_psr2_sel_fetch) 1338 return; 1339 1340 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) 1341 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1342 PLANE_SEL_FETCH_CTL_ENABLE); 1343 else 1344 icl_plane_disable_sel_fetch_arm(plane, crtc_state); 1345 } 1346 1347 static void 1348 icl_plane_update_arm(struct intel_plane *plane, 1349 const struct intel_crtc_state *crtc_state, 1350 const struct intel_plane_state *plane_state) 1351 { 1352 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1353 enum plane_id plane_id = plane->id; 1354 enum pipe pipe = plane->pipe; 1355 int color_plane = icl_plane_color_plane(plane_state); 1356 u32 plane_ctl; 1357 1358 plane_ctl = plane_state->ctl | 1359 skl_plane_ctl_crtc(crtc_state); 1360 1361 /* 1362 * Enable the scaler before the plane so that we don't 1363 * get a catastrophic underrun even if the two operations 1364 * end up happening in two different frames. 1365 * 1366 * TODO: split into noarm+arm pair 1367 */ 1368 if (plane_state->scaler_id >= 0) 1369 skl_program_plane_scaler(plane, crtc_state, plane_state); 1370 1371 icl_plane_update_sel_fetch_arm(plane, crtc_state, plane_state); 1372 1373 /* 1374 * The control register self-arms if the plane was previously 1375 * disabled. Try to make the plane enable atomic by writing 1376 * the control register just before the surface register. 1377 */ 1378 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1379 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1380 skl_plane_surf(plane_state, color_plane)); 1381 } 1382 1383 static void 1384 skl_plane_async_flip(struct intel_plane *plane, 1385 const struct intel_crtc_state *crtc_state, 1386 const struct intel_plane_state *plane_state, 1387 bool async_flip) 1388 { 1389 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1390 enum plane_id plane_id = plane->id; 1391 enum pipe pipe = plane->pipe; 1392 u32 plane_ctl = plane_state->ctl; 1393 1394 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1395 1396 if (async_flip) 1397 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1398 1399 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1400 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1401 skl_plane_surf(plane_state, 0)); 1402 } 1403 1404 static bool intel_format_is_p01x(u32 format) 1405 { 1406 switch (format) { 1407 case DRM_FORMAT_P010: 1408 case DRM_FORMAT_P012: 1409 case DRM_FORMAT_P016: 1410 return true; 1411 default: 1412 return false; 1413 } 1414 } 1415 1416 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1417 const struct intel_plane_state *plane_state) 1418 { 1419 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1420 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1421 const struct drm_framebuffer *fb = plane_state->hw.fb; 1422 unsigned int rotation = plane_state->hw.rotation; 1423 1424 if (!fb) 1425 return 0; 1426 1427 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1428 intel_fb_is_ccs_modifier(fb->modifier)) { 1429 drm_dbg_kms(&dev_priv->drm, 1430 "RC support only with 0/180 degree rotation (%x)\n", 1431 rotation); 1432 return -EINVAL; 1433 } 1434 1435 if (rotation & DRM_MODE_REFLECT_X && 1436 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1437 drm_dbg_kms(&dev_priv->drm, 1438 "horizontal flip is not supported with linear surface formats\n"); 1439 return -EINVAL; 1440 } 1441 1442 if (drm_rotation_90_or_270(rotation)) { 1443 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1444 drm_dbg_kms(&dev_priv->drm, 1445 "Y/Yf tiling required for 90/270!\n"); 1446 return -EINVAL; 1447 } 1448 1449 /* 1450 * 90/270 is not allowed with RGB64 16:16:16:16 and 1451 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1452 */ 1453 switch (fb->format->format) { 1454 case DRM_FORMAT_RGB565: 1455 if (DISPLAY_VER(dev_priv) >= 11) 1456 break; 1457 fallthrough; 1458 case DRM_FORMAT_C8: 1459 case DRM_FORMAT_XRGB16161616F: 1460 case DRM_FORMAT_XBGR16161616F: 1461 case DRM_FORMAT_ARGB16161616F: 1462 case DRM_FORMAT_ABGR16161616F: 1463 case DRM_FORMAT_Y210: 1464 case DRM_FORMAT_Y212: 1465 case DRM_FORMAT_Y216: 1466 case DRM_FORMAT_XVYU12_16161616: 1467 case DRM_FORMAT_XVYU16161616: 1468 drm_dbg_kms(&dev_priv->drm, 1469 "Unsupported pixel format %p4cc for 90/270!\n", 1470 &fb->format->format); 1471 return -EINVAL; 1472 default: 1473 break; 1474 } 1475 } 1476 1477 /* Y-tiling is not supported in IF-ID Interlace mode */ 1478 if (crtc_state->hw.enable && 1479 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1480 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1481 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1482 drm_dbg_kms(&dev_priv->drm, 1483 "Y/Yf tiling not supported in IF-ID mode\n"); 1484 return -EINVAL; 1485 } 1486 1487 /* Wa_1606054188:tgl,adl-s */ 1488 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1489 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1490 intel_format_is_p01x(fb->format->format)) { 1491 drm_dbg_kms(&dev_priv->drm, 1492 "Source color keying not supported with P01x formats\n"); 1493 return -EINVAL; 1494 } 1495 1496 return 0; 1497 } 1498 1499 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1500 const struct intel_plane_state *plane_state) 1501 { 1502 struct drm_i915_private *dev_priv = 1503 to_i915(plane_state->uapi.plane->dev); 1504 int crtc_x = plane_state->uapi.dst.x1; 1505 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1506 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 1507 1508 /* 1509 * Display WA #1175: glk 1510 * Planes other than the cursor may cause FIFO underflow and display 1511 * corruption if starting less than 4 pixels from the right edge of 1512 * the screen. 1513 * Besides the above WA fix the similar problem, where planes other 1514 * than the cursor ending less than 4 pixels from the left edge of the 1515 * screen may cause FIFO underflow and display corruption. 1516 */ 1517 if (DISPLAY_VER(dev_priv) == 10 && 1518 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1519 drm_dbg_kms(&dev_priv->drm, 1520 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1521 crtc_x + crtc_w < 4 ? "end" : "start", 1522 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1523 4, pipe_src_w - 4); 1524 return -ERANGE; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1531 { 1532 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1533 const struct drm_framebuffer *fb = plane_state->hw.fb; 1534 unsigned int rotation = plane_state->hw.rotation; 1535 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1536 1537 /* Display WA #1106 */ 1538 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1539 src_w & 3 && 1540 (rotation == DRM_MODE_ROTATE_270 || 1541 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1542 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1543 return -EINVAL; 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1550 const struct drm_framebuffer *fb) 1551 { 1552 /* 1553 * We don't yet know the final source width nor 1554 * whether we can use the HQ scaler mode. Assume 1555 * the best case. 1556 * FIXME need to properly check this later. 1557 */ 1558 if (DISPLAY_VER(dev_priv) >= 10 || 1559 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1560 return 0x30000 - 1; 1561 else 1562 return 0x20000 - 1; 1563 } 1564 1565 static int intel_plane_min_width(struct intel_plane *plane, 1566 const struct drm_framebuffer *fb, 1567 int color_plane, 1568 unsigned int rotation) 1569 { 1570 if (plane->min_width) 1571 return plane->min_width(fb, color_plane, rotation); 1572 else 1573 return 1; 1574 } 1575 1576 static int intel_plane_max_width(struct intel_plane *plane, 1577 const struct drm_framebuffer *fb, 1578 int color_plane, 1579 unsigned int rotation) 1580 { 1581 if (plane->max_width) 1582 return plane->max_width(fb, color_plane, rotation); 1583 else 1584 return INT_MAX; 1585 } 1586 1587 static int intel_plane_max_height(struct intel_plane *plane, 1588 const struct drm_framebuffer *fb, 1589 int color_plane, 1590 unsigned int rotation) 1591 { 1592 if (plane->max_height) 1593 return plane->max_height(fb, color_plane, rotation); 1594 else 1595 return INT_MAX; 1596 } 1597 1598 static bool 1599 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1600 int main_x, int main_y, u32 main_offset, 1601 int ccs_plane) 1602 { 1603 const struct drm_framebuffer *fb = plane_state->hw.fb; 1604 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1605 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1606 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1607 u32 alignment = intel_surf_alignment(fb, ccs_plane); 1608 int hsub; 1609 int vsub; 1610 1611 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1612 while (aux_offset >= main_offset && aux_y <= main_y) { 1613 int x, y; 1614 1615 if (aux_x == main_x && aux_y == main_y) 1616 break; 1617 1618 if (aux_offset == 0) 1619 break; 1620 1621 x = aux_x / hsub; 1622 y = aux_y / vsub; 1623 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1624 plane_state, 1625 ccs_plane, 1626 aux_offset, 1627 aux_offset - 1628 alignment); 1629 aux_x = x * hsub + aux_x % hsub; 1630 aux_y = y * vsub + aux_y % vsub; 1631 } 1632 1633 if (aux_x != main_x || aux_y != main_y) 1634 return false; 1635 1636 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1637 plane_state->view.color_plane[ccs_plane].x = aux_x; 1638 plane_state->view.color_plane[ccs_plane].y = aux_y; 1639 1640 return true; 1641 } 1642 1643 1644 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1645 int *x, int *y, u32 *offset) 1646 { 1647 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1648 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1649 const struct drm_framebuffer *fb = plane_state->hw.fb; 1650 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1651 const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1652 const u32 alignment = intel_surf_alignment(fb, 0); 1653 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1654 1655 intel_add_fb_offsets(x, y, plane_state, 0); 1656 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1657 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1658 return -EINVAL; 1659 1660 /* 1661 * AUX surface offset is specified as the distance from the 1662 * main surface offset, and it must be non-negative. Make 1663 * sure that is what we will get. 1664 */ 1665 if (aux_plane && *offset > aux_offset) 1666 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1667 *offset, 1668 aux_offset & ~(alignment - 1)); 1669 1670 /* 1671 * When using an X-tiled surface, the plane blows up 1672 * if the x offset + width exceed the stride. 1673 * 1674 * TODO: linear and Y-tiled seem fine, Yf untested, 1675 */ 1676 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1677 int cpp = fb->format->cpp[0]; 1678 1679 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1680 if (*offset == 0) { 1681 drm_dbg_kms(&dev_priv->drm, 1682 "Unable to find suitable display surface offset due to X-tiling\n"); 1683 return -EINVAL; 1684 } 1685 1686 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1687 *offset, 1688 *offset - alignment); 1689 } 1690 } 1691 1692 return 0; 1693 } 1694 1695 static int skl_check_main_surface(struct intel_plane_state *plane_state) 1696 { 1697 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1698 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1699 const struct drm_framebuffer *fb = plane_state->hw.fb; 1700 const unsigned int rotation = plane_state->hw.rotation; 1701 int x = plane_state->uapi.src.x1 >> 16; 1702 int y = plane_state->uapi.src.y1 >> 16; 1703 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1704 const int h = drm_rect_height(&plane_state->uapi.src) >> 16; 1705 const int min_width = intel_plane_min_width(plane, fb, 0, rotation); 1706 const int max_width = intel_plane_max_width(plane, fb, 0, rotation); 1707 const int max_height = intel_plane_max_height(plane, fb, 0, rotation); 1708 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1709 const u32 alignment = intel_surf_alignment(fb, 0); 1710 u32 offset; 1711 int ret; 1712 1713 if (w > max_width || w < min_width || h > max_height || h < 1) { 1714 drm_dbg_kms(&dev_priv->drm, 1715 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1716 w, h, min_width, max_width, max_height); 1717 return -EINVAL; 1718 } 1719 1720 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1721 if (ret) 1722 return ret; 1723 1724 /* 1725 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 1726 * they match with the main surface x/y offsets. On DG2 1727 * there's no aux plane on fb so skip this checking. 1728 */ 1729 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { 1730 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1731 offset, aux_plane)) { 1732 if (offset == 0) 1733 break; 1734 1735 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 1736 offset, offset - alignment); 1737 } 1738 1739 if (x != plane_state->view.color_plane[aux_plane].x || 1740 y != plane_state->view.color_plane[aux_plane].y) { 1741 drm_dbg_kms(&dev_priv->drm, 1742 "Unable to find suitable display surface offset due to CCS\n"); 1743 return -EINVAL; 1744 } 1745 } 1746 1747 if (DISPLAY_VER(dev_priv) >= 13) 1748 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 1749 else 1750 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 1751 1752 plane_state->view.color_plane[0].offset = offset; 1753 plane_state->view.color_plane[0].x = x; 1754 plane_state->view.color_plane[0].y = y; 1755 1756 /* 1757 * Put the final coordinates back so that the src 1758 * coordinate checks will see the right values. 1759 */ 1760 drm_rect_translate_to(&plane_state->uapi.src, 1761 x << 16, y << 16); 1762 1763 return 0; 1764 } 1765 1766 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 1767 { 1768 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1769 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1770 const struct drm_framebuffer *fb = plane_state->hw.fb; 1771 unsigned int rotation = plane_state->hw.rotation; 1772 int uv_plane = 1; 1773 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? 1774 skl_main_to_aux_plane(fb, uv_plane) : 0; 1775 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 1776 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 1777 int x = plane_state->uapi.src.x1 >> 17; 1778 int y = plane_state->uapi.src.y1 >> 17; 1779 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 1780 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 1781 u32 offset; 1782 1783 /* FIXME not quite sure how/if these apply to the chroma plane */ 1784 if (w > max_width || h > max_height) { 1785 drm_dbg_kms(&i915->drm, 1786 "CbCr source size %dx%d too big (limit %dx%d)\n", 1787 w, h, max_width, max_height); 1788 return -EINVAL; 1789 } 1790 1791 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 1792 offset = intel_plane_compute_aligned_offset(&x, &y, 1793 plane_state, uv_plane); 1794 1795 if (ccs_plane) { 1796 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1797 u32 alignment = intel_surf_alignment(fb, uv_plane); 1798 1799 if (offset > aux_offset) 1800 offset = intel_plane_adjust_aligned_offset(&x, &y, 1801 plane_state, 1802 uv_plane, 1803 offset, 1804 aux_offset & ~(alignment - 1)); 1805 1806 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1807 offset, ccs_plane)) { 1808 if (offset == 0) 1809 break; 1810 1811 offset = intel_plane_adjust_aligned_offset(&x, &y, 1812 plane_state, 1813 uv_plane, 1814 offset, offset - alignment); 1815 } 1816 1817 if (x != plane_state->view.color_plane[ccs_plane].x || 1818 y != plane_state->view.color_plane[ccs_plane].y) { 1819 drm_dbg_kms(&i915->drm, 1820 "Unable to find suitable display surface offset due to CCS\n"); 1821 return -EINVAL; 1822 } 1823 } 1824 1825 if (DISPLAY_VER(i915) >= 13) 1826 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 1827 else 1828 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 1829 1830 plane_state->view.color_plane[uv_plane].offset = offset; 1831 plane_state->view.color_plane[uv_plane].x = x; 1832 plane_state->view.color_plane[uv_plane].y = y; 1833 1834 return 0; 1835 } 1836 1837 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 1838 { 1839 const struct drm_framebuffer *fb = plane_state->hw.fb; 1840 int src_x = plane_state->uapi.src.x1 >> 16; 1841 int src_y = plane_state->uapi.src.y1 >> 16; 1842 u32 offset; 1843 int ccs_plane; 1844 1845 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 1846 int main_hsub, main_vsub; 1847 int hsub, vsub; 1848 int x, y; 1849 1850 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1851 continue; 1852 1853 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 1854 skl_ccs_to_main_plane(fb, ccs_plane)); 1855 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1856 1857 hsub *= main_hsub; 1858 vsub *= main_vsub; 1859 x = src_x / hsub; 1860 y = src_y / vsub; 1861 1862 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 1863 1864 offset = intel_plane_compute_aligned_offset(&x, &y, 1865 plane_state, 1866 ccs_plane); 1867 1868 plane_state->view.color_plane[ccs_plane].offset = offset; 1869 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 1870 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 1871 } 1872 1873 return 0; 1874 } 1875 1876 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 1877 { 1878 const struct drm_framebuffer *fb = plane_state->hw.fb; 1879 int ret; 1880 1881 ret = intel_plane_compute_gtt(plane_state); 1882 if (ret) 1883 return ret; 1884 1885 if (!plane_state->uapi.visible) 1886 return 0; 1887 1888 /* 1889 * Handle the AUX surface first since the main surface setup depends on 1890 * it. 1891 */ 1892 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1893 ret = skl_check_ccs_aux_surface(plane_state); 1894 if (ret) 1895 return ret; 1896 } 1897 1898 if (intel_format_info_is_yuv_semiplanar(fb->format, 1899 fb->modifier)) { 1900 ret = skl_check_nv12_aux_surface(plane_state); 1901 if (ret) 1902 return ret; 1903 } 1904 1905 ret = skl_check_main_surface(plane_state); 1906 if (ret) 1907 return ret; 1908 1909 return 0; 1910 } 1911 1912 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 1913 { 1914 if (!fb) 1915 return false; 1916 1917 switch (fb->format->format) { 1918 case DRM_FORMAT_C8: 1919 return false; 1920 case DRM_FORMAT_XRGB16161616F: 1921 case DRM_FORMAT_ARGB16161616F: 1922 case DRM_FORMAT_XBGR16161616F: 1923 case DRM_FORMAT_ABGR16161616F: 1924 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 1925 default: 1926 return true; 1927 } 1928 } 1929 1930 static void check_protection(struct intel_plane_state *plane_state) 1931 { 1932 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1933 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1934 const struct drm_framebuffer *fb = plane_state->hw.fb; 1935 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 1936 1937 if (DISPLAY_VER(i915) < 11) 1938 return; 1939 1940 plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; 1941 plane_state->force_black = i915_gem_object_is_protected(obj) && 1942 !plane_state->decrypt; 1943 } 1944 1945 static int skl_plane_check(struct intel_crtc_state *crtc_state, 1946 struct intel_plane_state *plane_state) 1947 { 1948 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1949 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1950 const struct drm_framebuffer *fb = plane_state->hw.fb; 1951 int min_scale = DRM_PLANE_NO_SCALING; 1952 int max_scale = DRM_PLANE_NO_SCALING; 1953 int ret; 1954 1955 ret = skl_plane_check_fb(crtc_state, plane_state); 1956 if (ret) 1957 return ret; 1958 1959 /* use scaler when colorkey is not required */ 1960 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 1961 min_scale = 1; 1962 max_scale = skl_plane_max_scale(dev_priv, fb); 1963 } 1964 1965 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1966 min_scale, max_scale, true); 1967 if (ret) 1968 return ret; 1969 1970 ret = skl_check_plane_surface(plane_state); 1971 if (ret) 1972 return ret; 1973 1974 if (!plane_state->uapi.visible) 1975 return 0; 1976 1977 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 1978 if (ret) 1979 return ret; 1980 1981 ret = intel_plane_check_src_coordinates(plane_state); 1982 if (ret) 1983 return ret; 1984 1985 ret = skl_plane_check_nv12_rotation(plane_state); 1986 if (ret) 1987 return ret; 1988 1989 check_protection(plane_state); 1990 1991 /* HW only has 8 bits pixel precision, disable plane if invisible */ 1992 if (!(plane_state->hw.alpha >> 8)) 1993 plane_state->uapi.visible = false; 1994 1995 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 1996 1997 if (DISPLAY_VER(dev_priv) >= 10) 1998 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 1999 plane_state); 2000 2001 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2002 icl_is_hdr_plane(dev_priv, plane->id)) 2003 /* Enable and use MPEG-2 chroma siting */ 2004 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2005 PLANE_CUS_HPHASE_0 | 2006 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2007 else 2008 plane_state->cus_ctl = 0; 2009 2010 return 0; 2011 } 2012 2013 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 2014 { 2015 return pipe - PIPE_A + INTEL_FBC_A; 2016 } 2017 2018 static bool skl_plane_has_fbc(struct drm_i915_private *i915, 2019 enum intel_fbc_id fbc_id, enum plane_id plane_id) 2020 { 2021 if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) 2022 return false; 2023 2024 if (DISPLAY_VER(i915) >= 20) 2025 return icl_is_hdr_plane(i915, plane_id); 2026 else 2027 return plane_id == PLANE_PRIMARY; 2028 } 2029 2030 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 2031 enum pipe pipe, enum plane_id plane_id) 2032 { 2033 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 2034 2035 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 2036 return dev_priv->display.fbc[fbc_id]; 2037 else 2038 return NULL; 2039 } 2040 2041 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2042 enum pipe pipe, enum plane_id plane_id) 2043 { 2044 /* Display WA #0870: skl, bxt */ 2045 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 2046 return false; 2047 2048 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 2049 return false; 2050 2051 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 2052 return false; 2053 2054 return true; 2055 } 2056 2057 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 2058 enum pipe pipe, enum plane_id plane_id, 2059 int *num_formats) 2060 { 2061 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2062 *num_formats = ARRAY_SIZE(skl_planar_formats); 2063 return skl_planar_formats; 2064 } else { 2065 *num_formats = ARRAY_SIZE(skl_plane_formats); 2066 return skl_plane_formats; 2067 } 2068 } 2069 2070 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 2071 enum pipe pipe, enum plane_id plane_id, 2072 int *num_formats) 2073 { 2074 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2075 *num_formats = ARRAY_SIZE(glk_planar_formats); 2076 return glk_planar_formats; 2077 } else { 2078 *num_formats = ARRAY_SIZE(skl_plane_formats); 2079 return skl_plane_formats; 2080 } 2081 } 2082 2083 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2084 enum pipe pipe, enum plane_id plane_id, 2085 int *num_formats) 2086 { 2087 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2088 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2089 return icl_hdr_plane_formats; 2090 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 2091 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2092 return icl_sdr_y_plane_formats; 2093 } else { 2094 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2095 return icl_sdr_uv_plane_formats; 2096 } 2097 } 2098 2099 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2100 u32 format, u64 modifier) 2101 { 2102 struct intel_plane *plane = to_intel_plane(_plane); 2103 2104 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2105 return false; 2106 2107 switch (format) { 2108 case DRM_FORMAT_XRGB8888: 2109 case DRM_FORMAT_XBGR8888: 2110 case DRM_FORMAT_ARGB8888: 2111 case DRM_FORMAT_ABGR8888: 2112 if (intel_fb_is_ccs_modifier(modifier)) 2113 return true; 2114 fallthrough; 2115 case DRM_FORMAT_RGB565: 2116 case DRM_FORMAT_XRGB2101010: 2117 case DRM_FORMAT_XBGR2101010: 2118 case DRM_FORMAT_ARGB2101010: 2119 case DRM_FORMAT_ABGR2101010: 2120 case DRM_FORMAT_YUYV: 2121 case DRM_FORMAT_YVYU: 2122 case DRM_FORMAT_UYVY: 2123 case DRM_FORMAT_VYUY: 2124 case DRM_FORMAT_NV12: 2125 case DRM_FORMAT_XYUV8888: 2126 case DRM_FORMAT_P010: 2127 case DRM_FORMAT_P012: 2128 case DRM_FORMAT_P016: 2129 case DRM_FORMAT_XVYU2101010: 2130 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2131 return true; 2132 fallthrough; 2133 case DRM_FORMAT_C8: 2134 case DRM_FORMAT_XBGR16161616F: 2135 case DRM_FORMAT_ABGR16161616F: 2136 case DRM_FORMAT_XRGB16161616F: 2137 case DRM_FORMAT_ARGB16161616F: 2138 case DRM_FORMAT_Y210: 2139 case DRM_FORMAT_Y212: 2140 case DRM_FORMAT_Y216: 2141 case DRM_FORMAT_XVYU12_16161616: 2142 case DRM_FORMAT_XVYU16161616: 2143 if (modifier == DRM_FORMAT_MOD_LINEAR || 2144 modifier == I915_FORMAT_MOD_X_TILED || 2145 modifier == I915_FORMAT_MOD_Y_TILED) 2146 return true; 2147 fallthrough; 2148 default: 2149 return false; 2150 } 2151 } 2152 2153 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2154 u32 format, u64 modifier) 2155 { 2156 struct intel_plane *plane = to_intel_plane(_plane); 2157 2158 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2159 return false; 2160 2161 switch (format) { 2162 case DRM_FORMAT_XRGB8888: 2163 case DRM_FORMAT_XBGR8888: 2164 case DRM_FORMAT_ARGB8888: 2165 case DRM_FORMAT_ABGR8888: 2166 if (intel_fb_is_ccs_modifier(modifier)) 2167 return true; 2168 fallthrough; 2169 case DRM_FORMAT_YUYV: 2170 case DRM_FORMAT_YVYU: 2171 case DRM_FORMAT_UYVY: 2172 case DRM_FORMAT_VYUY: 2173 case DRM_FORMAT_NV12: 2174 case DRM_FORMAT_XYUV8888: 2175 case DRM_FORMAT_P010: 2176 case DRM_FORMAT_P012: 2177 case DRM_FORMAT_P016: 2178 if (intel_fb_is_mc_ccs_modifier(modifier)) 2179 return true; 2180 fallthrough; 2181 case DRM_FORMAT_RGB565: 2182 case DRM_FORMAT_XRGB2101010: 2183 case DRM_FORMAT_XBGR2101010: 2184 case DRM_FORMAT_ARGB2101010: 2185 case DRM_FORMAT_ABGR2101010: 2186 case DRM_FORMAT_XVYU2101010: 2187 case DRM_FORMAT_C8: 2188 case DRM_FORMAT_XBGR16161616F: 2189 case DRM_FORMAT_ABGR16161616F: 2190 case DRM_FORMAT_XRGB16161616F: 2191 case DRM_FORMAT_ARGB16161616F: 2192 case DRM_FORMAT_Y210: 2193 case DRM_FORMAT_Y212: 2194 case DRM_FORMAT_Y216: 2195 case DRM_FORMAT_XVYU12_16161616: 2196 case DRM_FORMAT_XVYU16161616: 2197 if (!intel_fb_is_ccs_modifier(modifier)) 2198 return true; 2199 fallthrough; 2200 default: 2201 return false; 2202 } 2203 } 2204 2205 static const struct drm_plane_funcs skl_plane_funcs = { 2206 .update_plane = drm_atomic_helper_update_plane, 2207 .disable_plane = drm_atomic_helper_disable_plane, 2208 .destroy = intel_plane_destroy, 2209 .atomic_duplicate_state = intel_plane_duplicate_state, 2210 .atomic_destroy_state = intel_plane_destroy_state, 2211 .format_mod_supported = skl_plane_format_mod_supported, 2212 }; 2213 2214 static const struct drm_plane_funcs gen12_plane_funcs = { 2215 .update_plane = drm_atomic_helper_update_plane, 2216 .disable_plane = drm_atomic_helper_disable_plane, 2217 .destroy = intel_plane_destroy, 2218 .atomic_duplicate_state = intel_plane_duplicate_state, 2219 .atomic_destroy_state = intel_plane_destroy_state, 2220 .format_mod_supported = gen12_plane_format_mod_supported, 2221 }; 2222 2223 static void 2224 skl_plane_enable_flip_done(struct intel_plane *plane) 2225 { 2226 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2227 enum pipe pipe = plane->pipe; 2228 2229 spin_lock_irq(&i915->irq_lock); 2230 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2231 spin_unlock_irq(&i915->irq_lock); 2232 } 2233 2234 static void 2235 skl_plane_disable_flip_done(struct intel_plane *plane) 2236 { 2237 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2238 enum pipe pipe = plane->pipe; 2239 2240 spin_lock_irq(&i915->irq_lock); 2241 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2242 spin_unlock_irq(&i915->irq_lock); 2243 } 2244 2245 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2246 enum pipe pipe, enum plane_id plane_id) 2247 { 2248 /* Wa_22011186057 */ 2249 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2250 return false; 2251 2252 if (DISPLAY_VER(i915) >= 11) 2253 return true; 2254 2255 if (IS_GEMINILAKE(i915)) 2256 return pipe != PIPE_C; 2257 2258 return pipe != PIPE_C && 2259 (plane_id == PLANE_PRIMARY || 2260 plane_id == PLANE_SPRITE0); 2261 } 2262 2263 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 2264 enum plane_id plane_id) 2265 { 2266 if (DISPLAY_VER(i915) < 12) 2267 return false; 2268 2269 /* Wa_14010477008 */ 2270 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2271 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) 2272 return false; 2273 2274 /* Wa_22011186057 */ 2275 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2276 return false; 2277 2278 return plane_id < PLANE_SPRITE4; 2279 } 2280 2281 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2282 enum pipe pipe, enum plane_id plane_id) 2283 { 2284 u8 caps = INTEL_PLANE_CAP_TILING_X; 2285 2286 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2287 caps |= INTEL_PLANE_CAP_TILING_Y; 2288 if (DISPLAY_VER(i915) < 12) 2289 caps |= INTEL_PLANE_CAP_TILING_Yf; 2290 if (HAS_4TILE(i915)) 2291 caps |= INTEL_PLANE_CAP_TILING_4; 2292 2293 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2294 caps |= INTEL_PLANE_CAP_CCS_RC; 2295 if (DISPLAY_VER(i915) >= 12) 2296 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2297 } 2298 2299 if (gen12_plane_has_mc_ccs(i915, plane_id)) 2300 caps |= INTEL_PLANE_CAP_CCS_MC; 2301 2302 return caps; 2303 } 2304 2305 struct intel_plane * 2306 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2307 enum pipe pipe, enum plane_id plane_id) 2308 { 2309 const struct drm_plane_funcs *plane_funcs; 2310 struct intel_plane *plane; 2311 enum drm_plane_type plane_type; 2312 unsigned int supported_rotations; 2313 unsigned int supported_csc; 2314 const u64 *modifiers; 2315 const u32 *formats; 2316 int num_formats; 2317 int ret; 2318 2319 plane = intel_plane_alloc(); 2320 if (IS_ERR(plane)) 2321 return plane; 2322 2323 plane->pipe = pipe; 2324 plane->id = plane_id; 2325 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2326 2327 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2328 2329 if (DISPLAY_VER(dev_priv) >= 11) { 2330 plane->min_width = icl_plane_min_width; 2331 if (icl_is_hdr_plane(dev_priv, plane_id)) 2332 plane->max_width = icl_hdr_plane_max_width; 2333 else 2334 plane->max_width = icl_sdr_plane_max_width; 2335 plane->max_height = icl_plane_max_height; 2336 plane->min_cdclk = icl_plane_min_cdclk; 2337 } else if (DISPLAY_VER(dev_priv) >= 10) { 2338 plane->max_width = glk_plane_max_width; 2339 plane->max_height = skl_plane_max_height; 2340 plane->min_cdclk = glk_plane_min_cdclk; 2341 } else { 2342 plane->max_width = skl_plane_max_width; 2343 plane->max_height = skl_plane_max_height; 2344 plane->min_cdclk = skl_plane_min_cdclk; 2345 } 2346 2347 plane->max_stride = skl_plane_max_stride; 2348 if (DISPLAY_VER(dev_priv) >= 11) { 2349 plane->update_noarm = icl_plane_update_noarm; 2350 plane->update_arm = icl_plane_update_arm; 2351 plane->disable_arm = icl_plane_disable_arm; 2352 } else { 2353 plane->update_noarm = skl_plane_update_noarm; 2354 plane->update_arm = skl_plane_update_arm; 2355 plane->disable_arm = skl_plane_disable_arm; 2356 } 2357 plane->get_hw_state = skl_plane_get_hw_state; 2358 plane->check_plane = skl_plane_check; 2359 2360 if (plane_id == PLANE_PRIMARY) { 2361 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv, 2362 9, 10); 2363 plane->async_flip = skl_plane_async_flip; 2364 plane->enable_flip_done = skl_plane_enable_flip_done; 2365 plane->disable_flip_done = skl_plane_disable_flip_done; 2366 } 2367 2368 if (DISPLAY_VER(dev_priv) >= 11) 2369 formats = icl_get_plane_formats(dev_priv, pipe, 2370 plane_id, &num_formats); 2371 else if (DISPLAY_VER(dev_priv) >= 10) 2372 formats = glk_get_plane_formats(dev_priv, pipe, 2373 plane_id, &num_formats); 2374 else 2375 formats = skl_get_plane_formats(dev_priv, pipe, 2376 plane_id, &num_formats); 2377 2378 if (DISPLAY_VER(dev_priv) >= 12) 2379 plane_funcs = &gen12_plane_funcs; 2380 else 2381 plane_funcs = &skl_plane_funcs; 2382 2383 if (plane_id == PLANE_PRIMARY) 2384 plane_type = DRM_PLANE_TYPE_PRIMARY; 2385 else 2386 plane_type = DRM_PLANE_TYPE_OVERLAY; 2387 2388 modifiers = intel_fb_plane_get_modifiers(dev_priv, 2389 skl_get_plane_caps(dev_priv, pipe, plane_id)); 2390 2391 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2392 0, plane_funcs, 2393 formats, num_formats, modifiers, 2394 plane_type, 2395 "plane %d%c", plane_id + 1, 2396 pipe_name(pipe)); 2397 2398 kfree(modifiers); 2399 2400 if (ret) 2401 goto fail; 2402 2403 if (DISPLAY_VER(dev_priv) >= 13) 2404 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2405 else 2406 supported_rotations = 2407 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2408 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2409 2410 if (DISPLAY_VER(dev_priv) >= 11) 2411 supported_rotations |= DRM_MODE_REFLECT_X; 2412 2413 drm_plane_create_rotation_property(&plane->base, 2414 DRM_MODE_ROTATE_0, 2415 supported_rotations); 2416 2417 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2418 2419 if (DISPLAY_VER(dev_priv) >= 10) 2420 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2421 2422 drm_plane_create_color_properties(&plane->base, 2423 supported_csc, 2424 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2425 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2426 DRM_COLOR_YCBCR_BT709, 2427 DRM_COLOR_YCBCR_LIMITED_RANGE); 2428 2429 drm_plane_create_alpha_property(&plane->base); 2430 drm_plane_create_blend_mode_property(&plane->base, 2431 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2432 BIT(DRM_MODE_BLEND_PREMULTI) | 2433 BIT(DRM_MODE_BLEND_COVERAGE)); 2434 2435 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2436 2437 if (DISPLAY_VER(dev_priv) >= 12) 2438 drm_plane_enable_fb_damage_clips(&plane->base); 2439 2440 if (DISPLAY_VER(dev_priv) >= 11) 2441 drm_plane_create_scaling_filter_property(&plane->base, 2442 BIT(DRM_SCALING_FILTER_DEFAULT) | 2443 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2444 2445 intel_plane_helper_add(plane); 2446 2447 return plane; 2448 2449 fail: 2450 intel_plane_free(plane); 2451 2452 return ERR_PTR(ret); 2453 } 2454 2455 void 2456 skl_get_initial_plane_config(struct intel_crtc *crtc, 2457 struct intel_initial_plane_config *plane_config) 2458 { 2459 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2460 struct drm_device *dev = crtc->base.dev; 2461 struct drm_i915_private *dev_priv = to_i915(dev); 2462 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2463 enum plane_id plane_id = plane->id; 2464 enum pipe pipe; 2465 u32 val, base, offset, stride_mult, tiling, alpha; 2466 int fourcc, pixel_format; 2467 unsigned int aligned_height; 2468 struct drm_framebuffer *fb; 2469 struct intel_framebuffer *intel_fb; 2470 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); 2471 2472 if (!plane->get_hw_state(plane, &pipe)) 2473 return; 2474 2475 drm_WARN_ON(dev, pipe != crtc->pipe); 2476 2477 if (crtc_state->bigjoiner_pipes) { 2478 drm_dbg_kms(&dev_priv->drm, 2479 "Unsupported bigjoiner configuration for initial FB\n"); 2480 return; 2481 } 2482 2483 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2484 if (!intel_fb) { 2485 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2486 return; 2487 } 2488 2489 fb = &intel_fb->base; 2490 2491 fb->dev = dev; 2492 2493 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2494 2495 if (DISPLAY_VER(dev_priv) >= 11) 2496 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2497 else 2498 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2499 2500 if (DISPLAY_VER(dev_priv) >= 10) { 2501 u32 color_ctl; 2502 2503 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2504 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2505 } else { 2506 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2507 } 2508 2509 fourcc = skl_format_to_fourcc(pixel_format, 2510 val & PLANE_CTL_ORDER_RGBX, alpha); 2511 fb->format = drm_format_info(fourcc); 2512 2513 tiling = val & PLANE_CTL_TILED_MASK; 2514 switch (tiling) { 2515 case PLANE_CTL_TILED_LINEAR: 2516 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2517 break; 2518 case PLANE_CTL_TILED_X: 2519 plane_config->tiling = I915_TILING_X; 2520 fb->modifier = I915_FORMAT_MOD_X_TILED; 2521 break; 2522 case PLANE_CTL_TILED_Y: 2523 plane_config->tiling = I915_TILING_Y; 2524 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2525 if (DISPLAY_VER(dev_priv) >= 14) 2526 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; 2527 else if (DISPLAY_VER(dev_priv) >= 12) 2528 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; 2529 else 2530 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; 2531 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2532 if (DISPLAY_VER(dev_priv) >= 14) 2533 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; 2534 else 2535 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2536 else 2537 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2538 break; 2539 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2540 if (HAS_4TILE(dev_priv)) { 2541 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2542 PLANE_CTL_CLEAR_COLOR_DISABLE; 2543 2544 if ((val & rc_mask) == rc_mask) 2545 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; 2546 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2547 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; 2548 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2549 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; 2550 else 2551 fb->modifier = I915_FORMAT_MOD_4_TILED; 2552 } else { 2553 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2554 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2555 else 2556 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2557 } 2558 break; 2559 default: 2560 MISSING_CASE(tiling); 2561 goto error; 2562 } 2563 2564 if (!dev_priv->display.params.enable_dpt && 2565 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { 2566 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); 2567 goto error; 2568 } 2569 2570 /* 2571 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 2572 * while i915 HW rotation is clockwise, thats why this swapping. 2573 */ 2574 switch (val & PLANE_CTL_ROTATE_MASK) { 2575 case PLANE_CTL_ROTATE_0: 2576 plane_config->rotation = DRM_MODE_ROTATE_0; 2577 break; 2578 case PLANE_CTL_ROTATE_90: 2579 plane_config->rotation = DRM_MODE_ROTATE_270; 2580 break; 2581 case PLANE_CTL_ROTATE_180: 2582 plane_config->rotation = DRM_MODE_ROTATE_180; 2583 break; 2584 case PLANE_CTL_ROTATE_270: 2585 plane_config->rotation = DRM_MODE_ROTATE_90; 2586 break; 2587 } 2588 2589 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 2590 plane_config->rotation |= DRM_MODE_REFLECT_X; 2591 2592 /* 90/270 degree rotation would require extra work */ 2593 if (drm_rotation_90_or_270(plane_config->rotation)) 2594 goto error; 2595 2596 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 2597 plane_config->base = base; 2598 2599 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 2600 drm_WARN_ON(&dev_priv->drm, offset != 0); 2601 2602 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 2603 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 2604 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 2605 2606 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 2607 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 2608 2609 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 2610 2611 aligned_height = intel_fb_align_height(fb, 0, fb->height); 2612 2613 plane_config->size = fb->pitches[0] * aligned_height; 2614 2615 drm_dbg_kms(&dev_priv->drm, 2616 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 2617 crtc->base.name, plane->base.name, fb->width, fb->height, 2618 fb->format->cpp[0] * 8, base, fb->pitches[0], 2619 plane_config->size); 2620 2621 plane_config->fb = intel_fb; 2622 return; 2623 2624 error: 2625 kfree(intel_fb); 2626 } 2627