1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_blend.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_reg.h" 12 #include "i9xx_plane.h" 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_types.h" 18 #include "intel_fb.h" 19 #include "intel_fbc.h" 20 #include "intel_frontbuffer.h" 21 #include "intel_sprite.h" 22 23 /* Primary plane formats for gen <= 3 */ 24 static const u32 i8xx_primary_formats[] = { 25 DRM_FORMAT_C8, 26 DRM_FORMAT_XRGB1555, 27 DRM_FORMAT_RGB565, 28 DRM_FORMAT_XRGB8888, 29 }; 30 31 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 32 static const u32 ivb_primary_formats[] = { 33 DRM_FORMAT_C8, 34 DRM_FORMAT_RGB565, 35 DRM_FORMAT_XRGB8888, 36 DRM_FORMAT_XBGR8888, 37 DRM_FORMAT_XRGB2101010, 38 DRM_FORMAT_XBGR2101010, 39 }; 40 41 /* Primary plane formats for gen >= 4, except ivb */ 42 static const u32 i965_primary_formats[] = { 43 DRM_FORMAT_C8, 44 DRM_FORMAT_RGB565, 45 DRM_FORMAT_XRGB8888, 46 DRM_FORMAT_XBGR8888, 47 DRM_FORMAT_XRGB2101010, 48 DRM_FORMAT_XBGR2101010, 49 DRM_FORMAT_XBGR16161616F, 50 }; 51 52 /* Primary plane formats for vlv/chv */ 53 static const u32 vlv_primary_formats[] = { 54 DRM_FORMAT_C8, 55 DRM_FORMAT_RGB565, 56 DRM_FORMAT_XRGB8888, 57 DRM_FORMAT_XBGR8888, 58 DRM_FORMAT_ARGB8888, 59 DRM_FORMAT_ABGR8888, 60 DRM_FORMAT_XRGB2101010, 61 DRM_FORMAT_XBGR2101010, 62 DRM_FORMAT_ARGB2101010, 63 DRM_FORMAT_ABGR2101010, 64 DRM_FORMAT_XBGR16161616F, 65 }; 66 67 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 68 u32 format, u64 modifier) 69 { 70 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 71 return false; 72 73 switch (format) { 74 case DRM_FORMAT_C8: 75 case DRM_FORMAT_RGB565: 76 case DRM_FORMAT_XRGB1555: 77 case DRM_FORMAT_XRGB8888: 78 return modifier == DRM_FORMAT_MOD_LINEAR || 79 modifier == I915_FORMAT_MOD_X_TILED; 80 default: 81 return false; 82 } 83 } 84 85 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 86 u32 format, u64 modifier) 87 { 88 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 89 return false; 90 91 switch (format) { 92 case DRM_FORMAT_C8: 93 case DRM_FORMAT_RGB565: 94 case DRM_FORMAT_XRGB8888: 95 case DRM_FORMAT_XBGR8888: 96 case DRM_FORMAT_ARGB8888: 97 case DRM_FORMAT_ABGR8888: 98 case DRM_FORMAT_XRGB2101010: 99 case DRM_FORMAT_XBGR2101010: 100 case DRM_FORMAT_ARGB2101010: 101 case DRM_FORMAT_ABGR2101010: 102 case DRM_FORMAT_XBGR16161616F: 103 return modifier == DRM_FORMAT_MOD_LINEAR || 104 modifier == I915_FORMAT_MOD_X_TILED; 105 default: 106 return false; 107 } 108 } 109 110 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 111 enum i9xx_plane_id i9xx_plane) 112 { 113 if (!HAS_FBC(dev_priv)) 114 return false; 115 116 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 117 return i9xx_plane == PLANE_A; /* tied to pipe A */ 118 else if (IS_IVYBRIDGE(dev_priv)) 119 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 120 i9xx_plane == PLANE_C; 121 else if (DISPLAY_VER(dev_priv) >= 4) 122 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 123 else 124 return i9xx_plane == PLANE_A; 125 } 126 127 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, 128 enum i9xx_plane_id i9xx_plane) 129 { 130 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) 131 return dev_priv->display.fbc[INTEL_FBC_A]; 132 else 133 return NULL; 134 } 135 136 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 137 { 138 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 139 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 140 141 if (IS_CHERRYVIEW(dev_priv)) 142 return i9xx_plane == PLANE_B; 143 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 144 return false; 145 else if (DISPLAY_VER(dev_priv) == 4) 146 return i9xx_plane == PLANE_C; 147 else 148 return i9xx_plane == PLANE_B || 149 i9xx_plane == PLANE_C; 150 } 151 152 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 153 const struct intel_plane_state *plane_state) 154 { 155 struct drm_i915_private *dev_priv = 156 to_i915(plane_state->uapi.plane->dev); 157 const struct drm_framebuffer *fb = plane_state->hw.fb; 158 unsigned int rotation = plane_state->hw.rotation; 159 u32 dspcntr; 160 161 dspcntr = DISP_ENABLE; 162 163 if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || 164 IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 165 dspcntr |= DISP_TRICKLE_FEED_DISABLE; 166 167 switch (fb->format->format) { 168 case DRM_FORMAT_C8: 169 dspcntr |= DISP_FORMAT_8BPP; 170 break; 171 case DRM_FORMAT_XRGB1555: 172 dspcntr |= DISP_FORMAT_BGRX555; 173 break; 174 case DRM_FORMAT_ARGB1555: 175 dspcntr |= DISP_FORMAT_BGRA555; 176 break; 177 case DRM_FORMAT_RGB565: 178 dspcntr |= DISP_FORMAT_BGRX565; 179 break; 180 case DRM_FORMAT_XRGB8888: 181 dspcntr |= DISP_FORMAT_BGRX888; 182 break; 183 case DRM_FORMAT_XBGR8888: 184 dspcntr |= DISP_FORMAT_RGBX888; 185 break; 186 case DRM_FORMAT_ARGB8888: 187 dspcntr |= DISP_FORMAT_BGRA888; 188 break; 189 case DRM_FORMAT_ABGR8888: 190 dspcntr |= DISP_FORMAT_RGBA888; 191 break; 192 case DRM_FORMAT_XRGB2101010: 193 dspcntr |= DISP_FORMAT_BGRX101010; 194 break; 195 case DRM_FORMAT_XBGR2101010: 196 dspcntr |= DISP_FORMAT_RGBX101010; 197 break; 198 case DRM_FORMAT_ARGB2101010: 199 dspcntr |= DISP_FORMAT_BGRA101010; 200 break; 201 case DRM_FORMAT_ABGR2101010: 202 dspcntr |= DISP_FORMAT_RGBA101010; 203 break; 204 case DRM_FORMAT_XBGR16161616F: 205 dspcntr |= DISP_FORMAT_RGBX161616; 206 break; 207 default: 208 MISSING_CASE(fb->format->format); 209 return 0; 210 } 211 212 if (DISPLAY_VER(dev_priv) >= 4 && 213 fb->modifier == I915_FORMAT_MOD_X_TILED) 214 dspcntr |= DISP_TILED; 215 216 if (rotation & DRM_MODE_ROTATE_180) 217 dspcntr |= DISP_ROTATE_180; 218 219 if (rotation & DRM_MODE_REFLECT_X) 220 dspcntr |= DISP_MIRROR; 221 222 return dspcntr; 223 } 224 225 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 226 { 227 struct drm_i915_private *dev_priv = 228 to_i915(plane_state->uapi.plane->dev); 229 const struct drm_framebuffer *fb = plane_state->hw.fb; 230 int src_x, src_y, src_w; 231 u32 offset; 232 int ret; 233 234 ret = intel_plane_compute_gtt(plane_state); 235 if (ret) 236 return ret; 237 238 if (!plane_state->uapi.visible) 239 return 0; 240 241 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 242 src_x = plane_state->uapi.src.x1 >> 16; 243 src_y = plane_state->uapi.src.y1 >> 16; 244 245 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 246 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 247 return -EINVAL; 248 249 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 250 251 if (DISPLAY_VER(dev_priv) >= 4) 252 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 253 plane_state, 0); 254 else 255 offset = 0; 256 257 /* 258 * When using an X-tiled surface the plane starts to 259 * misbehave if the x offset + width exceeds the stride. 260 * hsw/bdw: underrun galore 261 * ilk/snb/ivb: wrap to the next tile row mid scanout 262 * i965/g4x: so far appear immune to this 263 * vlv/chv: TODO check 264 * 265 * Linear surfaces seem to work just fine, even on hsw/bdw 266 * despite them not using the linear offset anymore. 267 */ 268 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { 269 u32 alignment = intel_surf_alignment(fb, 0); 270 int cpp = fb->format->cpp[0]; 271 272 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 273 if (offset == 0) { 274 drm_dbg_kms(&dev_priv->drm, 275 "Unable to find suitable display surface offset due to X-tiling\n"); 276 return -EINVAL; 277 } 278 279 offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, 280 offset, offset - alignment); 281 } 282 } 283 284 /* 285 * Put the final coordinates back so that the src 286 * coordinate checks will see the right values. 287 */ 288 drm_rect_translate_to(&plane_state->uapi.src, 289 src_x << 16, src_y << 16); 290 291 /* HSW/BDW do this automagically in hardware */ 292 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 293 unsigned int rotation = plane_state->hw.rotation; 294 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 295 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 296 297 if (rotation & DRM_MODE_ROTATE_180) { 298 src_x += src_w - 1; 299 src_y += src_h - 1; 300 } else if (rotation & DRM_MODE_REFLECT_X) { 301 src_x += src_w - 1; 302 } 303 } 304 305 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 306 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); 307 } else if (DISPLAY_VER(dev_priv) >= 4 && 308 fb->modifier == I915_FORMAT_MOD_X_TILED) { 309 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); 310 } 311 312 plane_state->view.color_plane[0].offset = offset; 313 plane_state->view.color_plane[0].x = src_x; 314 plane_state->view.color_plane[0].y = src_y; 315 316 return 0; 317 } 318 319 static int 320 i9xx_plane_check(struct intel_crtc_state *crtc_state, 321 struct intel_plane_state *plane_state) 322 { 323 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 324 int ret; 325 326 ret = chv_plane_check_rotation(plane_state); 327 if (ret) 328 return ret; 329 330 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 331 DRM_PLANE_NO_SCALING, 332 DRM_PLANE_NO_SCALING, 333 i9xx_plane_has_windowing(plane)); 334 if (ret) 335 return ret; 336 337 ret = i9xx_check_plane_surface(plane_state); 338 if (ret) 339 return ret; 340 341 if (!plane_state->uapi.visible) 342 return 0; 343 344 ret = intel_plane_check_src_coordinates(plane_state); 345 if (ret) 346 return ret; 347 348 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 349 350 return 0; 351 } 352 353 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 354 { 355 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 356 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 357 u32 dspcntr = 0; 358 359 if (crtc_state->gamma_enable) 360 dspcntr |= DISP_PIPE_GAMMA_ENABLE; 361 362 if (crtc_state->csc_enable) 363 dspcntr |= DISP_PIPE_CSC_ENABLE; 364 365 if (DISPLAY_VER(dev_priv) < 5) 366 dspcntr |= DISP_PIPE_SEL(crtc->pipe); 367 368 return dspcntr; 369 } 370 371 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 372 const struct intel_plane_state *plane_state, 373 unsigned int *num, unsigned int *den) 374 { 375 const struct drm_framebuffer *fb = plane_state->hw.fb; 376 unsigned int cpp = fb->format->cpp[0]; 377 378 /* 379 * g4x bspec says 64bpp pixel rate can't exceed 80% 380 * of cdclk when the sprite plane is enabled on the 381 * same pipe. ilk/snb bspec says 64bpp pixel rate is 382 * never allowed to exceed 80% of cdclk. Let's just go 383 * with the ilk/snb limit always. 384 */ 385 if (cpp == 8) { 386 *num = 10; 387 *den = 8; 388 } else { 389 *num = 1; 390 *den = 1; 391 } 392 } 393 394 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 395 const struct intel_plane_state *plane_state) 396 { 397 unsigned int pixel_rate; 398 unsigned int num, den; 399 400 /* 401 * Note that crtc_state->pixel_rate accounts for both 402 * horizontal and vertical panel fitter downscaling factors. 403 * Pre-HSW bspec tells us to only consider the horizontal 404 * downscaling factor here. We ignore that and just consider 405 * both for simplicity. 406 */ 407 pixel_rate = crtc_state->pixel_rate; 408 409 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 410 411 /* two pixels per clock with double wide pipe */ 412 if (crtc_state->double_wide) 413 den *= 2; 414 415 return DIV_ROUND_UP(pixel_rate * num, den); 416 } 417 418 static void i9xx_plane_update_noarm(struct intel_plane *plane, 419 const struct intel_crtc_state *crtc_state, 420 const struct intel_plane_state *plane_state) 421 { 422 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 423 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 424 425 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), 426 plane_state->view.color_plane[0].mapping_stride); 427 428 if (DISPLAY_VER(dev_priv) < 4) { 429 int crtc_x = plane_state->uapi.dst.x1; 430 int crtc_y = plane_state->uapi.dst.y1; 431 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 432 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 433 434 /* 435 * PLANE_A doesn't actually have a full window 436 * generator but let's assume we still need to 437 * program whatever is there. 438 */ 439 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), 440 DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); 441 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), 442 DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); 443 } 444 } 445 446 static void i9xx_plane_update_arm(struct intel_plane *plane, 447 const struct intel_crtc_state *crtc_state, 448 const struct intel_plane_state *plane_state) 449 { 450 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 451 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 452 int x = plane_state->view.color_plane[0].x; 453 int y = plane_state->view.color_plane[0].y; 454 u32 dspcntr, dspaddr_offset, linear_offset; 455 456 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 457 458 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 459 460 if (DISPLAY_VER(dev_priv) >= 4) 461 dspaddr_offset = plane_state->view.color_plane[0].offset; 462 else 463 dspaddr_offset = linear_offset; 464 465 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 466 int crtc_x = plane_state->uapi.dst.x1; 467 int crtc_y = plane_state->uapi.dst.y1; 468 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 469 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 470 471 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), 472 PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); 473 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), 474 PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); 475 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); 476 } 477 478 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 479 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), 480 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 481 } else if (DISPLAY_VER(dev_priv) >= 4) { 482 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), 483 linear_offset); 484 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), 485 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 486 } 487 488 /* 489 * The control register self-arms if the plane was previously 490 * disabled. Try to make the plane enable atomic by writing 491 * the control register just before the surface register. 492 */ 493 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 494 495 if (DISPLAY_VER(dev_priv) >= 4) 496 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 497 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 498 else 499 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 500 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 501 } 502 503 static void i830_plane_update_arm(struct intel_plane *plane, 504 const struct intel_crtc_state *crtc_state, 505 const struct intel_plane_state *plane_state) 506 { 507 /* 508 * On i830/i845 all registers are self-arming [ALM040]. 509 * 510 * Additional breakage on i830 causes register reads to return 511 * the last latched value instead of the last written value [ALM026]. 512 */ 513 i9xx_plane_update_noarm(plane, crtc_state, plane_state); 514 i9xx_plane_update_arm(plane, crtc_state, plane_state); 515 } 516 517 static void i9xx_plane_disable_arm(struct intel_plane *plane, 518 const struct intel_crtc_state *crtc_state) 519 { 520 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 521 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 522 u32 dspcntr; 523 524 /* 525 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 526 * enable on ilk+ affect the pipe bottom color as 527 * well, so we must configure them even if the plane 528 * is disabled. 529 * 530 * On pre-g4x there is no way to gamma correct the 531 * pipe bottom color but we'll keep on doing this 532 * anyway so that the crtc state readout works correctly. 533 */ 534 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 535 536 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 537 538 if (DISPLAY_VER(dev_priv) >= 4) 539 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); 540 else 541 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); 542 } 543 544 static void 545 g4x_primary_async_flip(struct intel_plane *plane, 546 const struct intel_crtc_state *crtc_state, 547 const struct intel_plane_state *plane_state, 548 bool async_flip) 549 { 550 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 551 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 552 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 553 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 554 555 if (async_flip) 556 dspcntr |= DISP_ASYNC_FLIP; 557 558 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); 559 560 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 561 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 562 } 563 564 static void 565 vlv_primary_async_flip(struct intel_plane *plane, 566 const struct intel_crtc_state *crtc_state, 567 const struct intel_plane_state *plane_state, 568 bool async_flip) 569 { 570 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 571 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 572 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 573 574 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), 575 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 576 } 577 578 static void 579 bdw_primary_enable_flip_done(struct intel_plane *plane) 580 { 581 struct drm_i915_private *i915 = to_i915(plane->base.dev); 582 enum pipe pipe = plane->pipe; 583 584 spin_lock_irq(&i915->irq_lock); 585 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 586 spin_unlock_irq(&i915->irq_lock); 587 } 588 589 static void 590 bdw_primary_disable_flip_done(struct intel_plane *plane) 591 { 592 struct drm_i915_private *i915 = to_i915(plane->base.dev); 593 enum pipe pipe = plane->pipe; 594 595 spin_lock_irq(&i915->irq_lock); 596 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 597 spin_unlock_irq(&i915->irq_lock); 598 } 599 600 static void 601 ivb_primary_enable_flip_done(struct intel_plane *plane) 602 { 603 struct drm_i915_private *i915 = to_i915(plane->base.dev); 604 605 spin_lock_irq(&i915->irq_lock); 606 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 607 spin_unlock_irq(&i915->irq_lock); 608 } 609 610 static void 611 ivb_primary_disable_flip_done(struct intel_plane *plane) 612 { 613 struct drm_i915_private *i915 = to_i915(plane->base.dev); 614 615 spin_lock_irq(&i915->irq_lock); 616 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 617 spin_unlock_irq(&i915->irq_lock); 618 } 619 620 static void 621 ilk_primary_enable_flip_done(struct intel_plane *plane) 622 { 623 struct drm_i915_private *i915 = to_i915(plane->base.dev); 624 625 spin_lock_irq(&i915->irq_lock); 626 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 627 spin_unlock_irq(&i915->irq_lock); 628 } 629 630 static void 631 ilk_primary_disable_flip_done(struct intel_plane *plane) 632 { 633 struct drm_i915_private *i915 = to_i915(plane->base.dev); 634 635 spin_lock_irq(&i915->irq_lock); 636 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 637 spin_unlock_irq(&i915->irq_lock); 638 } 639 640 static void 641 vlv_primary_enable_flip_done(struct intel_plane *plane) 642 { 643 struct drm_i915_private *i915 = to_i915(plane->base.dev); 644 enum pipe pipe = plane->pipe; 645 646 spin_lock_irq(&i915->irq_lock); 647 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 648 spin_unlock_irq(&i915->irq_lock); 649 } 650 651 static void 652 vlv_primary_disable_flip_done(struct intel_plane *plane) 653 { 654 struct drm_i915_private *i915 = to_i915(plane->base.dev); 655 enum pipe pipe = plane->pipe; 656 657 spin_lock_irq(&i915->irq_lock); 658 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 659 spin_unlock_irq(&i915->irq_lock); 660 } 661 662 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 663 enum pipe *pipe) 664 { 665 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 666 enum intel_display_power_domain power_domain; 667 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 668 intel_wakeref_t wakeref; 669 bool ret; 670 u32 val; 671 672 /* 673 * Not 100% correct for planes that can move between pipes, 674 * but that's only the case for gen2-4 which don't have any 675 * display power wells. 676 */ 677 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 678 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 679 if (!wakeref) 680 return false; 681 682 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 683 684 ret = val & DISP_ENABLE; 685 686 if (DISPLAY_VER(dev_priv) >= 5) 687 *pipe = plane->pipe; 688 else 689 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); 690 691 intel_display_power_put(dev_priv, power_domain, wakeref); 692 693 return ret; 694 } 695 696 static unsigned int 697 hsw_primary_max_stride(struct intel_plane *plane, 698 u32 pixel_format, u64 modifier, 699 unsigned int rotation) 700 { 701 const struct drm_format_info *info = drm_format_info(pixel_format); 702 int cpp = info->cpp[0]; 703 704 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 705 return min(8192 * cpp, 32 * 1024); 706 } 707 708 static unsigned int 709 ilk_primary_max_stride(struct intel_plane *plane, 710 u32 pixel_format, u64 modifier, 711 unsigned int rotation) 712 { 713 const struct drm_format_info *info = drm_format_info(pixel_format); 714 int cpp = info->cpp[0]; 715 716 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 717 if (modifier == I915_FORMAT_MOD_X_TILED) 718 return min(4096 * cpp, 32 * 1024); 719 else 720 return 32 * 1024; 721 } 722 723 unsigned int 724 i965_plane_max_stride(struct intel_plane *plane, 725 u32 pixel_format, u64 modifier, 726 unsigned int rotation) 727 { 728 const struct drm_format_info *info = drm_format_info(pixel_format); 729 int cpp = info->cpp[0]; 730 731 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 732 if (modifier == I915_FORMAT_MOD_X_TILED) 733 return min(4096 * cpp, 16 * 1024); 734 else 735 return 32 * 1024; 736 } 737 738 static unsigned int 739 i9xx_plane_max_stride(struct intel_plane *plane, 740 u32 pixel_format, u64 modifier, 741 unsigned int rotation) 742 { 743 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 744 745 if (DISPLAY_VER(dev_priv) >= 3) { 746 if (modifier == I915_FORMAT_MOD_X_TILED) 747 return 8*1024; 748 else 749 return 16*1024; 750 } else { 751 if (plane->i9xx_plane == PLANE_C) 752 return 4*1024; 753 else 754 return 8*1024; 755 } 756 } 757 758 static const struct drm_plane_funcs i965_plane_funcs = { 759 .update_plane = drm_atomic_helper_update_plane, 760 .disable_plane = drm_atomic_helper_disable_plane, 761 .destroy = intel_plane_destroy, 762 .atomic_duplicate_state = intel_plane_duplicate_state, 763 .atomic_destroy_state = intel_plane_destroy_state, 764 .format_mod_supported = i965_plane_format_mod_supported, 765 }; 766 767 static const struct drm_plane_funcs i8xx_plane_funcs = { 768 .update_plane = drm_atomic_helper_update_plane, 769 .disable_plane = drm_atomic_helper_disable_plane, 770 .destroy = intel_plane_destroy, 771 .atomic_duplicate_state = intel_plane_duplicate_state, 772 .atomic_destroy_state = intel_plane_destroy_state, 773 .format_mod_supported = i8xx_plane_format_mod_supported, 774 }; 775 776 struct intel_plane * 777 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 778 { 779 struct intel_plane *plane; 780 const struct drm_plane_funcs *plane_funcs; 781 unsigned int supported_rotations; 782 const u64 *modifiers; 783 const u32 *formats; 784 int num_formats; 785 int ret, zpos; 786 787 plane = intel_plane_alloc(); 788 if (IS_ERR(plane)) 789 return plane; 790 791 plane->pipe = pipe; 792 /* 793 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 794 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 795 */ 796 if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && 797 INTEL_NUM_PIPES(dev_priv) == 2) 798 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 799 else 800 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 801 plane->id = PLANE_PRIMARY; 802 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 803 804 intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); 805 806 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 807 formats = vlv_primary_formats; 808 num_formats = ARRAY_SIZE(vlv_primary_formats); 809 } else if (DISPLAY_VER(dev_priv) >= 4) { 810 /* 811 * WaFP16GammaEnabling:ivb 812 * "Workaround : When using the 64-bit format, the plane 813 * output on each color channel has one quarter amplitude. 814 * It can be brought up to full amplitude by using pipe 815 * gamma correction or pipe color space conversion to 816 * multiply the plane output by four." 817 * 818 * There is no dedicated plane gamma for the primary plane, 819 * and using the pipe gamma/csc could conflict with other 820 * planes, so we choose not to expose fp16 on IVB primary 821 * planes. HSW primary planes no longer have this problem. 822 */ 823 if (IS_IVYBRIDGE(dev_priv)) { 824 formats = ivb_primary_formats; 825 num_formats = ARRAY_SIZE(ivb_primary_formats); 826 } else { 827 formats = i965_primary_formats; 828 num_formats = ARRAY_SIZE(i965_primary_formats); 829 } 830 } else { 831 formats = i8xx_primary_formats; 832 num_formats = ARRAY_SIZE(i8xx_primary_formats); 833 } 834 835 if (DISPLAY_VER(dev_priv) >= 4) 836 plane_funcs = &i965_plane_funcs; 837 else 838 plane_funcs = &i8xx_plane_funcs; 839 840 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 841 plane->min_cdclk = vlv_plane_min_cdclk; 842 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 843 plane->min_cdclk = hsw_plane_min_cdclk; 844 else if (IS_IVYBRIDGE(dev_priv)) 845 plane->min_cdclk = ivb_plane_min_cdclk; 846 else 847 plane->min_cdclk = i9xx_plane_min_cdclk; 848 849 if (HAS_GMCH(dev_priv)) { 850 if (DISPLAY_VER(dev_priv) >= 4) 851 plane->max_stride = i965_plane_max_stride; 852 else 853 plane->max_stride = i9xx_plane_max_stride; 854 } else { 855 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 856 plane->max_stride = hsw_primary_max_stride; 857 else 858 plane->max_stride = ilk_primary_max_stride; 859 } 860 861 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { 862 plane->update_arm = i830_plane_update_arm; 863 } else { 864 plane->update_noarm = i9xx_plane_update_noarm; 865 plane->update_arm = i9xx_plane_update_arm; 866 } 867 plane->disable_arm = i9xx_plane_disable_arm; 868 plane->get_hw_state = i9xx_plane_get_hw_state; 869 plane->check_plane = i9xx_plane_check; 870 871 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 872 plane->async_flip = vlv_primary_async_flip; 873 plane->enable_flip_done = vlv_primary_enable_flip_done; 874 plane->disable_flip_done = vlv_primary_disable_flip_done; 875 } else if (IS_BROADWELL(dev_priv)) { 876 plane->need_async_flip_disable_wa = true; 877 plane->async_flip = g4x_primary_async_flip; 878 plane->enable_flip_done = bdw_primary_enable_flip_done; 879 plane->disable_flip_done = bdw_primary_disable_flip_done; 880 } else if (DISPLAY_VER(dev_priv) >= 7) { 881 plane->async_flip = g4x_primary_async_flip; 882 plane->enable_flip_done = ivb_primary_enable_flip_done; 883 plane->disable_flip_done = ivb_primary_disable_flip_done; 884 } else if (DISPLAY_VER(dev_priv) >= 5) { 885 plane->async_flip = g4x_primary_async_flip; 886 plane->enable_flip_done = ilk_primary_enable_flip_done; 887 plane->disable_flip_done = ilk_primary_disable_flip_done; 888 } 889 890 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 891 892 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 893 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 894 0, plane_funcs, 895 formats, num_formats, 896 modifiers, 897 DRM_PLANE_TYPE_PRIMARY, 898 "primary %c", pipe_name(pipe)); 899 else 900 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 901 0, plane_funcs, 902 formats, num_formats, 903 modifiers, 904 DRM_PLANE_TYPE_PRIMARY, 905 "plane %c", 906 plane_name(plane->i9xx_plane)); 907 908 kfree(modifiers); 909 910 if (ret) 911 goto fail; 912 913 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 914 supported_rotations = 915 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 916 DRM_MODE_REFLECT_X; 917 } else if (DISPLAY_VER(dev_priv) >= 4) { 918 supported_rotations = 919 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 920 } else { 921 supported_rotations = DRM_MODE_ROTATE_0; 922 } 923 924 if (DISPLAY_VER(dev_priv) >= 4) 925 drm_plane_create_rotation_property(&plane->base, 926 DRM_MODE_ROTATE_0, 927 supported_rotations); 928 929 zpos = 0; 930 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 931 932 intel_plane_helper_add(plane); 933 934 return plane; 935 936 fail: 937 intel_plane_free(plane); 938 939 return ERR_PTR(ret); 940 } 941 942 static int i9xx_format_to_fourcc(int format) 943 { 944 switch (format) { 945 case DISP_FORMAT_8BPP: 946 return DRM_FORMAT_C8; 947 case DISP_FORMAT_BGRA555: 948 return DRM_FORMAT_ARGB1555; 949 case DISP_FORMAT_BGRX555: 950 return DRM_FORMAT_XRGB1555; 951 case DISP_FORMAT_BGRX565: 952 return DRM_FORMAT_RGB565; 953 default: 954 case DISP_FORMAT_BGRX888: 955 return DRM_FORMAT_XRGB8888; 956 case DISP_FORMAT_RGBX888: 957 return DRM_FORMAT_XBGR8888; 958 case DISP_FORMAT_BGRA888: 959 return DRM_FORMAT_ARGB8888; 960 case DISP_FORMAT_RGBA888: 961 return DRM_FORMAT_ABGR8888; 962 case DISP_FORMAT_BGRX101010: 963 return DRM_FORMAT_XRGB2101010; 964 case DISP_FORMAT_RGBX101010: 965 return DRM_FORMAT_XBGR2101010; 966 case DISP_FORMAT_BGRA101010: 967 return DRM_FORMAT_ARGB2101010; 968 case DISP_FORMAT_RGBA101010: 969 return DRM_FORMAT_ABGR2101010; 970 case DISP_FORMAT_RGBX161616: 971 return DRM_FORMAT_XBGR16161616F; 972 } 973 } 974 975 void 976 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 977 struct intel_initial_plane_config *plane_config) 978 { 979 struct drm_device *dev = crtc->base.dev; 980 struct drm_i915_private *dev_priv = to_i915(dev); 981 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 982 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 983 enum pipe pipe; 984 u32 val, base, offset; 985 int fourcc, pixel_format; 986 unsigned int aligned_height; 987 struct drm_framebuffer *fb; 988 struct intel_framebuffer *intel_fb; 989 990 if (!plane->get_hw_state(plane, &pipe)) 991 return; 992 993 drm_WARN_ON(dev, pipe != crtc->pipe); 994 995 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 996 if (!intel_fb) { 997 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 998 return; 999 } 1000 1001 fb = &intel_fb->base; 1002 1003 fb->dev = dev; 1004 1005 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 1006 1007 if (DISPLAY_VER(dev_priv) >= 4) { 1008 if (val & DISP_TILED) { 1009 plane_config->tiling = I915_TILING_X; 1010 fb->modifier = I915_FORMAT_MOD_X_TILED; 1011 } 1012 1013 if (val & DISP_ROTATE_180) 1014 plane_config->rotation = DRM_MODE_ROTATE_180; 1015 } 1016 1017 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && 1018 val & DISP_MIRROR) 1019 plane_config->rotation |= DRM_MODE_REFLECT_X; 1020 1021 pixel_format = val & DISP_FORMAT_MASK; 1022 fourcc = i9xx_format_to_fourcc(pixel_format); 1023 fb->format = drm_format_info(fourcc); 1024 1025 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1026 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); 1027 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1028 } else if (DISPLAY_VER(dev_priv) >= 4) { 1029 if (plane_config->tiling) 1030 offset = intel_de_read(dev_priv, 1031 DSPTILEOFF(i9xx_plane)); 1032 else 1033 offset = intel_de_read(dev_priv, 1034 DSPLINOFF(i9xx_plane)); 1035 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; 1036 } else { 1037 offset = 0; 1038 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); 1039 } 1040 plane_config->base = base; 1041 1042 drm_WARN_ON(&dev_priv->drm, offset != 0); 1043 1044 val = intel_de_read(dev_priv, PIPESRC(pipe)); 1045 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; 1046 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; 1047 1048 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); 1049 fb->pitches[0] = val & 0xffffffc0; 1050 1051 aligned_height = intel_fb_align_height(fb, 0, fb->height); 1052 1053 plane_config->size = fb->pitches[0] * aligned_height; 1054 1055 drm_dbg_kms(&dev_priv->drm, 1056 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 1057 crtc->base.name, plane->base.name, fb->width, fb->height, 1058 fb->format->cpp[0] * 8, base, fb->pitches[0], 1059 plane_config->size); 1060 1061 plane_config->fb = intel_fb; 1062 } 1063 1064 bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, 1065 const struct intel_initial_plane_config *plane_config) 1066 { 1067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1068 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1069 const struct intel_plane_state *plane_state = 1070 to_intel_plane_state(plane->base.state); 1071 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 1072 u32 base; 1073 1074 if (!plane_state->uapi.visible) 1075 return false; 1076 1077 base = intel_plane_ggtt_offset(plane_state); 1078 1079 /* 1080 * We may have moved the surface to a different 1081 * part of ggtt, make the plane aware of that. 1082 */ 1083 if (plane_config->base == base) 1084 return false; 1085 1086 if (DISPLAY_VER(dev_priv) >= 4) 1087 intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); 1088 else 1089 intel_de_write(dev_priv, DSPADDR(i9xx_plane), base); 1090 1091 return true; 1092 } 1093