1 /* Hisilicon Hibmc SoC drm driver 2 * 3 * Based on the bochs drm driver. 4 * 5 * Copyright (c) 2016 Huawei Limited. 6 * 7 * Author: 8 * Rongrong Zou <zourongrong@huawei.com> 9 * Rongrong Zou <zourongrong@gmail.com> 10 * Jianhua Li <lijianhua@huawei.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 */ 18 19 #ifndef HIBMC_DRM_HW_H 20 #define HIBMC_DRM_HW_H 21 22 /* register definition */ 23 #define HIBMC_MISC_CTRL 0x4 24 25 #define HIBMC_MSCCTL_LOCALMEM_RESET(x) ((x) << 6) 26 #define HIBMC_MSCCTL_LOCALMEM_RESET_MASK 0x40 27 28 #define HIBMC_CURRENT_GATE 0x000040 29 #define HIBMC_CURR_GATE_DISPLAY(x) ((x) << 2) 30 #define HIBMC_CURR_GATE_DISPLAY_MASK 0x4 31 32 #define HIBMC_CURR_GATE_LOCALMEM(x) ((x) << 1) 33 #define HIBMC_CURR_GATE_LOCALMEM_MASK 0x2 34 35 #define HIBMC_MODE0_GATE 0x000044 36 #define HIBMC_MODE1_GATE 0x000048 37 #define HIBMC_POWER_MODE_CTRL 0x00004C 38 39 #define HIBMC_PW_MODE_CTL_OSC_INPUT(x) ((x) << 3) 40 #define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK 0x8 41 42 #define HIBMC_PW_MODE_CTL_MODE(x) ((x) << 0) 43 #define HIBMC_PW_MODE_CTL_MODE_MASK 0x03 44 #define HIBMC_PW_MODE_CTL_MODE_SHIFT 0 45 46 #define HIBMC_PW_MODE_CTL_MODE_MODE0 0 47 #define HIBMC_PW_MODE_CTL_MODE_MODE1 1 48 #define HIBMC_PW_MODE_CTL_MODE_SLEEP 2 49 50 #define HIBMC_PANEL_PLL_CTRL 0x00005C 51 #define HIBMC_CRT_PLL_CTRL 0x000060 52 53 #define HIBMC_PLL_CTRL_BYPASS(x) ((x) << 18) 54 #define HIBMC_PLL_CTRL_BYPASS_MASK 0x40000 55 56 #define HIBMC_PLL_CTRL_POWER(x) ((x) << 17) 57 #define HIBMC_PLL_CTRL_POWER_MASK 0x20000 58 59 #define HIBMC_PLL_CTRL_INPUT(x) ((x) << 16) 60 #define HIBMC_PLL_CTRL_INPUT_MASK 0x10000 61 62 #define HIBMC_PLL_CTRL_POD(x) ((x) << 14) 63 #define HIBMC_PLL_CTRL_POD_MASK 0xC000 64 65 #define HIBMC_PLL_CTRL_OD(x) ((x) << 12) 66 #define HIBMC_PLL_CTRL_OD_MASK 0x3000 67 68 #define HIBMC_PLL_CTRL_N(x) ((x) << 8) 69 #define HIBMC_PLL_CTRL_N_MASK 0xF00 70 71 #define HIBMC_PLL_CTRL_M(x) ((x) << 0) 72 #define HIBMC_PLL_CTRL_M_MASK 0xFF 73 74 #define HIBMC_CRT_DISP_CTL 0x80200 75 76 #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25) 77 #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000 78 79 #define HIBMC_CRTSELECT_CRT 1 80 81 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) ((x) << 14) 82 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK 0x4000 83 84 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) ((x) << 13) 85 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK 0x2000 86 87 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) ((x) << 12) 88 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK 0x1000 89 90 #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8) 91 #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100 92 93 #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2) 94 #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4 95 96 #define HIBMC_CRT_DISP_CTL_FORMAT(x) ((x) << 0) 97 #define HIBMC_CRT_DISP_CTL_FORMAT_MASK 0x03 98 99 #define HIBMC_CRT_FB_ADDRESS 0x080204 100 101 #define HIBMC_CRT_FB_WIDTH 0x080208 102 #define HIBMC_CRT_FB_WIDTH_WIDTH(x) ((x) << 16) 103 #define HIBMC_CRT_FB_WIDTH_WIDTH_MASK 0x3FFF0000 104 #define HIBMC_CRT_FB_WIDTH_OFFS(x) ((x) << 0) 105 #define HIBMC_CRT_FB_WIDTH_OFFS_MASK 0x3FFF 106 107 #define HIBMC_CRT_HORZ_TOTAL 0x08020C 108 #define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) ((x) << 16) 109 #define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK 0xFFF0000 110 111 #define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) ((x) << 0) 112 #define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK 0xFFF 113 114 #define HIBMC_CRT_HORZ_SYNC 0x080210 115 #define HIBMC_CRT_HORZ_SYNC_WIDTH(x) ((x) << 16) 116 #define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK 0xFF0000 117 118 #define HIBMC_CRT_HORZ_SYNC_START(x) ((x) << 0) 119 #define HIBMC_CRT_HORZ_SYNC_START_MASK 0xFFF 120 121 #define HIBMC_CRT_VERT_TOTAL 0x080214 122 #define HIBMC_CRT_VERT_TOTAL_TOTAL(x) ((x) << 16) 123 #define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK 0x7FFF0000 124 125 #define HIBMC_CRT_VERT_TOTAL_DISP_END(x) ((x) << 0) 126 #define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK 0x7FF 127 128 #define HIBMC_CRT_VERT_SYNC 0x080218 129 #define HIBMC_CRT_VERT_SYNC_HEIGHT(x) ((x) << 16) 130 #define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK 0x3F0000 131 132 #define HIBMC_CRT_VERT_SYNC_START(x) ((x) << 0) 133 #define HIBMC_CRT_VERT_SYNC_START_MASK 0x7FF 134 135 /* Auto Centering */ 136 #define HIBMC_CRT_AUTO_CENTERING_TL 0x080280 137 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) ((x) << 16) 138 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK 0x7FF0000 139 140 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) ((x) << 0) 141 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7FF 142 143 #define HIBMC_CRT_AUTO_CENTERING_BR 0x080284 144 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) ((x) << 16) 145 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000 146 147 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) ((x) << 0) 148 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7FF 149 150 /* register to control panel output */ 151 #define HIBMC_DISPLAY_CONTROL_HISILE 0x80288 152 #define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) ((x) << 0) 153 #define HIBMC_DISPLAY_CONTROL_PANELDATE(x) ((x) << 1) 154 #define HIBMC_DISPLAY_CONTROL_FPEN(x) ((x) << 2) 155 #define HIBMC_DISPLAY_CONTROL_VBIASEN(x) ((x) << 3) 156 157 #define HIBMC_RAW_INTERRUPT 0x80290 158 #define HIBMC_RAW_INTERRUPT_VBLANK(x) ((x) << 2) 159 #define HIBMC_RAW_INTERRUPT_VBLANK_MASK 0x4 160 161 #define HIBMC_RAW_INTERRUPT_EN 0x80298 162 #define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) ((x) << 2) 163 #define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK 0x4 164 165 /* register and values for PLL control */ 166 #define CRT_PLL1_HS 0x802a8 167 #define CRT_PLL1_HS_OUTER_BYPASS(x) ((x) << 30) 168 #define CRT_PLL1_HS_INTER_BYPASS(x) ((x) << 29) 169 #define CRT_PLL1_HS_POWERON(x) ((x) << 24) 170 171 #define CRT_PLL1_HS_25MHZ 0x23d40f02 172 #define CRT_PLL1_HS_40MHZ 0x23940801 173 #define CRT_PLL1_HS_65MHZ 0x23940d01 174 #define CRT_PLL1_HS_78MHZ 0x23540F82 175 #define CRT_PLL1_HS_74MHZ 0x23941dc2 176 #define CRT_PLL1_HS_80MHZ 0x23941001 177 #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2 178 #define CRT_PLL1_HS_108MHZ 0x23b41b01 179 #define CRT_PLL1_HS_162MHZ 0x23480681 180 #define CRT_PLL1_HS_148MHZ 0x23541dc2 181 #define CRT_PLL1_HS_193MHZ 0x234807c1 182 183 #define CRT_PLL2_HS 0x802ac 184 #define CRT_PLL2_HS_25MHZ 0x206B851E 185 #define CRT_PLL2_HS_40MHZ 0x30000000 186 #define CRT_PLL2_HS_65MHZ 0x40000000 187 #define CRT_PLL2_HS_78MHZ 0x50E147AE 188 #define CRT_PLL2_HS_74MHZ 0x602B6AE7 189 #define CRT_PLL2_HS_80MHZ 0x70000000 190 #define CRT_PLL2_HS_108MHZ 0x80000000 191 #define CRT_PLL2_HS_162MHZ 0xA0000000 192 #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD 193 #define CRT_PLL2_HS_193MHZ 0xC0872B02 194 195 #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) 196 #endif 197