1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SWSMU_CODE_LAYER_L3 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v14_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "amdgpu_ras.h" 39 #include "smu_cmn.h" 40 41 #include "asic_reg/mp/mp_14_0_0_offset.h" 42 #include "asic_reg/mp/mp_14_0_0_sh_mask.h" 43 44 /* 45 * DO NOT use these for err/warn/info/debug messages. 46 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 47 * They are more MGPU friendly. 48 */ 49 #undef pr_err 50 #undef pr_warn 51 #undef pr_info 52 #undef pr_debug 53 54 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin"); 55 56 int smu_v14_0_init_microcode(struct smu_context *smu) 57 { 58 struct amdgpu_device *adev = smu->adev; 59 char fw_name[30]; 60 char ucode_prefix[15]; 61 int err = 0; 62 const struct smc_firmware_header_v1_0 *hdr; 63 const struct common_firmware_header *header; 64 struct amdgpu_firmware_info *ucode = NULL; 65 66 /* doesn't need to load smu firmware in IOV mode */ 67 if (amdgpu_sriov_vf(adev)) 68 return 0; 69 70 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 71 72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 73 74 err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); 75 if (err) 76 goto out; 77 78 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 79 amdgpu_ucode_print_smc_hdr(&hdr->header); 80 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 81 82 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 83 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 84 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 85 ucode->fw = adev->pm.fw; 86 header = (const struct common_firmware_header *)ucode->fw->data; 87 adev->firmware.fw_size += 88 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 89 } 90 91 out: 92 if (err) 93 amdgpu_ucode_release(&adev->pm.fw); 94 return err; 95 } 96 97 void smu_v14_0_fini_microcode(struct smu_context *smu) 98 { 99 struct amdgpu_device *adev = smu->adev; 100 101 amdgpu_ucode_release(&adev->pm.fw); 102 adev->pm.fw_version = 0; 103 } 104 105 int smu_v14_0_load_microcode(struct smu_context *smu) 106 { 107 #if 0 108 struct amdgpu_device *adev = smu->adev; 109 const uint32_t *src; 110 const struct smc_firmware_header_v1_0 *hdr; 111 uint32_t addr_start = MP1_SRAM; 112 uint32_t i; 113 uint32_t smc_fw_size; 114 uint32_t mp1_fw_flags; 115 116 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 117 src = (const uint32_t *)(adev->pm.fw->data + 118 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 119 smc_fw_size = hdr->header.ucode_size_bytes; 120 121 for (i = 1; i < smc_fw_size/4 - 1; i++) { 122 WREG32_PCIE(addr_start, src[i]); 123 addr_start += 4; 124 } 125 126 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 127 1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK); 128 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 129 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK); 130 131 for (i = 0; i < adev->usec_timeout; i++) { 132 mp1_fw_flags = RREG32_PCIE(MP1_Public | 133 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 134 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 135 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 136 break; 137 udelay(1); 138 } 139 140 if (i == adev->usec_timeout) 141 return -ETIME; 142 143 #endif 144 return 0; 145 146 } 147 148 int smu_v14_0_init_pptable_microcode(struct smu_context *smu) 149 { 150 struct amdgpu_device *adev = smu->adev; 151 struct amdgpu_firmware_info *ucode = NULL; 152 uint32_t size = 0, pptable_id = 0; 153 int ret = 0; 154 void *table; 155 156 /* doesn't need to load smu firmware in IOV mode */ 157 if (amdgpu_sriov_vf(adev)) 158 return 0; 159 160 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 161 return 0; 162 163 if (!adev->scpm_enabled) 164 return 0; 165 166 /* override pptable_id from driver parameter */ 167 if (amdgpu_smu_pptable_id >= 0) { 168 pptable_id = amdgpu_smu_pptable_id; 169 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 170 } else { 171 pptable_id = smu->smu_table.boot_values.pp_table_id; 172 } 173 174 /* "pptable_id == 0" means vbios carries the pptable. */ 175 if (!pptable_id) 176 return 0; 177 178 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 179 if (ret) 180 return ret; 181 182 smu->pptable_firmware.data = table; 183 smu->pptable_firmware.size = size; 184 185 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 186 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 187 ucode->fw = &smu->pptable_firmware; 188 adev->firmware.fw_size += 189 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 190 191 return 0; 192 } 193 194 int smu_v14_0_check_fw_status(struct smu_context *smu) 195 { 196 struct amdgpu_device *adev = smu->adev; 197 uint32_t mp1_fw_flags; 198 199 mp1_fw_flags = RREG32_PCIE(MP1_Public | 200 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 201 202 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 203 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 204 return 0; 205 206 return -EIO; 207 } 208 209 int smu_v14_0_check_fw_version(struct smu_context *smu) 210 { 211 struct amdgpu_device *adev = smu->adev; 212 uint32_t if_version = 0xff, smu_version = 0xff; 213 uint8_t smu_program, smu_major, smu_minor, smu_debug; 214 int ret = 0; 215 216 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 217 if (ret) 218 return ret; 219 220 smu_program = (smu_version >> 24) & 0xff; 221 smu_major = (smu_version >> 16) & 0xff; 222 smu_minor = (smu_version >> 8) & 0xff; 223 smu_debug = (smu_version >> 0) & 0xff; 224 if (smu->is_apu) 225 adev->pm.fw_version = smu_version; 226 227 switch (adev->ip_versions[MP1_HWIP][0]) { 228 case IP_VERSION(14, 0, 2): 229 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2; 230 break; 231 case IP_VERSION(14, 0, 0): 232 if ((smu->smc_fw_version < 0x5d3a00)) 233 dev_warn(smu->adev->dev, "The PMFW version(%x) is behind in this BIOS!\n", smu->smc_fw_version); 234 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0; 235 break; 236 default: 237 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", 238 adev->ip_versions[MP1_HWIP][0]); 239 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV; 240 break; 241 } 242 243 if (adev->pm.fw) 244 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", 245 smu_program, smu_version, smu_major, smu_minor, smu_debug); 246 247 /* 248 * 1. if_version mismatch is not critical as our fw is designed 249 * to be backward compatible. 250 * 2. New fw usually brings some optimizations. But that's visible 251 * only on the paired driver. 252 * Considering above, we just leave user a verbal message instead 253 * of halt driver loading. 254 */ 255 if (if_version != smu->smc_driver_if_version) { 256 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 257 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 258 smu->smc_driver_if_version, if_version, 259 smu_program, smu_version, smu_major, smu_minor, smu_debug); 260 dev_info(adev->dev, "SMU driver if version not matched\n"); 261 } 262 263 return ret; 264 } 265 266 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 267 { 268 struct amdgpu_device *adev = smu->adev; 269 uint32_t ppt_offset_bytes; 270 const struct smc_firmware_header_v2_0 *v2; 271 272 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 273 274 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 275 *size = le32_to_cpu(v2->ppt_size_bytes); 276 *table = (uint8_t *)v2 + ppt_offset_bytes; 277 278 return 0; 279 } 280 281 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table, 282 uint32_t *size, uint32_t pptable_id) 283 { 284 struct amdgpu_device *adev = smu->adev; 285 const struct smc_firmware_header_v2_1 *v2_1; 286 struct smc_soft_pptable_entry *entries; 287 uint32_t pptable_count = 0; 288 int i = 0; 289 290 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 291 entries = (struct smc_soft_pptable_entry *) 292 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 293 pptable_count = le32_to_cpu(v2_1->pptable_count); 294 for (i = 0; i < pptable_count; i++) { 295 if (le32_to_cpu(entries[i].id) == pptable_id) { 296 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 297 *size = le32_to_cpu(entries[i].ppt_size_bytes); 298 break; 299 } 300 } 301 302 if (i == pptable_count) 303 return -EINVAL; 304 305 return 0; 306 } 307 308 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 309 { 310 struct amdgpu_device *adev = smu->adev; 311 uint16_t atom_table_size; 312 uint8_t frev, crev; 313 int ret, index; 314 315 dev_info(adev->dev, "use vbios provided pptable\n"); 316 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 317 powerplayinfo); 318 319 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 320 (uint8_t **)table); 321 if (ret) 322 return ret; 323 324 if (size) 325 *size = atom_table_size; 326 327 return 0; 328 } 329 330 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu, 331 void **table, 332 uint32_t *size, 333 uint32_t pptable_id) 334 { 335 const struct smc_firmware_header_v1_0 *hdr; 336 struct amdgpu_device *adev = smu->adev; 337 uint16_t version_major, version_minor; 338 int ret; 339 340 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 341 if (!hdr) 342 return -EINVAL; 343 344 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 345 346 version_major = le16_to_cpu(hdr->header.header_version_major); 347 version_minor = le16_to_cpu(hdr->header.header_version_minor); 348 if (version_major != 2) { 349 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 350 version_major, version_minor); 351 return -EINVAL; 352 } 353 354 switch (version_minor) { 355 case 0: 356 ret = smu_v14_0_set_pptable_v2_0(smu, table, size); 357 break; 358 case 1: 359 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id); 360 break; 361 default: 362 ret = -EINVAL; 363 break; 364 } 365 366 return ret; 367 } 368 369 int smu_v14_0_setup_pptable(struct smu_context *smu) 370 { 371 struct amdgpu_device *adev = smu->adev; 372 uint32_t size = 0, pptable_id = 0; 373 void *table; 374 int ret = 0; 375 376 /* override pptable_id from driver parameter */ 377 if (amdgpu_smu_pptable_id >= 0) { 378 pptable_id = amdgpu_smu_pptable_id; 379 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 380 } else { 381 pptable_id = smu->smu_table.boot_values.pp_table_id; 382 } 383 384 /* force using vbios pptable in sriov mode */ 385 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 386 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size); 387 else 388 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 389 390 if (ret) 391 return ret; 392 393 if (!smu->smu_table.power_play_table) 394 smu->smu_table.power_play_table = table; 395 if (!smu->smu_table.power_play_table_size) 396 smu->smu_table.power_play_table_size = size; 397 398 return 0; 399 } 400 401 int smu_v14_0_init_smc_tables(struct smu_context *smu) 402 { 403 struct smu_table_context *smu_table = &smu->smu_table; 404 struct smu_table *tables = smu_table->tables; 405 int ret = 0; 406 407 smu_table->driver_pptable = 408 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 409 if (!smu_table->driver_pptable) { 410 ret = -ENOMEM; 411 goto err0_out; 412 } 413 414 smu_table->max_sustainable_clocks = 415 kzalloc(sizeof(struct smu_14_0_max_sustainable_clocks), GFP_KERNEL); 416 if (!smu_table->max_sustainable_clocks) { 417 ret = -ENOMEM; 418 goto err1_out; 419 } 420 421 if (tables[SMU_TABLE_OVERDRIVE].size) { 422 smu_table->overdrive_table = 423 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 424 if (!smu_table->overdrive_table) { 425 ret = -ENOMEM; 426 goto err2_out; 427 } 428 429 smu_table->boot_overdrive_table = 430 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 431 if (!smu_table->boot_overdrive_table) { 432 ret = -ENOMEM; 433 goto err3_out; 434 } 435 } 436 437 smu_table->combo_pptable = 438 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 439 if (!smu_table->combo_pptable) { 440 ret = -ENOMEM; 441 goto err4_out; 442 } 443 444 return 0; 445 446 err4_out: 447 kfree(smu_table->boot_overdrive_table); 448 err3_out: 449 kfree(smu_table->overdrive_table); 450 err2_out: 451 kfree(smu_table->max_sustainable_clocks); 452 err1_out: 453 kfree(smu_table->driver_pptable); 454 err0_out: 455 return ret; 456 } 457 458 int smu_v14_0_fini_smc_tables(struct smu_context *smu) 459 { 460 struct smu_table_context *smu_table = &smu->smu_table; 461 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 462 463 kfree(smu_table->gpu_metrics_table); 464 kfree(smu_table->combo_pptable); 465 kfree(smu_table->boot_overdrive_table); 466 kfree(smu_table->overdrive_table); 467 kfree(smu_table->max_sustainable_clocks); 468 kfree(smu_table->driver_pptable); 469 smu_table->gpu_metrics_table = NULL; 470 smu_table->combo_pptable = NULL; 471 smu_table->boot_overdrive_table = NULL; 472 smu_table->overdrive_table = NULL; 473 smu_table->max_sustainable_clocks = NULL; 474 smu_table->driver_pptable = NULL; 475 kfree(smu_table->hardcode_pptable); 476 smu_table->hardcode_pptable = NULL; 477 478 kfree(smu_table->ecc_table); 479 kfree(smu_table->metrics_table); 480 kfree(smu_table->watermarks_table); 481 smu_table->ecc_table = NULL; 482 smu_table->metrics_table = NULL; 483 smu_table->watermarks_table = NULL; 484 smu_table->metrics_time = 0; 485 486 kfree(smu_dpm->dpm_context); 487 kfree(smu_dpm->golden_dpm_context); 488 kfree(smu_dpm->dpm_current_power_state); 489 kfree(smu_dpm->dpm_request_power_state); 490 smu_dpm->dpm_context = NULL; 491 smu_dpm->golden_dpm_context = NULL; 492 smu_dpm->dpm_context_size = 0; 493 smu_dpm->dpm_current_power_state = NULL; 494 smu_dpm->dpm_request_power_state = NULL; 495 496 return 0; 497 } 498 499 int smu_v14_0_init_power(struct smu_context *smu) 500 { 501 struct smu_power_context *smu_power = &smu->smu_power; 502 503 if (smu_power->power_context || smu_power->power_context_size != 0) 504 return -EINVAL; 505 506 smu_power->power_context = kzalloc(sizeof(struct smu_14_0_dpm_context), 507 GFP_KERNEL); 508 if (!smu_power->power_context) 509 return -ENOMEM; 510 smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context); 511 512 return 0; 513 } 514 515 int smu_v14_0_fini_power(struct smu_context *smu) 516 { 517 struct smu_power_context *smu_power = &smu->smu_power; 518 519 if (!smu_power->power_context || smu_power->power_context_size == 0) 520 return -EINVAL; 521 522 kfree(smu_power->power_context); 523 smu_power->power_context = NULL; 524 smu_power->power_context_size = 0; 525 526 return 0; 527 } 528 529 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu) 530 { 531 int ret, index; 532 uint16_t size; 533 uint8_t frev, crev; 534 struct atom_common_table_header *header; 535 struct atom_firmware_info_v3_4 *v_3_4; 536 struct atom_firmware_info_v3_3 *v_3_3; 537 struct atom_firmware_info_v3_1 *v_3_1; 538 struct atom_smu_info_v3_6 *smu_info_v3_6; 539 struct atom_smu_info_v4_0 *smu_info_v4_0; 540 541 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 542 firmwareinfo); 543 544 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 545 (uint8_t **)&header); 546 if (ret) 547 return ret; 548 549 if (header->format_revision != 3) { 550 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n"); 551 return -EINVAL; 552 } 553 554 switch (header->content_revision) { 555 case 0: 556 case 1: 557 case 2: 558 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 559 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 560 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 561 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 562 smu->smu_table.boot_values.socclk = 0; 563 smu->smu_table.boot_values.dcefclk = 0; 564 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 565 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 566 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 567 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 568 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 569 smu->smu_table.boot_values.pp_table_id = 0; 570 break; 571 case 3: 572 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 573 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 574 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 575 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 576 smu->smu_table.boot_values.socclk = 0; 577 smu->smu_table.boot_values.dcefclk = 0; 578 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 579 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 580 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 581 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 582 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 583 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 584 break; 585 case 4: 586 default: 587 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 588 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 589 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 590 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 591 smu->smu_table.boot_values.socclk = 0; 592 smu->smu_table.boot_values.dcefclk = 0; 593 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 594 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 595 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 596 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 597 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 598 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 599 break; 600 } 601 602 smu->smu_table.boot_values.format_revision = header->format_revision; 603 smu->smu_table.boot_values.content_revision = header->content_revision; 604 605 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 606 smu_info); 607 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 608 (uint8_t **)&header)) { 609 610 if ((frev == 3) && (crev == 6)) { 611 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 612 613 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 614 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 615 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 616 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 617 } else if ((frev == 3) && (crev == 1)) { 618 return 0; 619 } else if ((frev == 4) && (crev == 0)) { 620 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 621 622 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 623 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 624 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 625 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 626 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 627 } else { 628 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 629 (uint32_t)frev, (uint32_t)crev); 630 } 631 } 632 633 return 0; 634 } 635 636 637 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu) 638 { 639 struct smu_table_context *smu_table = &smu->smu_table; 640 struct smu_table *memory_pool = &smu_table->memory_pool; 641 int ret = 0; 642 uint64_t address; 643 uint32_t address_low, address_high; 644 645 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 646 return ret; 647 648 address = memory_pool->mc_address; 649 address_high = (uint32_t)upper_32_bits(address); 650 address_low = (uint32_t)lower_32_bits(address); 651 652 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 653 address_high, NULL); 654 if (ret) 655 return ret; 656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 657 address_low, NULL); 658 if (ret) 659 return ret; 660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 661 (uint32_t)memory_pool->size, NULL); 662 if (ret) 663 return ret; 664 665 return ret; 666 } 667 668 int smu_v14_0_set_driver_table_location(struct smu_context *smu) 669 { 670 struct smu_table *driver_table = &smu->smu_table.driver_table; 671 int ret = 0; 672 673 if (driver_table->mc_address) { 674 ret = smu_cmn_send_smc_msg_with_param(smu, 675 SMU_MSG_SetDriverDramAddrHigh, 676 upper_32_bits(driver_table->mc_address), 677 NULL); 678 if (!ret) 679 ret = smu_cmn_send_smc_msg_with_param(smu, 680 SMU_MSG_SetDriverDramAddrLow, 681 lower_32_bits(driver_table->mc_address), 682 NULL); 683 } 684 685 return ret; 686 } 687 688 int smu_v14_0_set_tool_table_location(struct smu_context *smu) 689 { 690 int ret = 0; 691 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 692 693 if (tool_table->mc_address) { 694 ret = smu_cmn_send_smc_msg_with_param(smu, 695 SMU_MSG_SetToolsDramAddrHigh, 696 upper_32_bits(tool_table->mc_address), 697 NULL); 698 if (!ret) 699 ret = smu_cmn_send_smc_msg_with_param(smu, 700 SMU_MSG_SetToolsDramAddrLow, 701 lower_32_bits(tool_table->mc_address), 702 NULL); 703 } 704 705 return ret; 706 } 707 708 int smu_v14_0_set_allowed_mask(struct smu_context *smu) 709 { 710 struct smu_feature *feature = &smu->smu_feature; 711 int ret = 0; 712 uint32_t feature_mask[2]; 713 714 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 715 feature->feature_num < 64) 716 return -EINVAL; 717 718 bitmap_to_arr32(feature_mask, feature->allowed, 64); 719 720 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 721 feature_mask[1], NULL); 722 if (ret) 723 return ret; 724 725 return smu_cmn_send_smc_msg_with_param(smu, 726 SMU_MSG_SetAllowedFeaturesMaskLow, 727 feature_mask[0], 728 NULL); 729 } 730 731 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable) 732 { 733 int ret = 0; 734 struct amdgpu_device *adev = smu->adev; 735 736 switch (adev->ip_versions[MP1_HWIP][0]) { 737 case IP_VERSION(14, 0, 2): 738 case IP_VERSION(14, 0, 0): 739 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 740 return 0; 741 if (enable) 742 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 743 else 744 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 745 break; 746 default: 747 break; 748 } 749 750 return ret; 751 } 752 753 int smu_v14_0_system_features_control(struct smu_context *smu, 754 bool en) 755 { 756 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 757 SMU_MSG_DisableAllSmuFeatures), NULL); 758 } 759 760 int smu_v14_0_notify_display_change(struct smu_context *smu) 761 { 762 int ret = 0; 763 764 if (!smu->pm_enabled) 765 return ret; 766 767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 768 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 769 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 770 771 return ret; 772 } 773 774 int smu_v14_0_get_current_power_limit(struct smu_context *smu, 775 uint32_t *power_limit) 776 { 777 int power_src; 778 int ret = 0; 779 780 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 781 return -EINVAL; 782 783 power_src = smu_cmn_to_asic_specific_index(smu, 784 CMN2ASIC_MAPPING_PWR, 785 smu->adev->pm.ac_power ? 786 SMU_POWER_SOURCE_AC : 787 SMU_POWER_SOURCE_DC); 788 if (power_src < 0) 789 return -EINVAL; 790 791 ret = smu_cmn_send_smc_msg_with_param(smu, 792 SMU_MSG_GetPptLimit, 793 power_src << 16, 794 power_limit); 795 if (ret) 796 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 797 798 return ret; 799 } 800 801 int smu_v14_0_set_power_limit(struct smu_context *smu, 802 enum smu_ppt_limit_type limit_type, 803 uint32_t limit) 804 { 805 int ret = 0; 806 807 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 808 return -EINVAL; 809 810 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 811 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 812 return -EOPNOTSUPP; 813 } 814 815 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 816 if (ret) { 817 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 818 return ret; 819 } 820 821 smu->current_power_limit = limit; 822 823 return 0; 824 } 825 826 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev, 827 struct amdgpu_irq_src *source, 828 unsigned tyep, 829 enum amdgpu_interrupt_state state) 830 { 831 uint32_t val = 0; 832 833 switch (state) { 834 case AMDGPU_IRQ_STATE_DISABLE: 835 /* For THM irqs */ 836 // TODO 837 838 /* For MP1 SW irqs */ 839 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 840 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 841 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 842 843 break; 844 case AMDGPU_IRQ_STATE_ENABLE: 845 /* For THM irqs */ 846 // TODO 847 848 /* For MP1 SW irqs */ 849 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 850 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 851 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 852 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 853 854 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 855 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 856 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 857 858 break; 859 default: 860 break; 861 } 862 863 return 0; 864 } 865 866 static int smu_v14_0_irq_process(struct amdgpu_device *adev, 867 struct amdgpu_irq_src *source, 868 struct amdgpu_iv_entry *entry) 869 { 870 // TODO 871 872 return 0; 873 } 874 875 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = { 876 .set = smu_v14_0_set_irq_state, 877 .process = smu_v14_0_irq_process, 878 }; 879 880 int smu_v14_0_register_irq_handler(struct smu_context *smu) 881 { 882 struct amdgpu_device *adev = smu->adev; 883 struct amdgpu_irq_src *irq_src = &smu->irq_source; 884 int ret = 0; 885 886 if (amdgpu_sriov_vf(adev)) 887 return 0; 888 889 irq_src->num_types = 1; 890 irq_src->funcs = &smu_v14_0_irq_funcs; 891 892 // TODO: THM related 893 894 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 895 0xfe, 896 irq_src); 897 if (ret) 898 return ret; 899 900 return ret; 901 } 902 903 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu, 904 uint64_t event_arg) 905 { 906 int ret = 0; 907 908 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 909 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 910 911 return ret; 912 } 913 914 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 915 uint64_t event_arg) 916 { 917 int ret = -EINVAL; 918 919 switch (event) { 920 case SMU_EVENT_RESET_COMPLETE: 921 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg); 922 break; 923 default: 924 break; 925 } 926 927 return ret; 928 } 929 930 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 931 uint32_t *min, uint32_t *max) 932 { 933 int ret = 0, clk_id = 0; 934 uint32_t param = 0; 935 uint32_t clock_limit; 936 937 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 938 switch (clk_type) { 939 case SMU_MCLK: 940 case SMU_UCLK: 941 clock_limit = smu->smu_table.boot_values.uclk; 942 break; 943 case SMU_GFXCLK: 944 case SMU_SCLK: 945 clock_limit = smu->smu_table.boot_values.gfxclk; 946 break; 947 case SMU_SOCCLK: 948 clock_limit = smu->smu_table.boot_values.socclk; 949 break; 950 default: 951 clock_limit = 0; 952 break; 953 } 954 955 /* clock in Mhz unit */ 956 if (min) 957 *min = clock_limit / 100; 958 if (max) 959 *max = clock_limit / 100; 960 961 return 0; 962 } 963 964 clk_id = smu_cmn_to_asic_specific_index(smu, 965 CMN2ASIC_MAPPING_CLK, 966 clk_type); 967 if (clk_id < 0) { 968 ret = -EINVAL; 969 goto failed; 970 } 971 param = (clk_id & 0xffff) << 16; 972 973 if (max) { 974 if (smu->adev->pm.ac_power) 975 ret = smu_cmn_send_smc_msg_with_param(smu, 976 SMU_MSG_GetMaxDpmFreq, 977 param, 978 max); 979 else 980 ret = smu_cmn_send_smc_msg_with_param(smu, 981 SMU_MSG_GetDcModeMaxDpmFreq, 982 param, 983 max); 984 if (ret) 985 goto failed; 986 } 987 988 if (min) { 989 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 990 if (ret) 991 goto failed; 992 } 993 994 failed: 995 return ret; 996 } 997 998 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, 999 enum smu_clk_type clk_type, 1000 uint32_t min, 1001 uint32_t max) 1002 { 1003 int ret = 0, clk_id = 0; 1004 uint32_t param; 1005 1006 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1007 return 0; 1008 1009 clk_id = smu_cmn_to_asic_specific_index(smu, 1010 CMN2ASIC_MAPPING_CLK, 1011 clk_type); 1012 if (clk_id < 0) 1013 return clk_id; 1014 1015 if (max > 0) { 1016 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1017 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1018 param, NULL); 1019 if (ret) 1020 goto out; 1021 } 1022 1023 if (min > 0) { 1024 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1025 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1026 param, NULL); 1027 if (ret) 1028 goto out; 1029 } 1030 1031 out: 1032 return ret; 1033 } 1034 1035 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu, 1036 enum smu_clk_type clk_type, 1037 uint32_t min, 1038 uint32_t max) 1039 { 1040 int ret = 0, clk_id = 0; 1041 uint32_t param; 1042 1043 if (min <= 0 && max <= 0) 1044 return -EINVAL; 1045 1046 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1047 return 0; 1048 1049 clk_id = smu_cmn_to_asic_specific_index(smu, 1050 CMN2ASIC_MAPPING_CLK, 1051 clk_type); 1052 if (clk_id < 0) 1053 return clk_id; 1054 1055 if (max > 0) { 1056 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1057 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1058 param, NULL); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 if (min > 0) { 1064 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1065 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1066 param, NULL); 1067 if (ret) 1068 return ret; 1069 } 1070 1071 return ret; 1072 } 1073 1074 int smu_v14_0_set_performance_level(struct smu_context *smu, 1075 enum amd_dpm_forced_level level) 1076 { 1077 struct smu_14_0_dpm_context *dpm_context = 1078 smu->smu_dpm.dpm_context; 1079 struct smu_14_0_dpm_table *gfx_table = 1080 &dpm_context->dpm_tables.gfx_table; 1081 struct smu_14_0_dpm_table *mem_table = 1082 &dpm_context->dpm_tables.uclk_table; 1083 struct smu_14_0_dpm_table *soc_table = 1084 &dpm_context->dpm_tables.soc_table; 1085 struct smu_14_0_dpm_table *vclk_table = 1086 &dpm_context->dpm_tables.vclk_table; 1087 struct smu_14_0_dpm_table *dclk_table = 1088 &dpm_context->dpm_tables.dclk_table; 1089 struct smu_14_0_dpm_table *fclk_table = 1090 &dpm_context->dpm_tables.fclk_table; 1091 struct smu_umd_pstate_table *pstate_table = 1092 &smu->pstate_table; 1093 struct amdgpu_device *adev = smu->adev; 1094 uint32_t sclk_min = 0, sclk_max = 0; 1095 uint32_t mclk_min = 0, mclk_max = 0; 1096 uint32_t socclk_min = 0, socclk_max = 0; 1097 uint32_t vclk_min = 0, vclk_max = 0; 1098 uint32_t dclk_min = 0, dclk_max = 0; 1099 uint32_t fclk_min = 0, fclk_max = 0; 1100 int ret = 0, i; 1101 1102 switch (level) { 1103 case AMD_DPM_FORCED_LEVEL_HIGH: 1104 sclk_min = sclk_max = gfx_table->max; 1105 mclk_min = mclk_max = mem_table->max; 1106 socclk_min = socclk_max = soc_table->max; 1107 vclk_min = vclk_max = vclk_table->max; 1108 dclk_min = dclk_max = dclk_table->max; 1109 fclk_min = fclk_max = fclk_table->max; 1110 break; 1111 case AMD_DPM_FORCED_LEVEL_LOW: 1112 sclk_min = sclk_max = gfx_table->min; 1113 mclk_min = mclk_max = mem_table->min; 1114 socclk_min = socclk_max = soc_table->min; 1115 vclk_min = vclk_max = vclk_table->min; 1116 dclk_min = dclk_max = dclk_table->min; 1117 fclk_min = fclk_max = fclk_table->min; 1118 break; 1119 case AMD_DPM_FORCED_LEVEL_AUTO: 1120 sclk_min = gfx_table->min; 1121 sclk_max = gfx_table->max; 1122 mclk_min = mem_table->min; 1123 mclk_max = mem_table->max; 1124 socclk_min = soc_table->min; 1125 socclk_max = soc_table->max; 1126 vclk_min = vclk_table->min; 1127 vclk_max = vclk_table->max; 1128 dclk_min = dclk_table->min; 1129 dclk_max = dclk_table->max; 1130 fclk_min = fclk_table->min; 1131 fclk_max = fclk_table->max; 1132 break; 1133 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1134 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1135 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1136 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1137 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1138 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1139 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1140 break; 1141 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1142 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1143 break; 1144 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1145 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1146 break; 1147 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1148 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1149 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1150 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1151 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1152 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1153 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1154 break; 1155 case AMD_DPM_FORCED_LEVEL_MANUAL: 1156 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1157 return 0; 1158 default: 1159 dev_err(adev->dev, "Invalid performance level %d\n", level); 1160 return -EINVAL; 1161 } 1162 1163 if (sclk_min && sclk_max) { 1164 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1165 SMU_GFXCLK, 1166 sclk_min, 1167 sclk_max); 1168 if (ret) 1169 return ret; 1170 1171 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1172 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1173 } 1174 1175 if (mclk_min && mclk_max) { 1176 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1177 SMU_MCLK, 1178 mclk_min, 1179 mclk_max); 1180 if (ret) 1181 return ret; 1182 1183 pstate_table->uclk_pstate.curr.min = mclk_min; 1184 pstate_table->uclk_pstate.curr.max = mclk_max; 1185 } 1186 1187 if (socclk_min && socclk_max) { 1188 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1189 SMU_SOCCLK, 1190 socclk_min, 1191 socclk_max); 1192 if (ret) 1193 return ret; 1194 1195 pstate_table->socclk_pstate.curr.min = socclk_min; 1196 pstate_table->socclk_pstate.curr.max = socclk_max; 1197 } 1198 1199 if (vclk_min && vclk_max) { 1200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1201 if (adev->vcn.harvest_config & (1 << i)) 1202 continue; 1203 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1204 i ? SMU_VCLK1 : SMU_VCLK, 1205 vclk_min, 1206 vclk_max); 1207 if (ret) 1208 return ret; 1209 } 1210 pstate_table->vclk_pstate.curr.min = vclk_min; 1211 pstate_table->vclk_pstate.curr.max = vclk_max; 1212 } 1213 1214 if (dclk_min && dclk_max) { 1215 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1216 if (adev->vcn.harvest_config & (1 << i)) 1217 continue; 1218 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1219 i ? SMU_DCLK1 : SMU_DCLK, 1220 dclk_min, 1221 dclk_max); 1222 if (ret) 1223 return ret; 1224 } 1225 pstate_table->dclk_pstate.curr.min = dclk_min; 1226 pstate_table->dclk_pstate.curr.max = dclk_max; 1227 } 1228 1229 if (fclk_min && fclk_max) { 1230 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1231 SMU_FCLK, 1232 fclk_min, 1233 fclk_max); 1234 if (ret) 1235 return ret; 1236 1237 pstate_table->fclk_pstate.curr.min = fclk_min; 1238 pstate_table->fclk_pstate.curr.max = fclk_max; 1239 } 1240 1241 return ret; 1242 } 1243 1244 int smu_v14_0_set_power_source(struct smu_context *smu, 1245 enum smu_power_src_type power_src) 1246 { 1247 int pwr_source; 1248 1249 pwr_source = smu_cmn_to_asic_specific_index(smu, 1250 CMN2ASIC_MAPPING_PWR, 1251 (uint32_t)power_src); 1252 if (pwr_source < 0) 1253 return -EINVAL; 1254 1255 return smu_cmn_send_smc_msg_with_param(smu, 1256 SMU_MSG_NotifyPowerSource, 1257 pwr_source, 1258 NULL); 1259 } 1260 1261 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu, 1262 enum smu_clk_type clk_type, 1263 uint16_t level, 1264 uint32_t *value) 1265 { 1266 int ret = 0, clk_id = 0; 1267 uint32_t param; 1268 1269 if (!value) 1270 return -EINVAL; 1271 1272 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1273 return 0; 1274 1275 clk_id = smu_cmn_to_asic_specific_index(smu, 1276 CMN2ASIC_MAPPING_CLK, 1277 clk_type); 1278 if (clk_id < 0) 1279 return clk_id; 1280 1281 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1282 1283 ret = smu_cmn_send_smc_msg_with_param(smu, 1284 SMU_MSG_GetDpmFreqByIndex, 1285 param, 1286 value); 1287 if (ret) 1288 return ret; 1289 1290 *value = *value & 0x7fffffff; 1291 1292 return ret; 1293 } 1294 1295 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu, 1296 enum smu_clk_type clk_type, 1297 uint32_t *value) 1298 { 1299 int ret; 1300 1301 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1302 1303 return ret; 1304 } 1305 1306 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu, 1307 enum smu_clk_type clk_type, 1308 bool *is_fine_grained_dpm) 1309 { 1310 int ret = 0, clk_id = 0; 1311 uint32_t param; 1312 uint32_t value; 1313 1314 if (!is_fine_grained_dpm) 1315 return -EINVAL; 1316 1317 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1318 return 0; 1319 1320 clk_id = smu_cmn_to_asic_specific_index(smu, 1321 CMN2ASIC_MAPPING_CLK, 1322 clk_type); 1323 if (clk_id < 0) 1324 return clk_id; 1325 1326 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1327 1328 ret = smu_cmn_send_smc_msg_with_param(smu, 1329 SMU_MSG_GetDpmFreqByIndex, 1330 param, 1331 &value); 1332 if (ret) 1333 return ret; 1334 1335 /* 1336 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 1337 * now, we un-support it 1338 */ 1339 *is_fine_grained_dpm = value & 0x80000000; 1340 1341 return 0; 1342 } 1343 1344 int smu_v14_0_set_single_dpm_table(struct smu_context *smu, 1345 enum smu_clk_type clk_type, 1346 struct smu_14_0_dpm_table *single_dpm_table) 1347 { 1348 int ret = 0; 1349 uint32_t clk; 1350 int i; 1351 1352 ret = smu_v14_0_get_dpm_level_count(smu, 1353 clk_type, 1354 &single_dpm_table->count); 1355 if (ret) { 1356 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1357 return ret; 1358 } 1359 1360 ret = smu_v14_0_get_fine_grained_status(smu, 1361 clk_type, 1362 &single_dpm_table->is_fine_grained); 1363 if (ret) { 1364 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 1365 return ret; 1366 } 1367 1368 for (i = 0; i < single_dpm_table->count; i++) { 1369 ret = smu_v14_0_get_dpm_freq_by_index(smu, 1370 clk_type, 1371 i, 1372 &clk); 1373 if (ret) { 1374 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 1375 return ret; 1376 } 1377 1378 single_dpm_table->dpm_levels[i].value = clk; 1379 single_dpm_table->dpm_levels[i].enabled = true; 1380 1381 if (i == 0) 1382 single_dpm_table->min = clk; 1383 else if (i == single_dpm_table->count - 1) 1384 single_dpm_table->max = clk; 1385 } 1386 1387 return 0; 1388 } 1389 1390 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 1391 bool enable) 1392 { 1393 struct amdgpu_device *adev = smu->adev; 1394 int i, ret = 0; 1395 1396 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1397 if (adev->vcn.harvest_config & (1 << i)) 1398 continue; 1399 1400 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1401 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1402 i << 16U, NULL); 1403 if (ret) 1404 return ret; 1405 } 1406 1407 return ret; 1408 } 1409 1410 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 1411 bool enable) 1412 { 1413 return smu_cmn_send_smc_msg_with_param(smu, enable ? 1414 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 1415 0, NULL); 1416 } 1417 1418 int smu_v14_0_run_btc(struct smu_context *smu) 1419 { 1420 int res; 1421 1422 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 1423 if (res) 1424 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 1425 1426 return res; 1427 } 1428 1429 int smu_v14_0_gpo_control(struct smu_context *smu, 1430 bool enablement) 1431 { 1432 int res; 1433 1434 res = smu_cmn_send_smc_msg_with_param(smu, 1435 SMU_MSG_AllowGpo, 1436 enablement ? 1 : 0, 1437 NULL); 1438 if (res) 1439 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); 1440 1441 return res; 1442 } 1443 1444 int smu_v14_0_deep_sleep_control(struct smu_context *smu, 1445 bool enablement) 1446 { 1447 struct amdgpu_device *adev = smu->adev; 1448 int ret = 0; 1449 1450 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 1451 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 1452 if (ret) { 1453 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 1454 return ret; 1455 } 1456 } 1457 1458 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 1459 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 1460 if (ret) { 1461 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 1462 return ret; 1463 } 1464 } 1465 1466 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 1467 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 1468 if (ret) { 1469 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 1470 return ret; 1471 } 1472 } 1473 1474 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 1475 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 1476 if (ret) { 1477 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 1478 return ret; 1479 } 1480 } 1481 1482 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 1483 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 1484 if (ret) { 1485 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 1486 return ret; 1487 } 1488 } 1489 1490 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 1491 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 1492 if (ret) { 1493 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 1494 return ret; 1495 } 1496 } 1497 1498 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 1499 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 1500 if (ret) { 1501 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 1502 return ret; 1503 } 1504 } 1505 1506 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 1507 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 1508 if (ret) { 1509 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 1510 return ret; 1511 } 1512 } 1513 1514 return ret; 1515 } 1516 1517 int smu_v14_0_gfx_ulv_control(struct smu_context *smu, 1518 bool enablement) 1519 { 1520 int ret = 0; 1521 1522 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 1523 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 1524 1525 return ret; 1526 } 1527 1528 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu, 1529 enum smu_baco_seq baco_seq) 1530 { 1531 struct smu_baco_context *smu_baco = &smu->smu_baco; 1532 int ret; 1533 1534 ret = smu_cmn_send_smc_msg_with_param(smu, 1535 SMU_MSG_ArmD3, 1536 baco_seq, 1537 NULL); 1538 if (ret) 1539 return ret; 1540 1541 if (baco_seq == BACO_SEQ_BAMACO || 1542 baco_seq == BACO_SEQ_BACO) 1543 smu_baco->state = SMU_BACO_STATE_ENTER; 1544 else 1545 smu_baco->state = SMU_BACO_STATE_EXIT; 1546 1547 return 0; 1548 } 1549 1550 bool smu_v14_0_baco_is_support(struct smu_context *smu) 1551 { 1552 struct smu_baco_context *smu_baco = &smu->smu_baco; 1553 1554 if (amdgpu_sriov_vf(smu->adev) || 1555 !smu_baco->platform_support) 1556 return false; 1557 1558 /* return true if ASIC is in BACO state already */ 1559 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 1560 return true; 1561 1562 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1563 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1564 return false; 1565 1566 return true; 1567 } 1568 1569 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu) 1570 { 1571 struct smu_baco_context *smu_baco = &smu->smu_baco; 1572 1573 return smu_baco->state; 1574 } 1575 1576 int smu_v14_0_baco_set_state(struct smu_context *smu, 1577 enum smu_baco_state state) 1578 { 1579 struct smu_baco_context *smu_baco = &smu->smu_baco; 1580 struct amdgpu_device *adev = smu->adev; 1581 int ret = 0; 1582 1583 if (smu_v14_0_baco_get_state(smu) == state) 1584 return 0; 1585 1586 if (state == SMU_BACO_STATE_ENTER) { 1587 ret = smu_cmn_send_smc_msg_with_param(smu, 1588 SMU_MSG_EnterBaco, 1589 smu_baco->maco_support ? 1590 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 1591 NULL); 1592 } else { 1593 ret = smu_cmn_send_smc_msg(smu, 1594 SMU_MSG_ExitBaco, 1595 NULL); 1596 if (ret) 1597 return ret; 1598 1599 /* clear vbios scratch 6 and 7 for coming asic reinit */ 1600 WREG32(adev->bios_scratch_reg_offset + 6, 0); 1601 WREG32(adev->bios_scratch_reg_offset + 7, 0); 1602 } 1603 1604 if (!ret) 1605 smu_baco->state = state; 1606 1607 return ret; 1608 } 1609 1610 int smu_v14_0_baco_enter(struct smu_context *smu) 1611 { 1612 int ret = 0; 1613 1614 ret = smu_v14_0_baco_set_state(smu, 1615 SMU_BACO_STATE_ENTER); 1616 if (ret) 1617 return ret; 1618 1619 msleep(10); 1620 1621 return ret; 1622 } 1623 1624 int smu_v14_0_baco_exit(struct smu_context *smu) 1625 { 1626 return smu_v14_0_baco_set_state(smu, 1627 SMU_BACO_STATE_EXIT); 1628 } 1629 1630 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu) 1631 { 1632 uint16_t index; 1633 1634 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1635 SMU_MSG_EnableGfxImu); 1636 /* Param 1 to tell PMFW to enable GFXOFF feature */ 1637 return smu_cmn_send_msg_without_waiting(smu, index, 1); 1638 } 1639 1640 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu) 1641 { 1642 struct smu_table_context *smu_table = &smu->smu_table; 1643 1644 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 1645 smu_table->clocks_table, false); 1646 } 1647 1648 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu, 1649 enum PP_OD_DPM_TABLE_COMMAND type, 1650 long input[], uint32_t size) 1651 { 1652 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1653 int ret = 0; 1654 1655 /* Only allowed in manual mode */ 1656 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1657 return -EINVAL; 1658 1659 switch (type) { 1660 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1661 if (size != 2) { 1662 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1663 return -EINVAL; 1664 } 1665 1666 if (input[0] == 0) { 1667 if (input[1] < smu->gfx_default_hard_min_freq) { 1668 dev_warn(smu->adev->dev, 1669 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1670 input[1], smu->gfx_default_hard_min_freq); 1671 return -EINVAL; 1672 } 1673 smu->gfx_actual_hard_min_freq = input[1]; 1674 } else if (input[0] == 1) { 1675 if (input[1] > smu->gfx_default_soft_max_freq) { 1676 dev_warn(smu->adev->dev, 1677 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1678 input[1], smu->gfx_default_soft_max_freq); 1679 return -EINVAL; 1680 } 1681 smu->gfx_actual_soft_max_freq = input[1]; 1682 } else { 1683 return -EINVAL; 1684 } 1685 break; 1686 case PP_OD_RESTORE_DEFAULT_TABLE: 1687 if (size != 0) { 1688 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1689 return -EINVAL; 1690 } 1691 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1692 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1693 break; 1694 case PP_OD_COMMIT_DPM_TABLE: 1695 if (size != 0) { 1696 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1697 return -EINVAL; 1698 } 1699 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1700 dev_err(smu->adev->dev, 1701 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1702 smu->gfx_actual_hard_min_freq, 1703 smu->gfx_actual_soft_max_freq); 1704 return -EINVAL; 1705 } 1706 1707 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1708 smu->gfx_actual_hard_min_freq, 1709 NULL); 1710 if (ret) { 1711 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1712 return ret; 1713 } 1714 1715 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1716 smu->gfx_actual_soft_max_freq, 1717 NULL); 1718 if (ret) { 1719 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1720 return ret; 1721 } 1722 break; 1723 default: 1724 return -ENOSYS; 1725 } 1726 1727 return ret; 1728 } 1729 1730