1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU11_DRIVER_IF_VANGOGH_H__ 24 #define __SMU11_DRIVER_IF_VANGOGH_H__ 25 26 // *** IMPORTANT *** 27 // SMU TEAM: Always increment the interface version if 28 // any structure is changed in this file 29 #define SMU13_DRIVER_IF_VERSION 3 30 31 typedef struct { 32 int32_t value; 33 uint32_t numFractionalBits; 34 } FloatInIntFormat_t; 35 36 typedef enum { 37 DSPCLK_DCFCLK = 0, 38 DSPCLK_DISPCLK, 39 DSPCLK_PIXCLK, 40 DSPCLK_PHYCLK, 41 DSPCLK_COUNT, 42 } DSPCLK_e; 43 44 typedef struct { 45 uint16_t Freq; // in MHz 46 uint16_t Vid; // min voltage in SVI2 VID 47 } DisplayClockTable_t; 48 49 typedef struct { 50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 52 uint16_t MinMclk; 53 uint16_t MaxMclk; 54 55 uint8_t WmSetting; 56 uint8_t WmType; // Used for normal pstate change or memory retraining 57 uint8_t Padding[2]; 58 } WatermarkRowGeneric_t; 59 60 #define NUM_WM_RANGES 4 61 #define WM_PSTATE_CHG 0 62 #define WM_RETRAINING 1 63 64 typedef enum { 65 WM_SOCCLK = 0, 66 WM_DCFCLK, 67 WM_COUNT, 68 } WM_CLOCK_e; 69 70 typedef struct { 71 // Watermarks 72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 73 74 uint32_t MmHubPadding[7]; // SMU internal use 75 } Watermarks_t; 76 77 typedef enum { 78 CUSTOM_DPM_SETTING_GFXCLK, 79 CUSTOM_DPM_SETTING_CCLK, 80 CUSTOM_DPM_SETTING_FCLK_CCX, 81 CUSTOM_DPM_SETTING_FCLK_GFX, 82 CUSTOM_DPM_SETTING_FCLK_STALLS, 83 CUSTOM_DPM_SETTING_LCLK, 84 CUSTOM_DPM_SETTING_COUNT, 85 } CUSTOM_DPM_SETTING_e; 86 87 typedef struct { 88 uint8_t ActiveHystLimit; 89 uint8_t IdleHystLimit; 90 uint8_t FPS; 91 uint8_t MinActiveFreqType; 92 FloatInIntFormat_t MinActiveFreq; 93 FloatInIntFormat_t PD_Data_limit; 94 FloatInIntFormat_t PD_Data_time_constant; 95 FloatInIntFormat_t PD_Data_error_coeff; 96 FloatInIntFormat_t PD_Data_error_rate_coeff; 97 } DpmActivityMonitorCoeffExt_t; 98 99 typedef struct { 100 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; 101 } CustomDpmSettings_t; 102 103 #define NUM_DCFCLK_DPM_LEVELS 7 104 #define NUM_DISPCLK_DPM_LEVELS 7 105 #define NUM_DPPCLK_DPM_LEVELS 7 106 #define NUM_SOCCLK_DPM_LEVELS 7 107 #define NUM_ISPICLK_DPM_LEVELS 7 108 #define NUM_ISPXCLK_DPM_LEVELS 7 109 #define NUM_VCN_DPM_LEVELS 5 110 #define NUM_FCLK_DPM_LEVELS 4 111 #define NUM_SOC_VOLTAGE_LEVELS 8 112 113 typedef struct { 114 uint32_t fclk; 115 uint32_t memclk; 116 uint32_t voltage; 117 } df_pstate_t; 118 119 typedef struct { 120 uint32_t vclk; 121 uint32_t dclk; 122 } vcn_clk_t; 123 124 //Freq in MHz 125 //Voltage in milli volts with 2 fractional bits 126 127 typedef struct { 128 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 129 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; 130 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; 131 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 132 uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS]; 133 uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS]; 134 vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS]; 135 136 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; 137 138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS]; 139 140 uint32_t MinGfxClk; 141 uint32_t MaxGfxClk; 142 143 uint8_t NumDfPstatesEnabled; 144 uint8_t NumDcfclkLevelsEnabled; 145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk 146 uint8_t NumSocClkLevelsEnabled; 147 148 uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk 149 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk 150 uint8_t spare[2]; 151 } DpmClocks_t; 152 153 154 // Throttler Status Bitmask 155 #define THROTTLER_STATUS_BIT_SPL 0 156 #define THROTTLER_STATUS_BIT_FPPT 1 157 #define THROTTLER_STATUS_BIT_SPPT 2 158 #define THROTTLER_STATUS_BIT_SPPT_APU 3 159 #define THROTTLER_STATUS_BIT_THM_CORE 4 160 #define THROTTLER_STATUS_BIT_THM_GFX 5 161 #define THROTTLER_STATUS_BIT_THM_SOC 6 162 #define THROTTLER_STATUS_BIT_TDC_VDD 7 163 #define THROTTLER_STATUS_BIT_TDC_SOC 8 164 #define THROTTLER_STATUS_BIT_TDC_GFX 9 165 #define THROTTLER_STATUS_BIT_TDC_CVIP 10 166 167 typedef struct { 168 uint16_t GfxclkFrequency; //[MHz] 169 uint16_t SocclkFrequency; //[MHz] 170 uint16_t VclkFrequency; //[MHz] 171 uint16_t DclkFrequency; //[MHz] 172 uint16_t MemclkFrequency; //[MHz] 173 uint16_t spare; 174 175 uint16_t GfxActivity; //[centi] 176 uint16_t UvdActivity; //[centi] 177 178 uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 179 uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 180 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 181 uint16_t CurrentSocketPower; //[mW] 182 183 //3rd party tools in Windows need info in the case of APUs 184 uint16_t CoreFrequency[8]; //[MHz] 185 uint16_t CorePower[8]; //[mW] 186 uint16_t CoreTemperature[8]; //[centi-Celsius] 187 uint16_t L3Frequency[2]; //[MHz] 188 uint16_t L3Temperature[2]; //[centi-Celsius] 189 190 uint16_t GfxTemperature; //[centi-Celsius] 191 uint16_t SocTemperature; //[centi-Celsius] 192 uint16_t EdgeTemperature; 193 uint16_t ThrottlerStatus; 194 } SmuMetrics_legacy_t; 195 196 typedef struct { 197 uint16_t GfxclkFrequency; //[MHz] 198 uint16_t SocclkFrequency; //[MHz] 199 uint16_t VclkFrequency; //[MHz] 200 uint16_t DclkFrequency; //[MHz] 201 uint16_t MemclkFrequency; //[MHz] 202 uint16_t spare; 203 204 uint16_t GfxActivity; //[centi] 205 uint16_t UvdActivity; //[centi] 206 uint16_t C0Residency[4]; //percentage 207 208 uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 209 uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 210 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX 211 uint16_t CurrentSocketPower; //[mW] 212 213 //3rd party tools in Windows need info in the case of APUs 214 uint16_t CoreFrequency[4]; //[MHz] 215 uint16_t CorePower[4]; //[mW] 216 uint16_t CoreTemperature[4]; //[centi-Celsius] 217 uint16_t L3Frequency[1]; //[MHz] 218 uint16_t L3Temperature[1]; //[centi-Celsius] 219 220 uint16_t GfxTemperature; //[centi-Celsius] 221 uint16_t SocTemperature; //[centi-Celsius] 222 uint16_t EdgeTemperature; 223 uint16_t ThrottlerStatus; 224 } SmuMetricsTable_t; 225 226 typedef struct { 227 SmuMetricsTable_t Current; 228 SmuMetricsTable_t Average; 229 //uint32_t AccCnt; 230 uint32_t SampleStartTime; 231 uint32_t SampleStopTime; 232 } SmuMetrics_t; 233 234 235 // Workload bits 236 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 237 #define WORKLOAD_PPLIB_VIDEO_BIT 2 238 #define WORKLOAD_PPLIB_VR_BIT 3 239 #define WORKLOAD_PPLIB_COMPUTE_BIT 4 240 #define WORKLOAD_PPLIB_CUSTOM_BIT 5 241 #define WORKLOAD_PPLIB_COUNT 6 242 243 #define TABLE_BIOS_IF 0 // Called by BIOS 244 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS 245 #define TABLE_CUSTOM_DPM 2 // Called by Driver 246 #define TABLE_SPARE1 3 247 #define TABLE_DPMCLOCKS 4 // Called by Driver 248 #define TABLE_SPARE2 5 // Called by Tools 249 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 250 #define TABLE_SMU_METRICS 7 // Called by Driver 251 #define TABLE_COUNT 8 252 253 //ISP tile definitions 254 typedef enum { 255 TILE_ISPX = 0, // ISPX 256 TILE_ISPM, // ISPM 257 TILE_ISPC, // ISPCORE 258 TILE_ISPPRE, // ISPPRE 259 TILE_ISPPOST, // ISPPOST 260 TILE_MAX 261 } TILE_NUM_e; 262 263 // Tile Selection (Based on arguments) 264 #define TILE_SEL_ISPX (1<<(TILE_ISPX)) 265 #define TILE_SEL_ISPM (1<<(TILE_ISPM)) 266 #define TILE_SEL_ISPC (1<<(TILE_ISPC)) 267 #define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE)) 268 #define TILE_SEL_ISPPOST (1<<(TILE_ISPPOST)) 269 270 // Mask for ISP tiles in PGFSM PWR Status Registers 271 //Bit[1:0] maps to ISPX, (ISPX) 272 //Bit[3:2] maps to ISPM, (ISPM) 273 //Bit[5:4] maps to ISPCORE, (ISPCORE) 274 //Bit[7:6] maps to ISPPRE, (ISPPRE) 275 //Bit[9:8] maps to POST, (ISPPOST 276 #define TILE_ISPX_MASK ((1<<0) | (1<<1)) 277 #define TILE_ISPM_MASK ((1<<2) | (1<<3)) 278 #define TILE_ISPC_MASK ((1<<4) | (1<<5)) 279 #define TILE_ISPPRE_MASK ((1<<6) | (1<<7)) 280 #define TILE_ISPPOST_MASK ((1<<8) | (1<<9)) 281 282 #endif 283