1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_5_ppt.h" 41 #include "amd_pcie.h" 42 43 /* 44 * DO NOT use these for err/warn/info/debug messages. 45 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 46 * They are more MGPU friendly. 47 */ 48 #undef pr_err 49 #undef pr_warn 50 #undef pr_info 51 #undef pr_debug 52 53 static const struct amd_pm_funcs swsmu_pm_funcs; 54 static int smu_force_smuclk_levels(struct smu_context *smu, 55 enum smu_clk_type clk_type, 56 uint32_t mask); 57 static int smu_handle_task(struct smu_context *smu, 58 enum amd_dpm_forced_level level, 59 enum amd_pp_task task_id); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(void *handle, u32 value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 72 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 73 return -EOPNOTSUPP; 74 75 return smu_get_pp_feature_mask(smu, buf); 76 } 77 78 static int smu_sys_set_pp_feature_mask(void *handle, 79 uint64_t new_mask) 80 { 81 struct smu_context *smu = handle; 82 83 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 84 return -EOPNOTSUPP; 85 86 return smu_set_pp_feature_mask(smu, new_mask); 87 } 88 89 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 90 { 91 if (!smu->ppt_funcs->get_gfx_off_status) 92 return -EINVAL; 93 94 *value = smu_get_gfx_off_status(smu); 95 96 return 0; 97 } 98 99 int smu_set_soft_freq_range(struct smu_context *smu, 100 enum smu_clk_type clk_type, 101 uint32_t min, 102 uint32_t max) 103 { 104 int ret = 0; 105 106 if (smu->ppt_funcs->set_soft_freq_limited_range) 107 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 108 clk_type, 109 min, 110 max); 111 112 return ret; 113 } 114 115 int smu_get_dpm_freq_range(struct smu_context *smu, 116 enum smu_clk_type clk_type, 117 uint32_t *min, 118 uint32_t *max) 119 { 120 int ret = -ENOTSUPP; 121 122 if (!min && !max) 123 return -EINVAL; 124 125 if (smu->ppt_funcs->get_dpm_ultimate_freq) 126 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 127 clk_type, 128 min, 129 max); 130 131 return ret; 132 } 133 134 static u32 smu_get_mclk(void *handle, bool low) 135 { 136 struct smu_context *smu = handle; 137 uint32_t clk_freq; 138 int ret = 0; 139 140 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 141 low ? &clk_freq : NULL, 142 !low ? &clk_freq : NULL); 143 if (ret) 144 return 0; 145 return clk_freq * 100; 146 } 147 148 static u32 smu_get_sclk(void *handle, bool low) 149 { 150 struct smu_context *smu = handle; 151 uint32_t clk_freq; 152 int ret = 0; 153 154 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 155 low ? &clk_freq : NULL, 156 !low ? &clk_freq : NULL); 157 if (ret) 158 return 0; 159 return clk_freq * 100; 160 } 161 162 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 163 bool enable) 164 { 165 struct smu_power_context *smu_power = &smu->smu_power; 166 struct smu_power_gate *power_gate = &smu_power->power_gate; 167 int ret = 0; 168 169 if (!smu->ppt_funcs->dpm_set_vcn_enable) 170 return 0; 171 172 if (atomic_read(&power_gate->vcn_gated) ^ enable) 173 return 0; 174 175 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 176 if (!ret) 177 atomic_set(&power_gate->vcn_gated, !enable); 178 179 return ret; 180 } 181 182 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 183 bool enable) 184 { 185 struct smu_power_context *smu_power = &smu->smu_power; 186 struct smu_power_gate *power_gate = &smu_power->power_gate; 187 int ret = 0; 188 189 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 190 return 0; 191 192 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 193 return 0; 194 195 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 196 if (!ret) 197 atomic_set(&power_gate->jpeg_gated, !enable); 198 199 return ret; 200 } 201 202 /** 203 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 204 * 205 * @handle: smu_context pointer 206 * @block_type: the IP block to power gate/ungate 207 * @gate: to power gate if true, ungate otherwise 208 * 209 * This API uses no smu->mutex lock protection due to: 210 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 211 * This is guarded to be race condition free by the caller. 212 * 2. Or get called on user setting request of power_dpm_force_performance_level. 213 * Under this case, the smu->mutex lock protection is already enforced on 214 * the parent API smu_force_performance_level of the call path. 215 */ 216 static int smu_dpm_set_power_gate(void *handle, 217 uint32_t block_type, 218 bool gate) 219 { 220 struct smu_context *smu = handle; 221 int ret = 0; 222 223 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 224 dev_WARN(smu->adev->dev, 225 "SMU uninitialized but power %s requested for %u!\n", 226 gate ? "gate" : "ungate", block_type); 227 return -EOPNOTSUPP; 228 } 229 230 switch (block_type) { 231 /* 232 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 233 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 234 */ 235 case AMD_IP_BLOCK_TYPE_UVD: 236 case AMD_IP_BLOCK_TYPE_VCN: 237 ret = smu_dpm_set_vcn_enable(smu, !gate); 238 if (ret) 239 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 240 gate ? "gate" : "ungate"); 241 break; 242 case AMD_IP_BLOCK_TYPE_GFX: 243 ret = smu_gfx_off_control(smu, gate); 244 if (ret) 245 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 246 gate ? "enable" : "disable"); 247 break; 248 case AMD_IP_BLOCK_TYPE_SDMA: 249 ret = smu_powergate_sdma(smu, gate); 250 if (ret) 251 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 252 gate ? "gate" : "ungate"); 253 break; 254 case AMD_IP_BLOCK_TYPE_JPEG: 255 ret = smu_dpm_set_jpeg_enable(smu, !gate); 256 if (ret) 257 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 258 gate ? "gate" : "ungate"); 259 break; 260 default: 261 dev_err(smu->adev->dev, "Unsupported block type!\n"); 262 return -EINVAL; 263 } 264 265 return ret; 266 } 267 268 /** 269 * smu_set_user_clk_dependencies - set user profile clock dependencies 270 * 271 * @smu: smu_context pointer 272 * @clk: enum smu_clk_type type 273 * 274 * Enable/Disable the clock dependency for the @clk type. 275 */ 276 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 277 { 278 if (smu->adev->in_suspend) 279 return; 280 281 if (clk == SMU_MCLK) { 282 smu->user_dpm_profile.clk_dependency = 0; 283 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 284 } else if (clk == SMU_FCLK) { 285 /* MCLK takes precedence over FCLK */ 286 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 287 return; 288 289 smu->user_dpm_profile.clk_dependency = 0; 290 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 291 } else if (clk == SMU_SOCCLK) { 292 /* MCLK takes precedence over SOCCLK */ 293 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 294 return; 295 296 smu->user_dpm_profile.clk_dependency = 0; 297 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 298 } else 299 /* Add clk dependencies here, if any */ 300 return; 301 } 302 303 /** 304 * smu_restore_dpm_user_profile - reinstate user dpm profile 305 * 306 * @smu: smu_context pointer 307 * 308 * Restore the saved user power configurations include power limit, 309 * clock frequencies, fan control mode and fan speed. 310 */ 311 static void smu_restore_dpm_user_profile(struct smu_context *smu) 312 { 313 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 314 int ret = 0; 315 316 if (!smu->adev->in_suspend) 317 return; 318 319 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 320 return; 321 322 /* Enable restore flag */ 323 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 324 325 /* set the user dpm power limit */ 326 if (smu->user_dpm_profile.power_limit) { 327 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 328 if (ret) 329 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 330 } 331 332 /* set the user dpm clock configurations */ 333 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 334 enum smu_clk_type clk_type; 335 336 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 337 /* 338 * Iterate over smu clk type and force the saved user clk 339 * configs, skip if clock dependency is enabled 340 */ 341 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 342 smu->user_dpm_profile.clk_mask[clk_type]) { 343 ret = smu_force_smuclk_levels(smu, clk_type, 344 smu->user_dpm_profile.clk_mask[clk_type]); 345 if (ret) 346 dev_err(smu->adev->dev, 347 "Failed to set clock type = %d\n", clk_type); 348 } 349 } 350 } 351 352 /* set the user dpm fan configurations */ 353 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 354 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 355 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 356 if (ret != -EOPNOTSUPP) { 357 smu->user_dpm_profile.fan_speed_pwm = 0; 358 smu->user_dpm_profile.fan_speed_rpm = 0; 359 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 360 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 361 } 362 363 if (smu->user_dpm_profile.fan_speed_pwm) { 364 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 365 if (ret != -EOPNOTSUPP) 366 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 367 } 368 369 if (smu->user_dpm_profile.fan_speed_rpm) { 370 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 371 if (ret != -EOPNOTSUPP) 372 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 373 } 374 } 375 376 /* Restore user customized OD settings */ 377 if (smu->user_dpm_profile.user_od) { 378 if (smu->ppt_funcs->restore_user_od_settings) { 379 ret = smu->ppt_funcs->restore_user_od_settings(smu); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 382 } 383 } 384 385 /* Disable restore flag */ 386 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 387 } 388 389 static int smu_get_power_num_states(void *handle, 390 struct pp_states_info *state_info) 391 { 392 if (!state_info) 393 return -EINVAL; 394 395 /* not support power state */ 396 memset(state_info, 0, sizeof(struct pp_states_info)); 397 state_info->nums = 1; 398 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 399 400 return 0; 401 } 402 403 bool is_support_sw_smu(struct amdgpu_device *adev) 404 { 405 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 406 if (adev->asic_type == CHIP_VEGA20) 407 return false; 408 409 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 410 return true; 411 412 return false; 413 } 414 415 bool is_support_cclk_dpm(struct amdgpu_device *adev) 416 { 417 struct smu_context *smu = adev->powerplay.pp_handle; 418 419 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 420 return false; 421 422 return true; 423 } 424 425 426 static int smu_sys_get_pp_table(void *handle, 427 char **table) 428 { 429 struct smu_context *smu = handle; 430 struct smu_table_context *smu_table = &smu->smu_table; 431 432 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 433 return -EOPNOTSUPP; 434 435 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 436 return -EINVAL; 437 438 if (smu_table->hardcode_pptable) 439 *table = smu_table->hardcode_pptable; 440 else 441 *table = smu_table->power_play_table; 442 443 return smu_table->power_play_table_size; 444 } 445 446 static int smu_sys_set_pp_table(void *handle, 447 const char *buf, 448 size_t size) 449 { 450 struct smu_context *smu = handle; 451 struct smu_table_context *smu_table = &smu->smu_table; 452 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 453 int ret = 0; 454 455 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 456 return -EOPNOTSUPP; 457 458 if (header->usStructureSize != size) { 459 dev_err(smu->adev->dev, "pp table size not matched !\n"); 460 return -EIO; 461 } 462 463 if (!smu_table->hardcode_pptable) { 464 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 465 if (!smu_table->hardcode_pptable) 466 return -ENOMEM; 467 } 468 469 memcpy(smu_table->hardcode_pptable, buf, size); 470 smu_table->power_play_table = smu_table->hardcode_pptable; 471 smu_table->power_play_table_size = size; 472 473 /* 474 * Special hw_fini action(for Navi1x, the DPMs disablement will be 475 * skipped) may be needed for custom pptable uploading. 476 */ 477 smu->uploading_custom_pp_table = true; 478 479 ret = smu_reset(smu); 480 if (ret) 481 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 482 483 smu->uploading_custom_pp_table = false; 484 485 return ret; 486 } 487 488 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 489 { 490 struct smu_feature *feature = &smu->smu_feature; 491 int ret = 0; 492 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 493 494 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 495 496 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 497 SMU_FEATURE_MAX/32); 498 if (ret) 499 return ret; 500 501 bitmap_or(feature->allowed, feature->allowed, 502 (unsigned long *)allowed_feature_mask, 503 feature->feature_num); 504 505 return ret; 506 } 507 508 static int smu_set_funcs(struct amdgpu_device *adev) 509 { 510 struct smu_context *smu = adev->powerplay.pp_handle; 511 512 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 513 smu->od_enabled = true; 514 515 switch (adev->ip_versions[MP1_HWIP][0]) { 516 case IP_VERSION(11, 0, 0): 517 case IP_VERSION(11, 0, 5): 518 case IP_VERSION(11, 0, 9): 519 navi10_set_ppt_funcs(smu); 520 break; 521 case IP_VERSION(11, 0, 7): 522 case IP_VERSION(11, 0, 11): 523 case IP_VERSION(11, 0, 12): 524 case IP_VERSION(11, 0, 13): 525 sienna_cichlid_set_ppt_funcs(smu); 526 break; 527 case IP_VERSION(12, 0, 0): 528 case IP_VERSION(12, 0, 1): 529 renoir_set_ppt_funcs(smu); 530 break; 531 case IP_VERSION(11, 5, 0): 532 vangogh_set_ppt_funcs(smu); 533 break; 534 case IP_VERSION(13, 0, 1): 535 case IP_VERSION(13, 0, 3): 536 case IP_VERSION(13, 0, 8): 537 yellow_carp_set_ppt_funcs(smu); 538 break; 539 case IP_VERSION(13, 0, 5): 540 smu_v13_0_5_set_ppt_funcs(smu); 541 break; 542 case IP_VERSION(11, 0, 8): 543 cyan_skillfish_set_ppt_funcs(smu); 544 break; 545 case IP_VERSION(11, 0, 2): 546 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 547 arcturus_set_ppt_funcs(smu); 548 /* OD is not supported on Arcturus */ 549 smu->od_enabled =false; 550 break; 551 case IP_VERSION(13, 0, 2): 552 aldebaran_set_ppt_funcs(smu); 553 /* Enable pp_od_clk_voltage node */ 554 smu->od_enabled = true; 555 break; 556 default: 557 return -EINVAL; 558 } 559 560 return 0; 561 } 562 563 static int smu_early_init(void *handle) 564 { 565 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 566 struct smu_context *smu; 567 568 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 569 if (!smu) 570 return -ENOMEM; 571 572 smu->adev = adev; 573 smu->pm_enabled = !!amdgpu_dpm; 574 smu->is_apu = false; 575 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 576 smu->smu_baco.platform_support = false; 577 smu->user_dpm_profile.fan_mode = -1; 578 579 adev->powerplay.pp_handle = smu; 580 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 581 582 return smu_set_funcs(adev); 583 } 584 585 static int smu_set_default_dpm_table(struct smu_context *smu) 586 { 587 struct smu_power_context *smu_power = &smu->smu_power; 588 struct smu_power_gate *power_gate = &smu_power->power_gate; 589 int vcn_gate, jpeg_gate; 590 int ret = 0; 591 592 if (!smu->ppt_funcs->set_default_dpm_table) 593 return 0; 594 595 vcn_gate = atomic_read(&power_gate->vcn_gated); 596 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 597 598 ret = smu_dpm_set_vcn_enable(smu, true); 599 if (ret) 600 return ret; 601 602 ret = smu_dpm_set_jpeg_enable(smu, true); 603 if (ret) 604 goto err_out; 605 606 ret = smu->ppt_funcs->set_default_dpm_table(smu); 607 if (ret) 608 dev_err(smu->adev->dev, 609 "Failed to setup default dpm clock tables!\n"); 610 611 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 612 err_out: 613 smu_dpm_set_vcn_enable(smu, !vcn_gate); 614 return ret; 615 } 616 617 static int smu_apply_default_config_table_settings(struct smu_context *smu) 618 { 619 struct amdgpu_device *adev = smu->adev; 620 int ret = 0; 621 622 ret = smu_get_default_config_table_settings(smu, 623 &adev->pm.config_table); 624 if (ret) 625 return ret; 626 627 return smu_set_config_table(smu, &adev->pm.config_table); 628 } 629 630 static int smu_late_init(void *handle) 631 { 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633 struct smu_context *smu = adev->powerplay.pp_handle; 634 int ret = 0; 635 636 smu_set_fine_grain_gfx_freq_parameters(smu); 637 638 if (!smu->pm_enabled) 639 return 0; 640 641 ret = smu_post_init(smu); 642 if (ret) { 643 dev_err(adev->dev, "Failed to post smu init!\n"); 644 return ret; 645 } 646 647 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 648 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 649 return 0; 650 651 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 652 ret = smu_set_default_od_settings(smu); 653 if (ret) { 654 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 655 return ret; 656 } 657 } 658 659 ret = smu_populate_umd_state_clk(smu); 660 if (ret) { 661 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 662 return ret; 663 } 664 665 ret = smu_get_asic_power_limits(smu, 666 &smu->current_power_limit, 667 &smu->default_power_limit, 668 &smu->max_power_limit); 669 if (ret) { 670 dev_err(adev->dev, "Failed to get asic power limits!\n"); 671 return ret; 672 } 673 674 if (!amdgpu_sriov_vf(adev)) 675 smu_get_unique_id(smu); 676 677 smu_get_fan_parameters(smu); 678 679 smu_handle_task(smu, 680 smu->smu_dpm.dpm_level, 681 AMD_PP_TASK_COMPLETE_INIT); 682 683 ret = smu_apply_default_config_table_settings(smu); 684 if (ret && (ret != -EOPNOTSUPP)) { 685 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 686 return ret; 687 } 688 689 smu_restore_dpm_user_profile(smu); 690 691 return 0; 692 } 693 694 static int smu_init_fb_allocations(struct smu_context *smu) 695 { 696 struct amdgpu_device *adev = smu->adev; 697 struct smu_table_context *smu_table = &smu->smu_table; 698 struct smu_table *tables = smu_table->tables; 699 struct smu_table *driver_table = &(smu_table->driver_table); 700 uint32_t max_table_size = 0; 701 int ret, i; 702 703 /* VRAM allocation for tool table */ 704 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 705 ret = amdgpu_bo_create_kernel(adev, 706 tables[SMU_TABLE_PMSTATUSLOG].size, 707 tables[SMU_TABLE_PMSTATUSLOG].align, 708 tables[SMU_TABLE_PMSTATUSLOG].domain, 709 &tables[SMU_TABLE_PMSTATUSLOG].bo, 710 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 711 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 712 if (ret) { 713 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 714 return ret; 715 } 716 } 717 718 /* VRAM allocation for driver table */ 719 for (i = 0; i < SMU_TABLE_COUNT; i++) { 720 if (tables[i].size == 0) 721 continue; 722 723 if (i == SMU_TABLE_PMSTATUSLOG) 724 continue; 725 726 if (max_table_size < tables[i].size) 727 max_table_size = tables[i].size; 728 } 729 730 driver_table->size = max_table_size; 731 driver_table->align = PAGE_SIZE; 732 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 733 734 ret = amdgpu_bo_create_kernel(adev, 735 driver_table->size, 736 driver_table->align, 737 driver_table->domain, 738 &driver_table->bo, 739 &driver_table->mc_address, 740 &driver_table->cpu_addr); 741 if (ret) { 742 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 743 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 744 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 745 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 746 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 747 } 748 749 return ret; 750 } 751 752 static int smu_fini_fb_allocations(struct smu_context *smu) 753 { 754 struct smu_table_context *smu_table = &smu->smu_table; 755 struct smu_table *tables = smu_table->tables; 756 struct smu_table *driver_table = &(smu_table->driver_table); 757 758 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 759 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 760 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 761 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 762 763 amdgpu_bo_free_kernel(&driver_table->bo, 764 &driver_table->mc_address, 765 &driver_table->cpu_addr); 766 767 return 0; 768 } 769 770 /** 771 * smu_alloc_memory_pool - allocate memory pool in the system memory 772 * 773 * @smu: amdgpu_device pointer 774 * 775 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 776 * and DramLogSetDramAddr can notify it changed. 777 * 778 * Returns 0 on success, error on failure. 779 */ 780 static int smu_alloc_memory_pool(struct smu_context *smu) 781 { 782 struct amdgpu_device *adev = smu->adev; 783 struct smu_table_context *smu_table = &smu->smu_table; 784 struct smu_table *memory_pool = &smu_table->memory_pool; 785 uint64_t pool_size = smu->pool_size; 786 int ret = 0; 787 788 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 789 return ret; 790 791 memory_pool->size = pool_size; 792 memory_pool->align = PAGE_SIZE; 793 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 794 795 switch (pool_size) { 796 case SMU_MEMORY_POOL_SIZE_256_MB: 797 case SMU_MEMORY_POOL_SIZE_512_MB: 798 case SMU_MEMORY_POOL_SIZE_1_GB: 799 case SMU_MEMORY_POOL_SIZE_2_GB: 800 ret = amdgpu_bo_create_kernel(adev, 801 memory_pool->size, 802 memory_pool->align, 803 memory_pool->domain, 804 &memory_pool->bo, 805 &memory_pool->mc_address, 806 &memory_pool->cpu_addr); 807 if (ret) 808 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 809 break; 810 default: 811 break; 812 } 813 814 return ret; 815 } 816 817 static int smu_free_memory_pool(struct smu_context *smu) 818 { 819 struct smu_table_context *smu_table = &smu->smu_table; 820 struct smu_table *memory_pool = &smu_table->memory_pool; 821 822 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 823 return 0; 824 825 amdgpu_bo_free_kernel(&memory_pool->bo, 826 &memory_pool->mc_address, 827 &memory_pool->cpu_addr); 828 829 memset(memory_pool, 0, sizeof(struct smu_table)); 830 831 return 0; 832 } 833 834 static int smu_alloc_dummy_read_table(struct smu_context *smu) 835 { 836 struct smu_table_context *smu_table = &smu->smu_table; 837 struct smu_table *dummy_read_1_table = 838 &smu_table->dummy_read_1_table; 839 struct amdgpu_device *adev = smu->adev; 840 int ret = 0; 841 842 dummy_read_1_table->size = 0x40000; 843 dummy_read_1_table->align = PAGE_SIZE; 844 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 845 846 ret = amdgpu_bo_create_kernel(adev, 847 dummy_read_1_table->size, 848 dummy_read_1_table->align, 849 dummy_read_1_table->domain, 850 &dummy_read_1_table->bo, 851 &dummy_read_1_table->mc_address, 852 &dummy_read_1_table->cpu_addr); 853 if (ret) 854 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 855 856 return ret; 857 } 858 859 static void smu_free_dummy_read_table(struct smu_context *smu) 860 { 861 struct smu_table_context *smu_table = &smu->smu_table; 862 struct smu_table *dummy_read_1_table = 863 &smu_table->dummy_read_1_table; 864 865 866 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 867 &dummy_read_1_table->mc_address, 868 &dummy_read_1_table->cpu_addr); 869 870 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 871 } 872 873 static int smu_smc_table_sw_init(struct smu_context *smu) 874 { 875 int ret; 876 877 /** 878 * Create smu_table structure, and init smc tables such as 879 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 880 */ 881 ret = smu_init_smc_tables(smu); 882 if (ret) { 883 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 884 return ret; 885 } 886 887 /** 888 * Create smu_power_context structure, and allocate smu_dpm_context and 889 * context size to fill the smu_power_context data. 890 */ 891 ret = smu_init_power(smu); 892 if (ret) { 893 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 894 return ret; 895 } 896 897 /* 898 * allocate vram bos to store smc table contents. 899 */ 900 ret = smu_init_fb_allocations(smu); 901 if (ret) 902 return ret; 903 904 ret = smu_alloc_memory_pool(smu); 905 if (ret) 906 return ret; 907 908 ret = smu_alloc_dummy_read_table(smu); 909 if (ret) 910 return ret; 911 912 ret = smu_i2c_init(smu); 913 if (ret) 914 return ret; 915 916 return 0; 917 } 918 919 static int smu_smc_table_sw_fini(struct smu_context *smu) 920 { 921 int ret; 922 923 smu_i2c_fini(smu); 924 925 smu_free_dummy_read_table(smu); 926 927 ret = smu_free_memory_pool(smu); 928 if (ret) 929 return ret; 930 931 ret = smu_fini_fb_allocations(smu); 932 if (ret) 933 return ret; 934 935 ret = smu_fini_power(smu); 936 if (ret) { 937 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 938 return ret; 939 } 940 941 ret = smu_fini_smc_tables(smu); 942 if (ret) { 943 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 944 return ret; 945 } 946 947 return 0; 948 } 949 950 static void smu_throttling_logging_work_fn(struct work_struct *work) 951 { 952 struct smu_context *smu = container_of(work, struct smu_context, 953 throttling_logging_work); 954 955 smu_log_thermal_throttling(smu); 956 } 957 958 static void smu_interrupt_work_fn(struct work_struct *work) 959 { 960 struct smu_context *smu = container_of(work, struct smu_context, 961 interrupt_work); 962 963 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 964 smu->ppt_funcs->interrupt_work(smu); 965 } 966 967 static int smu_sw_init(void *handle) 968 { 969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 970 struct smu_context *smu = adev->powerplay.pp_handle; 971 int ret; 972 973 smu->pool_size = adev->pm.smu_prv_buffer_size; 974 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 975 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 976 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 977 978 mutex_init(&smu->message_lock); 979 980 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 981 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 982 atomic64_set(&smu->throttle_int_counter, 0); 983 smu->watermarks_bitmap = 0; 984 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 985 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 986 987 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 988 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 989 990 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 991 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 992 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 993 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 994 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 995 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 996 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 997 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 998 999 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1000 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1001 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1002 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1003 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1004 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1005 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1006 smu->display_config = &adev->pm.pm_display_cfg; 1007 1008 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1009 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1010 1011 ret = smu_init_microcode(smu); 1012 if (ret) { 1013 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1014 return ret; 1015 } 1016 1017 ret = smu_smc_table_sw_init(smu); 1018 if (ret) { 1019 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1020 return ret; 1021 } 1022 1023 ret = smu_register_irq_handler(smu); 1024 if (ret) { 1025 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1026 return ret; 1027 } 1028 1029 /* If there is no way to query fan control mode, fan control is not supported */ 1030 if (!smu->ppt_funcs->get_fan_control_mode) 1031 smu->adev->pm.no_fan = true; 1032 1033 return 0; 1034 } 1035 1036 static int smu_sw_fini(void *handle) 1037 { 1038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1039 struct smu_context *smu = adev->powerplay.pp_handle; 1040 int ret; 1041 1042 ret = smu_smc_table_sw_fini(smu); 1043 if (ret) { 1044 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1045 return ret; 1046 } 1047 1048 smu_fini_microcode(smu); 1049 1050 return 0; 1051 } 1052 1053 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1054 { 1055 struct amdgpu_device *adev = smu->adev; 1056 struct smu_temperature_range *range = 1057 &smu->thermal_range; 1058 int ret = 0; 1059 1060 if (!smu->ppt_funcs->get_thermal_temperature_range) 1061 return 0; 1062 1063 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1064 if (ret) 1065 return ret; 1066 1067 adev->pm.dpm.thermal.min_temp = range->min; 1068 adev->pm.dpm.thermal.max_temp = range->max; 1069 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1070 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1071 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1072 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1073 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1074 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1075 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1076 1077 return ret; 1078 } 1079 1080 static int smu_smc_hw_setup(struct smu_context *smu) 1081 { 1082 struct smu_feature *feature = &smu->smu_feature; 1083 struct amdgpu_device *adev = smu->adev; 1084 uint32_t pcie_gen = 0, pcie_width = 0; 1085 uint64_t features_supported; 1086 int ret = 0; 1087 1088 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1089 dev_info(adev->dev, "dpm has been enabled\n"); 1090 /* this is needed specifically */ 1091 switch (adev->ip_versions[MP1_HWIP][0]) { 1092 case IP_VERSION(11, 0, 7): 1093 case IP_VERSION(11, 0, 11): 1094 case IP_VERSION(11, 5, 0): 1095 case IP_VERSION(11, 0, 12): 1096 ret = smu_system_features_control(smu, true); 1097 if (ret) 1098 dev_err(adev->dev, "Failed system features control!\n"); 1099 break; 1100 default: 1101 break; 1102 } 1103 return ret; 1104 } 1105 1106 ret = smu_init_display_count(smu, 0); 1107 if (ret) { 1108 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1109 return ret; 1110 } 1111 1112 ret = smu_set_driver_table_location(smu); 1113 if (ret) { 1114 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1115 return ret; 1116 } 1117 1118 /* 1119 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1120 */ 1121 ret = smu_set_tool_table_location(smu); 1122 if (ret) { 1123 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1124 return ret; 1125 } 1126 1127 /* 1128 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1129 * pool location. 1130 */ 1131 ret = smu_notify_memory_pool_location(smu); 1132 if (ret) { 1133 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1134 return ret; 1135 } 1136 1137 /* smu_dump_pptable(smu); */ 1138 /* 1139 * Copy pptable bo in the vram to smc with SMU MSGs such as 1140 * SetDriverDramAddr and TransferTableDram2Smu. 1141 */ 1142 ret = smu_write_pptable(smu); 1143 if (ret) { 1144 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1145 return ret; 1146 } 1147 1148 /* issue Run*Btc msg */ 1149 ret = smu_run_btc(smu); 1150 if (ret) 1151 return ret; 1152 1153 ret = smu_feature_set_allowed_mask(smu); 1154 if (ret) { 1155 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1156 return ret; 1157 } 1158 1159 ret = smu_system_features_control(smu, true); 1160 if (ret) { 1161 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1162 return ret; 1163 } 1164 1165 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1166 if (ret) { 1167 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1168 return ret; 1169 } 1170 bitmap_copy(feature->supported, 1171 (unsigned long *)&features_supported, 1172 feature->feature_num); 1173 1174 if (!smu_is_dpm_running(smu)) 1175 dev_info(adev->dev, "dpm has been disabled\n"); 1176 1177 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1178 pcie_gen = 3; 1179 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1180 pcie_gen = 2; 1181 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1182 pcie_gen = 1; 1183 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1184 pcie_gen = 0; 1185 1186 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1187 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1188 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1189 */ 1190 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1191 pcie_width = 6; 1192 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1193 pcie_width = 5; 1194 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1195 pcie_width = 4; 1196 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1197 pcie_width = 3; 1198 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1199 pcie_width = 2; 1200 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1201 pcie_width = 1; 1202 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1203 if (ret) { 1204 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1205 return ret; 1206 } 1207 1208 ret = smu_get_thermal_temperature_range(smu); 1209 if (ret) { 1210 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1211 return ret; 1212 } 1213 1214 ret = smu_enable_thermal_alert(smu); 1215 if (ret) { 1216 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1217 return ret; 1218 } 1219 1220 /* 1221 * Set initialized values (get from vbios) to dpm tables context such as 1222 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1223 * type of clks. 1224 */ 1225 ret = smu_set_default_dpm_table(smu); 1226 if (ret) { 1227 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1228 return ret; 1229 } 1230 1231 ret = smu_notify_display_change(smu); 1232 if (ret) { 1233 dev_err(adev->dev, "Failed to notify display change!\n"); 1234 return ret; 1235 } 1236 1237 /* 1238 * Set min deep sleep dce fclk with bootup value from vbios via 1239 * SetMinDeepSleepDcefclk MSG. 1240 */ 1241 ret = smu_set_min_dcef_deep_sleep(smu, 1242 smu->smu_table.boot_values.dcefclk / 100); 1243 1244 return ret; 1245 } 1246 1247 static int smu_start_smc_engine(struct smu_context *smu) 1248 { 1249 struct amdgpu_device *adev = smu->adev; 1250 int ret = 0; 1251 1252 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1253 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1254 if (smu->ppt_funcs->load_microcode) { 1255 ret = smu->ppt_funcs->load_microcode(smu); 1256 if (ret) 1257 return ret; 1258 } 1259 } 1260 } 1261 1262 if (smu->ppt_funcs->check_fw_status) { 1263 ret = smu->ppt_funcs->check_fw_status(smu); 1264 if (ret) { 1265 dev_err(adev->dev, "SMC is not ready\n"); 1266 return ret; 1267 } 1268 } 1269 1270 /* 1271 * Send msg GetDriverIfVersion to check if the return value is equal 1272 * with DRIVER_IF_VERSION of smc header. 1273 */ 1274 ret = smu_check_fw_version(smu); 1275 if (ret) 1276 return ret; 1277 1278 return ret; 1279 } 1280 1281 static int smu_hw_init(void *handle) 1282 { 1283 int ret; 1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1285 struct smu_context *smu = adev->powerplay.pp_handle; 1286 1287 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1288 smu->pm_enabled = false; 1289 return 0; 1290 } 1291 1292 ret = smu_start_smc_engine(smu); 1293 if (ret) { 1294 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1295 return ret; 1296 } 1297 1298 if (smu->is_apu) { 1299 smu_dpm_set_vcn_enable(smu, true); 1300 smu_dpm_set_jpeg_enable(smu, true); 1301 smu_set_gfx_cgpg(smu, true); 1302 } 1303 1304 if (!smu->pm_enabled) 1305 return 0; 1306 1307 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1308 ret = smu_get_vbios_bootup_values(smu); 1309 if (ret) { 1310 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1311 return ret; 1312 } 1313 1314 ret = smu_setup_pptable(smu); 1315 if (ret) { 1316 dev_err(adev->dev, "Failed to setup pptable!\n"); 1317 return ret; 1318 } 1319 1320 ret = smu_get_driver_allowed_feature_mask(smu); 1321 if (ret) 1322 return ret; 1323 1324 ret = smu_smc_hw_setup(smu); 1325 if (ret) { 1326 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1327 return ret; 1328 } 1329 1330 /* 1331 * Move maximum sustainable clock retrieving here considering 1332 * 1. It is not needed on resume(from S3). 1333 * 2. DAL settings come between .hw_init and .late_init of SMU. 1334 * And DAL needs to know the maximum sustainable clocks. Thus 1335 * it cannot be put in .late_init(). 1336 */ 1337 ret = smu_init_max_sustainable_clocks(smu); 1338 if (ret) { 1339 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1340 return ret; 1341 } 1342 1343 adev->pm.dpm_enabled = true; 1344 1345 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1346 1347 return 0; 1348 } 1349 1350 static int smu_disable_dpms(struct smu_context *smu) 1351 { 1352 struct amdgpu_device *adev = smu->adev; 1353 int ret = 0; 1354 /* 1355 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1356 * the workaround which always reset the asic in suspend. 1357 * It's likely that workaround will be dropped in the future. 1358 * Then the change here should be dropped together. 1359 */ 1360 bool use_baco = !smu->is_apu && 1361 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1362 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1363 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1364 1365 /* 1366 * For custom pptable uploading, skip the DPM features 1367 * disable process on Navi1x ASICs. 1368 * - As the gfx related features are under control of 1369 * RLC on those ASICs. RLC reinitialization will be 1370 * needed to reenable them. That will cost much more 1371 * efforts. 1372 * 1373 * - SMU firmware can handle the DPM reenablement 1374 * properly. 1375 */ 1376 if (smu->uploading_custom_pp_table) { 1377 switch (adev->ip_versions[MP1_HWIP][0]) { 1378 case IP_VERSION(11, 0, 0): 1379 case IP_VERSION(11, 0, 5): 1380 case IP_VERSION(11, 0, 9): 1381 case IP_VERSION(11, 0, 7): 1382 case IP_VERSION(11, 0, 11): 1383 case IP_VERSION(11, 5, 0): 1384 case IP_VERSION(11, 0, 12): 1385 case IP_VERSION(11, 0, 13): 1386 return 0; 1387 default: 1388 break; 1389 } 1390 } 1391 1392 /* 1393 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1394 * on BACO in. Driver involvement is unnecessary. 1395 */ 1396 if (use_baco) { 1397 switch (adev->ip_versions[MP1_HWIP][0]) { 1398 case IP_VERSION(11, 0, 7): 1399 case IP_VERSION(11, 0, 0): 1400 case IP_VERSION(11, 0, 5): 1401 case IP_VERSION(11, 0, 9): 1402 return 0; 1403 default: 1404 break; 1405 } 1406 } 1407 1408 /* 1409 * For gpu reset, runpm and hibernation through BACO, 1410 * BACO feature has to be kept enabled. 1411 */ 1412 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1413 ret = smu_disable_all_features_with_exception(smu, 1414 SMU_FEATURE_BACO_BIT); 1415 if (ret) 1416 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1417 } else { 1418 ret = smu_system_features_control(smu, false); 1419 if (ret) 1420 dev_err(adev->dev, "Failed to disable smu features.\n"); 1421 } 1422 1423 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1424 adev->gfx.rlc.funcs->stop) 1425 adev->gfx.rlc.funcs->stop(adev); 1426 1427 return ret; 1428 } 1429 1430 static int smu_smc_hw_cleanup(struct smu_context *smu) 1431 { 1432 struct amdgpu_device *adev = smu->adev; 1433 int ret = 0; 1434 1435 cancel_work_sync(&smu->throttling_logging_work); 1436 cancel_work_sync(&smu->interrupt_work); 1437 1438 ret = smu_disable_thermal_alert(smu); 1439 if (ret) { 1440 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1441 return ret; 1442 } 1443 1444 ret = smu_disable_dpms(smu); 1445 if (ret) { 1446 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1447 return ret; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int smu_hw_fini(void *handle) 1454 { 1455 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1456 struct smu_context *smu = adev->powerplay.pp_handle; 1457 1458 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1459 return 0; 1460 1461 smu_dpm_set_vcn_enable(smu, false); 1462 smu_dpm_set_jpeg_enable(smu, false); 1463 1464 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1465 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1466 1467 if (!smu->pm_enabled) 1468 return 0; 1469 1470 adev->pm.dpm_enabled = false; 1471 1472 return smu_smc_hw_cleanup(smu); 1473 } 1474 1475 static void smu_late_fini(void *handle) 1476 { 1477 struct amdgpu_device *adev = handle; 1478 struct smu_context *smu = adev->powerplay.pp_handle; 1479 1480 kfree(smu); 1481 } 1482 1483 static int smu_reset(struct smu_context *smu) 1484 { 1485 struct amdgpu_device *adev = smu->adev; 1486 int ret; 1487 1488 ret = smu_hw_fini(adev); 1489 if (ret) 1490 return ret; 1491 1492 ret = smu_hw_init(adev); 1493 if (ret) 1494 return ret; 1495 1496 ret = smu_late_init(adev); 1497 if (ret) 1498 return ret; 1499 1500 return 0; 1501 } 1502 1503 static int smu_suspend(void *handle) 1504 { 1505 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1506 struct smu_context *smu = adev->powerplay.pp_handle; 1507 int ret; 1508 1509 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1510 return 0; 1511 1512 if (!smu->pm_enabled) 1513 return 0; 1514 1515 adev->pm.dpm_enabled = false; 1516 1517 ret = smu_smc_hw_cleanup(smu); 1518 if (ret) 1519 return ret; 1520 1521 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1522 1523 smu_set_gfx_cgpg(smu, false); 1524 1525 return 0; 1526 } 1527 1528 static int smu_resume(void *handle) 1529 { 1530 int ret; 1531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1532 struct smu_context *smu = adev->powerplay.pp_handle; 1533 1534 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1535 return 0; 1536 1537 if (!smu->pm_enabled) 1538 return 0; 1539 1540 dev_info(adev->dev, "SMU is resuming...\n"); 1541 1542 ret = smu_start_smc_engine(smu); 1543 if (ret) { 1544 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1545 return ret; 1546 } 1547 1548 ret = smu_smc_hw_setup(smu); 1549 if (ret) { 1550 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1551 return ret; 1552 } 1553 1554 smu_set_gfx_cgpg(smu, true); 1555 1556 smu->disable_uclk_switch = 0; 1557 1558 adev->pm.dpm_enabled = true; 1559 1560 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1561 1562 return 0; 1563 } 1564 1565 static int smu_display_configuration_change(void *handle, 1566 const struct amd_pp_display_configuration *display_config) 1567 { 1568 struct smu_context *smu = handle; 1569 int index = 0; 1570 int num_of_active_display = 0; 1571 1572 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1573 return -EOPNOTSUPP; 1574 1575 if (!display_config) 1576 return -EINVAL; 1577 1578 smu_set_min_dcef_deep_sleep(smu, 1579 display_config->min_dcef_deep_sleep_set_clk / 100); 1580 1581 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1582 if (display_config->displays[index].controller_id != 0) 1583 num_of_active_display++; 1584 } 1585 1586 return 0; 1587 } 1588 1589 static int smu_set_clockgating_state(void *handle, 1590 enum amd_clockgating_state state) 1591 { 1592 return 0; 1593 } 1594 1595 static int smu_set_powergating_state(void *handle, 1596 enum amd_powergating_state state) 1597 { 1598 return 0; 1599 } 1600 1601 static int smu_enable_umd_pstate(void *handle, 1602 enum amd_dpm_forced_level *level) 1603 { 1604 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1605 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1606 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1607 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1608 1609 struct smu_context *smu = (struct smu_context*)(handle); 1610 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1611 1612 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1613 return -EINVAL; 1614 1615 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1616 /* enter umd pstate, save current level, disable gfx cg*/ 1617 if (*level & profile_mode_mask) { 1618 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1619 smu_gpo_control(smu, false); 1620 smu_gfx_ulv_control(smu, false); 1621 smu_deep_sleep_control(smu, false); 1622 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1623 } 1624 } else { 1625 /* exit umd pstate, restore level, enable gfx cg*/ 1626 if (!(*level & profile_mode_mask)) { 1627 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1628 *level = smu_dpm_ctx->saved_dpm_level; 1629 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1630 smu_deep_sleep_control(smu, true); 1631 smu_gfx_ulv_control(smu, true); 1632 smu_gpo_control(smu, true); 1633 } 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int smu_bump_power_profile_mode(struct smu_context *smu, 1640 long *param, 1641 uint32_t param_size) 1642 { 1643 int ret = 0; 1644 1645 if (smu->ppt_funcs->set_power_profile_mode) 1646 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1647 1648 return ret; 1649 } 1650 1651 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1652 enum amd_dpm_forced_level level, 1653 bool skip_display_settings) 1654 { 1655 int ret = 0; 1656 int index = 0; 1657 long workload; 1658 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1659 1660 if (!skip_display_settings) { 1661 ret = smu_display_config_changed(smu); 1662 if (ret) { 1663 dev_err(smu->adev->dev, "Failed to change display config!"); 1664 return ret; 1665 } 1666 } 1667 1668 ret = smu_apply_clocks_adjust_rules(smu); 1669 if (ret) { 1670 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1671 return ret; 1672 } 1673 1674 if (!skip_display_settings) { 1675 ret = smu_notify_smc_display_config(smu); 1676 if (ret) { 1677 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1678 return ret; 1679 } 1680 } 1681 1682 if (smu_dpm_ctx->dpm_level != level) { 1683 ret = smu_asic_set_performance_level(smu, level); 1684 if (ret) { 1685 dev_err(smu->adev->dev, "Failed to set performance level!"); 1686 return ret; 1687 } 1688 1689 /* update the saved copy */ 1690 smu_dpm_ctx->dpm_level = level; 1691 } 1692 1693 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1694 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1695 index = fls(smu->workload_mask); 1696 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1697 workload = smu->workload_setting[index]; 1698 1699 if (smu->power_profile_mode != workload) 1700 smu_bump_power_profile_mode(smu, &workload, 0); 1701 } 1702 1703 return ret; 1704 } 1705 1706 static int smu_handle_task(struct smu_context *smu, 1707 enum amd_dpm_forced_level level, 1708 enum amd_pp_task task_id) 1709 { 1710 int ret = 0; 1711 1712 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1713 return -EOPNOTSUPP; 1714 1715 switch (task_id) { 1716 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1717 ret = smu_pre_display_config_changed(smu); 1718 if (ret) 1719 return ret; 1720 ret = smu_adjust_power_state_dynamic(smu, level, false); 1721 break; 1722 case AMD_PP_TASK_COMPLETE_INIT: 1723 case AMD_PP_TASK_READJUST_POWER_STATE: 1724 ret = smu_adjust_power_state_dynamic(smu, level, true); 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 return ret; 1731 } 1732 1733 static int smu_handle_dpm_task(void *handle, 1734 enum amd_pp_task task_id, 1735 enum amd_pm_state_type *user_state) 1736 { 1737 struct smu_context *smu = handle; 1738 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1739 1740 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1741 1742 } 1743 1744 static int smu_switch_power_profile(void *handle, 1745 enum PP_SMC_POWER_PROFILE type, 1746 bool en) 1747 { 1748 struct smu_context *smu = handle; 1749 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1750 long workload; 1751 uint32_t index; 1752 1753 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1754 return -EOPNOTSUPP; 1755 1756 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1757 return -EINVAL; 1758 1759 if (!en) { 1760 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1761 index = fls(smu->workload_mask); 1762 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1763 workload = smu->workload_setting[index]; 1764 } else { 1765 smu->workload_mask |= (1 << smu->workload_prority[type]); 1766 index = fls(smu->workload_mask); 1767 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1768 workload = smu->workload_setting[index]; 1769 } 1770 1771 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1772 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1773 smu_bump_power_profile_mode(smu, &workload, 0); 1774 1775 return 0; 1776 } 1777 1778 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1779 { 1780 struct smu_context *smu = handle; 1781 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1782 1783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1784 return -EOPNOTSUPP; 1785 1786 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1787 return -EINVAL; 1788 1789 return smu_dpm_ctx->dpm_level; 1790 } 1791 1792 static int smu_force_performance_level(void *handle, 1793 enum amd_dpm_forced_level level) 1794 { 1795 struct smu_context *smu = handle; 1796 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1797 int ret = 0; 1798 1799 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1800 return -EOPNOTSUPP; 1801 1802 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1803 return -EINVAL; 1804 1805 ret = smu_enable_umd_pstate(smu, &level); 1806 if (ret) 1807 return ret; 1808 1809 ret = smu_handle_task(smu, level, 1810 AMD_PP_TASK_READJUST_POWER_STATE); 1811 1812 /* reset user dpm clock state */ 1813 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1814 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1815 smu->user_dpm_profile.clk_dependency = 0; 1816 } 1817 1818 return ret; 1819 } 1820 1821 static int smu_set_display_count(void *handle, uint32_t count) 1822 { 1823 struct smu_context *smu = handle; 1824 1825 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1826 return -EOPNOTSUPP; 1827 1828 return smu_init_display_count(smu, count); 1829 } 1830 1831 static int smu_force_smuclk_levels(struct smu_context *smu, 1832 enum smu_clk_type clk_type, 1833 uint32_t mask) 1834 { 1835 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1836 int ret = 0; 1837 1838 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1839 return -EOPNOTSUPP; 1840 1841 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1842 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1843 return -EINVAL; 1844 } 1845 1846 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1847 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1848 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1849 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1850 smu_set_user_clk_dependencies(smu, clk_type); 1851 } 1852 } 1853 1854 return ret; 1855 } 1856 1857 static int smu_force_ppclk_levels(void *handle, 1858 enum pp_clock_type type, 1859 uint32_t mask) 1860 { 1861 struct smu_context *smu = handle; 1862 enum smu_clk_type clk_type; 1863 1864 switch (type) { 1865 case PP_SCLK: 1866 clk_type = SMU_SCLK; break; 1867 case PP_MCLK: 1868 clk_type = SMU_MCLK; break; 1869 case PP_PCIE: 1870 clk_type = SMU_PCIE; break; 1871 case PP_SOCCLK: 1872 clk_type = SMU_SOCCLK; break; 1873 case PP_FCLK: 1874 clk_type = SMU_FCLK; break; 1875 case PP_DCEFCLK: 1876 clk_type = SMU_DCEFCLK; break; 1877 case PP_VCLK: 1878 clk_type = SMU_VCLK; break; 1879 case PP_DCLK: 1880 clk_type = SMU_DCLK; break; 1881 case OD_SCLK: 1882 clk_type = SMU_OD_SCLK; break; 1883 case OD_MCLK: 1884 clk_type = SMU_OD_MCLK; break; 1885 case OD_VDDC_CURVE: 1886 clk_type = SMU_OD_VDDC_CURVE; break; 1887 case OD_RANGE: 1888 clk_type = SMU_OD_RANGE; break; 1889 default: 1890 return -EINVAL; 1891 } 1892 1893 return smu_force_smuclk_levels(smu, clk_type, mask); 1894 } 1895 1896 /* 1897 * On system suspending or resetting, the dpm_enabled 1898 * flag will be cleared. So that those SMU services which 1899 * are not supported will be gated. 1900 * However, the mp1 state setting should still be granted 1901 * even if the dpm_enabled cleared. 1902 */ 1903 static int smu_set_mp1_state(void *handle, 1904 enum pp_mp1_state mp1_state) 1905 { 1906 struct smu_context *smu = handle; 1907 int ret = 0; 1908 1909 if (!smu->pm_enabled) 1910 return -EOPNOTSUPP; 1911 1912 if (smu->ppt_funcs && 1913 smu->ppt_funcs->set_mp1_state) 1914 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1915 1916 return ret; 1917 } 1918 1919 static int smu_set_df_cstate(void *handle, 1920 enum pp_df_cstate state) 1921 { 1922 struct smu_context *smu = handle; 1923 int ret = 0; 1924 1925 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1926 return -EOPNOTSUPP; 1927 1928 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1929 return 0; 1930 1931 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1932 if (ret) 1933 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1934 1935 return ret; 1936 } 1937 1938 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1939 { 1940 int ret = 0; 1941 1942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1943 return -EOPNOTSUPP; 1944 1945 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1946 return 0; 1947 1948 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1949 if (ret) 1950 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1951 1952 return ret; 1953 } 1954 1955 int smu_write_watermarks_table(struct smu_context *smu) 1956 { 1957 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1958 return -EOPNOTSUPP; 1959 1960 return smu_set_watermarks_table(smu, NULL); 1961 } 1962 1963 static int smu_set_watermarks_for_clock_ranges(void *handle, 1964 struct pp_smu_wm_range_sets *clock_ranges) 1965 { 1966 struct smu_context *smu = handle; 1967 1968 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1969 return -EOPNOTSUPP; 1970 1971 if (smu->disable_watermark) 1972 return 0; 1973 1974 return smu_set_watermarks_table(smu, clock_ranges); 1975 } 1976 1977 int smu_set_ac_dc(struct smu_context *smu) 1978 { 1979 int ret = 0; 1980 1981 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1982 return -EOPNOTSUPP; 1983 1984 /* controlled by firmware */ 1985 if (smu->dc_controlled_by_gpio) 1986 return 0; 1987 1988 ret = smu_set_power_source(smu, 1989 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1990 SMU_POWER_SOURCE_DC); 1991 if (ret) 1992 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1993 smu->adev->pm.ac_power ? "AC" : "DC"); 1994 1995 return ret; 1996 } 1997 1998 const struct amd_ip_funcs smu_ip_funcs = { 1999 .name = "smu", 2000 .early_init = smu_early_init, 2001 .late_init = smu_late_init, 2002 .sw_init = smu_sw_init, 2003 .sw_fini = smu_sw_fini, 2004 .hw_init = smu_hw_init, 2005 .hw_fini = smu_hw_fini, 2006 .late_fini = smu_late_fini, 2007 .suspend = smu_suspend, 2008 .resume = smu_resume, 2009 .is_idle = NULL, 2010 .check_soft_reset = NULL, 2011 .wait_for_idle = NULL, 2012 .soft_reset = NULL, 2013 .set_clockgating_state = smu_set_clockgating_state, 2014 .set_powergating_state = smu_set_powergating_state, 2015 }; 2016 2017 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2018 { 2019 .type = AMD_IP_BLOCK_TYPE_SMC, 2020 .major = 11, 2021 .minor = 0, 2022 .rev = 0, 2023 .funcs = &smu_ip_funcs, 2024 }; 2025 2026 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2027 { 2028 .type = AMD_IP_BLOCK_TYPE_SMC, 2029 .major = 12, 2030 .minor = 0, 2031 .rev = 0, 2032 .funcs = &smu_ip_funcs, 2033 }; 2034 2035 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2036 { 2037 .type = AMD_IP_BLOCK_TYPE_SMC, 2038 .major = 13, 2039 .minor = 0, 2040 .rev = 0, 2041 .funcs = &smu_ip_funcs, 2042 }; 2043 2044 static int smu_load_microcode(void *handle) 2045 { 2046 struct smu_context *smu = handle; 2047 struct amdgpu_device *adev = smu->adev; 2048 int ret = 0; 2049 2050 if (!smu->pm_enabled) 2051 return -EOPNOTSUPP; 2052 2053 /* This should be used for non PSP loading */ 2054 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2055 return 0; 2056 2057 if (smu->ppt_funcs->load_microcode) { 2058 ret = smu->ppt_funcs->load_microcode(smu); 2059 if (ret) { 2060 dev_err(adev->dev, "Load microcode failed\n"); 2061 return ret; 2062 } 2063 } 2064 2065 if (smu->ppt_funcs->check_fw_status) { 2066 ret = smu->ppt_funcs->check_fw_status(smu); 2067 if (ret) { 2068 dev_err(adev->dev, "SMC is not ready\n"); 2069 return ret; 2070 } 2071 } 2072 2073 return ret; 2074 } 2075 2076 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2077 { 2078 int ret = 0; 2079 2080 if (smu->ppt_funcs->set_gfx_cgpg) 2081 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2082 2083 return ret; 2084 } 2085 2086 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2087 { 2088 struct smu_context *smu = handle; 2089 int ret = 0; 2090 2091 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2092 return -EOPNOTSUPP; 2093 2094 if (!smu->ppt_funcs->set_fan_speed_rpm) 2095 return -EOPNOTSUPP; 2096 2097 if (speed == U32_MAX) 2098 return -EINVAL; 2099 2100 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2101 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2102 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2103 smu->user_dpm_profile.fan_speed_rpm = speed; 2104 2105 /* Override custom PWM setting as they cannot co-exist */ 2106 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2107 smu->user_dpm_profile.fan_speed_pwm = 0; 2108 } 2109 2110 return ret; 2111 } 2112 2113 /** 2114 * smu_get_power_limit - Request one of the SMU Power Limits 2115 * 2116 * @handle: pointer to smu context 2117 * @limit: requested limit is written back to this variable 2118 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2119 * @pp_power_type: &pp_power_type type of power 2120 * Return: 0 on success, <0 on error 2121 * 2122 */ 2123 int smu_get_power_limit(void *handle, 2124 uint32_t *limit, 2125 enum pp_power_limit_level pp_limit_level, 2126 enum pp_power_type pp_power_type) 2127 { 2128 struct smu_context *smu = handle; 2129 struct amdgpu_device *adev = smu->adev; 2130 enum smu_ppt_limit_level limit_level; 2131 uint32_t limit_type; 2132 int ret = 0; 2133 2134 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2135 return -EOPNOTSUPP; 2136 2137 switch(pp_power_type) { 2138 case PP_PWR_TYPE_SUSTAINED: 2139 limit_type = SMU_DEFAULT_PPT_LIMIT; 2140 break; 2141 case PP_PWR_TYPE_FAST: 2142 limit_type = SMU_FAST_PPT_LIMIT; 2143 break; 2144 default: 2145 return -EOPNOTSUPP; 2146 break; 2147 } 2148 2149 switch(pp_limit_level){ 2150 case PP_PWR_LIMIT_CURRENT: 2151 limit_level = SMU_PPT_LIMIT_CURRENT; 2152 break; 2153 case PP_PWR_LIMIT_DEFAULT: 2154 limit_level = SMU_PPT_LIMIT_DEFAULT; 2155 break; 2156 case PP_PWR_LIMIT_MAX: 2157 limit_level = SMU_PPT_LIMIT_MAX; 2158 break; 2159 case PP_PWR_LIMIT_MIN: 2160 default: 2161 return -EOPNOTSUPP; 2162 break; 2163 } 2164 2165 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2166 if (smu->ppt_funcs->get_ppt_limit) 2167 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2168 } else { 2169 switch (limit_level) { 2170 case SMU_PPT_LIMIT_CURRENT: 2171 switch (adev->ip_versions[MP1_HWIP][0]) { 2172 case IP_VERSION(13, 0, 2): 2173 case IP_VERSION(11, 0, 7): 2174 case IP_VERSION(11, 0, 11): 2175 case IP_VERSION(11, 0, 12): 2176 case IP_VERSION(11, 0, 13): 2177 ret = smu_get_asic_power_limits(smu, 2178 &smu->current_power_limit, 2179 NULL, 2180 NULL); 2181 break; 2182 default: 2183 break; 2184 } 2185 *limit = smu->current_power_limit; 2186 break; 2187 case SMU_PPT_LIMIT_DEFAULT: 2188 *limit = smu->default_power_limit; 2189 break; 2190 case SMU_PPT_LIMIT_MAX: 2191 *limit = smu->max_power_limit; 2192 break; 2193 default: 2194 break; 2195 } 2196 } 2197 2198 return ret; 2199 } 2200 2201 static int smu_set_power_limit(void *handle, uint32_t limit) 2202 { 2203 struct smu_context *smu = handle; 2204 uint32_t limit_type = limit >> 24; 2205 int ret = 0; 2206 2207 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2208 return -EOPNOTSUPP; 2209 2210 limit &= (1<<24)-1; 2211 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2212 if (smu->ppt_funcs->set_power_limit) 2213 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2214 2215 if (limit > smu->max_power_limit) { 2216 dev_err(smu->adev->dev, 2217 "New power limit (%d) is over the max allowed %d\n", 2218 limit, smu->max_power_limit); 2219 return -EINVAL; 2220 } 2221 2222 if (!limit) 2223 limit = smu->current_power_limit; 2224 2225 if (smu->ppt_funcs->set_power_limit) { 2226 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2227 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2228 smu->user_dpm_profile.power_limit = limit; 2229 } 2230 2231 return ret; 2232 } 2233 2234 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2235 { 2236 int ret = 0; 2237 2238 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2239 return -EOPNOTSUPP; 2240 2241 if (smu->ppt_funcs->print_clk_levels) 2242 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2243 2244 return ret; 2245 } 2246 2247 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2248 { 2249 enum smu_clk_type clk_type; 2250 2251 switch (type) { 2252 case PP_SCLK: 2253 clk_type = SMU_SCLK; break; 2254 case PP_MCLK: 2255 clk_type = SMU_MCLK; break; 2256 case PP_PCIE: 2257 clk_type = SMU_PCIE; break; 2258 case PP_SOCCLK: 2259 clk_type = SMU_SOCCLK; break; 2260 case PP_FCLK: 2261 clk_type = SMU_FCLK; break; 2262 case PP_DCEFCLK: 2263 clk_type = SMU_DCEFCLK; break; 2264 case PP_VCLK: 2265 clk_type = SMU_VCLK; break; 2266 case PP_DCLK: 2267 clk_type = SMU_DCLK; break; 2268 case OD_SCLK: 2269 clk_type = SMU_OD_SCLK; break; 2270 case OD_MCLK: 2271 clk_type = SMU_OD_MCLK; break; 2272 case OD_VDDC_CURVE: 2273 clk_type = SMU_OD_VDDC_CURVE; break; 2274 case OD_RANGE: 2275 clk_type = SMU_OD_RANGE; break; 2276 case OD_VDDGFX_OFFSET: 2277 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2278 case OD_CCLK: 2279 clk_type = SMU_OD_CCLK; break; 2280 default: 2281 clk_type = SMU_CLK_COUNT; break; 2282 } 2283 2284 return clk_type; 2285 } 2286 2287 static int smu_print_ppclk_levels(void *handle, 2288 enum pp_clock_type type, 2289 char *buf) 2290 { 2291 struct smu_context *smu = handle; 2292 enum smu_clk_type clk_type; 2293 2294 clk_type = smu_convert_to_smuclk(type); 2295 if (clk_type == SMU_CLK_COUNT) 2296 return -EINVAL; 2297 2298 return smu_print_smuclk_levels(smu, clk_type, buf); 2299 } 2300 2301 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2302 { 2303 struct smu_context *smu = handle; 2304 enum smu_clk_type clk_type; 2305 2306 clk_type = smu_convert_to_smuclk(type); 2307 if (clk_type == SMU_CLK_COUNT) 2308 return -EINVAL; 2309 2310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2311 return -EOPNOTSUPP; 2312 2313 if (!smu->ppt_funcs->emit_clk_levels) 2314 return -ENOENT; 2315 2316 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2317 2318 } 2319 2320 static int smu_od_edit_dpm_table(void *handle, 2321 enum PP_OD_DPM_TABLE_COMMAND type, 2322 long *input, uint32_t size) 2323 { 2324 struct smu_context *smu = handle; 2325 int ret = 0; 2326 2327 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2328 return -EOPNOTSUPP; 2329 2330 if (smu->ppt_funcs->od_edit_dpm_table) { 2331 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2332 } 2333 2334 return ret; 2335 } 2336 2337 static int smu_read_sensor(void *handle, 2338 int sensor, 2339 void *data, 2340 int *size_arg) 2341 { 2342 struct smu_context *smu = handle; 2343 struct smu_umd_pstate_table *pstate_table = 2344 &smu->pstate_table; 2345 int ret = 0; 2346 uint32_t *size, size_val; 2347 2348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2349 return -EOPNOTSUPP; 2350 2351 if (!data || !size_arg) 2352 return -EINVAL; 2353 2354 size_val = *size_arg; 2355 size = &size_val; 2356 2357 if (smu->ppt_funcs->read_sensor) 2358 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2359 goto unlock; 2360 2361 switch (sensor) { 2362 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2363 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2364 *size = 4; 2365 break; 2366 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2367 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2368 *size = 4; 2369 break; 2370 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2371 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2372 *size = 8; 2373 break; 2374 case AMDGPU_PP_SENSOR_UVD_POWER: 2375 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2376 *size = 4; 2377 break; 2378 case AMDGPU_PP_SENSOR_VCE_POWER: 2379 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2380 *size = 4; 2381 break; 2382 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2383 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2384 *size = 4; 2385 break; 2386 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2387 *(uint32_t *)data = 0; 2388 *size = 4; 2389 break; 2390 default: 2391 *size = 0; 2392 ret = -EOPNOTSUPP; 2393 break; 2394 } 2395 2396 unlock: 2397 // assign uint32_t to int 2398 *size_arg = size_val; 2399 2400 return ret; 2401 } 2402 2403 static int smu_get_power_profile_mode(void *handle, char *buf) 2404 { 2405 struct smu_context *smu = handle; 2406 2407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2408 !smu->ppt_funcs->get_power_profile_mode) 2409 return -EOPNOTSUPP; 2410 if (!buf) 2411 return -EINVAL; 2412 2413 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2414 } 2415 2416 static int smu_set_power_profile_mode(void *handle, 2417 long *param, 2418 uint32_t param_size) 2419 { 2420 struct smu_context *smu = handle; 2421 2422 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2423 !smu->ppt_funcs->set_power_profile_mode) 2424 return -EOPNOTSUPP; 2425 2426 return smu_bump_power_profile_mode(smu, param, param_size); 2427 } 2428 2429 2430 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2431 { 2432 struct smu_context *smu = handle; 2433 2434 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2435 return -EOPNOTSUPP; 2436 2437 if (!smu->ppt_funcs->get_fan_control_mode) 2438 return -EOPNOTSUPP; 2439 2440 if (!fan_mode) 2441 return -EINVAL; 2442 2443 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2444 2445 return 0; 2446 } 2447 2448 static int smu_set_fan_control_mode(void *handle, u32 value) 2449 { 2450 struct smu_context *smu = handle; 2451 int ret = 0; 2452 2453 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2454 return -EOPNOTSUPP; 2455 2456 if (!smu->ppt_funcs->set_fan_control_mode) 2457 return -EOPNOTSUPP; 2458 2459 if (value == U32_MAX) 2460 return -EINVAL; 2461 2462 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2463 if (ret) 2464 goto out; 2465 2466 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2467 smu->user_dpm_profile.fan_mode = value; 2468 2469 /* reset user dpm fan speed */ 2470 if (value != AMD_FAN_CTRL_MANUAL) { 2471 smu->user_dpm_profile.fan_speed_pwm = 0; 2472 smu->user_dpm_profile.fan_speed_rpm = 0; 2473 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2474 } 2475 } 2476 2477 out: 2478 return ret; 2479 } 2480 2481 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2482 { 2483 struct smu_context *smu = handle; 2484 int ret = 0; 2485 2486 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2487 return -EOPNOTSUPP; 2488 2489 if (!smu->ppt_funcs->get_fan_speed_pwm) 2490 return -EOPNOTSUPP; 2491 2492 if (!speed) 2493 return -EINVAL; 2494 2495 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2496 2497 return ret; 2498 } 2499 2500 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2501 { 2502 struct smu_context *smu = handle; 2503 int ret = 0; 2504 2505 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2506 return -EOPNOTSUPP; 2507 2508 if (!smu->ppt_funcs->set_fan_speed_pwm) 2509 return -EOPNOTSUPP; 2510 2511 if (speed == U32_MAX) 2512 return -EINVAL; 2513 2514 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2515 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2516 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2517 smu->user_dpm_profile.fan_speed_pwm = speed; 2518 2519 /* Override custom RPM setting as they cannot co-exist */ 2520 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2521 smu->user_dpm_profile.fan_speed_rpm = 0; 2522 } 2523 2524 return ret; 2525 } 2526 2527 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2528 { 2529 struct smu_context *smu = handle; 2530 int ret = 0; 2531 2532 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2533 return -EOPNOTSUPP; 2534 2535 if (!smu->ppt_funcs->get_fan_speed_rpm) 2536 return -EOPNOTSUPP; 2537 2538 if (!speed) 2539 return -EINVAL; 2540 2541 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2542 2543 return ret; 2544 } 2545 2546 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2547 { 2548 struct smu_context *smu = handle; 2549 2550 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2551 return -EOPNOTSUPP; 2552 2553 return smu_set_min_dcef_deep_sleep(smu, clk); 2554 } 2555 2556 static int smu_get_clock_by_type_with_latency(void *handle, 2557 enum amd_pp_clock_type type, 2558 struct pp_clock_levels_with_latency *clocks) 2559 { 2560 struct smu_context *smu = handle; 2561 enum smu_clk_type clk_type; 2562 int ret = 0; 2563 2564 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2565 return -EOPNOTSUPP; 2566 2567 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2568 switch (type) { 2569 case amd_pp_sys_clock: 2570 clk_type = SMU_GFXCLK; 2571 break; 2572 case amd_pp_mem_clock: 2573 clk_type = SMU_MCLK; 2574 break; 2575 case amd_pp_dcef_clock: 2576 clk_type = SMU_DCEFCLK; 2577 break; 2578 case amd_pp_disp_clock: 2579 clk_type = SMU_DISPCLK; 2580 break; 2581 default: 2582 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2583 return -EINVAL; 2584 } 2585 2586 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2587 } 2588 2589 return ret; 2590 } 2591 2592 static int smu_display_clock_voltage_request(void *handle, 2593 struct pp_display_clock_request *clock_req) 2594 { 2595 struct smu_context *smu = handle; 2596 int ret = 0; 2597 2598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2599 return -EOPNOTSUPP; 2600 2601 if (smu->ppt_funcs->display_clock_voltage_request) 2602 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2603 2604 return ret; 2605 } 2606 2607 2608 static int smu_display_disable_memory_clock_switch(void *handle, 2609 bool disable_memory_clock_switch) 2610 { 2611 struct smu_context *smu = handle; 2612 int ret = -EINVAL; 2613 2614 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2615 return -EOPNOTSUPP; 2616 2617 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2618 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2619 2620 return ret; 2621 } 2622 2623 static int smu_set_xgmi_pstate(void *handle, 2624 uint32_t pstate) 2625 { 2626 struct smu_context *smu = handle; 2627 int ret = 0; 2628 2629 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2630 return -EOPNOTSUPP; 2631 2632 if (smu->ppt_funcs->set_xgmi_pstate) 2633 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2634 2635 if(ret) 2636 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2637 2638 return ret; 2639 } 2640 2641 static int smu_get_baco_capability(void *handle, bool *cap) 2642 { 2643 struct smu_context *smu = handle; 2644 2645 *cap = false; 2646 2647 if (!smu->pm_enabled) 2648 return 0; 2649 2650 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2651 *cap = smu->ppt_funcs->baco_is_support(smu); 2652 2653 return 0; 2654 } 2655 2656 static int smu_baco_set_state(void *handle, int state) 2657 { 2658 struct smu_context *smu = handle; 2659 int ret = 0; 2660 2661 if (!smu->pm_enabled) 2662 return -EOPNOTSUPP; 2663 2664 if (state == 0) { 2665 if (smu->ppt_funcs->baco_exit) 2666 ret = smu->ppt_funcs->baco_exit(smu); 2667 } else if (state == 1) { 2668 if (smu->ppt_funcs->baco_enter) 2669 ret = smu->ppt_funcs->baco_enter(smu); 2670 } else { 2671 return -EINVAL; 2672 } 2673 2674 if (ret) 2675 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2676 (state)?"enter":"exit"); 2677 2678 return ret; 2679 } 2680 2681 bool smu_mode1_reset_is_support(struct smu_context *smu) 2682 { 2683 bool ret = false; 2684 2685 if (!smu->pm_enabled) 2686 return false; 2687 2688 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2689 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2690 2691 return ret; 2692 } 2693 2694 bool smu_mode2_reset_is_support(struct smu_context *smu) 2695 { 2696 bool ret = false; 2697 2698 if (!smu->pm_enabled) 2699 return false; 2700 2701 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2702 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2703 2704 return ret; 2705 } 2706 2707 int smu_mode1_reset(struct smu_context *smu) 2708 { 2709 int ret = 0; 2710 2711 if (!smu->pm_enabled) 2712 return -EOPNOTSUPP; 2713 2714 if (smu->ppt_funcs->mode1_reset) 2715 ret = smu->ppt_funcs->mode1_reset(smu); 2716 2717 return ret; 2718 } 2719 2720 static int smu_mode2_reset(void *handle) 2721 { 2722 struct smu_context *smu = handle; 2723 int ret = 0; 2724 2725 if (!smu->pm_enabled) 2726 return -EOPNOTSUPP; 2727 2728 if (smu->ppt_funcs->mode2_reset) 2729 ret = smu->ppt_funcs->mode2_reset(smu); 2730 2731 if (ret) 2732 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2733 2734 return ret; 2735 } 2736 2737 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2738 struct pp_smu_nv_clock_table *max_clocks) 2739 { 2740 struct smu_context *smu = handle; 2741 int ret = 0; 2742 2743 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2744 return -EOPNOTSUPP; 2745 2746 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2747 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2748 2749 return ret; 2750 } 2751 2752 static int smu_get_uclk_dpm_states(void *handle, 2753 unsigned int *clock_values_in_khz, 2754 unsigned int *num_states) 2755 { 2756 struct smu_context *smu = handle; 2757 int ret = 0; 2758 2759 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2760 return -EOPNOTSUPP; 2761 2762 if (smu->ppt_funcs->get_uclk_dpm_states) 2763 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2764 2765 return ret; 2766 } 2767 2768 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2769 { 2770 struct smu_context *smu = handle; 2771 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2772 2773 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2774 return -EOPNOTSUPP; 2775 2776 if (smu->ppt_funcs->get_current_power_state) 2777 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2778 2779 return pm_state; 2780 } 2781 2782 static int smu_get_dpm_clock_table(void *handle, 2783 struct dpm_clocks *clock_table) 2784 { 2785 struct smu_context *smu = handle; 2786 int ret = 0; 2787 2788 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2789 return -EOPNOTSUPP; 2790 2791 if (smu->ppt_funcs->get_dpm_clock_table) 2792 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2793 2794 return ret; 2795 } 2796 2797 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2798 { 2799 struct smu_context *smu = handle; 2800 2801 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2802 return -EOPNOTSUPP; 2803 2804 if (!smu->ppt_funcs->get_gpu_metrics) 2805 return -EOPNOTSUPP; 2806 2807 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2808 } 2809 2810 static int smu_enable_mgpu_fan_boost(void *handle) 2811 { 2812 struct smu_context *smu = handle; 2813 int ret = 0; 2814 2815 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2816 return -EOPNOTSUPP; 2817 2818 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2819 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2820 2821 return ret; 2822 } 2823 2824 static int smu_gfx_state_change_set(void *handle, 2825 uint32_t state) 2826 { 2827 struct smu_context *smu = handle; 2828 int ret = 0; 2829 2830 if (smu->ppt_funcs->gfx_state_change_set) 2831 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2832 2833 return ret; 2834 } 2835 2836 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2837 { 2838 int ret = 0; 2839 2840 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2841 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2842 2843 return ret; 2844 } 2845 2846 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2847 { 2848 int ret = -EOPNOTSUPP; 2849 2850 if (smu->ppt_funcs && 2851 smu->ppt_funcs->get_ecc_info) 2852 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2853 2854 return ret; 2855 2856 } 2857 2858 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2859 { 2860 struct smu_context *smu = handle; 2861 struct smu_table_context *smu_table = &smu->smu_table; 2862 struct smu_table *memory_pool = &smu_table->memory_pool; 2863 2864 if (!addr || !size) 2865 return -EINVAL; 2866 2867 *addr = NULL; 2868 *size = 0; 2869 if (memory_pool->bo) { 2870 *addr = memory_pool->cpu_addr; 2871 *size = memory_pool->size; 2872 } 2873 2874 return 0; 2875 } 2876 2877 static const struct amd_pm_funcs swsmu_pm_funcs = { 2878 /* export for sysfs */ 2879 .set_fan_control_mode = smu_set_fan_control_mode, 2880 .get_fan_control_mode = smu_get_fan_control_mode, 2881 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2882 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2883 .force_clock_level = smu_force_ppclk_levels, 2884 .print_clock_levels = smu_print_ppclk_levels, 2885 .emit_clock_levels = smu_emit_ppclk_levels, 2886 .force_performance_level = smu_force_performance_level, 2887 .read_sensor = smu_read_sensor, 2888 .get_performance_level = smu_get_performance_level, 2889 .get_current_power_state = smu_get_current_power_state, 2890 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2891 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2892 .get_pp_num_states = smu_get_power_num_states, 2893 .get_pp_table = smu_sys_get_pp_table, 2894 .set_pp_table = smu_sys_set_pp_table, 2895 .switch_power_profile = smu_switch_power_profile, 2896 /* export to amdgpu */ 2897 .dispatch_tasks = smu_handle_dpm_task, 2898 .load_firmware = smu_load_microcode, 2899 .set_powergating_by_smu = smu_dpm_set_power_gate, 2900 .set_power_limit = smu_set_power_limit, 2901 .get_power_limit = smu_get_power_limit, 2902 .get_power_profile_mode = smu_get_power_profile_mode, 2903 .set_power_profile_mode = smu_set_power_profile_mode, 2904 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2905 .set_mp1_state = smu_set_mp1_state, 2906 .gfx_state_change_set = smu_gfx_state_change_set, 2907 /* export to DC */ 2908 .get_sclk = smu_get_sclk, 2909 .get_mclk = smu_get_mclk, 2910 .display_configuration_change = smu_display_configuration_change, 2911 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2912 .display_clock_voltage_request = smu_display_clock_voltage_request, 2913 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2914 .set_active_display_count = smu_set_display_count, 2915 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2916 .get_asic_baco_capability = smu_get_baco_capability, 2917 .set_asic_baco_state = smu_baco_set_state, 2918 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2919 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2920 .asic_reset_mode_2 = smu_mode2_reset, 2921 .set_df_cstate = smu_set_df_cstate, 2922 .set_xgmi_pstate = smu_set_xgmi_pstate, 2923 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2924 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2925 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2926 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2927 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2928 .get_dpm_clock_table = smu_get_dpm_clock_table, 2929 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2930 }; 2931 2932 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2933 uint64_t event_arg) 2934 { 2935 int ret = -EINVAL; 2936 2937 if (smu->ppt_funcs->wait_for_event) 2938 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2939 2940 return ret; 2941 } 2942 2943 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 2944 { 2945 2946 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 2947 return -EOPNOTSUPP; 2948 2949 /* Confirm the buffer allocated is of correct size */ 2950 if (size != smu->stb_context.stb_buf_size) 2951 return -EINVAL; 2952 2953 /* 2954 * No need to lock smu mutex as we access STB directly through MMIO 2955 * and not going through SMU messaging route (for now at least). 2956 * For registers access rely on implementation internal locking. 2957 */ 2958 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 2959 } 2960 2961 #if defined(CONFIG_DEBUG_FS) 2962 2963 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 2964 { 2965 struct amdgpu_device *adev = filp->f_inode->i_private; 2966 struct smu_context *smu = adev->powerplay.pp_handle; 2967 unsigned char *buf; 2968 int r; 2969 2970 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 2971 if (!buf) 2972 return -ENOMEM; 2973 2974 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 2975 if (r) 2976 goto out; 2977 2978 filp->private_data = buf; 2979 2980 return 0; 2981 2982 out: 2983 kvfree(buf); 2984 return r; 2985 } 2986 2987 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 2988 loff_t *pos) 2989 { 2990 struct amdgpu_device *adev = filp->f_inode->i_private; 2991 struct smu_context *smu = adev->powerplay.pp_handle; 2992 2993 2994 if (!filp->private_data) 2995 return -EINVAL; 2996 2997 return simple_read_from_buffer(buf, 2998 size, 2999 pos, filp->private_data, 3000 smu->stb_context.stb_buf_size); 3001 } 3002 3003 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3004 { 3005 kvfree(filp->private_data); 3006 filp->private_data = NULL; 3007 3008 return 0; 3009 } 3010 3011 /* 3012 * We have to define not only read method but also 3013 * open and release because .read takes up to PAGE_SIZE 3014 * data each time so and so is invoked multiple times. 3015 * We allocate the STB buffer in .open and release it 3016 * in .release 3017 */ 3018 static const struct file_operations smu_stb_debugfs_fops = { 3019 .owner = THIS_MODULE, 3020 .open = smu_stb_debugfs_open, 3021 .read = smu_stb_debugfs_read, 3022 .release = smu_stb_debugfs_release, 3023 .llseek = default_llseek, 3024 }; 3025 3026 #endif 3027 3028 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3029 { 3030 #if defined(CONFIG_DEBUG_FS) 3031 3032 struct smu_context *smu = adev->powerplay.pp_handle; 3033 3034 if (!smu->stb_context.stb_buf_size) 3035 return; 3036 3037 debugfs_create_file_size("amdgpu_smu_stb_dump", 3038 S_IRUSR, 3039 adev_to_drm(adev)->primary->debugfs_root, 3040 adev, 3041 &smu_stb_debugfs_fops, 3042 smu->stb_context.stb_buf_size); 3043 #endif 3044 } 3045 3046 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3047 { 3048 int ret = 0; 3049 3050 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3051 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3052 3053 return ret; 3054 } 3055 3056 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3057 { 3058 int ret = 0; 3059 3060 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3061 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3062 3063 return ret; 3064 } 3065