1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _smuio_13_0_6_OFFSET_HEADER 24 #define _smuio_13_0_6_OFFSET_HEADER 25 26 27 28 // addressBlock: smuio_smuio_reset_SmuSmuioDec 29 // base address: 0x5a300 30 #define regSMUIO_MP_RESET_INTR 0x00c1 31 #define regSMUIO_MP_RESET_INTR_BASE_IDX 0 32 #define regSMUIO_SOC_HALT 0x00c2 33 #define regSMUIO_SOC_HALT_BASE_IDX 0 34 35 36 // addressBlock: smuio_smuio_tsc_SmuSmuioDec 37 // base address: 0x5a8a0 38 #define regPWROK_REFCLK_GAP_CYCLES 0x0028 39 #define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 40 #define regGOLDEN_TSC_INCREMENT_UPPER 0x002b 41 #define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 42 #define regGOLDEN_TSC_INCREMENT_LOWER 0x002c 43 #define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 44 #define regGOLDEN_TSC_COUNT_UPPER 0x002d 45 #define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 46 #define regGOLDEN_TSC_COUNT_LOWER 0x002e 47 #define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 48 #define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x002f 49 #define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 50 #define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0030 51 #define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 52 #define regSOC_GAP_PWROK 0x0031 53 #define regSOC_GAP_PWROK_BASE_IDX 1 54 55 56 // addressBlock: smuio_smuio_swtimer_SmuSmuioDec 57 // base address: 0x5ac70 58 #define regPWR_DISP_TIMER_CONTROL 0x011d 59 #define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 60 #define regPWR_DISP_TIMER_DEBUG 0x011e 61 #define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 62 #define regPWR_DISP_TIMER2_CONTROL 0x011f 63 #define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 64 #define regPWR_DISP_TIMER2_DEBUG 0x0120 65 #define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 66 #define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0121 67 #define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 68 #define regPWR_IH_CONTROL 0x0122 69 #define regPWR_IH_CONTROL_BASE_IDX 1 70 71 72 // addressBlock: smuio_smuio_misc_SmuSmuioDec 73 // base address: 0x5a000 74 #define regSMUIO_MCM_CONFIG 0x0023 75 #define regSMUIO_MCM_CONFIG_BASE_IDX 0 76 #define regIP_DISCOVERY_VERSION 0x0000 77 #define regIP_DISCOVERY_VERSION_BASE_IDX 1 78 #define regSCRATCH_REGISTER0 0x01bd 79 #define regSCRATCH_REGISTER0_BASE_IDX 1 80 #define regSCRATCH_REGISTER1 0x01be 81 #define regSCRATCH_REGISTER1_BASE_IDX 1 82 #define regSCRATCH_REGISTER2 0x01bf 83 #define regSCRATCH_REGISTER2_BASE_IDX 1 84 #define regSCRATCH_REGISTER3 0x01c0 85 #define regSCRATCH_REGISTER3_BASE_IDX 1 86 #define regSCRATCH_REGISTER4 0x01c1 87 #define regSCRATCH_REGISTER4_BASE_IDX 1 88 #define regSCRATCH_REGISTER5 0x01c2 89 #define regSCRATCH_REGISTER5_BASE_IDX 1 90 #define regSCRATCH_REGISTER6 0x01c3 91 #define regSCRATCH_REGISTER6_BASE_IDX 1 92 #define regSCRATCH_REGISTER7 0x01c4 93 #define regSCRATCH_REGISTER7_BASE_IDX 1 94 95 96 // addressBlock: smuio_smuio_i2c_SmuSmuioDec 97 // base address: 0x5a100 98 #define regCKSVII2C_IC_CON 0x0040 99 #define regCKSVII2C_IC_CON_BASE_IDX 0 100 #define regCKSVII2C_IC_TAR 0x0041 101 #define regCKSVII2C_IC_TAR_BASE_IDX 0 102 #define regCKSVII2C_IC_SAR 0x0042 103 #define regCKSVII2C_IC_SAR_BASE_IDX 0 104 #define regCKSVII2C_IC_HS_MADDR 0x0043 105 #define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0 106 #define regCKSVII2C_IC_DATA_CMD 0x0044 107 #define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0 108 #define regCKSVII2C_IC_SS_SCL_HCNT 0x0045 109 #define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 110 #define regCKSVII2C_IC_SS_SCL_LCNT 0x0046 111 #define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 112 #define regCKSVII2C_IC_FS_SCL_HCNT 0x0047 113 #define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 114 #define regCKSVII2C_IC_FS_SCL_LCNT 0x0048 115 #define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 116 #define regCKSVII2C_IC_HS_SCL_HCNT 0x0049 117 #define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 118 #define regCKSVII2C_IC_HS_SCL_LCNT 0x004a 119 #define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 120 #define regCKSVII2C_IC_INTR_STAT 0x004b 121 #define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0 122 #define regCKSVII2C_IC_INTR_MASK 0x004c 123 #define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0 124 #define regCKSVII2C_IC_RAW_INTR_STAT 0x004d 125 #define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 126 #define regCKSVII2C_IC_RX_TL 0x004e 127 #define regCKSVII2C_IC_RX_TL_BASE_IDX 0 128 #define regCKSVII2C_IC_TX_TL 0x004f 129 #define regCKSVII2C_IC_TX_TL_BASE_IDX 0 130 #define regCKSVII2C_IC_CLR_INTR 0x0050 131 #define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0 132 #define regCKSVII2C_IC_CLR_RX_UNDER 0x0051 133 #define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 134 #define regCKSVII2C_IC_CLR_RX_OVER 0x0052 135 #define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 136 #define regCKSVII2C_IC_CLR_TX_OVER 0x0053 137 #define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 138 #define regCKSVII2C_IC_CLR_RD_REQ 0x0054 139 #define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 140 #define regCKSVII2C_IC_CLR_TX_ABRT 0x0055 141 #define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 142 #define regCKSVII2C_IC_CLR_RX_DONE 0x0056 143 #define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 144 #define regCKSVII2C_IC_CLR_ACTIVITY 0x0057 145 #define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 146 #define regCKSVII2C_IC_CLR_STOP_DET 0x0058 147 #define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 148 #define regCKSVII2C_IC_CLR_START_DET 0x0059 149 #define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 150 #define regCKSVII2C_IC_CLR_GEN_CALL 0x005a 151 #define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 152 #define regCKSVII2C_IC_ENABLE 0x005b 153 #define regCKSVII2C_IC_ENABLE_BASE_IDX 0 154 #define regCKSVII2C_IC_STATUS 0x005c 155 #define regCKSVII2C_IC_STATUS_BASE_IDX 0 156 #define regCKSVII2C_IC_TXFLR 0x005d 157 #define regCKSVII2C_IC_TXFLR_BASE_IDX 0 158 #define regCKSVII2C_IC_RXFLR 0x005e 159 #define regCKSVII2C_IC_RXFLR_BASE_IDX 0 160 #define regCKSVII2C_IC_SDA_HOLD 0x005f 161 #define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 162 #define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 163 #define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 164 #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 165 #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 166 #define regCKSVII2C_IC_DMA_CR 0x0062 167 #define regCKSVII2C_IC_DMA_CR_BASE_IDX 0 168 #define regCKSVII2C_IC_DMA_TDLR 0x0063 169 #define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 170 #define regCKSVII2C_IC_DMA_RDLR 0x0064 171 #define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 172 #define regCKSVII2C_IC_SDA_SETUP 0x0065 173 #define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 174 #define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 175 #define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 176 #define regCKSVII2C_IC_ENABLE_STATUS 0x0067 177 #define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 178 #define regCKSVII2C_IC_FS_SPKLEN 0x0068 179 #define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 180 #define regCKSVII2C_IC_HS_SPKLEN 0x0069 181 #define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 182 #define regCKSVII2C_IC_CLR_RESTART_DET 0x006a 183 #define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 184 #define regCKSVII2C_IC_COMP_PARAM_1 0x006d 185 #define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 186 #define regCKSVII2C_IC_COMP_VERSION 0x006e 187 #define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 188 #define regCKSVII2C_IC_COMP_TYPE 0x006f 189 #define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 190 #define regCKSVII2C1_IC_CON 0x0080 191 #define regCKSVII2C1_IC_CON_BASE_IDX 0 192 #define regCKSVII2C1_IC_TAR 0x0081 193 #define regCKSVII2C1_IC_TAR_BASE_IDX 0 194 #define regCKSVII2C1_IC_SAR 0x0082 195 #define regCKSVII2C1_IC_SAR_BASE_IDX 0 196 #define regCKSVII2C1_IC_HS_MADDR 0x0083 197 #define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 198 #define regCKSVII2C1_IC_DATA_CMD 0x0084 199 #define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 200 #define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085 201 #define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 202 #define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086 203 #define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 204 #define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087 205 #define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 206 #define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088 207 #define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 208 #define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089 209 #define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 210 #define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a 211 #define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 212 #define regCKSVII2C1_IC_INTR_STAT 0x008b 213 #define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 214 #define regCKSVII2C1_IC_INTR_MASK 0x008c 215 #define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 216 #define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d 217 #define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 218 #define regCKSVII2C1_IC_RX_TL 0x008e 219 #define regCKSVII2C1_IC_RX_TL_BASE_IDX 0 220 #define regCKSVII2C1_IC_TX_TL 0x008f 221 #define regCKSVII2C1_IC_TX_TL_BASE_IDX 0 222 #define regCKSVII2C1_IC_CLR_INTR 0x0090 223 #define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 224 #define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091 225 #define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 226 #define regCKSVII2C1_IC_CLR_RX_OVER 0x0092 227 #define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 228 #define regCKSVII2C1_IC_CLR_TX_OVER 0x0093 229 #define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 230 #define regCKSVII2C1_IC_CLR_RD_REQ 0x0094 231 #define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 232 #define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095 233 #define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 234 #define regCKSVII2C1_IC_CLR_RX_DONE 0x0096 235 #define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 236 #define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097 237 #define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 238 #define regCKSVII2C1_IC_CLR_STOP_DET 0x0098 239 #define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 240 #define regCKSVII2C1_IC_CLR_START_DET 0x0099 241 #define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 242 #define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a 243 #define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 244 #define regCKSVII2C1_IC_ENABLE 0x009b 245 #define regCKSVII2C1_IC_ENABLE_BASE_IDX 0 246 #define regCKSVII2C1_IC_STATUS 0x009c 247 #define regCKSVII2C1_IC_STATUS_BASE_IDX 0 248 #define regCKSVII2C1_IC_TXFLR 0x009d 249 #define regCKSVII2C1_IC_TXFLR_BASE_IDX 0 250 #define regCKSVII2C1_IC_RXFLR 0x009e 251 #define regCKSVII2C1_IC_RXFLR_BASE_IDX 0 252 #define regCKSVII2C1_IC_SDA_HOLD 0x009f 253 #define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 254 #define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 255 #define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 256 #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 257 #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 258 #define regCKSVII2C1_IC_DMA_CR 0x00a2 259 #define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0 260 #define regCKSVII2C1_IC_DMA_TDLR 0x00a3 261 #define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 262 #define regCKSVII2C1_IC_DMA_RDLR 0x00a4 263 #define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 264 #define regCKSVII2C1_IC_SDA_SETUP 0x00a5 265 #define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 266 #define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 267 #define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 268 #define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7 269 #define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 270 #define regCKSVII2C1_IC_FS_SPKLEN 0x00a8 271 #define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 272 #define regCKSVII2C1_IC_HS_SPKLEN 0x00a9 273 #define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 274 #define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa 275 #define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 276 #define regCKSVII2C1_IC_COMP_PARAM_1 0x00ad 277 #define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 278 #define regCKSVII2C1_IC_COMP_VERSION 0x00ae 279 #define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 280 #define regCKSVII2C1_IC_COMP_TYPE 0x00af 281 #define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 282 #define regSMUIO_PWRMGT 0x018c 283 #define regSMUIO_PWRMGT_BASE_IDX 0 284 285 286 // addressBlock: smuio_smuio_rom_SmuSmuioDec 287 // base address: 0x5a380 288 #define regROM_CNTL 0x00e0 289 #define regROM_CNTL_BASE_IDX 0 290 #define regPAGE_MIRROR_CNTL 0x00e1 291 #define regPAGE_MIRROR_CNTL_BASE_IDX 0 292 #define regROM_STATUS 0x00e2 293 #define regROM_STATUS_BASE_IDX 0 294 #define regCGTT_ROM_CLK_CTRL0 0x00e3 295 #define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0 296 #define regROM_INDEX 0x00e4 297 #define regROM_INDEX_BASE_IDX 0 298 #define regROM_DATA 0x00e5 299 #define regROM_DATA_BASE_IDX 0 300 #define regROM_START 0x00e6 301 #define regROM_START_BASE_IDX 0 302 #define regROM_SW_CNTL 0x00e8 303 #define regROM_SW_CNTL_BASE_IDX 0 304 #define regROM_SW_STATUS 0x00e9 305 #define regROM_SW_STATUS_BASE_IDX 0 306 #define regROM_SW_COMMAND 0x00ea 307 #define regROM_SW_COMMAND_BASE_IDX 0 308 #define regROM_SW_DATA_1 0x00ec 309 #define regROM_SW_DATA_1_BASE_IDX 0 310 #define regROM_SW_DATA_2 0x00ed 311 #define regROM_SW_DATA_2_BASE_IDX 0 312 #define regROM_SW_DATA_3 0x00ee 313 #define regROM_SW_DATA_3_BASE_IDX 0 314 #define regROM_SW_DATA_4 0x00ef 315 #define regROM_SW_DATA_4_BASE_IDX 0 316 #define regROM_SW_DATA_5 0x00f0 317 #define regROM_SW_DATA_5_BASE_IDX 0 318 #define regROM_SW_DATA_6 0x00f1 319 #define regROM_SW_DATA_6_BASE_IDX 0 320 #define regROM_SW_DATA_7 0x00f2 321 #define regROM_SW_DATA_7_BASE_IDX 0 322 #define regROM_SW_DATA_8 0x00f3 323 #define regROM_SW_DATA_8_BASE_IDX 0 324 #define regROM_SW_DATA_9 0x00f4 325 #define regROM_SW_DATA_9_BASE_IDX 0 326 #define regROM_SW_DATA_10 0x00f5 327 #define regROM_SW_DATA_10_BASE_IDX 0 328 #define regROM_SW_DATA_11 0x00f6 329 #define regROM_SW_DATA_11_BASE_IDX 0 330 #define regROM_SW_DATA_12 0x00f7 331 #define regROM_SW_DATA_12_BASE_IDX 0 332 #define regROM_SW_DATA_13 0x00f8 333 #define regROM_SW_DATA_13_BASE_IDX 0 334 #define regROM_SW_DATA_14 0x00f9 335 #define regROM_SW_DATA_14_BASE_IDX 0 336 #define regROM_SW_DATA_15 0x00fa 337 #define regROM_SW_DATA_15_BASE_IDX 0 338 #define regROM_SW_DATA_16 0x00fb 339 #define regROM_SW_DATA_16_BASE_IDX 0 340 #define regROM_SW_DATA_17 0x00fc 341 #define regROM_SW_DATA_17_BASE_IDX 0 342 #define regROM_SW_DATA_18 0x00fd 343 #define regROM_SW_DATA_18_BASE_IDX 0 344 #define regROM_SW_DATA_19 0x00fe 345 #define regROM_SW_DATA_19_BASE_IDX 0 346 #define regROM_SW_DATA_20 0x00ff 347 #define regROM_SW_DATA_20_BASE_IDX 0 348 #define regROM_SW_DATA_21 0x0100 349 #define regROM_SW_DATA_21_BASE_IDX 0 350 #define regROM_SW_DATA_22 0x0101 351 #define regROM_SW_DATA_22_BASE_IDX 0 352 #define regROM_SW_DATA_23 0x0102 353 #define regROM_SW_DATA_23_BASE_IDX 0 354 #define regROM_SW_DATA_24 0x0103 355 #define regROM_SW_DATA_24_BASE_IDX 0 356 #define regROM_SW_DATA_25 0x0104 357 #define regROM_SW_DATA_25_BASE_IDX 0 358 #define regROM_SW_DATA_26 0x0105 359 #define regROM_SW_DATA_26_BASE_IDX 0 360 #define regROM_SW_DATA_27 0x0106 361 #define regROM_SW_DATA_27_BASE_IDX 0 362 #define regROM_SW_DATA_28 0x0107 363 #define regROM_SW_DATA_28_BASE_IDX 0 364 #define regROM_SW_DATA_29 0x0108 365 #define regROM_SW_DATA_29_BASE_IDX 0 366 #define regROM_SW_DATA_30 0x0109 367 #define regROM_SW_DATA_30_BASE_IDX 0 368 #define regROM_SW_DATA_31 0x010a 369 #define regROM_SW_DATA_31_BASE_IDX 0 370 #define regROM_SW_DATA_32 0x010b 371 #define regROM_SW_DATA_32_BASE_IDX 0 372 #define regROM_SW_DATA_33 0x010c 373 #define regROM_SW_DATA_33_BASE_IDX 0 374 #define regROM_SW_DATA_34 0x010d 375 #define regROM_SW_DATA_34_BASE_IDX 0 376 #define regROM_SW_DATA_35 0x010e 377 #define regROM_SW_DATA_35_BASE_IDX 0 378 #define regROM_SW_DATA_36 0x010f 379 #define regROM_SW_DATA_36_BASE_IDX 0 380 #define regROM_SW_DATA_37 0x0110 381 #define regROM_SW_DATA_37_BASE_IDX 0 382 #define regROM_SW_DATA_38 0x0111 383 #define regROM_SW_DATA_38_BASE_IDX 0 384 #define regROM_SW_DATA_39 0x0112 385 #define regROM_SW_DATA_39_BASE_IDX 0 386 #define regROM_SW_DATA_40 0x0113 387 #define regROM_SW_DATA_40_BASE_IDX 0 388 #define regROM_SW_DATA_41 0x0114 389 #define regROM_SW_DATA_41_BASE_IDX 0 390 #define regROM_SW_DATA_42 0x0115 391 #define regROM_SW_DATA_42_BASE_IDX 0 392 #define regROM_SW_DATA_43 0x0116 393 #define regROM_SW_DATA_43_BASE_IDX 0 394 #define regROM_SW_DATA_44 0x0117 395 #define regROM_SW_DATA_44_BASE_IDX 0 396 #define regROM_SW_DATA_45 0x0118 397 #define regROM_SW_DATA_45_BASE_IDX 0 398 #define regROM_SW_DATA_46 0x0119 399 #define regROM_SW_DATA_46_BASE_IDX 0 400 #define regROM_SW_DATA_47 0x011a 401 #define regROM_SW_DATA_47_BASE_IDX 0 402 #define regROM_SW_DATA_48 0x011b 403 #define regROM_SW_DATA_48_BASE_IDX 0 404 #define regROM_SW_DATA_49 0x011c 405 #define regROM_SW_DATA_49_BASE_IDX 0 406 #define regROM_SW_DATA_50 0x011d 407 #define regROM_SW_DATA_50_BASE_IDX 0 408 #define regROM_SW_DATA_51 0x011e 409 #define regROM_SW_DATA_51_BASE_IDX 0 410 #define regROM_SW_DATA_52 0x011f 411 #define regROM_SW_DATA_52_BASE_IDX 0 412 #define regROM_SW_DATA_53 0x0120 413 #define regROM_SW_DATA_53_BASE_IDX 0 414 #define regROM_SW_DATA_54 0x0121 415 #define regROM_SW_DATA_54_BASE_IDX 0 416 #define regROM_SW_DATA_55 0x0122 417 #define regROM_SW_DATA_55_BASE_IDX 0 418 #define regROM_SW_DATA_56 0x0123 419 #define regROM_SW_DATA_56_BASE_IDX 0 420 #define regROM_SW_DATA_57 0x0124 421 #define regROM_SW_DATA_57_BASE_IDX 0 422 #define regROM_SW_DATA_58 0x0125 423 #define regROM_SW_DATA_58_BASE_IDX 0 424 #define regROM_SW_DATA_59 0x0126 425 #define regROM_SW_DATA_59_BASE_IDX 0 426 #define regROM_SW_DATA_60 0x0127 427 #define regROM_SW_DATA_60_BASE_IDX 0 428 #define regROM_SW_DATA_61 0x0128 429 #define regROM_SW_DATA_61_BASE_IDX 0 430 #define regROM_SW_DATA_62 0x0129 431 #define regROM_SW_DATA_62_BASE_IDX 0 432 #define regROM_SW_DATA_63 0x012a 433 #define regROM_SW_DATA_63_BASE_IDX 0 434 #define regROM_SW_DATA_64 0x012b 435 #define regROM_SW_DATA_64_BASE_IDX 0 436 437 438 // addressBlock: smuio_smuio_gpio_SmuSmuioDec 439 // base address: 0x5a500 440 #define regSMU_GPIOPAD_SW_INT_STAT 0x0140 441 #define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 442 #define regSMU_GPIOPAD_MASK 0x0141 443 #define regSMU_GPIOPAD_MASK_BASE_IDX 0 444 #define regSMU_GPIOPAD_A 0x0142 445 #define regSMU_GPIOPAD_A_BASE_IDX 0 446 #define regSMU_GPIOPAD_TXIMPSEL 0x0143 447 #define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 448 #define regSMU_GPIOPAD_EN 0x0144 449 #define regSMU_GPIOPAD_EN_BASE_IDX 0 450 #define regSMU_GPIOPAD_Y 0x0145 451 #define regSMU_GPIOPAD_Y_BASE_IDX 0 452 #define regSMU_GPIOPAD_RXEN 0x0146 453 #define regSMU_GPIOPAD_RXEN_BASE_IDX 0 454 #define regSMU_GPIOPAD_RCVR_SEL0 0x0147 455 #define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 456 #define regSMU_GPIOPAD_RCVR_SEL1 0x0148 457 #define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 458 #define regSMU_GPIOPAD_PU_EN 0x0149 459 #define regSMU_GPIOPAD_PU_EN_BASE_IDX 0 460 #define regSMU_GPIOPAD_PD_EN 0x014a 461 #define regSMU_GPIOPAD_PD_EN_BASE_IDX 0 462 #define regSMU_GPIOPAD_PINSTRAPS 0x014b 463 #define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 464 #define regDFT_PINSTRAPS 0x014c 465 #define regDFT_PINSTRAPS_BASE_IDX 0 466 #define regSMU_GPIOPAD_INT_STAT_EN 0x014d 467 #define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 468 #define regSMU_GPIOPAD_INT_STAT 0x014e 469 #define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0 470 #define regSMU_GPIOPAD_INT_STAT_AK 0x014f 471 #define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 472 #define regSMU_GPIOPAD_INT_EN 0x0150 473 #define regSMU_GPIOPAD_INT_EN_BASE_IDX 0 474 #define regSMU_GPIOPAD_INT_TYPE 0x0151 475 #define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 476 #define regSMU_GPIOPAD_INT_POLARITY 0x0152 477 #define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 478 #define regSMUIO_PCC_GPIO_SELECT 0x0155 479 #define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 480 #define regSMU_GPIOPAD_S0 0x0156 481 #define regSMU_GPIOPAD_S0_BASE_IDX 0 482 #define regSMU_GPIOPAD_S1 0x0157 483 #define regSMU_GPIOPAD_S1_BASE_IDX 0 484 #define regSMU_GPIOPAD_SCHMEN 0x0158 485 #define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0 486 #define regSMU_GPIOPAD_SCL_EN 0x0159 487 #define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0 488 #define regSMU_GPIOPAD_SDA_EN 0x015a 489 #define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0 490 #define regSMUIO_GPIO_INT0_SELECT 0x015b 491 #define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 492 #define regSMUIO_GPIO_INT1_SELECT 0x015c 493 #define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 494 #define regSMUIO_GPIO_INT2_SELECT 0x015d 495 #define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 496 #define regSMUIO_GPIO_INT3_SELECT 0x015e 497 #define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 498 #define regSMU_GPIOPAD_MP_INT0_STAT 0x015f 499 #define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 500 #define regSMU_GPIOPAD_MP_INT1_STAT 0x0160 501 #define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 502 #define regSMU_GPIOPAD_MP_INT2_STAT 0x0161 503 #define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 504 #define regSMU_GPIOPAD_MP_INT3_STAT 0x0162 505 #define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 506 #define regSMIO_INDEX 0x0163 507 #define regSMIO_INDEX_BASE_IDX 0 508 #define regS0_VID_SMIO_CNTL 0x0164 509 #define regS0_VID_SMIO_CNTL_BASE_IDX 0 510 #define regS1_VID_SMIO_CNTL 0x0165 511 #define regS1_VID_SMIO_CNTL_BASE_IDX 0 512 #define regOPEN_DRAIN_SELECT 0x0166 513 #define regOPEN_DRAIN_SELECT_BASE_IDX 0 514 #define regSMIO_ENABLE 0x0167 515 #define regSMIO_ENABLE_BASE_IDX 0 516 517 #endif 518