1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "include/logger_interface.h" 28 #include "../dce110/irq_service_dce110.h" 29 30 31 #include "yellow_carp_offset.h" 32 #include "dcn/dcn_3_1_2_offset.h" 33 #include "dcn/dcn_3_1_2_sh_mask.h" 34 35 #include "irq_service_dcn31.h" 36 37 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 38 39 static enum dc_irq_source to_dal_irq_source_dcn31(struct irq_service *irq_service, 40 uint32_t src_id, 41 uint32_t ext_id) 42 { 43 switch (src_id) { 44 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 45 return DC_IRQ_SOURCE_VBLANK1; 46 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 47 return DC_IRQ_SOURCE_VBLANK2; 48 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 49 return DC_IRQ_SOURCE_VBLANK3; 50 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 51 return DC_IRQ_SOURCE_VBLANK4; 52 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 53 return DC_IRQ_SOURCE_VBLANK5; 54 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 55 return DC_IRQ_SOURCE_VBLANK6; 56 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: 57 return DC_IRQ_SOURCE_DC1_VLINE0; 58 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: 59 return DC_IRQ_SOURCE_DC2_VLINE0; 60 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: 61 return DC_IRQ_SOURCE_DC3_VLINE0; 62 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: 63 return DC_IRQ_SOURCE_DC4_VLINE0; 64 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: 65 return DC_IRQ_SOURCE_DC5_VLINE0; 66 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: 67 return DC_IRQ_SOURCE_DC6_VLINE0; 68 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 69 return DC_IRQ_SOURCE_PFLIP1; 70 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 71 return DC_IRQ_SOURCE_PFLIP2; 72 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 73 return DC_IRQ_SOURCE_PFLIP3; 74 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 75 return DC_IRQ_SOURCE_PFLIP4; 76 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 77 return DC_IRQ_SOURCE_PFLIP5; 78 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 79 return DC_IRQ_SOURCE_PFLIP6; 80 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 81 return DC_IRQ_SOURCE_VUPDATE1; 82 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 83 return DC_IRQ_SOURCE_VUPDATE2; 84 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 85 return DC_IRQ_SOURCE_VUPDATE3; 86 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 87 return DC_IRQ_SOURCE_VUPDATE4; 88 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 89 return DC_IRQ_SOURCE_VUPDATE5; 90 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 91 return DC_IRQ_SOURCE_VUPDATE6; 92 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: 93 return DC_IRQ_SOURCE_DMCUB_OUTBOX; 94 case DCN_1_0__SRCID__DC_HPD1_INT: 95 /* generic src_id for all HPD and HPDRX interrupts */ 96 switch (ext_id) { 97 case DCN_1_0__CTXID__DC_HPD1_INT: 98 return DC_IRQ_SOURCE_HPD1; 99 case DCN_1_0__CTXID__DC_HPD2_INT: 100 return DC_IRQ_SOURCE_HPD2; 101 case DCN_1_0__CTXID__DC_HPD3_INT: 102 return DC_IRQ_SOURCE_HPD3; 103 case DCN_1_0__CTXID__DC_HPD4_INT: 104 return DC_IRQ_SOURCE_HPD4; 105 case DCN_1_0__CTXID__DC_HPD5_INT: 106 return DC_IRQ_SOURCE_HPD5; 107 case DCN_1_0__CTXID__DC_HPD6_INT: 108 return DC_IRQ_SOURCE_HPD6; 109 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 110 return DC_IRQ_SOURCE_HPD1RX; 111 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 112 return DC_IRQ_SOURCE_HPD2RX; 113 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 114 return DC_IRQ_SOURCE_HPD3RX; 115 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 116 return DC_IRQ_SOURCE_HPD4RX; 117 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 118 return DC_IRQ_SOURCE_HPD5RX; 119 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 120 return DC_IRQ_SOURCE_HPD6RX; 121 default: 122 return DC_IRQ_SOURCE_INVALID; 123 } 124 break; 125 126 default: 127 return DC_IRQ_SOURCE_INVALID; 128 } 129 } 130 131 static bool hpd_ack( 132 struct irq_service *irq_service, 133 const struct irq_source_info *info) 134 { 135 uint32_t addr = info->status_reg; 136 uint32_t value = dm_read_reg(irq_service->ctx, addr); 137 uint32_t current_status = 138 get_reg_field_value( 139 value, 140 HPD0_DC_HPD_INT_STATUS, 141 DC_HPD_SENSE_DELAYED); 142 143 dal_irq_service_ack_generic(irq_service, info); 144 145 value = dm_read_reg(irq_service->ctx, info->enable_reg); 146 147 set_reg_field_value( 148 value, 149 current_status ? 0 : 1, 150 HPD0_DC_HPD_INT_CONTROL, 151 DC_HPD_INT_POLARITY); 152 153 dm_write_reg(irq_service->ctx, info->enable_reg, value); 154 155 return true; 156 } 157 158 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 159 .set = NULL, 160 .ack = hpd_ack 161 }; 162 163 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 164 .set = NULL, 165 .ack = NULL 166 }; 167 168 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 169 .set = NULL, 170 .ack = NULL 171 }; 172 173 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 174 .set = NULL, 175 .ack = NULL 176 }; 177 178 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 179 .set = NULL, 180 .ack = NULL 181 }; 182 183 static const struct irq_source_info_funcs outbox_irq_info_funcs = { 184 .set = NULL, 185 .ack = NULL 186 }; 187 188 static const struct irq_source_info_funcs vline0_irq_info_funcs = { 189 .set = NULL, 190 .ack = NULL 191 }; 192 193 #undef BASE_INNER 194 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 195 196 /* compile time expand base address. */ 197 #define BASE(seg) \ 198 BASE_INNER(seg) 199 200 #define SRI(reg_name, block, id)\ 201 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 202 reg ## block ## id ## _ ## reg_name 203 204 #define SRI_DMUB(reg_name)\ 205 BASE(reg ## reg_name ## _BASE_IDX) + \ 206 reg ## reg_name 207 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 209 .enable_reg = SRI(reg1, block, reg_num),\ 210 .enable_mask = \ 211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 212 .enable_value = {\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 215 },\ 216 .ack_reg = SRI(reg2, block, reg_num),\ 217 .ack_mask = \ 218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 219 .ack_value = \ 220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 221 222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 223 .enable_reg = SRI_DMUB(reg1),\ 224 .enable_mask = \ 225 reg1 ## __ ## mask1 ## _MASK,\ 226 .enable_value = {\ 227 reg1 ## __ ## mask1 ## _MASK,\ 228 ~reg1 ## __ ## mask1 ## _MASK \ 229 },\ 230 .ack_reg = SRI_DMUB(reg2),\ 231 .ack_mask = \ 232 reg2 ## __ ## mask2 ## _MASK,\ 233 .ack_value = \ 234 reg2 ## __ ## mask2 ## _MASK \ 235 236 #define hpd_int_entry(reg_num)\ 237 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 238 IRQ_REG_ENTRY(HPD, reg_num,\ 239 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 240 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 241 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 242 .funcs = &hpd_irq_info_funcs\ 243 } 244 245 #define hpd_rx_int_entry(reg_num)\ 246 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 247 IRQ_REG_ENTRY(HPD, reg_num,\ 248 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 249 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 250 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 251 .funcs = &hpd_rx_irq_info_funcs\ 252 } 253 #define pflip_int_entry(reg_num)\ 254 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 255 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 256 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 257 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 258 .funcs = &pflip_irq_info_funcs\ 259 } 260 261 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 262 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 263 */ 264 #define vupdate_no_lock_int_entry(reg_num)\ 265 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 266 IRQ_REG_ENTRY(OTG, reg_num,\ 267 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 268 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 269 .funcs = &vupdate_no_lock_irq_info_funcs\ 270 } 271 272 #define vblank_int_entry(reg_num)\ 273 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 274 IRQ_REG_ENTRY(OTG, reg_num,\ 275 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 276 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 277 .funcs = &vblank_irq_info_funcs\ 278 } 279 280 #define vline0_int_entry(reg_num)\ 281 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ 282 IRQ_REG_ENTRY(OTG, reg_num,\ 283 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ 284 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ 285 .funcs = &vline0_irq_info_funcs\ 286 } 287 #define dmub_outbox_int_entry()\ 288 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ 289 IRQ_REG_ENTRY_DMUB(\ 290 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ 291 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ 292 .funcs = &outbox_irq_info_funcs\ 293 } 294 295 #define dummy_irq_entry() \ 296 {\ 297 .funcs = &dummy_irq_info_funcs\ 298 } 299 300 #define i2c_int_entry(reg_num) \ 301 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 302 303 #define dp_sink_int_entry(reg_num) \ 304 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 305 306 #define gpio_pad_int_entry(reg_num) \ 307 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 308 309 #define dc_underflow_int_entry(reg_num) \ 310 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 311 312 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 313 .set = dal_irq_service_dummy_set, 314 .ack = dal_irq_service_dummy_ack 315 }; 316 317 static const struct irq_source_info 318 irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = { 319 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 320 hpd_int_entry(0), 321 hpd_int_entry(1), 322 hpd_int_entry(2), 323 hpd_int_entry(3), 324 hpd_int_entry(4), 325 hpd_rx_int_entry(0), 326 hpd_rx_int_entry(1), 327 hpd_rx_int_entry(2), 328 hpd_rx_int_entry(3), 329 hpd_rx_int_entry(4), 330 i2c_int_entry(1), 331 i2c_int_entry(2), 332 i2c_int_entry(3), 333 i2c_int_entry(4), 334 i2c_int_entry(5), 335 i2c_int_entry(6), 336 dp_sink_int_entry(1), 337 dp_sink_int_entry(2), 338 dp_sink_int_entry(3), 339 dp_sink_int_entry(4), 340 dp_sink_int_entry(5), 341 dp_sink_int_entry(6), 342 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 343 pflip_int_entry(0), 344 pflip_int_entry(1), 345 pflip_int_entry(2), 346 pflip_int_entry(3), 347 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 348 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 349 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 350 gpio_pad_int_entry(0), 351 gpio_pad_int_entry(1), 352 gpio_pad_int_entry(2), 353 gpio_pad_int_entry(3), 354 gpio_pad_int_entry(4), 355 gpio_pad_int_entry(5), 356 gpio_pad_int_entry(6), 357 gpio_pad_int_entry(7), 358 gpio_pad_int_entry(8), 359 gpio_pad_int_entry(9), 360 gpio_pad_int_entry(10), 361 gpio_pad_int_entry(11), 362 gpio_pad_int_entry(12), 363 gpio_pad_int_entry(13), 364 gpio_pad_int_entry(14), 365 gpio_pad_int_entry(15), 366 gpio_pad_int_entry(16), 367 gpio_pad_int_entry(17), 368 gpio_pad_int_entry(18), 369 gpio_pad_int_entry(19), 370 gpio_pad_int_entry(20), 371 gpio_pad_int_entry(21), 372 gpio_pad_int_entry(22), 373 gpio_pad_int_entry(23), 374 gpio_pad_int_entry(24), 375 gpio_pad_int_entry(25), 376 gpio_pad_int_entry(26), 377 gpio_pad_int_entry(27), 378 gpio_pad_int_entry(28), 379 gpio_pad_int_entry(29), 380 gpio_pad_int_entry(30), 381 dc_underflow_int_entry(1), 382 dc_underflow_int_entry(2), 383 dc_underflow_int_entry(3), 384 dc_underflow_int_entry(4), 385 dc_underflow_int_entry(5), 386 dc_underflow_int_entry(6), 387 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 388 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 389 vupdate_no_lock_int_entry(0), 390 vupdate_no_lock_int_entry(1), 391 vupdate_no_lock_int_entry(2), 392 vupdate_no_lock_int_entry(3), 393 vblank_int_entry(0), 394 vblank_int_entry(1), 395 vblank_int_entry(2), 396 vblank_int_entry(3), 397 vline0_int_entry(0), 398 vline0_int_entry(1), 399 vline0_int_entry(2), 400 vline0_int_entry(3), 401 [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), 402 [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), 403 dmub_outbox_int_entry(), 404 }; 405 406 static const struct irq_service_funcs irq_service_funcs_dcn31 = { 407 .to_dal_irq_source = to_dal_irq_source_dcn31 408 }; 409 410 static void dcn31_irq_construct( 411 struct irq_service *irq_service, 412 struct irq_service_init_data *init_data) 413 { 414 dal_irq_service_construct(irq_service, init_data); 415 416 irq_service->info = irq_source_info_dcn31; 417 irq_service->funcs = &irq_service_funcs_dcn31; 418 } 419 420 struct irq_service *dal_irq_service_dcn31_create( 421 struct irq_service_init_data *init_data) 422 { 423 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 424 GFP_KERNEL); 425 426 if (!irq_service) 427 return NULL; 428 429 dcn31_irq_construct(irq_service, init_data); 430 return irq_service; 431 } 432