1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN) 37 #include "mpc.h" 38 #endif 39 #include "dwb.h" 40 #include "mcif_wb.h" 41 #include "panel_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 #include "link_hwss.h" 58 59 /************ link *****************/ 60 struct link_init_data { 61 const struct dc *dc; 62 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 63 uint32_t connector_index; /* this will be mapped to the HPD pins */ 64 uint32_t link_index; /* this is mapped to DAL display_index 65 TODO: remove it when DC is complete. */ 66 bool is_dpia_link; 67 }; 68 69 struct dc_link *link_create(const struct link_init_data *init_params); 70 void link_destroy(struct dc_link **link); 71 72 enum dc_status dc_link_validate_mode_timing( 73 const struct dc_stream_state *stream, 74 struct dc_link *link, 75 const struct dc_crtc_timing *timing); 76 77 void core_link_resume(struct dc_link *link); 78 79 void core_link_enable_stream( 80 struct dc_state *state, 81 struct pipe_ctx *pipe_ctx); 82 83 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 84 85 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 86 /********** DAL Core*********************/ 87 #include "transform.h" 88 #include "dpp.h" 89 90 struct resource_pool; 91 struct dc_state; 92 struct resource_context; 93 struct clk_bw_params; 94 95 struct resource_funcs { 96 void (*destroy)(struct resource_pool **pool); 97 void (*link_init)(struct dc_link *link); 98 struct panel_cntl*(*panel_cntl_create)( 99 const struct panel_cntl_init_data *panel_cntl_init_data); 100 struct link_encoder *(*link_enc_create)( 101 const struct encoder_init_data *init); 102 /* Create a minimal link encoder object with no dc_link object 103 * associated with it. */ 104 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 105 106 bool (*validate_bandwidth)( 107 struct dc *dc, 108 struct dc_state *context, 109 bool fast_validate); 110 void (*calculate_wm_and_dlg)( 111 struct dc *dc, struct dc_state *context, 112 display_e2e_pipe_params_st *pipes, 113 int pipe_cnt, 114 int vlevel); 115 void (*update_soc_for_wm_a)( 116 struct dc *dc, struct dc_state *context); 117 int (*populate_dml_pipes)( 118 struct dc *dc, 119 struct dc_state *context, 120 display_e2e_pipe_params_st *pipes, 121 bool fast_validate); 122 123 /* 124 * Algorithm for assigning available link encoders to links. 125 * 126 * Update link_enc_assignments table and link_enc_avail list accordingly in 127 * struct resource_context. 128 */ 129 void (*link_encs_assign)( 130 struct dc *dc, 131 struct dc_state *state, 132 struct dc_stream_state *streams[], 133 uint8_t stream_count); 134 /* 135 * Unassign a link encoder from a stream. 136 * 137 * Update link_enc_assignments table and link_enc_avail list accordingly in 138 * struct resource_context. 139 */ 140 void (*link_enc_unassign)( 141 struct dc_state *state, 142 struct dc_stream_state *stream); 143 144 enum dc_status (*validate_global)( 145 struct dc *dc, 146 struct dc_state *context); 147 148 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 149 struct dc_state *context, 150 const struct resource_pool *pool, 151 struct dc_stream_state *stream); 152 153 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 154 155 enum dc_status (*add_stream_to_ctx)( 156 struct dc *dc, 157 struct dc_state *new_ctx, 158 struct dc_stream_state *dc_stream); 159 160 enum dc_status (*remove_stream_from_ctx)( 161 struct dc *dc, 162 struct dc_state *new_ctx, 163 struct dc_stream_state *stream); 164 enum dc_status (*patch_unknown_plane_state)( 165 struct dc_plane_state *plane_state); 166 167 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 168 struct resource_context *res_ctx, 169 const struct resource_pool *pool, 170 struct dc_stream_state *stream); 171 void (*populate_dml_writeback_from_context)( 172 struct dc *dc, 173 struct resource_context *res_ctx, 174 display_e2e_pipe_params_st *pipes); 175 176 void (*set_mcif_arb_params)( 177 struct dc *dc, 178 struct dc_state *context, 179 display_e2e_pipe_params_st *pipes, 180 int pipe_cnt); 181 void (*update_bw_bounding_box)( 182 struct dc *dc, 183 struct clk_bw_params *bw_params); 184 #if defined(CONFIG_DRM_AMD_DC_DCN) 185 bool (*acquire_post_bldn_3dlut)( 186 struct resource_context *res_ctx, 187 const struct resource_pool *pool, 188 int mpcc_id, 189 struct dc_3dlut **lut, 190 struct dc_transfer_func **shaper); 191 192 bool (*release_post_bldn_3dlut)( 193 struct resource_context *res_ctx, 194 const struct resource_pool *pool, 195 struct dc_3dlut **lut, 196 struct dc_transfer_func **shaper); 197 #endif 198 enum dc_status (*add_dsc_to_stream_resource)( 199 struct dc *dc, struct dc_state *state, 200 struct dc_stream_state *stream); 201 }; 202 203 struct audio_support{ 204 bool dp_audio; 205 bool hdmi_audio_on_dongle; 206 bool hdmi_audio_native; 207 }; 208 209 #define NO_UNDERLAY_PIPE -1 210 211 struct resource_pool { 212 struct mem_input *mis[MAX_PIPES]; 213 struct hubp *hubps[MAX_PIPES]; 214 struct input_pixel_processor *ipps[MAX_PIPES]; 215 struct transform *transforms[MAX_PIPES]; 216 struct dpp *dpps[MAX_PIPES]; 217 struct output_pixel_processor *opps[MAX_PIPES]; 218 struct timing_generator *timing_generators[MAX_PIPES]; 219 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 220 struct hubbub *hubbub; 221 struct mpc *mpc; 222 struct pp_smu_funcs *pp_smu; 223 struct dce_aux *engines[MAX_PIPES]; 224 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 225 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 226 bool i2c_hw_buffer_in_use; 227 228 struct dwbc *dwbc[MAX_DWB_PIPES]; 229 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 230 struct { 231 unsigned int gsl_0:1; 232 unsigned int gsl_1:1; 233 unsigned int gsl_2:1; 234 } gsl_groups; 235 236 struct display_stream_compressor *dscs[MAX_PIPES]; 237 238 unsigned int pipe_count; 239 unsigned int underlay_pipe_index; 240 unsigned int stream_enc_count; 241 242 /* An array for accessing the link encoder objects that have been created. 243 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 244 */ 245 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 246 /* Number of DIG link encoder objects created - i.e. number of valid 247 * entries in link_encoders array. 248 */ 249 unsigned int dig_link_enc_count; 250 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 251 unsigned int usb4_dpia_count; 252 253 unsigned int hpo_dp_stream_enc_count; 254 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 255 unsigned int hpo_dp_link_enc_count; 256 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 257 #if defined(CONFIG_DRM_AMD_DC_DCN) 258 struct dc_3dlut *mpc_lut[MAX_PIPES]; 259 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 260 #endif 261 struct { 262 unsigned int xtalin_clock_inKhz; 263 unsigned int dccg_ref_clock_inKhz; 264 unsigned int dchub_ref_clock_inKhz; 265 } ref_clocks; 266 unsigned int timing_generator_count; 267 unsigned int mpcc_count; 268 269 unsigned int writeback_pipe_count; 270 /* 271 * reserved clock source for DP 272 */ 273 struct clock_source *dp_clock_source; 274 275 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 276 unsigned int clk_src_count; 277 278 struct audio *audios[MAX_AUDIOS]; 279 unsigned int audio_count; 280 struct audio_support audio_support; 281 282 struct dccg *dccg; 283 struct irq_service *irqs; 284 285 struct abm *abm; 286 struct dmcu *dmcu; 287 struct dmub_psr *psr; 288 289 #if defined(CONFIG_DRM_AMD_DC_DCN) 290 struct abm *multiple_abms[MAX_PIPES]; 291 #endif 292 293 const struct resource_funcs *funcs; 294 const struct resource_caps *res_cap; 295 296 struct ddc_service *oem_device; 297 }; 298 299 struct dcn_fe_bandwidth { 300 int dppclk_khz; 301 302 }; 303 304 struct stream_resource { 305 struct output_pixel_processor *opp; 306 struct display_stream_compressor *dsc; 307 struct timing_generator *tg; 308 struct stream_encoder *stream_enc; 309 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 310 struct audio *audio; 311 312 struct pixel_clk_params pix_clk_params; 313 struct encoder_info_frame encoder_info_frame; 314 315 struct abm *abm; 316 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 317 * otherwise it's using group number 'gsl_group-1' 318 */ 319 uint8_t gsl_group; 320 }; 321 322 struct plane_resource { 323 struct scaler_data scl_data; 324 struct hubp *hubp; 325 struct mem_input *mi; 326 struct input_pixel_processor *ipp; 327 struct transform *xfm; 328 struct dpp *dpp; 329 uint8_t mpcc_inst; 330 331 struct dcn_fe_bandwidth bw; 332 }; 333 334 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 335 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 336 337 /* all mappable hardware resources used to enable a link */ 338 struct link_resource { 339 struct hpo_dp_link_encoder *hpo_dp_link_enc; 340 }; 341 342 union pipe_update_flags { 343 struct { 344 uint32_t enable : 1; 345 uint32_t disable : 1; 346 uint32_t odm : 1; 347 uint32_t global_sync : 1; 348 uint32_t opp_changed : 1; 349 uint32_t tg_changed : 1; 350 uint32_t mpcc : 1; 351 uint32_t dppclk : 1; 352 uint32_t hubp_interdependent : 1; 353 uint32_t hubp_rq_dlg_ttu : 1; 354 uint32_t gamut_remap : 1; 355 uint32_t scaler : 1; 356 uint32_t viewport : 1; 357 uint32_t plane_changed : 1; 358 uint32_t det_size : 1; 359 } bits; 360 uint32_t raw; 361 }; 362 363 struct pipe_ctx { 364 struct dc_plane_state *plane_state; 365 struct dc_stream_state *stream; 366 367 struct plane_resource plane_res; 368 struct stream_resource stream_res; 369 struct link_resource link_res; 370 371 struct clock_source *clock_source; 372 373 struct pll_settings pll_settings; 374 375 uint8_t pipe_idx; 376 uint8_t pipe_idx_syncd; 377 378 struct pipe_ctx *top_pipe; 379 struct pipe_ctx *bottom_pipe; 380 struct pipe_ctx *next_odm_pipe; 381 struct pipe_ctx *prev_odm_pipe; 382 383 #ifdef CONFIG_DRM_AMD_DC_DCN 384 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 385 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 386 struct _vcs_dpi_display_rq_regs_st rq_regs; 387 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 388 struct _vcs_dpi_display_rq_params_st dml_rq_param; 389 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 390 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 391 int det_buffer_size_kb; 392 bool unbounded_req; 393 #endif 394 union pipe_update_flags update_flags; 395 struct dwbc *dwbc; 396 struct mcif_wb *mcif_wb; 397 bool vtp_locked; 398 }; 399 400 /* Data used for dynamic link encoder assignment. 401 * Tracks current and future assignments; available link encoders; 402 * and mode of operation (whether to use current or future assignments). 403 */ 404 struct link_enc_cfg_context { 405 enum link_enc_cfg_mode mode; 406 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 407 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 408 struct link_enc_assignment transient_assignments[MAX_PIPES]; 409 }; 410 411 struct resource_context { 412 struct pipe_ctx pipe_ctx[MAX_PIPES]; 413 bool is_stream_enc_acquired[MAX_PIPES * 2]; 414 bool is_audio_acquired[MAX_PIPES]; 415 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 416 uint8_t dp_clock_source_ref_count; 417 bool is_dsc_acquired[MAX_PIPES]; 418 struct link_enc_cfg_context link_enc_cfg_ctx; 419 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 420 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 421 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 422 #if defined(CONFIG_DRM_AMD_DC_DCN) 423 bool is_mpc_3dlut_acquired[MAX_PIPES]; 424 #endif 425 }; 426 427 struct dce_bw_output { 428 bool cpuc_state_change_enable; 429 bool cpup_state_change_enable; 430 bool stutter_mode_enable; 431 bool nbp_state_change_enable; 432 bool all_displays_in_sync; 433 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 434 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 435 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 436 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 437 int sclk_khz; 438 int sclk_deep_sleep_khz; 439 int yclk_khz; 440 int dispclk_khz; 441 int blackout_recovery_time_us; 442 }; 443 444 struct dcn_bw_writeback { 445 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 446 }; 447 448 struct dcn_bw_output { 449 struct dc_clocks clk; 450 struct dcn_watermark_set watermarks; 451 struct dcn_bw_writeback bw_writeback; 452 int compbuf_size_kb; 453 }; 454 455 union bw_output { 456 struct dcn_bw_output dcn; 457 struct dce_bw_output dce; 458 }; 459 460 struct bw_context { 461 union bw_output bw; 462 struct display_mode_lib dml; 463 }; 464 /** 465 * struct dc_state - The full description of a state requested by a user 466 * 467 * @streams: Stream properties 468 * @stream_status: The planes on a given stream 469 * @res_ctx: Persistent state of resources 470 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 471 * @pp_display_cfg: PowerPlay clocks and settings 472 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 473 * 474 */ 475 struct dc_state { 476 struct dc_stream_state *streams[MAX_PIPES]; 477 struct dc_stream_status stream_status[MAX_PIPES]; 478 uint8_t stream_count; 479 uint8_t stream_mask; 480 481 struct resource_context res_ctx; 482 483 struct bw_context bw_ctx; 484 485 /* Note: these are big structures, do *not* put on stack! */ 486 struct dm_pp_display_configuration pp_display_cfg; 487 #ifdef CONFIG_DRM_AMD_DC_DCN 488 struct dcn_bw_internal_vars dcn_bw_vars; 489 #endif 490 491 struct clk_mgr *clk_mgr; 492 493 struct kref refcount; 494 495 struct { 496 unsigned int stutter_period_us; 497 } perf_params; 498 }; 499 500 #endif /* _CORE_TYPES_H_ */ 501