1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "dc_bios_types.h" 29 #include "core_types.h" 30 #include "core_status.h" 31 #include "resource.h" 32 #include "dm_helpers.h" 33 #include "dce110_hwseq.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "dce/dce_hwseq.h" 36 #include "gpio_service_interface.h" 37 38 #include "dce110/dce110_compressor.h" 39 40 #include "bios/bios_parser_helper.h" 41 #include "timing_generator.h" 42 #include "mem_input.h" 43 #include "opp.h" 44 #include "ipp.h" 45 #include "transform.h" 46 #include "stream_encoder.h" 47 #include "link_encoder.h" 48 #include "link_enc_cfg.h" 49 #include "link_hwss.h" 50 #include "link.h" 51 #include "dccg.h" 52 #include "clock_source.h" 53 #include "clk_mgr.h" 54 #include "abm.h" 55 #include "audio.h" 56 #include "reg_helper.h" 57 #include "panel_cntl.h" 58 #include "dc_state_priv.h" 59 #include "dpcd_defs.h" 60 /* include DCE11 register header files */ 61 #include "dce/dce_11_0_d.h" 62 #include "dce/dce_11_0_sh_mask.h" 63 #include "custom_float.h" 64 65 #include "atomfirmware.h" 66 67 #include "dcn10/dcn10_hwseq.h" 68 69 #define GAMMA_HW_POINTS_NUM 256 70 71 /* 72 * All values are in milliseconds; 73 * For eDP, after power-up/power/down, 74 * 300/500 msec max. delay from LCDVCC to black video generation 75 */ 76 #define PANEL_POWER_UP_TIMEOUT 300 77 #define PANEL_POWER_DOWN_TIMEOUT 500 78 #define HPD_CHECK_INTERVAL 10 79 #define OLED_POST_T7_DELAY 100 80 #define OLED_PRE_T11_DELAY 150 81 82 #define CTX \ 83 hws->ctx 84 85 #define DC_LOGGER \ 86 ctx->logger 87 #define DC_LOGGER_INIT() \ 88 struct dc_context *ctx = dc->ctx 89 90 #define REG(reg)\ 91 hws->regs->reg 92 93 #undef FN 94 #define FN(reg_name, field_name) \ 95 hws->shifts->field_name, hws->masks->field_name 96 97 struct dce110_hw_seq_reg_offsets { 98 uint32_t crtc; 99 }; 100 101 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 102 { 103 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 104 }, 105 { 106 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 113 } 114 }; 115 116 #define HW_REG_BLND(reg, id)\ 117 (reg + reg_offsets[id].blnd) 118 119 #define HW_REG_CRTC(reg, id)\ 120 (reg + reg_offsets[id].crtc) 121 122 #define MAX_WATERMARK 0xFFFF 123 #define SAFE_NBP_MARK 0x7FFF 124 125 /******************************************************************************* 126 * Private definitions 127 ******************************************************************************/ 128 /***************************PIPE_CONTROL***********************************/ 129 static void dce110_init_pte(struct dc_context *ctx) 130 { 131 uint32_t addr; 132 uint32_t value = 0; 133 uint32_t chunk_int = 0; 134 uint32_t chunk_mul = 0; 135 136 addr = mmUNP_DVMM_PTE_CONTROL; 137 value = dm_read_reg(ctx, addr); 138 139 set_reg_field_value( 140 value, 141 0, 142 DVMM_PTE_CONTROL, 143 DVMM_USE_SINGLE_PTE); 144 145 set_reg_field_value( 146 value, 147 1, 148 DVMM_PTE_CONTROL, 149 DVMM_PTE_BUFFER_MODE0); 150 151 set_reg_field_value( 152 value, 153 1, 154 DVMM_PTE_CONTROL, 155 DVMM_PTE_BUFFER_MODE1); 156 157 dm_write_reg(ctx, addr, value); 158 159 addr = mmDVMM_PTE_REQ; 160 value = dm_read_reg(ctx, addr); 161 162 chunk_int = get_reg_field_value( 163 value, 164 DVMM_PTE_REQ, 165 HFLIP_PTEREQ_PER_CHUNK_INT); 166 167 chunk_mul = get_reg_field_value( 168 value, 169 DVMM_PTE_REQ, 170 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 171 172 if (chunk_int != 0x4 || chunk_mul != 0x4) { 173 174 set_reg_field_value( 175 value, 176 255, 177 DVMM_PTE_REQ, 178 MAX_PTEREQ_TO_ISSUE); 179 180 set_reg_field_value( 181 value, 182 4, 183 DVMM_PTE_REQ, 184 HFLIP_PTEREQ_PER_CHUNK_INT); 185 186 set_reg_field_value( 187 value, 188 4, 189 DVMM_PTE_REQ, 190 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 191 192 dm_write_reg(ctx, addr, value); 193 } 194 } 195 /**************************************************************************/ 196 197 static void enable_display_pipe_clock_gating( 198 struct dc_context *ctx, 199 bool clock_gating) 200 { 201 /*TODO*/ 202 } 203 204 static bool dce110_enable_display_power_gating( 205 struct dc *dc, 206 uint8_t controller_id, 207 struct dc_bios *dcb, 208 enum pipe_gating_control power_gating) 209 { 210 enum bp_result bp_result = BP_RESULT_OK; 211 enum bp_pipe_control_action cntl; 212 struct dc_context *ctx = dc->ctx; 213 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 214 215 if (power_gating == PIPE_GATING_CONTROL_INIT) 216 cntl = ASIC_PIPE_INIT; 217 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 218 cntl = ASIC_PIPE_ENABLE; 219 else 220 cntl = ASIC_PIPE_DISABLE; 221 222 if (controller_id == underlay_idx) 223 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 224 225 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { 226 227 bp_result = dcb->funcs->enable_disp_power_gating( 228 dcb, controller_id + 1, cntl); 229 230 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 231 * by default when command table is called 232 * 233 * Bios parser accepts controller_id = 6 as indicative of 234 * underlay pipe in dce110. But we do not support more 235 * than 3. 236 */ 237 if (controller_id < CONTROLLER_ID_MAX - 1) 238 dm_write_reg(ctx, 239 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 240 0); 241 } 242 243 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 244 dce110_init_pte(ctx); 245 246 if (bp_result == BP_RESULT_OK) 247 return true; 248 else 249 return false; 250 } 251 252 static void build_prescale_params(struct ipp_prescale_params *prescale_params, 253 const struct dc_plane_state *plane_state) 254 { 255 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 256 257 switch (plane_state->format) { 258 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 259 prescale_params->scale = 0x2082; 260 break; 261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 262 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 263 prescale_params->scale = 0x2020; 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 267 prescale_params->scale = 0x2008; 268 break; 269 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 270 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 272 prescale_params->scale = 0x2000; 273 break; 274 default: 275 ASSERT(false); 276 break; 277 } 278 } 279 280 static bool 281 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 282 const struct dc_plane_state *plane_state) 283 { 284 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 285 const struct dc_transfer_func *tf = NULL; 286 struct ipp_prescale_params prescale_params = { 0 }; 287 bool result = true; 288 289 if (ipp == NULL) 290 return false; 291 292 if (plane_state->in_transfer_func) 293 tf = plane_state->in_transfer_func; 294 295 build_prescale_params(&prescale_params, plane_state); 296 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 297 298 if (plane_state->gamma_correction && 299 !plane_state->gamma_correction->is_identity && 300 dce_use_lut(plane_state->format)) 301 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 302 303 if (tf == NULL) { 304 /* Default case if no input transfer function specified */ 305 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 306 } else if (tf->type == TF_TYPE_PREDEFINED) { 307 switch (tf->tf) { 308 case TRANSFER_FUNCTION_SRGB: 309 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 310 break; 311 case TRANSFER_FUNCTION_BT709: 312 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 313 break; 314 case TRANSFER_FUNCTION_LINEAR: 315 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 316 break; 317 case TRANSFER_FUNCTION_PQ: 318 default: 319 result = false; 320 break; 321 } 322 } else if (tf->type == TF_TYPE_BYPASS) { 323 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 324 } else { 325 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 326 result = false; 327 } 328 329 return result; 330 } 331 332 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 333 struct curve_points *arr_points, 334 uint32_t hw_points_num) 335 { 336 struct custom_float_format fmt; 337 338 struct pwl_result_data *rgb = rgb_resulted; 339 340 uint32_t i = 0; 341 342 fmt.exponenta_bits = 6; 343 fmt.mantissa_bits = 12; 344 fmt.sign = true; 345 346 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 347 &arr_points[0].custom_float_x)) { 348 BREAK_TO_DEBUGGER(); 349 return false; 350 } 351 352 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 353 &arr_points[0].custom_float_offset)) { 354 BREAK_TO_DEBUGGER(); 355 return false; 356 } 357 358 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 359 &arr_points[0].custom_float_slope)) { 360 BREAK_TO_DEBUGGER(); 361 return false; 362 } 363 364 fmt.mantissa_bits = 10; 365 fmt.sign = false; 366 367 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 368 &arr_points[1].custom_float_x)) { 369 BREAK_TO_DEBUGGER(); 370 return false; 371 } 372 373 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 374 &arr_points[1].custom_float_y)) { 375 BREAK_TO_DEBUGGER(); 376 return false; 377 } 378 379 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 380 &arr_points[1].custom_float_slope)) { 381 BREAK_TO_DEBUGGER(); 382 return false; 383 } 384 385 fmt.mantissa_bits = 12; 386 fmt.sign = true; 387 388 while (i != hw_points_num) { 389 if (!convert_to_custom_float_format(rgb->red, &fmt, 390 &rgb->red_reg)) { 391 BREAK_TO_DEBUGGER(); 392 return false; 393 } 394 395 if (!convert_to_custom_float_format(rgb->green, &fmt, 396 &rgb->green_reg)) { 397 BREAK_TO_DEBUGGER(); 398 return false; 399 } 400 401 if (!convert_to_custom_float_format(rgb->blue, &fmt, 402 &rgb->blue_reg)) { 403 BREAK_TO_DEBUGGER(); 404 return false; 405 } 406 407 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 408 &rgb->delta_red_reg)) { 409 BREAK_TO_DEBUGGER(); 410 return false; 411 } 412 413 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 414 &rgb->delta_green_reg)) { 415 BREAK_TO_DEBUGGER(); 416 return false; 417 } 418 419 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 420 &rgb->delta_blue_reg)) { 421 BREAK_TO_DEBUGGER(); 422 return false; 423 } 424 425 ++rgb; 426 ++i; 427 } 428 429 return true; 430 } 431 432 #define MAX_LOW_POINT 25 433 #define NUMBER_REGIONS 16 434 #define NUMBER_SW_SEGMENTS 16 435 436 static bool 437 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 438 struct pwl_params *regamma_params) 439 { 440 struct curve_points *arr_points; 441 struct pwl_result_data *rgb_resulted; 442 struct pwl_result_data *rgb; 443 struct pwl_result_data *rgb_plus_1; 444 struct fixed31_32 y_r; 445 struct fixed31_32 y_g; 446 struct fixed31_32 y_b; 447 struct fixed31_32 y1_min; 448 struct fixed31_32 y3_max; 449 450 int32_t region_start, region_end; 451 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 452 453 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 454 return false; 455 456 arr_points = regamma_params->arr_points; 457 rgb_resulted = regamma_params->rgb_resulted; 458 hw_points = 0; 459 460 memset(regamma_params, 0, sizeof(struct pwl_params)); 461 462 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 463 /* 16 segments 464 * segments are from 2^-11 to 2^5 465 */ 466 region_start = -11; 467 region_end = region_start + NUMBER_REGIONS; 468 469 for (i = 0; i < NUMBER_REGIONS; i++) 470 seg_distr[i] = 4; 471 472 } else { 473 /* 10 segments 474 * segment is from 2^-10 to 2^1 475 * We include an extra segment for range [2^0, 2^1). This is to 476 * ensure that colors with normalized values of 1 don't miss the 477 * LUT. 478 */ 479 region_start = -10; 480 region_end = 1; 481 482 seg_distr[0] = 4; 483 seg_distr[1] = 4; 484 seg_distr[2] = 4; 485 seg_distr[3] = 4; 486 seg_distr[4] = 4; 487 seg_distr[5] = 4; 488 seg_distr[6] = 4; 489 seg_distr[7] = 4; 490 seg_distr[8] = 4; 491 seg_distr[9] = 4; 492 seg_distr[10] = 0; 493 seg_distr[11] = -1; 494 seg_distr[12] = -1; 495 seg_distr[13] = -1; 496 seg_distr[14] = -1; 497 seg_distr[15] = -1; 498 } 499 500 for (k = 0; k < 16; k++) { 501 if (seg_distr[k] != -1) 502 hw_points += (1 << seg_distr[k]); 503 } 504 505 j = 0; 506 for (k = 0; k < (region_end - region_start); k++) { 507 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 508 start_index = (region_start + k + MAX_LOW_POINT) * 509 NUMBER_SW_SEGMENTS; 510 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 511 i += increment) { 512 if (j == hw_points - 1) 513 break; 514 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 515 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 516 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 517 j++; 518 } 519 } 520 521 /* last point */ 522 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 523 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 524 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 525 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 526 527 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 528 dc_fixpt_from_int(region_start)); 529 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 530 dc_fixpt_from_int(region_end)); 531 532 y_r = rgb_resulted[0].red; 533 y_g = rgb_resulted[0].green; 534 y_b = rgb_resulted[0].blue; 535 536 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 537 538 arr_points[0].y = y1_min; 539 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 540 arr_points[0].x); 541 542 y_r = rgb_resulted[hw_points - 1].red; 543 y_g = rgb_resulted[hw_points - 1].green; 544 y_b = rgb_resulted[hw_points - 1].blue; 545 546 /* see comment above, m_arrPoints[1].y should be the Y value for the 547 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 548 */ 549 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 550 551 arr_points[1].y = y3_max; 552 553 arr_points[1].slope = dc_fixpt_zero; 554 555 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 556 /* for PQ, we want to have a straight line from last HW X point, 557 * and the slope to be such that we hit 1.0 at 10000 nits. 558 */ 559 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 560 561 arr_points[1].slope = dc_fixpt_div( 562 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 563 dc_fixpt_sub(end_value, arr_points[1].x)); 564 } 565 566 regamma_params->hw_points_num = hw_points; 567 568 k = 0; 569 for (i = 1; i < 16; i++) { 570 if (seg_distr[k] != -1) { 571 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 572 regamma_params->arr_curve_points[i].offset = 573 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 574 } 575 k++; 576 } 577 578 if (seg_distr[k] != -1) 579 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 580 581 rgb = rgb_resulted; 582 rgb_plus_1 = rgb_resulted + 1; 583 584 i = 1; 585 586 while (i != hw_points + 1) { 587 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 588 rgb_plus_1->red = rgb->red; 589 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 590 rgb_plus_1->green = rgb->green; 591 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 592 rgb_plus_1->blue = rgb->blue; 593 594 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 595 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 596 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 597 598 ++rgb_plus_1; 599 ++rgb; 600 ++i; 601 } 602 603 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 604 605 return true; 606 } 607 608 static bool 609 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 610 const struct dc_stream_state *stream) 611 { 612 struct transform *xfm = pipe_ctx->plane_res.xfm; 613 614 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 615 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 616 617 if (stream->out_transfer_func && 618 stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 619 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 620 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 621 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 622 &xfm->regamma_params)) { 623 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 624 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 625 } else { 626 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 627 } 628 629 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 630 631 return true; 632 } 633 634 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 635 { 636 bool is_hdmi_tmds; 637 bool is_dp; 638 639 ASSERT(pipe_ctx->stream); 640 641 if (pipe_ctx->stream_res.stream_enc == NULL) 642 return; /* this is not root pipe */ 643 644 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 645 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 646 647 if (!is_hdmi_tmds && !is_dp) 648 return; 649 650 if (is_hdmi_tmds) 651 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 652 pipe_ctx->stream_res.stream_enc, 653 &pipe_ctx->stream_res.encoder_info_frame); 654 else { 655 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 656 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 657 pipe_ctx->stream_res.stream_enc, 658 &pipe_ctx->stream_res.encoder_info_frame); 659 660 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 661 pipe_ctx->stream_res.stream_enc, 662 &pipe_ctx->stream_res.encoder_info_frame); 663 } 664 } 665 666 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 667 { 668 enum dc_lane_count lane_count = 669 pipe_ctx->stream->link->cur_link_settings.lane_count; 670 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 671 struct dc_link *link = pipe_ctx->stream->link; 672 const struct dc *dc = link->dc; 673 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 674 uint32_t active_total_with_borders; 675 uint32_t early_control = 0; 676 struct timing_generator *tg = pipe_ctx->stream_res.tg; 677 678 link_hwss->setup_stream_encoder(pipe_ctx); 679 680 dc->hwss.update_info_frame(pipe_ctx); 681 682 /* enable early control to avoid corruption on DP monitor*/ 683 active_total_with_borders = 684 timing->h_addressable 685 + timing->h_border_left 686 + timing->h_border_right; 687 688 if (lane_count != 0) 689 early_control = active_total_with_borders % lane_count; 690 691 if (early_control == 0) 692 early_control = lane_count; 693 694 tg->funcs->set_early_control(tg, early_control); 695 } 696 697 static enum bp_result link_transmitter_control( 698 struct dc_bios *bios, 699 struct bp_transmitter_control *cntl) 700 { 701 enum bp_result result; 702 703 result = bios->funcs->transmitter_control(bios, cntl); 704 705 return result; 706 } 707 708 /* 709 * @brief 710 * eDP only. 711 */ 712 void dce110_edp_wait_for_hpd_ready( 713 struct dc_link *link, 714 bool power_up) 715 { 716 struct dc_context *ctx = link->ctx; 717 struct graphics_object_id connector = link->link_enc->connector; 718 struct gpio *hpd; 719 bool edp_hpd_high = false; 720 uint32_t time_elapsed = 0; 721 uint32_t timeout = power_up ? 722 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 723 724 if (dal_graphics_object_id_get_connector_id(connector) 725 != CONNECTOR_ID_EDP) { 726 BREAK_TO_DEBUGGER(); 727 return; 728 } 729 730 if (!power_up) 731 /* 732 * From KV, we will not HPD low after turning off VCC - 733 * instead, we will check the SW timer in power_up(). 734 */ 735 return; 736 737 /* 738 * When we power on/off the eDP panel, 739 * we need to wait until SENSE bit is high/low. 740 */ 741 742 /* obtain HPD */ 743 /* TODO what to do with this? */ 744 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 745 746 if (!hpd) { 747 BREAK_TO_DEBUGGER(); 748 return; 749 } 750 751 if (link != NULL) { 752 if (link->panel_config.pps.extra_t3_ms > 0) { 753 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms; 754 755 msleep(extra_t3_in_ms); 756 } 757 } 758 759 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 760 761 /* wait until timeout or panel detected */ 762 763 do { 764 uint32_t detected = 0; 765 766 dal_gpio_get_value(hpd, &detected); 767 768 if (!(detected ^ power_up)) { 769 edp_hpd_high = true; 770 break; 771 } 772 773 msleep(HPD_CHECK_INTERVAL); 774 775 time_elapsed += HPD_CHECK_INTERVAL; 776 } while (time_elapsed < timeout); 777 778 dal_gpio_close(hpd); 779 780 dal_gpio_destroy_irq(&hpd); 781 782 /* ensure that the panel is detected */ 783 if (!edp_hpd_high) 784 DC_LOG_DC("%s: wait timed out!\n", __func__); 785 } 786 787 void dce110_edp_power_control( 788 struct dc_link *link, 789 bool power_up) 790 { 791 struct dc_context *ctx = link->ctx; 792 struct bp_transmitter_control cntl = { 0 }; 793 enum bp_result bp_result; 794 uint8_t pwrseq_instance; 795 796 797 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 798 != CONNECTOR_ID_EDP) { 799 BREAK_TO_DEBUGGER(); 800 return; 801 } 802 803 if (!link->panel_cntl) 804 return; 805 if (power_up != 806 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 807 808 unsigned long long current_ts = dm_get_timestamp(ctx); 809 unsigned long long time_since_edp_poweroff_ms = 810 div64_u64(dm_get_elapse_time_in_ns( 811 ctx, 812 current_ts, 813 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 814 unsigned long long time_since_edp_poweron_ms = 815 div64_u64(dm_get_elapse_time_in_ns( 816 ctx, 817 current_ts, 818 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000); 819 DC_LOG_HW_RESUME_S3( 820 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 821 __func__, 822 power_up, 823 current_ts, 824 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 825 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link), 826 time_since_edp_poweroff_ms, 827 time_since_edp_poweron_ms); 828 829 /* Send VBIOS command to prompt eDP panel power */ 830 if (power_up) { 831 /* edp requires a min of 500ms from LCDVDD off to on */ 832 unsigned long long remaining_min_edp_poweroff_time_ms = 500; 833 834 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 835 if (link->local_sink != NULL) 836 remaining_min_edp_poweroff_time_ms += 837 link->panel_config.pps.extra_t12_ms; 838 839 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 840 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 841 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 842 remaining_min_edp_poweroff_time_ms = 843 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 844 else 845 remaining_min_edp_poweroff_time_ms = 0; 846 } 847 848 if (remaining_min_edp_poweroff_time_ms) { 849 DC_LOG_HW_RESUME_S3( 850 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 851 __func__, remaining_min_edp_poweroff_time_ms); 852 msleep(remaining_min_edp_poweroff_time_ms); 853 DC_LOG_HW_RESUME_S3( 854 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 855 __func__, remaining_min_edp_poweroff_time_ms); 856 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 857 __func__, remaining_min_edp_poweroff_time_ms); 858 } else { 859 DC_LOG_HW_RESUME_S3( 860 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 861 __func__, remaining_min_edp_poweroff_time_ms); 862 } 863 } 864 865 DC_LOG_HW_RESUME_S3( 866 "%s: BEGIN: Panel Power action: %s\n", 867 __func__, (power_up ? "On":"Off")); 868 869 cntl.action = power_up ? 870 TRANSMITTER_CONTROL_POWER_ON : 871 TRANSMITTER_CONTROL_POWER_OFF; 872 cntl.transmitter = link->link_enc->transmitter; 873 cntl.connector_obj_id = link->link_enc->connector; 874 cntl.coherent = false; 875 cntl.lanes_number = LANE_COUNT_FOUR; 876 cntl.hpd_sel = link->link_enc->hpd_source; 877 pwrseq_instance = link->panel_cntl->pwrseq_inst; 878 879 if (ctx->dc->ctx->dmub_srv && 880 ctx->dc->debug.dmub_command_table) { 881 882 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) { 883 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 884 LVTMA_CONTROL_POWER_ON, 885 pwrseq_instance, link->link_powered_externally); 886 } else { 887 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 888 LVTMA_CONTROL_POWER_OFF, 889 pwrseq_instance, link->link_powered_externally); 890 } 891 } 892 893 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 894 895 DC_LOG_HW_RESUME_S3( 896 "%s: END: Panel Power action: %s bp_result=%u\n", 897 __func__, (power_up ? "On":"Off"), 898 bp_result); 899 900 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up); 901 902 DC_LOG_HW_RESUME_S3( 903 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 904 __func__, 905 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 906 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)); 907 908 if (bp_result != BP_RESULT_OK) 909 DC_LOG_ERROR( 910 "%s: Panel Power bp_result: %d\n", 911 __func__, bp_result); 912 } else { 913 DC_LOG_HW_RESUME_S3( 914 "%s: Skipping Panel Power action: %s\n", 915 __func__, (power_up ? "On":"Off")); 916 } 917 } 918 919 void dce110_edp_wait_for_T12( 920 struct dc_link *link) 921 { 922 struct dc_context *ctx = link->ctx; 923 924 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 925 != CONNECTOR_ID_EDP) { 926 BREAK_TO_DEBUGGER(); 927 return; 928 } 929 930 if (!link->panel_cntl) 931 return; 932 933 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 934 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 935 unsigned int t12_duration = 500; // Default T12 as per spec 936 unsigned long long current_ts = dm_get_timestamp(ctx); 937 unsigned long long time_since_edp_poweroff_ms = 938 div64_u64(dm_get_elapse_time_in_ns( 939 ctx, 940 current_ts, 941 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 942 943 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 944 945 if (time_since_edp_poweroff_ms < t12_duration) 946 msleep(t12_duration - time_since_edp_poweroff_ms); 947 } 948 } 949 /*todo: cloned in stream enc, fix*/ 950 /* 951 * @brief 952 * eDP only. Control the backlight of the eDP panel 953 */ 954 void dce110_edp_backlight_control( 955 struct dc_link *link, 956 bool enable) 957 { 958 struct dc_context *ctx = link->ctx; 959 struct bp_transmitter_control cntl = { 0 }; 960 uint8_t pwrseq_instance; 961 unsigned int pre_T11_delay = OLED_PRE_T11_DELAY; 962 unsigned int post_T7_delay = OLED_POST_T7_DELAY; 963 964 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 965 != CONNECTOR_ID_EDP) { 966 BREAK_TO_DEBUGGER(); 967 return; 968 } 969 970 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled || 971 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 972 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { 973 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 974 975 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 976 DC_LOG_HW_RESUME_S3( 977 "%s: panel already powered up/off. Do nothing.\n", 978 __func__); 979 return; 980 } 981 } 982 983 /* Send VBIOS command to control eDP panel backlight */ 984 985 DC_LOG_HW_RESUME_S3( 986 "%s: backlight action: %s\n", 987 __func__, (enable ? "On":"Off")); 988 989 cntl.action = enable ? 990 TRANSMITTER_CONTROL_BACKLIGHT_ON : 991 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 992 993 /*cntl.engine_id = ctx->engine;*/ 994 cntl.transmitter = link->link_enc->transmitter; 995 cntl.connector_obj_id = link->link_enc->connector; 996 /*todo: unhardcode*/ 997 cntl.lanes_number = LANE_COUNT_FOUR; 998 cntl.hpd_sel = link->link_enc->hpd_source; 999 cntl.signal = SIGNAL_TYPE_EDP; 1000 1001 /* For eDP, the following delays might need to be considered 1002 * after link training completed: 1003 * idle period - min. accounts for required BS-Idle pattern, 1004 * max. allows for source frame synchronization); 1005 * 50 msec max. delay from valid video data from source 1006 * to video on dislpay or backlight enable. 1007 * 1008 * Disable the delay for now. 1009 * Enable it in the future if necessary. 1010 */ 1011 /* dc_service_sleep_in_milliseconds(50); */ 1012 /*edp 1.2*/ 1013 pwrseq_instance = link->panel_cntl->pwrseq_inst; 1014 1015 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1016 if (!link->dc->config.edp_no_power_sequencing) 1017 /* 1018 * Sometimes, DP receiver chip power-controlled externally by an 1019 * Embedded Controller could be treated and used as eDP, 1020 * if it drives mobile display. In this case, 1021 * we shouldn't be doing power-sequencing, hence we can skip 1022 * waiting for T7-ready. 1023 */ 1024 ctx->dc->link_srv->edp_receiver_ready_T7(link); 1025 else 1026 DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1027 } 1028 1029 /* Setting link_powered_externally will bypass delays in the backlight 1030 * as they are not required if the link is being powered by a different 1031 * source. 1032 */ 1033 if (ctx->dc->ctx->dmub_srv && 1034 ctx->dc->debug.dmub_command_table) { 1035 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1036 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1037 LVTMA_CONTROL_LCD_BLON, 1038 pwrseq_instance, link->link_powered_externally); 1039 else 1040 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1041 LVTMA_CONTROL_LCD_BLOFF, 1042 pwrseq_instance, link->link_powered_externally); 1043 } 1044 1045 link_transmitter_control(ctx->dc_bios, &cntl); 1046 1047 if (enable && link->dpcd_sink_ext_caps.bits.oled && 1048 !link->dc->config.edp_no_power_sequencing) { 1049 post_T7_delay += link->panel_config.pps.extra_post_t7_ms; 1050 msleep(post_T7_delay); 1051 } 1052 1053 if (link->dpcd_sink_ext_caps.bits.oled || 1054 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1055 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 1056 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable); 1057 1058 /*edp 1.2*/ 1059 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1060 if (!link->dc->config.edp_no_power_sequencing) 1061 /* 1062 * Sometimes, DP receiver chip power-controlled externally by an 1063 * Embedded Controller could be treated and used as eDP, 1064 * if it drives mobile display. In this case, 1065 * we shouldn't be doing power-sequencing, hence we can skip 1066 * waiting for T9-ready. 1067 */ 1068 ctx->dc->link_srv->edp_add_delay_for_T9(link); 1069 else 1070 DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1071 } 1072 1073 if (!enable && link->dpcd_sink_ext_caps.bits.oled) { 1074 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms; 1075 msleep(pre_T11_delay); 1076 } 1077 } 1078 1079 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 1080 { 1081 /* notify audio driver for audio modes of monitor */ 1082 struct dc *dc; 1083 struct clk_mgr *clk_mgr; 1084 unsigned int i, num_audio = 1; 1085 const struct link_hwss *link_hwss; 1086 1087 if (!pipe_ctx->stream) 1088 return; 1089 1090 dc = pipe_ctx->stream->ctx->dc; 1091 clk_mgr = dc->clk_mgr; 1092 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1093 1094 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 1095 return; 1096 1097 if (pipe_ctx->stream_res.audio) { 1098 for (i = 0; i < MAX_PIPES; i++) { 1099 /*current_state not updated yet*/ 1100 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1101 num_audio++; 1102 } 1103 1104 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1105 1106 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 1107 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1108 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1109 1110 link_hwss->enable_audio_packet(pipe_ctx); 1111 1112 if (pipe_ctx->stream_res.audio) 1113 pipe_ctx->stream_res.audio->enabled = true; 1114 } 1115 } 1116 1117 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 1118 { 1119 struct dc *dc; 1120 struct clk_mgr *clk_mgr; 1121 const struct link_hwss *link_hwss; 1122 1123 if (!pipe_ctx || !pipe_ctx->stream) 1124 return; 1125 1126 dc = pipe_ctx->stream->ctx->dc; 1127 clk_mgr = dc->clk_mgr; 1128 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1129 1130 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 1131 return; 1132 1133 link_hwss->disable_audio_packet(pipe_ctx); 1134 1135 if (pipe_ctx->stream_res.audio) { 1136 pipe_ctx->stream_res.audio->enabled = false; 1137 1138 if (clk_mgr->funcs->enable_pme_wa) 1139 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1140 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1141 1142 /* TODO: notify audio driver for if audio modes list changed 1143 * add audio mode list change flag */ 1144 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1145 * stream->stream_engine_id); 1146 */ 1147 } 1148 } 1149 1150 void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1151 { 1152 struct dc_stream_state *stream = pipe_ctx->stream; 1153 struct dc_link *link = stream->link; 1154 struct dc *dc = pipe_ctx->stream->ctx->dc; 1155 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1156 struct dccg *dccg = dc->res_pool->dccg; 1157 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1158 struct dtbclk_dto_params dto_params = {0}; 1159 int dp_hpo_inst; 1160 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 1161 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 1162 1163 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1164 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1165 pipe_ctx->stream_res.stream_enc); 1166 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1167 pipe_ctx->stream_res.stream_enc); 1168 } 1169 1170 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1171 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1172 pipe_ctx->stream_res.hpo_dp_stream_enc); 1173 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1174 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1175 pipe_ctx->stream_res.stream_enc); 1176 1177 dc->hwss.disable_audio_stream(pipe_ctx); 1178 1179 link_hwss->reset_stream_encoder(pipe_ctx); 1180 1181 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) { 1182 dto_params.otg_inst = tg->inst; 1183 dto_params.timing = &pipe_ctx->stream->timing; 1184 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 1185 if (dccg) { 1186 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1187 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1188 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1189 } 1190 } else if (dccg && dccg->funcs->disable_symclk_se) { 1191 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 1192 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 1193 } 1194 1195 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1196 /* TODO: This looks like a bug to me as we are disabling HPO IO when 1197 * we are just disabling a single HPO stream. Shouldn't we disable HPO 1198 * HW control only when HPOs for all streams are disabled? 1199 */ 1200 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 1201 pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 1202 pipe_ctx->stream->ctx->dc->hwseq, false); 1203 } 1204 } 1205 1206 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1207 struct dc_link_settings *link_settings) 1208 { 1209 struct encoder_unblank_param params = { { 0 } }; 1210 struct dc_stream_state *stream = pipe_ctx->stream; 1211 struct dc_link *link = stream->link; 1212 struct dce_hwseq *hws = link->dc->hwseq; 1213 1214 /* only 3 items below are used by unblank */ 1215 params.timing = pipe_ctx->stream->timing; 1216 params.link_settings.link_rate = link_settings->link_rate; 1217 1218 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1219 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1220 1221 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1222 hws->funcs.edp_backlight_control(link, true); 1223 } 1224 } 1225 1226 void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1227 { 1228 struct dc_stream_state *stream = pipe_ctx->stream; 1229 struct dc_link *link = stream->link; 1230 struct dce_hwseq *hws = link->dc->hwseq; 1231 1232 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1233 if (!link->skip_implict_edp_power_control) 1234 hws->funcs.edp_backlight_control(link, false); 1235 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1236 } 1237 1238 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1239 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1240 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1241 pipe_ctx->stream_res.hpo_dp_stream_enc); 1242 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1243 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1244 1245 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1246 /* 1247 * After output is idle pattern some sinks need time to recognize the stream 1248 * has changed or they enter protection state and hang. 1249 */ 1250 msleep(60); 1251 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1252 if (!link->dc->config.edp_no_power_sequencing) { 1253 /* 1254 * Sometimes, DP receiver chip power-controlled externally by an 1255 * Embedded Controller could be treated and used as eDP, 1256 * if it drives mobile display. In this case, 1257 * we shouldn't be doing power-sequencing, hence we can skip 1258 * waiting for T9-ready. 1259 */ 1260 link->dc->link_srv->edp_receiver_ready_T9(link); 1261 } 1262 } 1263 } 1264 1265 } 1266 1267 1268 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1269 { 1270 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1271 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1272 } 1273 1274 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1275 { 1276 switch (crtc_id) { 1277 case CONTROLLER_ID_D0: 1278 return DTO_SOURCE_ID0; 1279 case CONTROLLER_ID_D1: 1280 return DTO_SOURCE_ID1; 1281 case CONTROLLER_ID_D2: 1282 return DTO_SOURCE_ID2; 1283 case CONTROLLER_ID_D3: 1284 return DTO_SOURCE_ID3; 1285 case CONTROLLER_ID_D4: 1286 return DTO_SOURCE_ID4; 1287 case CONTROLLER_ID_D5: 1288 return DTO_SOURCE_ID5; 1289 default: 1290 return DTO_SOURCE_UNKNOWN; 1291 } 1292 } 1293 1294 static void build_audio_output( 1295 struct dc_state *state, 1296 const struct pipe_ctx *pipe_ctx, 1297 struct audio_output *audio_output) 1298 { 1299 const struct dc_stream_state *stream = pipe_ctx->stream; 1300 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1301 1302 audio_output->signal = pipe_ctx->stream->signal; 1303 1304 /* audio_crtc_info */ 1305 1306 audio_output->crtc_info.h_total = 1307 stream->timing.h_total; 1308 1309 /* 1310 * Audio packets are sent during actual CRTC blank physical signal, we 1311 * need to specify actual active signal portion 1312 */ 1313 audio_output->crtc_info.h_active = 1314 stream->timing.h_addressable 1315 + stream->timing.h_border_left 1316 + stream->timing.h_border_right; 1317 1318 audio_output->crtc_info.v_active = 1319 stream->timing.v_addressable 1320 + stream->timing.v_border_top 1321 + stream->timing.v_border_bottom; 1322 1323 audio_output->crtc_info.pixel_repetition = 1; 1324 1325 audio_output->crtc_info.interlaced = 1326 stream->timing.flags.INTERLACE; 1327 1328 audio_output->crtc_info.refresh_rate = 1329 (stream->timing.pix_clk_100hz*100)/ 1330 (stream->timing.h_total*stream->timing.v_total); 1331 1332 audio_output->crtc_info.color_depth = 1333 stream->timing.display_color_depth; 1334 1335 audio_output->crtc_info.requested_pixel_clock_100Hz = 1336 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1337 1338 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1339 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1340 1341 /*for HDMI, audio ACR is with deep color ratio factor*/ 1342 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 1343 audio_output->crtc_info.requested_pixel_clock_100Hz == 1344 (stream->timing.pix_clk_100hz)) { 1345 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1346 audio_output->crtc_info.requested_pixel_clock_100Hz = 1347 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1348 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1349 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1350 1351 } 1352 } 1353 1354 if (state->clk_mgr && 1355 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1356 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1357 audio_output->pll_info.audio_dto_source_clock_in_khz = 1358 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1359 state->clk_mgr); 1360 } 1361 1362 audio_output->pll_info.feed_back_divider = 1363 pipe_ctx->pll_settings.feedback_divider; 1364 1365 audio_output->pll_info.dto_source = 1366 translate_to_dto_source( 1367 pipe_ctx->stream_res.tg->inst + 1); 1368 1369 /* TODO hard code to enable for now. Need get from stream */ 1370 audio_output->pll_info.ss_enabled = true; 1371 1372 audio_output->pll_info.ss_percentage = 1373 pipe_ctx->pll_settings.ss_percentage; 1374 } 1375 1376 static void program_scaler(const struct dc *dc, 1377 const struct pipe_ctx *pipe_ctx) 1378 { 1379 struct tg_color color = {0}; 1380 1381 /* TOFPGA */ 1382 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1383 return; 1384 1385 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1386 get_surface_visual_confirm_color(pipe_ctx, &color); 1387 else 1388 color_space_to_black_color(dc, 1389 pipe_ctx->stream->output_color_space, 1390 &color); 1391 1392 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1393 pipe_ctx->plane_res.xfm, 1394 pipe_ctx->plane_res.scl_data.lb_params.depth, 1395 &pipe_ctx->stream->bit_depth_params); 1396 1397 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1398 /* 1399 * The way 420 is packed, 2 channels carry Y component, 1 channel 1400 * alternate between Cb and Cr, so both channels need the pixel 1401 * value for Y 1402 */ 1403 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1404 color.color_r_cr = color.color_g_y; 1405 1406 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1407 pipe_ctx->stream_res.tg, 1408 &color); 1409 } 1410 1411 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1412 &pipe_ctx->plane_res.scl_data); 1413 } 1414 1415 static enum dc_status dce110_enable_stream_timing( 1416 struct pipe_ctx *pipe_ctx, 1417 struct dc_state *context, 1418 struct dc *dc) 1419 { 1420 struct dc_stream_state *stream = pipe_ctx->stream; 1421 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1422 pipe_ctx[pipe_ctx->pipe_idx]; 1423 struct tg_color black_color = {0}; 1424 1425 if (!pipe_ctx_old->stream) { 1426 1427 /* program blank color */ 1428 color_space_to_black_color(dc, 1429 stream->output_color_space, &black_color); 1430 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1431 pipe_ctx->stream_res.tg, 1432 &black_color); 1433 1434 /* 1435 * Must blank CRTC after disabling power gating and before any 1436 * programming, otherwise CRTC will be hung in bad state 1437 */ 1438 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1439 1440 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1441 pipe_ctx->clock_source, 1442 &pipe_ctx->stream_res.pix_clk_params, 1443 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1444 &pipe_ctx->pll_settings)) { 1445 BREAK_TO_DEBUGGER(); 1446 return DC_ERROR_UNEXPECTED; 1447 } 1448 1449 if (dc_is_hdmi_tmds_signal(stream->signal)) { 1450 stream->link->phy_state.symclk_ref_cnts.otg = 1; 1451 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 1452 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1453 else 1454 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 1455 } 1456 1457 pipe_ctx->stream_res.tg->funcs->program_timing( 1458 pipe_ctx->stream_res.tg, 1459 &stream->timing, 1460 0, 1461 0, 1462 0, 1463 0, 1464 pipe_ctx->stream->signal, 1465 true); 1466 } 1467 1468 if (!pipe_ctx_old->stream) { 1469 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1470 pipe_ctx->stream_res.tg)) { 1471 BREAK_TO_DEBUGGER(); 1472 return DC_ERROR_UNEXPECTED; 1473 } 1474 } 1475 1476 return DC_OK; 1477 } 1478 1479 enum dc_status dce110_apply_single_controller_ctx_to_hw( 1480 struct pipe_ctx *pipe_ctx, 1481 struct dc_state *context, 1482 struct dc *dc) 1483 { 1484 struct dc_stream_state *stream = pipe_ctx->stream; 1485 struct dc_link *link = stream->link; 1486 struct drr_params params = {0}; 1487 unsigned int event_triggers = 0; 1488 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1489 struct dce_hwseq *hws = dc->hwseq; 1490 const struct link_hwss *link_hwss = get_link_hwss( 1491 link, &pipe_ctx->link_res); 1492 1493 1494 if (hws->funcs.disable_stream_gating) { 1495 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1496 } 1497 1498 if (pipe_ctx->stream_res.audio != NULL) { 1499 struct audio_output audio_output; 1500 1501 build_audio_output(context, pipe_ctx, &audio_output); 1502 1503 link_hwss->setup_audio_output(pipe_ctx, &audio_output, 1504 pipe_ctx->stream_res.audio->inst); 1505 1506 pipe_ctx->stream_res.audio->funcs->az_configure( 1507 pipe_ctx->stream_res.audio, 1508 pipe_ctx->stream->signal, 1509 &audio_output.crtc_info, 1510 &pipe_ctx->stream->audio_info); 1511 } 1512 1513 /* make sure no pipes syncd to the pipe being enabled */ 1514 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1515 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1516 1517 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1518 pipe_ctx->stream_res.opp, 1519 &stream->bit_depth_params, 1520 &stream->clamping); 1521 1522 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1523 pipe_ctx->stream_res.opp, 1524 COLOR_SPACE_YCBCR601, 1525 stream->timing.display_color_depth, 1526 stream->signal); 1527 1528 while (odm_pipe) { 1529 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1530 odm_pipe->stream_res.opp, 1531 COLOR_SPACE_YCBCR601, 1532 stream->timing.display_color_depth, 1533 stream->signal); 1534 1535 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1536 odm_pipe->stream_res.opp, 1537 &stream->bit_depth_params, 1538 &stream->clamping); 1539 odm_pipe = odm_pipe->next_odm_pipe; 1540 } 1541 1542 /* DCN3.1 FPGA Workaround 1543 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1544 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1545 * function core_link_enable_stream 1546 */ 1547 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))) 1548 /* */ 1549 /* Do not touch stream timing on seamless boot optimization. */ 1550 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1551 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1552 1553 if (hws->funcs.setup_vupdate_interrupt) 1554 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1555 1556 params.vertical_total_min = stream->adjust.v_total_min; 1557 params.vertical_total_max = stream->adjust.v_total_max; 1558 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1559 pipe_ctx->stream_res.tg->funcs->set_drr( 1560 pipe_ctx->stream_res.tg, ¶ms); 1561 1562 // DRR should set trigger event to monitor surface update event 1563 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1564 event_triggers = 0x80; 1565 /* Event triggers and num frames initialized for DRR, but can be 1566 * later updated for PSR use. Note DRR trigger events are generated 1567 * regardless of whether num frames met. 1568 */ 1569 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1570 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1571 pipe_ctx->stream_res.tg, event_triggers, 2); 1572 1573 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1574 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1575 pipe_ctx->stream_res.stream_enc, 1576 pipe_ctx->stream_res.tg->inst); 1577 1578 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1579 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 1580 1581 if (!stream->dpms_off) 1582 dc->link_srv->set_dpms_on(context, pipe_ctx); 1583 1584 /* DCN3.1 FPGA Workaround 1585 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1586 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1587 * function core_link_enable_stream 1588 */ 1589 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1590 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1591 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1592 } 1593 1594 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 1595 1596 /* Phantom and main stream share the same link (because the stream 1597 * is constructed with the same sink). Make sure not to override 1598 * and link programming on the main. 1599 */ 1600 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { 1601 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1602 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false; 1603 } 1604 return DC_OK; 1605 } 1606 1607 /******************************************************************************/ 1608 1609 static void power_down_encoders(struct dc *dc) 1610 { 1611 int i; 1612 1613 for (i = 0; i < dc->link_count; i++) { 1614 enum signal_type signal = dc->links[i]->connector_signal; 1615 1616 dc->link_srv->blank_dp_stream(dc->links[i], false); 1617 1618 if (signal != SIGNAL_TYPE_EDP) 1619 signal = SIGNAL_TYPE_NONE; 1620 1621 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) 1622 dc->links[i]->link_enc->funcs->disable_output( 1623 dc->links[i]->link_enc, signal); 1624 1625 dc->links[i]->link_status.link_active = false; 1626 memset(&dc->links[i]->cur_link_settings, 0, 1627 sizeof(dc->links[i]->cur_link_settings)); 1628 } 1629 } 1630 1631 static void power_down_controllers(struct dc *dc) 1632 { 1633 int i; 1634 1635 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1636 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1637 dc->res_pool->timing_generators[i]); 1638 } 1639 } 1640 1641 static void power_down_clock_sources(struct dc *dc) 1642 { 1643 int i; 1644 1645 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1646 dc->res_pool->dp_clock_source) == false) 1647 dm_error("Failed to power down pll! (dp clk src)\n"); 1648 1649 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1650 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1651 dc->res_pool->clock_sources[i]) == false) 1652 dm_error("Failed to power down pll! (clk src index=%d)\n", i); 1653 } 1654 } 1655 1656 static void power_down_all_hw_blocks(struct dc *dc) 1657 { 1658 power_down_encoders(dc); 1659 1660 power_down_controllers(dc); 1661 1662 power_down_clock_sources(dc); 1663 1664 if (dc->fbc_compressor) 1665 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1666 } 1667 1668 static void disable_vga_and_power_gate_all_controllers( 1669 struct dc *dc) 1670 { 1671 int i; 1672 struct timing_generator *tg; 1673 struct dc_context *ctx = dc->ctx; 1674 1675 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1676 tg = dc->res_pool->timing_generators[i]; 1677 1678 if (tg->funcs->disable_vga) 1679 tg->funcs->disable_vga(tg); 1680 } 1681 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1682 /* Enable CLOCK gating for each pipe BEFORE controller 1683 * powergating. */ 1684 enable_display_pipe_clock_gating(ctx, 1685 true); 1686 1687 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1688 dc->hwss.disable_plane(dc, dc->current_state, 1689 &dc->current_state->res_ctx.pipe_ctx[i]); 1690 } 1691 } 1692 1693 1694 static void get_edp_streams(struct dc_state *context, 1695 struct dc_stream_state **edp_streams, 1696 int *edp_stream_num) 1697 { 1698 int i; 1699 1700 *edp_stream_num = 0; 1701 for (i = 0; i < context->stream_count; i++) { 1702 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 1703 edp_streams[*edp_stream_num] = context->streams[i]; 1704 if (++(*edp_stream_num) == MAX_NUM_EDP) 1705 return; 1706 } 1707 } 1708 } 1709 1710 static void get_edp_links_with_sink( 1711 struct dc *dc, 1712 struct dc_link **edp_links_with_sink, 1713 int *edp_with_sink_num) 1714 { 1715 int i; 1716 1717 /* check if there is an eDP panel not in use */ 1718 *edp_with_sink_num = 0; 1719 for (i = 0; i < dc->link_count; i++) { 1720 if (dc->links[i]->local_sink && 1721 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1722 edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 1723 if (++(*edp_with_sink_num) == MAX_NUM_EDP) 1724 return; 1725 } 1726 } 1727 } 1728 1729 /* 1730 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 1731 * 1. Power down all DC HW blocks 1732 * 2. Disable VGA engine on all controllers 1733 * 3. Enable power gating for controller 1734 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1735 */ 1736 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 1737 { 1738 struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 1739 struct dc_link *edp_links[MAX_NUM_EDP]; 1740 struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 1741 struct dc_link *edp_link_with_sink = NULL; 1742 struct dc_link *edp_link = NULL; 1743 struct dce_hwseq *hws = dc->hwseq; 1744 int edp_with_sink_num; 1745 int edp_num; 1746 int edp_stream_num; 1747 int i; 1748 bool can_apply_edp_fast_boot = false; 1749 bool can_apply_seamless_boot = false; 1750 bool keep_edp_vdd_on = false; 1751 DC_LOGGER_INIT(); 1752 1753 1754 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 1755 dc_get_edp_links(dc, edp_links, &edp_num); 1756 1757 if (hws->funcs.init_pipes) 1758 hws->funcs.init_pipes(dc, context); 1759 1760 get_edp_streams(context, edp_streams, &edp_stream_num); 1761 1762 // Check fastboot support, disable on DCE8 because of blank screens 1763 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1764 dc->ctx->dce_version != DCE_VERSION_8_1 && 1765 dc->ctx->dce_version != DCE_VERSION_8_3) { 1766 for (i = 0; i < edp_num; i++) { 1767 edp_link = edp_links[i]; 1768 if (edp_link != edp_streams[0]->link) 1769 continue; 1770 // enable fastboot if backend is enabled on eDP 1771 if (edp_link->link_enc->funcs->is_dig_enabled && 1772 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 1773 edp_link->link_status.link_active) { 1774 struct dc_stream_state *edp_stream = edp_streams[0]; 1775 1776 can_apply_edp_fast_boot = dc_validate_boot_timing(dc, 1777 edp_stream->sink, &edp_stream->timing); 1778 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 1779 if (can_apply_edp_fast_boot) 1780 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1781 1782 break; 1783 } 1784 } 1785 // We are trying to enable eDP, don't power down VDD 1786 if (can_apply_edp_fast_boot) 1787 keep_edp_vdd_on = true; 1788 } 1789 1790 // Check seamless boot support 1791 for (i = 0; i < context->stream_count; i++) { 1792 if (context->streams[i]->apply_seamless_boot_optimization) { 1793 can_apply_seamless_boot = true; 1794 break; 1795 } 1796 } 1797 1798 /* eDP should not have stream in resume from S4 and so even with VBios post 1799 * it should get turned off 1800 */ 1801 if (edp_with_sink_num) 1802 edp_link_with_sink = edp_links_with_sink[0]; 1803 1804 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 1805 if (edp_link_with_sink && !keep_edp_vdd_on) { 1806 /*turn off backlight before DP_blank and encoder powered down*/ 1807 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1808 } 1809 /*resume from S3, no vbios posting, no need to power down again*/ 1810 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 1811 1812 power_down_all_hw_blocks(dc); 1813 disable_vga_and_power_gate_all_controllers(dc); 1814 if (edp_link_with_sink && !keep_edp_vdd_on) 1815 dc->hwss.edp_power_control(edp_link_with_sink, false); 1816 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 1817 } 1818 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 1819 } 1820 1821 static uint32_t compute_pstate_blackout_duration( 1822 struct bw_fixed blackout_duration, 1823 const struct dc_stream_state *stream) 1824 { 1825 uint32_t total_dest_line_time_ns; 1826 uint32_t pstate_blackout_duration_ns; 1827 1828 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 1829 1830 total_dest_line_time_ns = 1000000UL * 1831 (stream->timing.h_total * 10) / 1832 stream->timing.pix_clk_100hz + 1833 pstate_blackout_duration_ns; 1834 1835 return total_dest_line_time_ns; 1836 } 1837 1838 static void dce110_set_displaymarks( 1839 const struct dc *dc, 1840 struct dc_state *context) 1841 { 1842 uint8_t i, num_pipes; 1843 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1844 1845 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1846 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1847 uint32_t total_dest_line_time_ns; 1848 1849 if (pipe_ctx->stream == NULL) 1850 continue; 1851 1852 total_dest_line_time_ns = compute_pstate_blackout_duration( 1853 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 1854 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 1855 pipe_ctx->plane_res.mi, 1856 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1857 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1858 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1859 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1860 total_dest_line_time_ns); 1861 if (i == underlay_idx) { 1862 num_pipes++; 1863 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1864 pipe_ctx->plane_res.mi, 1865 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1866 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1867 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1868 total_dest_line_time_ns); 1869 } 1870 num_pipes++; 1871 } 1872 } 1873 1874 void dce110_set_safe_displaymarks( 1875 struct resource_context *res_ctx, 1876 const struct resource_pool *pool) 1877 { 1878 int i; 1879 int underlay_idx = pool->underlay_pipe_index; 1880 struct dce_watermarks max_marks = { 1881 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 1882 struct dce_watermarks nbp_marks = { 1883 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 1884 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 1885 1886 for (i = 0; i < MAX_PIPES; i++) { 1887 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 1888 continue; 1889 1890 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 1891 res_ctx->pipe_ctx[i].plane_res.mi, 1892 nbp_marks, 1893 max_marks, 1894 min_marks, 1895 max_marks, 1896 MAX_WATERMARK); 1897 1898 if (i == underlay_idx) 1899 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1900 res_ctx->pipe_ctx[i].plane_res.mi, 1901 nbp_marks, 1902 max_marks, 1903 max_marks, 1904 MAX_WATERMARK); 1905 1906 } 1907 } 1908 1909 /******************************************************************************* 1910 * Public functions 1911 ******************************************************************************/ 1912 1913 static void set_drr(struct pipe_ctx **pipe_ctx, 1914 int num_pipes, struct dc_crtc_timing_adjust adjust) 1915 { 1916 int i = 0; 1917 struct drr_params params = {0}; 1918 // DRR should set trigger event to monitor surface update event 1919 unsigned int event_triggers = 0x80; 1920 // Note DRR trigger events are generated regardless of whether num frames met. 1921 unsigned int num_frames = 2; 1922 1923 params.vertical_total_max = adjust.v_total_max; 1924 params.vertical_total_min = adjust.v_total_min; 1925 1926 /* TODO: If multiple pipes are to be supported, you need 1927 * some GSL stuff. Static screen triggers may be programmed differently 1928 * as well. 1929 */ 1930 for (i = 0; i < num_pipes; i++) { 1931 pipe_ctx[i]->stream_res.tg->funcs->set_drr( 1932 pipe_ctx[i]->stream_res.tg, ¶ms); 1933 1934 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 1935 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 1936 pipe_ctx[i]->stream_res.tg, 1937 event_triggers, num_frames); 1938 } 1939 } 1940 1941 static void get_position(struct pipe_ctx **pipe_ctx, 1942 int num_pipes, 1943 struct crtc_position *position) 1944 { 1945 int i = 0; 1946 1947 /* TODO: handle pipes > 1 1948 */ 1949 for (i = 0; i < num_pipes; i++) 1950 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 1951 } 1952 1953 static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 1954 int num_pipes, const struct dc_static_screen_params *params) 1955 { 1956 unsigned int i; 1957 unsigned int triggers = 0; 1958 1959 if (params->triggers.overlay_update) 1960 triggers |= 0x100; 1961 if (params->triggers.surface_update) 1962 triggers |= 0x80; 1963 if (params->triggers.cursor_update) 1964 triggers |= 0x2; 1965 if (params->triggers.force_trigger) 1966 triggers |= 0x1; 1967 1968 if (num_pipes) { 1969 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1970 1971 if (dc->fbc_compressor) 1972 triggers |= 0x84; 1973 } 1974 1975 for (i = 0; i < num_pipes; i++) 1976 pipe_ctx[i]->stream_res.tg->funcs-> 1977 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1978 triggers, params->num_frames); 1979 } 1980 1981 /* 1982 * Check if FBC can be enabled 1983 */ 1984 static bool should_enable_fbc(struct dc *dc, 1985 struct dc_state *context, 1986 uint32_t *pipe_idx) 1987 { 1988 uint32_t i; 1989 struct pipe_ctx *pipe_ctx = NULL; 1990 struct resource_context *res_ctx = &context->res_ctx; 1991 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1992 1993 1994 ASSERT(dc->fbc_compressor); 1995 1996 /* FBC memory should be allocated */ 1997 if (!dc->ctx->fbc_gpu_addr) 1998 return false; 1999 2000 /* Only supports single display */ 2001 if (context->stream_count != 1) 2002 return false; 2003 2004 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2005 if (res_ctx->pipe_ctx[i].stream) { 2006 2007 pipe_ctx = &res_ctx->pipe_ctx[i]; 2008 2009 /* fbc not applicable on underlay pipe */ 2010 if (pipe_ctx->pipe_idx != underlay_idx) { 2011 *pipe_idx = i; 2012 break; 2013 } 2014 } 2015 } 2016 2017 if (i == dc->res_pool->pipe_count) 2018 return false; 2019 2020 if (!pipe_ctx->stream->link) 2021 return false; 2022 2023 /* Only supports eDP */ 2024 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 2025 return false; 2026 2027 /* PSR should not be enabled */ 2028 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 2029 return false; 2030 2031 /* Replay should not be enabled */ 2032 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled) 2033 return false; 2034 2035 /* Nothing to compress */ 2036 if (!pipe_ctx->plane_state) 2037 return false; 2038 2039 /* Only for non-linear tiling */ 2040 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2041 return false; 2042 2043 return true; 2044 } 2045 2046 /* 2047 * Enable FBC 2048 */ 2049 static void enable_fbc( 2050 struct dc *dc, 2051 struct dc_state *context) 2052 { 2053 uint32_t pipe_idx = 0; 2054 2055 if (should_enable_fbc(dc, context, &pipe_idx)) { 2056 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2057 struct compr_addr_and_pitch_params params = {0, 0, 0}; 2058 struct compressor *compr = dc->fbc_compressor; 2059 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2060 2061 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 2062 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 2063 params.inst = pipe_ctx->stream_res.tg->inst; 2064 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2065 2066 compr->funcs->surface_address_and_pitch(compr, ¶ms); 2067 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2068 2069 compr->funcs->enable_fbc(compr, ¶ms); 2070 } 2071 } 2072 2073 static void dce110_reset_hw_ctx_wrap( 2074 struct dc *dc, 2075 struct dc_state *context) 2076 { 2077 int i; 2078 2079 /* Reset old context */ 2080 /* look up the targets that have been removed since last commit */ 2081 for (i = 0; i < MAX_PIPES; i++) { 2082 struct pipe_ctx *pipe_ctx_old = 2083 &dc->current_state->res_ctx.pipe_ctx[i]; 2084 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2085 2086 /* Note: We need to disable output if clock sources change, 2087 * since bios does optimization and doesn't apply if changing 2088 * PHY when not already disabled. 2089 */ 2090 2091 /* Skip underlay pipe since it will be handled in commit surface*/ 2092 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 2093 continue; 2094 2095 if (!pipe_ctx->stream || 2096 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2097 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2098 2099 /* Disable if new stream is null. O/w, if stream is 2100 * disabled already, no need to disable again. 2101 */ 2102 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 2103 dc->link_srv->set_dpms_off(pipe_ctx_old); 2104 2105 /* free acquired resources*/ 2106 if (pipe_ctx_old->stream_res.audio) { 2107 /*disable az_endpoint*/ 2108 pipe_ctx_old->stream_res.audio->funcs-> 2109 az_disable(pipe_ctx_old->stream_res.audio); 2110 2111 /*free audio*/ 2112 if (dc->caps.dynamic_audio == true) { 2113 /*we have to dynamic arbitrate the audio endpoints*/ 2114 /*we free the resource, need reset is_audio_acquired*/ 2115 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2116 pipe_ctx_old->stream_res.audio, false); 2117 pipe_ctx_old->stream_res.audio = NULL; 2118 } 2119 } 2120 } 2121 2122 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 2123 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 2124 dm_error("DC: failed to blank crtc!\n"); 2125 BREAK_TO_DEBUGGER(); 2126 } 2127 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 2128 if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal)) 2129 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0; 2130 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2131 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 2132 2133 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2134 dc->res_pool, 2135 old_clk)) 2136 old_clk->funcs->cs_power_down(old_clk); 2137 2138 dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old); 2139 2140 pipe_ctx_old->stream = NULL; 2141 } 2142 } 2143 } 2144 2145 static void dce110_setup_audio_dto( 2146 struct dc *dc, 2147 struct dc_state *context) 2148 { 2149 int i; 2150 2151 /* program audio wall clock. use HDMI as clock source if HDMI 2152 * audio active. Otherwise, use DP as clock source 2153 * first, loop to find any HDMI audio, if not, loop find DP audio 2154 */ 2155 /* Setup audio rate clock source */ 2156 /* Issue: 2157 * Audio lag happened on DP monitor when unplug a HDMI monitor 2158 * 2159 * Cause: 2160 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 2161 * is set to either dto0 or dto1, audio should work fine. 2162 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 2163 * set to dto0 will cause audio lag. 2164 * 2165 * Solution: 2166 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 2167 * find first available pipe with audio, setup audio wall DTO per topology 2168 * instead of per pipe. 2169 */ 2170 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2171 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2172 2173 if (pipe_ctx->stream == NULL) 2174 continue; 2175 2176 if (pipe_ctx->top_pipe) 2177 continue; 2178 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2179 continue; 2180 if (pipe_ctx->stream_res.audio != NULL) { 2181 struct audio_output audio_output; 2182 2183 build_audio_output(context, pipe_ctx, &audio_output); 2184 2185 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2186 struct dtbclk_dto_params dto_params = {0}; 2187 2188 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2189 dc->res_pool->dccg, &dto_params); 2190 2191 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2192 pipe_ctx->stream_res.audio, 2193 pipe_ctx->stream->signal, 2194 &audio_output.crtc_info, 2195 &audio_output.pll_info); 2196 } else 2197 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2198 pipe_ctx->stream_res.audio, 2199 pipe_ctx->stream->signal, 2200 &audio_output.crtc_info, 2201 &audio_output.pll_info); 2202 break; 2203 } 2204 } 2205 2206 /* no HDMI audio is found, try DP audio */ 2207 if (i == dc->res_pool->pipe_count) { 2208 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2209 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2210 2211 if (pipe_ctx->stream == NULL) 2212 continue; 2213 2214 if (pipe_ctx->top_pipe) 2215 continue; 2216 2217 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2218 continue; 2219 2220 if (pipe_ctx->stream_res.audio != NULL) { 2221 struct audio_output audio_output; 2222 2223 build_audio_output(context, pipe_ctx, &audio_output); 2224 2225 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2226 pipe_ctx->stream_res.audio, 2227 pipe_ctx->stream->signal, 2228 &audio_output.crtc_info, 2229 &audio_output.pll_info); 2230 break; 2231 } 2232 } 2233 } 2234 } 2235 2236 enum dc_status dce110_apply_ctx_to_hw( 2237 struct dc *dc, 2238 struct dc_state *context) 2239 { 2240 struct dce_hwseq *hws = dc->hwseq; 2241 struct dc_bios *dcb = dc->ctx->dc_bios; 2242 enum dc_status status; 2243 int i; 2244 2245 /* reset syncd pipes from disabled pipes */ 2246 if (dc->config.use_pipe_ctx_sync_logic) 2247 reset_syncd_pipes_from_disabled_pipes(dc, context); 2248 2249 /* Reset old context */ 2250 /* look up the targets that have been removed since last commit */ 2251 hws->funcs.reset_hw_ctx_wrap(dc, context); 2252 2253 /* Skip applying if no targets */ 2254 if (context->stream_count <= 0) 2255 return DC_OK; 2256 2257 /* Apply new context */ 2258 dcb->funcs->set_scratch_critical_state(dcb, true); 2259 2260 /* below is for real asic only */ 2261 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2262 struct pipe_ctx *pipe_ctx_old = 2263 &dc->current_state->res_ctx.pipe_ctx[i]; 2264 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2265 2266 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2267 continue; 2268 2269 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2270 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2271 dce_crtc_switch_to_clk_src(dc->hwseq, 2272 pipe_ctx->clock_source, i); 2273 continue; 2274 } 2275 2276 hws->funcs.enable_display_power_gating( 2277 dc, i, dc->ctx->dc_bios, 2278 PIPE_GATING_CONTROL_DISABLE); 2279 } 2280 2281 if (dc->fbc_compressor) 2282 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2283 2284 dce110_setup_audio_dto(dc, context); 2285 2286 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2287 struct pipe_ctx *pipe_ctx_old = 2288 &dc->current_state->res_ctx.pipe_ctx[i]; 2289 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2290 2291 if (pipe_ctx->stream == NULL) 2292 continue; 2293 2294 if (pipe_ctx->stream == pipe_ctx_old->stream && 2295 pipe_ctx->stream->link->link_state_valid) { 2296 continue; 2297 } 2298 2299 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2300 continue; 2301 2302 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2303 continue; 2304 2305 status = dce110_apply_single_controller_ctx_to_hw( 2306 pipe_ctx, 2307 context, 2308 dc); 2309 2310 if (DC_OK != status) 2311 return status; 2312 2313 #ifdef CONFIG_DRM_AMD_DC_FP 2314 if (hws->funcs.resync_fifo_dccg_dio) 2315 hws->funcs.resync_fifo_dccg_dio(hws, dc, context); 2316 #endif 2317 } 2318 2319 if (dc->fbc_compressor) 2320 enable_fbc(dc, dc->current_state); 2321 2322 dcb->funcs->set_scratch_critical_state(dcb, false); 2323 2324 return DC_OK; 2325 } 2326 2327 /******************************************************************************* 2328 * Front End programming 2329 ******************************************************************************/ 2330 static void set_default_colors(struct pipe_ctx *pipe_ctx) 2331 { 2332 struct default_adjustment default_adjust = { 0 }; 2333 2334 default_adjust.force_hw_default = false; 2335 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2336 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2337 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2338 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2339 2340 /* display color depth */ 2341 default_adjust.color_depth = 2342 pipe_ctx->stream->timing.display_color_depth; 2343 2344 /* Lb color depth */ 2345 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2346 2347 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2348 pipe_ctx->plane_res.xfm, &default_adjust); 2349 } 2350 2351 2352 /******************************************************************************* 2353 * In order to turn on/off specific surface we will program 2354 * Blender + CRTC 2355 * 2356 * In case that we have two surfaces and they have a different visibility 2357 * we can't turn off the CRTC since it will turn off the entire display 2358 * 2359 * |----------------------------------------------- | 2360 * |bottom pipe|curr pipe | | | 2361 * |Surface |Surface | Blender | CRCT | 2362 * |visibility |visibility | Configuration| | 2363 * |------------------------------------------------| 2364 * | off | off | CURRENT_PIPE | blank | 2365 * | off | on | CURRENT_PIPE | unblank | 2366 * | on | off | OTHER_PIPE | unblank | 2367 * | on | on | BLENDING | unblank | 2368 * -------------------------------------------------| 2369 * 2370 ******************************************************************************/ 2371 static void program_surface_visibility(const struct dc *dc, 2372 struct pipe_ctx *pipe_ctx) 2373 { 2374 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2375 bool blank_target = false; 2376 2377 if (pipe_ctx->bottom_pipe) { 2378 2379 /* For now we are supporting only two pipes */ 2380 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2381 2382 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2383 if (pipe_ctx->plane_state->visible) 2384 blender_mode = BLND_MODE_BLENDING; 2385 else 2386 blender_mode = BLND_MODE_OTHER_PIPE; 2387 2388 } else if (!pipe_ctx->plane_state->visible) 2389 blank_target = true; 2390 2391 } else if (!pipe_ctx->plane_state->visible) 2392 blank_target = true; 2393 2394 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2395 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2396 2397 } 2398 2399 static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2400 { 2401 int i = 0; 2402 struct xfm_grph_csc_adjustment adjust; 2403 memset(&adjust, 0, sizeof(adjust)); 2404 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2405 2406 2407 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2408 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2409 2410 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2411 adjust.temperature_matrix[i] = 2412 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2413 } 2414 2415 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2416 } 2417 static void update_plane_addr(const struct dc *dc, 2418 struct pipe_ctx *pipe_ctx) 2419 { 2420 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2421 2422 if (plane_state == NULL) 2423 return; 2424 2425 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2426 pipe_ctx->plane_res.mi, 2427 &plane_state->address, 2428 plane_state->flip_immediate); 2429 2430 plane_state->status.requested_address = plane_state->address; 2431 } 2432 2433 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2434 { 2435 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2436 2437 if (plane_state == NULL) 2438 return; 2439 2440 plane_state->status.is_flip_pending = 2441 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2442 pipe_ctx->plane_res.mi); 2443 2444 if (plane_state->status.is_flip_pending && !plane_state->visible) 2445 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2446 2447 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2448 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2449 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2450 plane_state->status.is_right_eye =\ 2451 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2452 } 2453 } 2454 2455 void dce110_power_down(struct dc *dc) 2456 { 2457 power_down_all_hw_blocks(dc); 2458 disable_vga_and_power_gate_all_controllers(dc); 2459 } 2460 2461 static bool wait_for_reset_trigger_to_occur( 2462 struct dc_context *dc_ctx, 2463 struct timing_generator *tg) 2464 { 2465 struct dc_context *ctx = dc_ctx; 2466 bool rc = false; 2467 2468 /* To avoid endless loop we wait at most 2469 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2470 const uint32_t frames_to_wait_on_triggered_reset = 10; 2471 uint32_t i; 2472 2473 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2474 2475 if (!tg->funcs->is_counter_moving(tg)) { 2476 DC_ERROR("TG counter is not moving!\n"); 2477 break; 2478 } 2479 2480 if (tg->funcs->did_triggered_reset_occur(tg)) { 2481 rc = true; 2482 /* usually occurs at i=1 */ 2483 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2484 i); 2485 break; 2486 } 2487 2488 /* Wait for one frame. */ 2489 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2490 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2491 } 2492 2493 if (false == rc) 2494 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2495 2496 return rc; 2497 } 2498 2499 /* Enable timing synchronization for a group of Timing Generators. */ 2500 static void dce110_enable_timing_synchronization( 2501 struct dc *dc, 2502 struct dc_state *state, 2503 int group_index, 2504 int group_size, 2505 struct pipe_ctx *grouped_pipes[]) 2506 { 2507 struct dc_context *dc_ctx = dc->ctx; 2508 struct dcp_gsl_params gsl_params = { 0 }; 2509 int i; 2510 DC_LOGGER_INIT(); 2511 2512 DC_SYNC_INFO("GSL: Setting-up...\n"); 2513 2514 /* Designate a single TG in the group as a master. 2515 * Since HW doesn't care which one, we always assign 2516 * the 1st one in the group. */ 2517 gsl_params.gsl_group = 0; 2518 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2519 2520 for (i = 0; i < group_size; i++) 2521 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2522 grouped_pipes[i]->stream_res.tg, &gsl_params); 2523 2524 /* Reset slave controllers on master VSync */ 2525 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2526 2527 for (i = 1 /* skip the master */; i < group_size; i++) 2528 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2529 grouped_pipes[i]->stream_res.tg, 2530 gsl_params.gsl_group); 2531 2532 for (i = 1 /* skip the master */; i < group_size; i++) { 2533 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2534 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2535 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2536 grouped_pipes[i]->stream_res.tg); 2537 } 2538 2539 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2540 * is that the sync'ed displays will not drift out of sync over time*/ 2541 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2542 for (i = 0; i < group_size; i++) 2543 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2544 2545 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2546 } 2547 2548 static void dce110_enable_per_frame_crtc_position_reset( 2549 struct dc *dc, 2550 int group_size, 2551 struct pipe_ctx *grouped_pipes[]) 2552 { 2553 struct dc_context *dc_ctx = dc->ctx; 2554 struct dcp_gsl_params gsl_params = { 0 }; 2555 int i; 2556 DC_LOGGER_INIT(); 2557 2558 gsl_params.gsl_group = 0; 2559 gsl_params.gsl_master = 0; 2560 2561 for (i = 0; i < group_size; i++) 2562 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2563 grouped_pipes[i]->stream_res.tg, &gsl_params); 2564 2565 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2566 2567 for (i = 1; i < group_size; i++) 2568 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2569 grouped_pipes[i]->stream_res.tg, 2570 gsl_params.gsl_master, 2571 &grouped_pipes[i]->stream->triggered_crtc_reset); 2572 2573 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2574 for (i = 1; i < group_size; i++) 2575 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2576 2577 for (i = 0; i < group_size; i++) 2578 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2579 2580 } 2581 2582 static void init_pipes(struct dc *dc, struct dc_state *context) 2583 { 2584 // Do nothing 2585 } 2586 2587 static void init_hw(struct dc *dc) 2588 { 2589 int i; 2590 struct dc_bios *bp; 2591 struct transform *xfm; 2592 struct abm *abm; 2593 struct dmcu *dmcu; 2594 struct dce_hwseq *hws = dc->hwseq; 2595 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 2596 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 2597 2598 bp = dc->ctx->dc_bios; 2599 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2600 xfm = dc->res_pool->transforms[i]; 2601 xfm->funcs->transform_reset(xfm); 2602 2603 hws->funcs.enable_display_power_gating( 2604 dc, i, bp, 2605 PIPE_GATING_CONTROL_INIT); 2606 hws->funcs.enable_display_power_gating( 2607 dc, i, bp, 2608 PIPE_GATING_CONTROL_DISABLE); 2609 hws->funcs.enable_display_pipe_clock_gating( 2610 dc->ctx, 2611 true); 2612 } 2613 2614 dce_clock_gating_power_up(dc->hwseq, false); 2615 /***************************************/ 2616 2617 for (i = 0; i < dc->link_count; i++) { 2618 /****************************************/ 2619 /* Power up AND update implementation according to the 2620 * required signal (which may be different from the 2621 * default signal on connector). */ 2622 struct dc_link *link = dc->links[i]; 2623 2624 link->link_enc->funcs->hw_init(link->link_enc); 2625 } 2626 2627 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2628 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2629 2630 tg->funcs->disable_vga(tg); 2631 2632 /* Blank controller using driver code instead of 2633 * command table. */ 2634 tg->funcs->set_blank(tg, true); 2635 hwss_wait_for_blank_complete(tg); 2636 } 2637 2638 for (i = 0; i < dc->res_pool->audio_count; i++) { 2639 struct audio *audio = dc->res_pool->audios[i]; 2640 audio->funcs->hw_init(audio); 2641 } 2642 2643 for (i = 0; i < dc->link_count; i++) { 2644 struct dc_link *link = dc->links[i]; 2645 2646 if (link->panel_cntl) { 2647 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 2648 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL; 2649 } 2650 } 2651 2652 abm = dc->res_pool->abm; 2653 if (abm != NULL) 2654 abm->funcs->abm_init(abm, backlight, user_level); 2655 2656 dmcu = dc->res_pool->dmcu; 2657 if (dmcu != NULL && abm != NULL) 2658 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 2659 2660 if (dc->fbc_compressor) 2661 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2662 2663 } 2664 2665 2666 void dce110_prepare_bandwidth( 2667 struct dc *dc, 2668 struct dc_state *context) 2669 { 2670 struct clk_mgr *dccg = dc->clk_mgr; 2671 2672 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2673 if (dccg) 2674 dccg->funcs->update_clocks( 2675 dccg, 2676 context, 2677 false); 2678 } 2679 2680 void dce110_optimize_bandwidth( 2681 struct dc *dc, 2682 struct dc_state *context) 2683 { 2684 struct clk_mgr *dccg = dc->clk_mgr; 2685 2686 dce110_set_displaymarks(dc, context); 2687 2688 if (dccg) 2689 dccg->funcs->update_clocks( 2690 dccg, 2691 context, 2692 true); 2693 } 2694 2695 static void dce110_program_front_end_for_pipe( 2696 struct dc *dc, struct pipe_ctx *pipe_ctx) 2697 { 2698 struct mem_input *mi = pipe_ctx->plane_res.mi; 2699 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2700 struct xfm_grph_csc_adjustment adjust; 2701 struct out_csc_color_matrix tbl_entry; 2702 unsigned int i; 2703 struct dce_hwseq *hws = dc->hwseq; 2704 2705 memset(&tbl_entry, 0, sizeof(tbl_entry)); 2706 2707 memset(&adjust, 0, sizeof(adjust)); 2708 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2709 2710 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 2711 2712 set_default_colors(pipe_ctx); 2713 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2714 == true) { 2715 tbl_entry.color_space = 2716 pipe_ctx->stream->output_color_space; 2717 2718 for (i = 0; i < 12; i++) 2719 tbl_entry.regval[i] = 2720 pipe_ctx->stream->csc_color_matrix.matrix[i]; 2721 2722 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 2723 (pipe_ctx->plane_res.xfm, &tbl_entry); 2724 } 2725 2726 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2727 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2728 2729 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2730 adjust.temperature_matrix[i] = 2731 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2732 } 2733 2734 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2735 2736 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 2737 2738 program_scaler(dc, pipe_ctx); 2739 2740 mi->funcs->mem_input_program_surface_config( 2741 mi, 2742 plane_state->format, 2743 &plane_state->tiling_info, 2744 &plane_state->plane_size, 2745 plane_state->rotation, 2746 NULL, 2747 false); 2748 if (mi->funcs->set_blank) 2749 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2750 2751 if (dc->config.gpu_vm_support) 2752 mi->funcs->mem_input_program_pte_vm( 2753 pipe_ctx->plane_res.mi, 2754 plane_state->format, 2755 &plane_state->tiling_info, 2756 plane_state->rotation); 2757 2758 /* Moved programming gamma from dc to hwss */ 2759 if (pipe_ctx->plane_state->update_flags.bits.full_update || 2760 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2761 pipe_ctx->plane_state->update_flags.bits.gamma_change) 2762 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2763 2764 if (pipe_ctx->plane_state->update_flags.bits.full_update) 2765 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2766 2767 DC_LOG_SURFACE( 2768 "Pipe:%d %p: addr hi:0x%x, " 2769 "addr low:0x%x, " 2770 "src: %d, %d, %d," 2771 " %d; dst: %d, %d, %d, %d;" 2772 "clip: %d, %d, %d, %d\n", 2773 pipe_ctx->pipe_idx, 2774 (void *) pipe_ctx->plane_state, 2775 pipe_ctx->plane_state->address.grph.addr.high_part, 2776 pipe_ctx->plane_state->address.grph.addr.low_part, 2777 pipe_ctx->plane_state->src_rect.x, 2778 pipe_ctx->plane_state->src_rect.y, 2779 pipe_ctx->plane_state->src_rect.width, 2780 pipe_ctx->plane_state->src_rect.height, 2781 pipe_ctx->plane_state->dst_rect.x, 2782 pipe_ctx->plane_state->dst_rect.y, 2783 pipe_ctx->plane_state->dst_rect.width, 2784 pipe_ctx->plane_state->dst_rect.height, 2785 pipe_ctx->plane_state->clip_rect.x, 2786 pipe_ctx->plane_state->clip_rect.y, 2787 pipe_ctx->plane_state->clip_rect.width, 2788 pipe_ctx->plane_state->clip_rect.height); 2789 2790 DC_LOG_SURFACE( 2791 "Pipe %d: width, height, x, y\n" 2792 "viewport:%d, %d, %d, %d\n" 2793 "recout: %d, %d, %d, %d\n", 2794 pipe_ctx->pipe_idx, 2795 pipe_ctx->plane_res.scl_data.viewport.width, 2796 pipe_ctx->plane_res.scl_data.viewport.height, 2797 pipe_ctx->plane_res.scl_data.viewport.x, 2798 pipe_ctx->plane_res.scl_data.viewport.y, 2799 pipe_ctx->plane_res.scl_data.recout.width, 2800 pipe_ctx->plane_res.scl_data.recout.height, 2801 pipe_ctx->plane_res.scl_data.recout.x, 2802 pipe_ctx->plane_res.scl_data.recout.y); 2803 } 2804 2805 static void dce110_apply_ctx_for_surface( 2806 struct dc *dc, 2807 const struct dc_stream_state *stream, 2808 int num_planes, 2809 struct dc_state *context) 2810 { 2811 int i; 2812 2813 if (num_planes == 0) 2814 return; 2815 2816 if (dc->fbc_compressor) 2817 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2818 2819 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2820 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2821 2822 if (pipe_ctx->stream != stream) 2823 continue; 2824 2825 /* Need to allocate mem before program front end for Fiji */ 2826 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 2827 pipe_ctx->plane_res.mi, 2828 pipe_ctx->stream->timing.h_total, 2829 pipe_ctx->stream->timing.v_total, 2830 pipe_ctx->stream->timing.pix_clk_100hz / 10, 2831 context->stream_count); 2832 2833 dce110_program_front_end_for_pipe(dc, pipe_ctx); 2834 2835 dc->hwss.update_plane_addr(dc, pipe_ctx); 2836 2837 program_surface_visibility(dc, pipe_ctx); 2838 2839 } 2840 2841 if (dc->fbc_compressor) 2842 enable_fbc(dc, context); 2843 } 2844 2845 static void dce110_post_unlock_program_front_end( 2846 struct dc *dc, 2847 struct dc_state *context) 2848 { 2849 } 2850 2851 static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) 2852 { 2853 struct dce_hwseq *hws = dc->hwseq; 2854 int fe_idx = pipe_ctx->plane_res.mi ? 2855 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2856 2857 /* Do not power down fe when stream is active on dce*/ 2858 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 2859 return; 2860 2861 hws->funcs.enable_display_power_gating( 2862 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2863 2864 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2865 dc->res_pool->transforms[fe_idx]); 2866 } 2867 2868 static void dce110_wait_for_mpcc_disconnect( 2869 struct dc *dc, 2870 struct resource_pool *res_pool, 2871 struct pipe_ctx *pipe_ctx) 2872 { 2873 /* do nothing*/ 2874 } 2875 2876 static void program_output_csc(struct dc *dc, 2877 struct pipe_ctx *pipe_ctx, 2878 enum dc_color_space colorspace, 2879 uint16_t *matrix, 2880 int opp_id) 2881 { 2882 int i; 2883 struct out_csc_color_matrix tbl_entry; 2884 2885 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2886 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 2887 2888 for (i = 0; i < 12; i++) 2889 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2890 2891 tbl_entry.color_space = color_space; 2892 2893 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 2894 pipe_ctx->plane_res.xfm, &tbl_entry); 2895 } 2896 } 2897 2898 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 2899 { 2900 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 2901 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2902 struct mem_input *mi = pipe_ctx->plane_res.mi; 2903 struct dc_cursor_mi_param param = { 2904 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 2905 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 2906 .viewport = pipe_ctx->plane_res.scl_data.viewport, 2907 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 2908 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 2909 .rotation = pipe_ctx->plane_state->rotation, 2910 .mirror = pipe_ctx->plane_state->horizontal_mirror 2911 }; 2912 2913 /** 2914 * If the cursor's source viewport is clipped then we need to 2915 * translate the cursor to appear in the correct position on 2916 * the screen. 2917 * 2918 * This translation isn't affected by scaling so it needs to be 2919 * done *after* we adjust the position for the scale factor. 2920 * 2921 * This is only done by opt-in for now since there are still 2922 * some usecases like tiled display that might enable the 2923 * cursor on both streams while expecting dc to clip it. 2924 */ 2925 if (pos_cpy.translate_by_source) { 2926 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 2927 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2928 } 2929 2930 if (pipe_ctx->plane_state->address.type 2931 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2932 pos_cpy.enable = false; 2933 2934 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 2935 pos_cpy.enable = false; 2936 2937 if (ipp->funcs->ipp_cursor_set_position) 2938 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2939 if (mi->funcs->set_cursor_position) 2940 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 2941 } 2942 2943 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 2944 { 2945 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 2946 2947 if (pipe_ctx->plane_res.ipp && 2948 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 2949 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 2950 pipe_ctx->plane_res.ipp, attributes); 2951 2952 if (pipe_ctx->plane_res.mi && 2953 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 2954 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 2955 pipe_ctx->plane_res.mi, attributes); 2956 2957 if (pipe_ctx->plane_res.xfm && 2958 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 2959 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 2960 pipe_ctx->plane_res.xfm, attributes); 2961 } 2962 2963 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 2964 uint32_t backlight_pwm_u16_16, 2965 uint32_t frame_ramp) 2966 { 2967 struct dc_link *link = pipe_ctx->stream->link; 2968 struct dc *dc = link->ctx->dc; 2969 struct abm *abm = pipe_ctx->stream_res.abm; 2970 struct panel_cntl *panel_cntl = link->panel_cntl; 2971 struct dmcu *dmcu = dc->res_pool->dmcu; 2972 bool fw_set_brightness = true; 2973 /* DMCU -1 for all controller id values, 2974 * therefore +1 here 2975 */ 2976 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 2977 2978 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 2979 return false; 2980 2981 if (dmcu) 2982 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2983 2984 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 2985 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 2986 else 2987 abm->funcs->set_backlight_level_pwm( 2988 abm, 2989 backlight_pwm_u16_16, 2990 frame_ramp, 2991 controller_id, 2992 link->panel_cntl->inst); 2993 2994 return true; 2995 } 2996 2997 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 2998 { 2999 struct abm *abm = pipe_ctx->stream_res.abm; 3000 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3001 3002 if (abm) 3003 abm->funcs->set_abm_immediate_disable(abm, 3004 pipe_ctx->stream->link->panel_cntl->inst); 3005 3006 if (panel_cntl) 3007 panel_cntl->funcs->store_backlight_level(panel_cntl); 3008 } 3009 3010 void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 3011 { 3012 struct abm *abm = pipe_ctx->stream_res.abm; 3013 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3014 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 3015 3016 if (abm && panel_cntl) 3017 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 3018 } 3019 3020 void dce110_enable_lvds_link_output(struct dc_link *link, 3021 const struct link_resource *link_res, 3022 enum clock_source_id clock_source, 3023 uint32_t pixel_clock) 3024 { 3025 link->link_enc->funcs->enable_lvds_output( 3026 link->link_enc, 3027 clock_source, 3028 pixel_clock); 3029 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3030 } 3031 3032 void dce110_enable_tmds_link_output(struct dc_link *link, 3033 const struct link_resource *link_res, 3034 enum signal_type signal, 3035 enum clock_source_id clock_source, 3036 enum dc_color_depth color_depth, 3037 uint32_t pixel_clock) 3038 { 3039 link->link_enc->funcs->enable_tmds_output( 3040 link->link_enc, 3041 clock_source, 3042 color_depth, 3043 signal, 3044 pixel_clock); 3045 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3046 } 3047 3048 void dce110_enable_dp_link_output( 3049 struct dc_link *link, 3050 const struct link_resource *link_res, 3051 enum signal_type signal, 3052 enum clock_source_id clock_source, 3053 const struct dc_link_settings *link_settings) 3054 { 3055 struct dc *dc = link->ctx->dc; 3056 struct dmcu *dmcu = dc->res_pool->dmcu; 3057 struct pipe_ctx *pipes = 3058 link->dc->current_state->res_ctx.pipe_ctx; 3059 struct clock_source *dp_cs = 3060 link->dc->res_pool->dp_clock_source; 3061 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3062 unsigned int i; 3063 3064 /* 3065 * Add the logic to extract BOTH power up and power down sequences 3066 * from enable/disable link output and only call edp panel control 3067 * in enable_link_dp and disable_link_dp once. 3068 */ 3069 if (link->connector_signal == SIGNAL_TYPE_EDP) { 3070 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 3071 } 3072 3073 /* If the current pixel clock source is not DTO(happens after 3074 * switching from HDMI passive dongle to DP on the same connector), 3075 * switch the pixel clock source to DTO. 3076 */ 3077 3078 for (i = 0; i < MAX_PIPES; i++) { 3079 if (pipes[i].stream != NULL && 3080 pipes[i].stream->link == link) { 3081 if (pipes[i].clock_source != NULL && 3082 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 3083 pipes[i].clock_source = dp_cs; 3084 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = 3085 pipes[i].stream->timing.pix_clk_100hz; 3086 pipes[i].clock_source->funcs->program_pix_clk( 3087 pipes[i].clock_source, 3088 &pipes[i].stream_res.pix_clk_params, 3089 dc->link_srv->dp_get_encoding_format(link_settings), 3090 &pipes[i].pll_settings); 3091 } 3092 } 3093 } 3094 3095 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { 3096 if (dc->clk_mgr->funcs->notify_link_rate_change) 3097 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); 3098 } 3099 3100 if (dmcu != NULL && dmcu->funcs->lock_phy) 3101 dmcu->funcs->lock_phy(dmcu); 3102 3103 if (link_hwss->ext.enable_dp_link_output) 3104 link_hwss->ext.enable_dp_link_output(link, link_res, signal, 3105 clock_source, link_settings); 3106 3107 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3108 3109 if (dmcu != NULL && dmcu->funcs->unlock_phy) 3110 dmcu->funcs->unlock_phy(dmcu); 3111 3112 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY); 3113 } 3114 3115 void dce110_disable_link_output(struct dc_link *link, 3116 const struct link_resource *link_res, 3117 enum signal_type signal) 3118 { 3119 struct dc *dc = link->ctx->dc; 3120 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3121 struct dmcu *dmcu = dc->res_pool->dmcu; 3122 3123 if (signal == SIGNAL_TYPE_EDP && 3124 link->dc->hwss.edp_backlight_control && 3125 !link->skip_implict_edp_power_control) 3126 link->dc->hwss.edp_backlight_control(link, false); 3127 else if (dmcu != NULL && dmcu->funcs->lock_phy) 3128 dmcu->funcs->lock_phy(dmcu); 3129 3130 link_hwss->disable_link_output(link, link_res, signal); 3131 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 3132 /* 3133 * Add the logic to extract BOTH power up and power down sequences 3134 * from enable/disable link output and only call edp panel control 3135 * in enable_link_dp and disable_link_dp once. 3136 */ 3137 if (dmcu != NULL && dmcu->funcs->lock_phy) 3138 dmcu->funcs->unlock_phy(dmcu); 3139 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 3140 } 3141 3142 static const struct hw_sequencer_funcs dce110_funcs = { 3143 .program_gamut_remap = program_gamut_remap, 3144 .program_output_csc = program_output_csc, 3145 .init_hw = init_hw, 3146 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 3147 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3148 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 3149 .update_plane_addr = update_plane_addr, 3150 .update_pending_status = dce110_update_pending_status, 3151 .enable_accelerated_mode = dce110_enable_accelerated_mode, 3152 .enable_timing_synchronization = dce110_enable_timing_synchronization, 3153 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 3154 .update_info_frame = dce110_update_info_frame, 3155 .enable_stream = dce110_enable_stream, 3156 .disable_stream = dce110_disable_stream, 3157 .unblank_stream = dce110_unblank_stream, 3158 .blank_stream = dce110_blank_stream, 3159 .enable_audio_stream = dce110_enable_audio_stream, 3160 .disable_audio_stream = dce110_disable_audio_stream, 3161 .disable_plane = dce110_power_down_fe, 3162 .pipe_control_lock = dce_pipe_control_lock, 3163 .interdependent_update_lock = NULL, 3164 .cursor_lock = dce_pipe_control_lock, 3165 .prepare_bandwidth = dce110_prepare_bandwidth, 3166 .optimize_bandwidth = dce110_optimize_bandwidth, 3167 .set_drr = set_drr, 3168 .get_position = get_position, 3169 .set_static_screen_control = set_static_screen_control, 3170 .setup_stereo = NULL, 3171 .set_avmute = dce110_set_avmute, 3172 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3173 .edp_backlight_control = dce110_edp_backlight_control, 3174 .edp_power_control = dce110_edp_power_control, 3175 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 3176 .set_cursor_position = dce110_set_cursor_position, 3177 .set_cursor_attribute = dce110_set_cursor_attribute, 3178 .set_backlight_level = dce110_set_backlight_level, 3179 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3180 .set_pipe = dce110_set_pipe, 3181 .enable_lvds_link_output = dce110_enable_lvds_link_output, 3182 .enable_tmds_link_output = dce110_enable_tmds_link_output, 3183 .enable_dp_link_output = dce110_enable_dp_link_output, 3184 .disable_link_output = dce110_disable_link_output, 3185 }; 3186 3187 static const struct hwseq_private_funcs dce110_private_funcs = { 3188 .init_pipes = init_pipes, 3189 .update_plane_addr = update_plane_addr, 3190 .set_input_transfer_func = dce110_set_input_transfer_func, 3191 .set_output_transfer_func = dce110_set_output_transfer_func, 3192 .power_down = dce110_power_down, 3193 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3194 .enable_display_power_gating = dce110_enable_display_power_gating, 3195 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3196 .enable_stream_timing = dce110_enable_stream_timing, 3197 .disable_stream_gating = NULL, 3198 .enable_stream_gating = NULL, 3199 .edp_backlight_control = dce110_edp_backlight_control, 3200 }; 3201 3202 void dce110_hw_sequencer_construct(struct dc *dc) 3203 { 3204 dc->hwss = dce110_funcs; 3205 dc->hwseq->funcs = dce110_private_funcs; 3206 } 3207 3208