1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dsc_helper.h> 27 28 #include "reg_helper.h" 29 #include "dcn20_dsc.h" 30 #include "dsc/dscc_types.h" 31 #include "dsc/rc_calc.h" 32 33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 34 35 /* Object I/F functions */ 36 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 37 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 38 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 39 struct dsc_optc_config *dsc_optc_cfg); 40 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 41 static void dsc2_disable(struct display_stream_compressor *dsc); 42 static void dsc2_disconnect(struct display_stream_compressor *dsc); 43 44 static const struct dsc_funcs dcn20_dsc_funcs = { 45 .dsc_get_enc_caps = dsc2_get_enc_caps, 46 .dsc_read_state = dsc2_read_state, 47 .dsc_validate_stream = dsc2_validate_stream, 48 .dsc_set_config = dsc2_set_config, 49 .dsc_get_packed_pps = dsc2_get_packed_pps, 50 .dsc_enable = dsc2_enable, 51 .dsc_disable = dsc2_disable, 52 .dsc_disconnect = dsc2_disconnect, 53 }; 54 55 /* Macro definitios for REG_SET macros*/ 56 #define CTX \ 57 dsc20->base.ctx 58 59 #define REG(reg)\ 60 dsc20->dsc_regs->reg 61 62 #undef FN 63 #define FN(reg_name, field_name) \ 64 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 65 #define DC_LOGGER \ 66 dsc->ctx->logger 67 68 enum dsc_bits_per_comp { 69 DSC_BPC_8 = 8, 70 DSC_BPC_10 = 10, 71 DSC_BPC_12 = 12, 72 DSC_BPC_UNKNOWN 73 }; 74 75 /* API functions (external or via structure->function_pointer) */ 76 77 void dsc2_construct(struct dcn20_dsc *dsc, 78 struct dc_context *ctx, 79 int inst, 80 const struct dcn20_dsc_registers *dsc_regs, 81 const struct dcn20_dsc_shift *dsc_shift, 82 const struct dcn20_dsc_mask *dsc_mask) 83 { 84 dsc->base.ctx = ctx; 85 dsc->base.inst = inst; 86 dsc->base.funcs = &dcn20_dsc_funcs; 87 88 dsc->dsc_regs = dsc_regs; 89 dsc->dsc_shift = dsc_shift; 90 dsc->dsc_mask = dsc_mask; 91 92 dsc->max_image_width = 5184; 93 } 94 95 96 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 97 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 98 99 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 100 * can be doubled, tripled etc. by using additional DSC engines. 101 */ 102 void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 103 { 104 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 105 106 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 107 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 108 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 109 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 110 111 dsc_enc_caps->lb_bit_depth = 13; 112 dsc_enc_caps->is_block_pred_supported = true; 113 114 dsc_enc_caps->color_formats.bits.RGB = 1; 115 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 116 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 117 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 118 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 119 120 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 121 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 122 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 123 124 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 125 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 126 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 127 * be sufficient to process the input pixel rate fed into a single DSC engine. 128 */ 129 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 130 131 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 132 * throughput and number of slices, but also introduces a lower limit of 2 slices 133 */ 134 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 135 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 136 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 137 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 138 } 139 140 /* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our 141 * throughput and number of slices 142 */ 143 if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) { 144 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1; 145 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1; 146 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4; 147 } 148 149 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 150 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 151 } 152 153 154 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 155 * into a dcn_dsc_state struct. 156 */ 157 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 158 { 159 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 160 161 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 162 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 163 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 164 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 165 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 166 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 167 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 168 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 169 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 170 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 171 } 172 173 174 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 175 { 176 struct dsc_optc_config dsc_optc_cfg; 177 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 178 179 if (dsc_cfg->pic_width > dsc20->max_image_width) 180 return false; 181 182 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 183 } 184 185 186 void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 187 { 188 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 189 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 190 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 191 config->dc_dsc_cfg.bits_per_pixel, 192 config->dc_dsc_cfg.bits_per_pixel / 16, 193 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 194 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 195 } 196 197 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 198 struct dsc_optc_config *dsc_optc_cfg) 199 { 200 bool is_config_ok; 201 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 202 203 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 204 dsc_config_log(dsc, dsc_cfg); 205 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 206 ASSERT(is_config_ok); 207 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 208 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 209 dsc_write_to_registers(dsc, &dsc20->reg_vals); 210 } 211 212 213 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 214 { 215 bool is_config_ok; 216 struct dsc_reg_values dsc_reg_vals; 217 struct dsc_optc_config dsc_optc_cfg; 218 219 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 220 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 221 222 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 223 dsc_config_log(dsc, dsc_cfg); 224 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 225 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 226 ASSERT(is_config_ok); 227 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 228 dsc_log_pps(dsc, &dsc_reg_vals.pps); 229 230 return is_config_ok; 231 } 232 233 234 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 235 { 236 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 237 int dsc_clock_en; 238 int dsc_fw_config; 239 int enabled_opp_pipe; 240 241 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 242 243 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 244 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 245 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 246 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 247 ASSERT(0); 248 } 249 250 REG_UPDATE(DSC_TOP_CONTROL, 251 DSC_CLOCK_EN, 1); 252 253 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 254 DSCRM_DSC_FORWARD_EN, 1, 255 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 256 } 257 258 259 static void dsc2_disable(struct display_stream_compressor *dsc) 260 { 261 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 262 int dsc_clock_en; 263 int dsc_fw_config; 264 int enabled_opp_pipe; 265 266 DC_LOG_DSC("disable DSC %d", dsc->inst); 267 268 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 269 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 270 if (!dsc_clock_en || !dsc_fw_config) { 271 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 272 ASSERT(0); 273 } 274 275 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 276 DSCRM_DSC_FORWARD_EN, 0); 277 278 REG_UPDATE(DSC_TOP_CONTROL, 279 DSC_CLOCK_EN, 0); 280 } 281 282 static void dsc2_disconnect(struct display_stream_compressor *dsc) 283 { 284 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 285 286 DC_LOG_DSC("disconnect DSC %d", dsc->inst); 287 288 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 289 DSCRM_DSC_FORWARD_EN, 0); 290 } 291 292 /* This module's internal functions */ 293 void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 294 { 295 int i; 296 int bits_per_pixel = pps->bits_per_pixel; 297 298 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 299 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 300 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 301 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 302 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 303 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 304 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 305 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 306 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 307 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 308 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 309 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 310 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 311 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 312 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 313 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 314 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 315 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 316 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 317 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 318 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 319 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 320 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 321 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 322 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 323 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 324 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 325 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 326 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 327 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 328 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 329 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 330 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 331 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 332 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 333 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 334 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 335 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 336 337 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 338 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 339 340 for (i = 0; i < NUM_BUF_RANGES; i++) { 341 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 342 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 343 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 344 } 345 } 346 347 void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override) 348 { 349 uint8_t i; 350 351 rc->rc_model_size = override->rc_model_size; 352 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++) 353 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i]; 354 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) { 355 rc->qp_min[i] = override->rc_minqp[i]; 356 rc->qp_max[i] = override->rc_maxqp[i]; 357 rc->ofs[i] = override->rc_offset[i]; 358 } 359 360 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi; 361 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo; 362 rc->rc_edge_factor = override->rc_edge_factor; 363 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0; 364 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1; 365 366 rc->initial_fullness_offset = override->initial_fullness_offset; 367 rc->initial_xmit_delay = override->initial_delay; 368 369 rc->flatness_min_qp = override->flatness_min_qp; 370 rc->flatness_max_qp = override->flatness_max_qp; 371 rc->flatness_det_thresh = override->flatness_det_thresh; 372 } 373 374 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 375 struct dsc_optc_config *dsc_optc_cfg) 376 { 377 struct dsc_parameters dsc_params; 378 struct rc_params rc; 379 380 /* Validate input parameters */ 381 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 382 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 383 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 384 ASSERT(dsc_cfg->pic_width); 385 ASSERT(dsc_cfg->pic_height); 386 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 387 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 388 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 389 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 390 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 391 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 392 393 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 394 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 395 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 396 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 397 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 398 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 399 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 400 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 401 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 402 dm_output_to_console("%s: Invalid parameters\n", __func__); 403 return false; 404 } 405 406 dsc_init_reg_values(dsc_reg_vals); 407 408 /* Copy input config */ 409 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 410 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 411 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 412 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 413 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 414 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 415 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 416 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 417 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 418 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 419 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; 420 421 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 422 // see what happens when the same condition doesn't apply for slice_width/pic_width. 423 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 424 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 425 426 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 427 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 428 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 429 return false; 430 } 431 432 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 433 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 434 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 435 else 436 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 437 438 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 439 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 440 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 441 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 442 443 calc_rc_params(&rc, &dsc_reg_vals->pps); 444 445 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd) 446 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd); 447 448 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) { 449 dm_output_to_console("%s: DSC config failed\n", __func__); 450 return false; 451 } 452 453 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 454 455 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 456 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 457 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 458 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 459 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 460 461 return true; 462 } 463 464 465 enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 466 { 467 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 468 469 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 470 471 switch (dc_pix_enc) { 472 case PIXEL_ENCODING_RGB: 473 dsc_pix_fmt = DSC_PIXFMT_RGB; 474 break; 475 case PIXEL_ENCODING_YCBCR422: 476 if (is_ycbcr422_simple) 477 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 478 else 479 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 480 break; 481 case PIXEL_ENCODING_YCBCR444: 482 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 483 break; 484 case PIXEL_ENCODING_YCBCR420: 485 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 486 break; 487 default: 488 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 489 break; 490 } 491 492 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 493 return dsc_pix_fmt; 494 } 495 496 497 enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 498 { 499 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 500 501 switch (dc_color_depth) { 502 case COLOR_DEPTH_888: 503 bpc = DSC_BPC_8; 504 break; 505 case COLOR_DEPTH_101010: 506 bpc = DSC_BPC_10; 507 break; 508 case COLOR_DEPTH_121212: 509 bpc = DSC_BPC_12; 510 break; 511 default: 512 bpc = DSC_BPC_UNKNOWN; 513 break; 514 } 515 516 return bpc; 517 } 518 519 520 void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 521 { 522 int i; 523 524 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 525 526 /* Non-PPS values */ 527 reg_vals->dsc_clock_enable = 1; 528 reg_vals->dsc_clock_gating_disable = 0; 529 reg_vals->underflow_recovery_en = 0; 530 reg_vals->underflow_occurred_int_en = 0; 531 reg_vals->underflow_occurred_status = 0; 532 reg_vals->ich_reset_at_eol = 0; 533 reg_vals->alternate_ich_encoding_en = 0; 534 reg_vals->rc_buffer_model_size = 0; 535 /*reg_vals->disable_ich = 0;*/ 536 reg_vals->dsc_dbg_en = 0; 537 538 for (i = 0; i < 4; i++) 539 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 540 541 /* PPS values */ 542 reg_vals->pps.dsc_version_minor = 2; 543 reg_vals->pps.dsc_version_major = 1; 544 reg_vals->pps.line_buf_depth = 9; 545 reg_vals->pps.bits_per_component = 8; 546 reg_vals->pps.block_pred_enable = 1; 547 reg_vals->pps.slice_chunk_size = 0; 548 reg_vals->pps.pic_width = 0; 549 reg_vals->pps.pic_height = 0; 550 reg_vals->pps.slice_width = 0; 551 reg_vals->pps.slice_height = 0; 552 reg_vals->pps.initial_xmit_delay = 170; 553 reg_vals->pps.initial_dec_delay = 0; 554 reg_vals->pps.initial_scale_value = 0; 555 reg_vals->pps.scale_increment_interval = 0; 556 reg_vals->pps.scale_decrement_interval = 0; 557 reg_vals->pps.nfl_bpg_offset = 0; 558 reg_vals->pps.slice_bpg_offset = 0; 559 reg_vals->pps.nsl_bpg_offset = 0; 560 reg_vals->pps.initial_offset = 6144; 561 reg_vals->pps.final_offset = 0; 562 reg_vals->pps.flatness_min_qp = 3; 563 reg_vals->pps.flatness_max_qp = 12; 564 reg_vals->pps.rc_model_size = 8192; 565 reg_vals->pps.rc_edge_factor = 6; 566 reg_vals->pps.rc_quant_incr_limit0 = 11; 567 reg_vals->pps.rc_quant_incr_limit1 = 11; 568 reg_vals->pps.rc_tgt_offset_low = 3; 569 reg_vals->pps.rc_tgt_offset_high = 3; 570 } 571 572 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 573 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 574 * affects non-PPS register values. 575 */ 576 void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 577 { 578 int i; 579 580 reg_vals->pps = dsc_params->pps; 581 582 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 583 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 584 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 585 586 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 587 } 588 589 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 590 { 591 uint32_t temp_int; 592 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 593 594 REG_SET(DSC_DEBUG_CONTROL, 0, 595 DSC_DBG_EN, reg_vals->dsc_dbg_en); 596 597 // dsccif registers 598 REG_SET_5(DSCCIF_CONFIG0, 0, 599 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 600 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 601 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 602 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 603 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 604 605 REG_SET_2(DSCCIF_CONFIG1, 0, 606 PIC_WIDTH, reg_vals->pps.pic_width, 607 PIC_HEIGHT, reg_vals->pps.pic_height); 608 609 // dscc registers 610 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) { 611 REG_SET_3(DSCC_CONFIG0, 0, 612 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 613 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 614 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 615 } else { 616 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, 617 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE, 618 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, 619 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, 620 reg_vals->num_slices_v - 1); 621 } 622 623 REG_SET(DSCC_CONFIG1, 0, 624 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 625 /*REG_SET_2(DSCC_CONFIG1, 0, 626 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 627 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 628 629 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 630 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 631 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 632 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 633 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 634 635 REG_SET_3(DSCC_PPS_CONFIG0, 0, 636 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 637 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 638 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 639 640 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 641 temp_int = reg_vals->bpp_x32; 642 else 643 temp_int = reg_vals->bpp_x32 >> 1; 644 645 REG_SET_7(DSCC_PPS_CONFIG1, 0, 646 BITS_PER_PIXEL, temp_int, 647 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 648 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 649 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 650 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 651 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 652 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 653 654 REG_SET_2(DSCC_PPS_CONFIG2, 0, 655 PIC_WIDTH, reg_vals->pps.pic_width, 656 PIC_HEIGHT, reg_vals->pps.pic_height); 657 658 REG_SET_2(DSCC_PPS_CONFIG3, 0, 659 SLICE_WIDTH, reg_vals->pps.slice_width, 660 SLICE_HEIGHT, reg_vals->pps.slice_height); 661 662 REG_SET(DSCC_PPS_CONFIG4, 0, 663 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 664 665 REG_SET_2(DSCC_PPS_CONFIG5, 0, 666 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 667 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 668 669 REG_SET_3(DSCC_PPS_CONFIG6, 0, 670 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 671 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 672 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 673 674 REG_SET_2(DSCC_PPS_CONFIG7, 0, 675 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 676 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 677 678 REG_SET_2(DSCC_PPS_CONFIG8, 0, 679 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 680 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 681 682 REG_SET_2(DSCC_PPS_CONFIG9, 0, 683 INITIAL_OFFSET, reg_vals->pps.initial_offset, 684 FINAL_OFFSET, reg_vals->pps.final_offset); 685 686 REG_SET_3(DSCC_PPS_CONFIG10, 0, 687 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 688 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 689 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 690 691 REG_SET_5(DSCC_PPS_CONFIG11, 0, 692 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 693 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 694 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 695 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 696 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 697 698 REG_SET_4(DSCC_PPS_CONFIG12, 0, 699 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 700 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 701 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 702 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 703 704 REG_SET_4(DSCC_PPS_CONFIG13, 0, 705 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 706 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 707 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 708 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 709 710 REG_SET_4(DSCC_PPS_CONFIG14, 0, 711 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 712 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 713 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 714 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 715 716 REG_SET_5(DSCC_PPS_CONFIG15, 0, 717 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 718 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 719 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 720 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 721 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 722 723 REG_SET_6(DSCC_PPS_CONFIG16, 0, 724 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 725 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 726 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 727 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 728 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 729 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 730 731 REG_SET_6(DSCC_PPS_CONFIG17, 0, 732 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 733 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 734 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 735 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 736 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 737 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 738 739 REG_SET_6(DSCC_PPS_CONFIG18, 0, 740 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 741 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 742 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 743 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 744 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 745 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 746 747 REG_SET_6(DSCC_PPS_CONFIG19, 0, 748 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 749 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 750 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 751 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 752 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 753 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 754 755 REG_SET_6(DSCC_PPS_CONFIG20, 0, 756 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 757 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 758 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 759 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 760 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 761 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 762 763 REG_SET_6(DSCC_PPS_CONFIG21, 0, 764 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 765 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 766 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 767 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 768 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 769 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 770 771 REG_SET_6(DSCC_PPS_CONFIG22, 0, 772 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 773 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 774 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 775 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 776 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 777 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 778 779 } 780 781