1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "display_mode_lib.h" 27 #include "dc_features.h" 28 29 static const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 30 .rob_buffer_size_kbytes = 64, 31 .det_buffer_size_kbytes = 164, 32 .dpte_buffer_size_in_pte_reqs = 42, 33 .dpp_output_buffer_pixels = 2560, 34 .opp_output_buffer_lines = 1, 35 .pixel_chunk_size_kbytes = 8, 36 .pte_enable = 1, 37 .pte_chunk_size_kbytes = 2, 38 .meta_chunk_size_kbytes = 2, 39 .writeback_chunk_size_kbytes = 2, 40 .line_buffer_size_bits = 589824, 41 .max_line_buffer_lines = 12, 42 .IsLineBufferBppFixed = 0, 43 .LineBufferFixedBpp = -1, 44 .writeback_luma_buffer_size_kbytes = 12, 45 .writeback_chroma_buffer_size_kbytes = 8, 46 .max_num_dpp = 4, 47 .max_num_wb = 2, 48 .max_dchub_pscl_bw_pix_per_clk = 4, 49 .max_pscl_lb_bw_pix_per_clk = 2, 50 .max_lb_vscl_bw_pix_per_clk = 4, 51 .max_vscl_hscl_bw_pix_per_clk = 4, 52 .max_hscl_ratio = 4, 53 .max_vscl_ratio = 4, 54 .hscl_mults = 4, 55 .vscl_mults = 4, 56 .max_hscl_taps = 8, 57 .max_vscl_taps = 8, 58 .dispclk_ramp_margin_percent = 1, 59 .underscan_factor = 1.10, 60 .min_vblank_lines = 14, 61 .dppclk_delay_subtotal = 90, 62 .dispclk_delay_subtotal = 42, 63 .dcfclk_cstate_latency = 10, 64 .max_inter_dcn_tile_repeaters = 8, 65 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 66 .bug_forcing_LC_req_same_size_fixed = 0, 67 }; 68 69 static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 70 .sr_exit_time_us = 9.0, 71 .sr_enter_plus_exit_time_us = 11.0, 72 .urgent_latency_us = 4.0, 73 .writeback_latency_us = 12.0, 74 .ideal_dram_bw_after_urgent_percent = 80.0, 75 .max_request_size_bytes = 256, 76 .downspread_percent = 0.5, 77 .dram_page_open_time_ns = 50.0, 78 .dram_rw_turnaround_time_ns = 17.5, 79 .dram_return_buffer_per_channel_bytes = 8192, 80 .round_trip_ping_latency_dcfclk_cycles = 128, 81 .urgent_out_of_order_return_per_channel_bytes = 256, 82 .channel_interleave_bytes = 256, 83 .num_banks = 8, 84 .num_chans = 2, 85 .vmm_page_size_bytes = 4096, 86 .dram_clock_change_latency_us = 17.0, 87 .writeback_dram_clock_change_latency_us = 23.0, 88 .return_bus_width_bytes = 64, 89 }; 90 91 static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project) 92 { 93 switch (project) { 94 case DML_PROJECT_RAVEN1: 95 *soc = dcn1_0_soc; 96 break; 97 default: 98 ASSERT(0); 99 break; 100 } 101 } 102 103 static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project) 104 { 105 switch (project) { 106 case DML_PROJECT_RAVEN1: 107 *ip = dcn1_0_ip; 108 break; 109 default: 110 ASSERT(0); 111 break; 112 } 113 } 114 115 void dml_init_instance(struct display_mode_lib *lib, enum dml_project project) 116 { 117 if (lib->project != project) { 118 set_soc_bounding_box(&lib->soc, project); 119 set_ip_params(&lib->ip, project); 120 lib->project = project; 121 } 122 } 123 124