1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = 0xf; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 103 void hubp1_clear_underflow(struct hubp *hubp) 104 { 105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108 } 109 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 111 { 112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113 uint32_t blank_en = blank ? 1 : 0; 114 115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 116 } 117 118 void hubp1_vready_workaround(struct hubp *hubp, 119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 120 { 121 uint32_t value = 0; 122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 123 124 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 125 value = REG_READ(HUBPREQ_DEBUG_DB); 126 127 /* hack mode disable */ 128 value |= 0x100; 129 value &= ~0x1000; 130 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 133 /* if (eco_fix_needed(otg_global_sync_timing) 134 * set HBUBREQ_DEBUG_DB[12] = 1 */ 135 value |= 0x1000; 136 } 137 138 REG_WRITE(HUBPREQ_DEBUG_DB, value); 139 } 140 141 void hubp1_program_tiling( 142 struct hubp *hubp, 143 const union dc_tiling_info *info, 144 const enum surface_pixel_format pixel_format) 145 { 146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 148 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 149 NUM_PIPES, log_2(info->gfx9.num_pipes), 150 NUM_BANKS, log_2(info->gfx9.num_banks), 151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 152 NUM_SE, log_2(info->gfx9.num_shader_engines), 153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 155 156 REG_UPDATE_4(DCSURF_TILING_CONFIG, 157 SW_MODE, info->gfx9.swizzle, 158 META_LINEAR, info->gfx9.meta_linear, 159 RB_ALIGNED, info->gfx9.rb_aligned, 160 PIPE_ALIGNED, info->gfx9.pipe_aligned); 161 } 162 163 void hubp1_program_size( 164 struct hubp *hubp, 165 enum surface_pixel_format format, 166 const union plane_size *plane_size, 167 struct dc_plane_dcc_param *dcc) 168 { 169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 170 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 171 172 /* Program data and meta surface pitch (calculation from addrlib) 173 * 444 or 420 luma 174 */ 175 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 176 ASSERT(plane_size->video.chroma_pitch != 0); 177 /* Chroma pitch zero can cause system hang! */ 178 179 pitch = plane_size->video.luma_pitch - 1; 180 meta_pitch = dcc->video.meta_pitch_l - 1; 181 pitch_c = plane_size->video.chroma_pitch - 1; 182 meta_pitch_c = dcc->video.meta_pitch_c - 1; 183 } else { 184 pitch = plane_size->grph.surface_pitch - 1; 185 meta_pitch = dcc->grph.meta_pitch - 1; 186 pitch_c = 0; 187 meta_pitch_c = 0; 188 } 189 190 if (!dcc->enable) { 191 meta_pitch = 0; 192 meta_pitch_c = 0; 193 } 194 195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 196 PITCH, pitch, META_PITCH, meta_pitch); 197 198 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 200 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 201 } 202 203 void hubp1_program_rotation( 204 struct hubp *hubp, 205 enum dc_rotation_angle rotation, 206 bool horizontal_mirror) 207 { 208 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 209 uint32_t mirror; 210 211 212 if (horizontal_mirror) 213 mirror = 1; 214 else 215 mirror = 0; 216 217 /* Program rotation angle and horz mirror - no mirror */ 218 if (rotation == ROTATION_ANGLE_0) 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 220 ROTATION_ANGLE, 0, 221 H_MIRROR_EN, mirror); 222 else if (rotation == ROTATION_ANGLE_90) 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 224 ROTATION_ANGLE, 1, 225 H_MIRROR_EN, mirror); 226 else if (rotation == ROTATION_ANGLE_180) 227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 228 ROTATION_ANGLE, 2, 229 H_MIRROR_EN, mirror); 230 else if (rotation == ROTATION_ANGLE_270) 231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 232 ROTATION_ANGLE, 3, 233 H_MIRROR_EN, mirror); 234 } 235 236 void hubp1_program_pixel_format( 237 struct hubp *hubp, 238 enum surface_pixel_format format) 239 { 240 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 241 uint32_t red_bar = 3; 242 uint32_t blue_bar = 2; 243 244 /* swap for ABGR format */ 245 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 246 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 249 red_bar = 2; 250 blue_bar = 3; 251 } 252 253 REG_UPDATE_2(HUBPRET_CONTROL, 254 CROSSBAR_SRC_CB_B, blue_bar, 255 CROSSBAR_SRC_CR_R, red_bar); 256 257 /* Mapping is same as ipp programming (cnvc) */ 258 259 switch (format) { 260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 261 REG_UPDATE(DCSURF_SURFACE_CONFIG, 262 SURFACE_PIXEL_FORMAT, 1); 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 265 REG_UPDATE(DCSURF_SURFACE_CONFIG, 266 SURFACE_PIXEL_FORMAT, 3); 267 break; 268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 270 REG_UPDATE(DCSURF_SURFACE_CONFIG, 271 SURFACE_PIXEL_FORMAT, 8); 272 break; 273 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 274 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 276 REG_UPDATE(DCSURF_SURFACE_CONFIG, 277 SURFACE_PIXEL_FORMAT, 10); 278 break; 279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 280 REG_UPDATE(DCSURF_SURFACE_CONFIG, 281 SURFACE_PIXEL_FORMAT, 22); 282 break; 283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 284 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 285 REG_UPDATE(DCSURF_SURFACE_CONFIG, 286 SURFACE_PIXEL_FORMAT, 24); 287 break; 288 289 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 290 REG_UPDATE(DCSURF_SURFACE_CONFIG, 291 SURFACE_PIXEL_FORMAT, 65); 292 break; 293 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 294 REG_UPDATE(DCSURF_SURFACE_CONFIG, 295 SURFACE_PIXEL_FORMAT, 64); 296 break; 297 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 298 REG_UPDATE(DCSURF_SURFACE_CONFIG, 299 SURFACE_PIXEL_FORMAT, 67); 300 break; 301 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 302 REG_UPDATE(DCSURF_SURFACE_CONFIG, 303 SURFACE_PIXEL_FORMAT, 66); 304 break; 305 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 306 REG_UPDATE(DCSURF_SURFACE_CONFIG, 307 SURFACE_PIXEL_FORMAT, 12); 308 break; 309 default: 310 BREAK_TO_DEBUGGER(); 311 break; 312 } 313 314 /* don't see the need of program the xbar in DCN 1.0 */ 315 } 316 317 bool hubp1_program_surface_flip_and_addr( 318 struct hubp *hubp, 319 const struct dc_plane_address *address, 320 bool flip_immediate, 321 uint8_t vmid) 322 { 323 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 324 325 326 //program flip type 327 REG_UPDATE(DCSURF_FLIP_CONTROL, 328 SURFACE_FLIP_TYPE, flip_immediate); 329 330 331 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 332 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 333 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 334 335 } else { 336 // turn off stereo if not in stereo 337 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 338 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 339 } 340 341 342 343 /* HW automatically latch rest of address register on write to 344 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 345 * 346 * program high first and then the low addr, order matters! 347 */ 348 switch (address->type) { 349 case PLN_ADDR_TYPE_GRAPHICS: 350 /* DCN1.0 does not support const color 351 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 352 * base on address->grph.dcc_const_color 353 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 354 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 355 */ 356 357 if (address->grph.addr.quad_part == 0) 358 break; 359 360 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 361 PRIMARY_SURFACE_TMZ, address->tmz_surface, 362 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 363 364 if (address->grph.meta_addr.quad_part != 0) { 365 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 366 PRIMARY_META_SURFACE_ADDRESS_HIGH, 367 address->grph.meta_addr.high_part); 368 369 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 370 PRIMARY_META_SURFACE_ADDRESS, 371 address->grph.meta_addr.low_part); 372 } 373 374 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 375 PRIMARY_SURFACE_ADDRESS_HIGH, 376 address->grph.addr.high_part); 377 378 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 379 PRIMARY_SURFACE_ADDRESS, 380 address->grph.addr.low_part); 381 break; 382 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 383 if (address->video_progressive.luma_addr.quad_part == 0 384 || address->video_progressive.chroma_addr.quad_part == 0) 385 break; 386 387 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 388 PRIMARY_SURFACE_TMZ, address->tmz_surface, 389 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 390 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 391 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 392 393 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 394 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 395 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 396 address->video_progressive.chroma_meta_addr.high_part); 397 398 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 399 PRIMARY_META_SURFACE_ADDRESS_C, 400 address->video_progressive.chroma_meta_addr.low_part); 401 402 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 403 PRIMARY_META_SURFACE_ADDRESS_HIGH, 404 address->video_progressive.luma_meta_addr.high_part); 405 406 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 407 PRIMARY_META_SURFACE_ADDRESS, 408 address->video_progressive.luma_meta_addr.low_part); 409 } 410 411 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 412 PRIMARY_SURFACE_ADDRESS_HIGH_C, 413 address->video_progressive.chroma_addr.high_part); 414 415 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 416 PRIMARY_SURFACE_ADDRESS_C, 417 address->video_progressive.chroma_addr.low_part); 418 419 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 420 PRIMARY_SURFACE_ADDRESS_HIGH, 421 address->video_progressive.luma_addr.high_part); 422 423 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 424 PRIMARY_SURFACE_ADDRESS, 425 address->video_progressive.luma_addr.low_part); 426 break; 427 case PLN_ADDR_TYPE_GRPH_STEREO: 428 if (address->grph_stereo.left_addr.quad_part == 0) 429 break; 430 if (address->grph_stereo.right_addr.quad_part == 0) 431 break; 432 433 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 434 PRIMARY_SURFACE_TMZ, address->tmz_surface, 435 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 436 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 437 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 438 SECONDARY_SURFACE_TMZ, address->tmz_surface, 439 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 440 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 441 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 442 443 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 444 445 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 446 SECONDARY_META_SURFACE_ADDRESS_HIGH, 447 address->grph_stereo.right_meta_addr.high_part); 448 449 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 450 SECONDARY_META_SURFACE_ADDRESS, 451 address->grph_stereo.right_meta_addr.low_part); 452 } 453 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 454 455 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 456 PRIMARY_META_SURFACE_ADDRESS_HIGH, 457 address->grph_stereo.left_meta_addr.high_part); 458 459 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 460 PRIMARY_META_SURFACE_ADDRESS, 461 address->grph_stereo.left_meta_addr.low_part); 462 } 463 464 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 465 SECONDARY_SURFACE_ADDRESS_HIGH, 466 address->grph_stereo.right_addr.high_part); 467 468 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 469 SECONDARY_SURFACE_ADDRESS, 470 address->grph_stereo.right_addr.low_part); 471 472 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 473 PRIMARY_SURFACE_ADDRESS_HIGH, 474 address->grph_stereo.left_addr.high_part); 475 476 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 477 PRIMARY_SURFACE_ADDRESS, 478 address->grph_stereo.left_addr.low_part); 479 break; 480 default: 481 BREAK_TO_DEBUGGER(); 482 break; 483 } 484 485 hubp->request_address = *address; 486 487 return true; 488 } 489 490 void hubp1_dcc_control(struct hubp *hubp, bool enable, 491 bool independent_64b_blks) 492 { 493 uint32_t dcc_en = enable ? 1 : 0; 494 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 495 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 496 497 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 498 PRIMARY_SURFACE_DCC_EN, dcc_en, 499 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 500 SECONDARY_SURFACE_DCC_EN, dcc_en, 501 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 502 } 503 504 void hubp1_program_surface_config( 505 struct hubp *hubp, 506 enum surface_pixel_format format, 507 union dc_tiling_info *tiling_info, 508 union plane_size *plane_size, 509 enum dc_rotation_angle rotation, 510 struct dc_plane_dcc_param *dcc, 511 bool horizontal_mirror, 512 unsigned int compat_level) 513 { 514 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 515 hubp1_program_tiling(hubp, tiling_info, format); 516 hubp1_program_size(hubp, format, plane_size, dcc); 517 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 518 hubp1_program_pixel_format(hubp, format); 519 } 520 521 void hubp1_program_requestor( 522 struct hubp *hubp, 523 struct _vcs_dpi_display_rq_regs_st *rq_regs) 524 { 525 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 526 527 REG_UPDATE(HUBPRET_CONTROL, 528 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 529 REG_SET_4(DCN_EXPANSION_MODE, 0, 530 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 531 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 532 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 533 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 534 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 535 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 536 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 537 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 538 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 539 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 540 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 541 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 542 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 543 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 544 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 545 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 546 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 547 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 548 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 549 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 550 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 551 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 552 } 553 554 555 void hubp1_program_deadline( 556 struct hubp *hubp, 557 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 558 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 559 { 560 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 561 562 /* DLG - Per hubp */ 563 REG_SET_2(BLANK_OFFSET_0, 0, 564 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 565 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 566 567 REG_SET(BLANK_OFFSET_1, 0, 568 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 569 570 REG_SET(DST_DIMENSIONS, 0, 571 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 572 573 REG_SET_2(DST_AFTER_SCALER, 0, 574 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 575 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 576 577 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 578 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 579 580 /* DLG - Per luma/chroma */ 581 REG_SET(VBLANK_PARAMETERS_1, 0, 582 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 583 584 if (REG(NOM_PARAMETERS_0)) 585 REG_SET(NOM_PARAMETERS_0, 0, 586 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 587 588 if (REG(NOM_PARAMETERS_1)) 589 REG_SET(NOM_PARAMETERS_1, 0, 590 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 591 592 REG_SET(NOM_PARAMETERS_4, 0, 593 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 594 595 REG_SET(NOM_PARAMETERS_5, 0, 596 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 597 598 REG_SET_2(PER_LINE_DELIVERY, 0, 599 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 600 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 601 602 REG_SET(VBLANK_PARAMETERS_2, 0, 603 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 604 605 if (REG(NOM_PARAMETERS_2)) 606 REG_SET(NOM_PARAMETERS_2, 0, 607 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 608 609 if (REG(NOM_PARAMETERS_3)) 610 REG_SET(NOM_PARAMETERS_3, 0, 611 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 612 613 REG_SET(NOM_PARAMETERS_6, 0, 614 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 615 616 REG_SET(NOM_PARAMETERS_7, 0, 617 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 618 619 /* TTU - per hubp */ 620 REG_SET_2(DCN_TTU_QOS_WM, 0, 621 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 622 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 623 624 /* TTU - per luma/chroma */ 625 /* Assumed surf0 is luma and 1 is chroma */ 626 627 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 628 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 629 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 630 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 631 632 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 633 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 634 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 635 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 636 637 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 638 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 639 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 640 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 641 } 642 643 static void hubp1_setup( 644 struct hubp *hubp, 645 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 646 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 647 struct _vcs_dpi_display_rq_regs_st *rq_regs, 648 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 649 { 650 /* otg is locked when this func is called. Register are double buffered. 651 * disable the requestors is not needed 652 */ 653 hubp1_program_requestor(hubp, rq_regs); 654 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 655 hubp1_vready_workaround(hubp, pipe_dest); 656 } 657 658 static void hubp1_setup_interdependent( 659 struct hubp *hubp, 660 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 661 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 662 { 663 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 664 665 REG_SET_2(PREFETCH_SETTINS, 0, 666 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 667 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 668 669 REG_SET(PREFETCH_SETTINS_C, 0, 670 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 671 672 REG_SET_2(VBLANK_PARAMETERS_0, 0, 673 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 674 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 675 676 REG_SET(VBLANK_PARAMETERS_3, 0, 677 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 678 679 REG_SET(VBLANK_PARAMETERS_4, 0, 680 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 681 682 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 683 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 684 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 685 686 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 687 REFCYC_PER_REQ_DELIVERY_PRE, 688 ttu_attr->refcyc_per_req_delivery_pre_l); 689 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 690 REFCYC_PER_REQ_DELIVERY_PRE, 691 ttu_attr->refcyc_per_req_delivery_pre_c); 692 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 693 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 694 695 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 696 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 697 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 698 } 699 700 bool hubp1_is_flip_pending(struct hubp *hubp) 701 { 702 uint32_t flip_pending = 0; 703 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 704 struct dc_plane_address earliest_inuse_address; 705 706 REG_GET(DCSURF_FLIP_CONTROL, 707 SURFACE_FLIP_PENDING, &flip_pending); 708 709 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 710 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 711 712 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 713 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 714 715 if (flip_pending) 716 return true; 717 718 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 719 return true; 720 721 return false; 722 } 723 724 uint32_t aperture_default_system = 1; 725 uint32_t context0_default_system; /* = 0;*/ 726 727 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 728 struct vm_system_aperture_param *apt) 729 { 730 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 731 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 732 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 733 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 734 735 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 736 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 737 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 738 739 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 740 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 741 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 742 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 743 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 744 745 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 746 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 747 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 748 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 749 750 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 751 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 752 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 753 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 754 } 755 756 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 757 const struct vm_context0_param *vm0) 758 { 759 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 760 /* pte base */ 761 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 762 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 763 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 764 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 765 766 /* pte start */ 767 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 768 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 769 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 770 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 771 772 /* pte end */ 773 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 774 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 775 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 776 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 777 778 /* fault handling */ 779 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 780 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 781 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 782 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 783 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 784 785 /* control: enable VM PTE*/ 786 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 787 ENABLE_L1_TLB, 1, 788 SYSTEM_ACCESS_MODE, 3); 789 } 790 791 void min_set_viewport( 792 struct hubp *hubp, 793 const struct rect *viewport, 794 const struct rect *viewport_c) 795 { 796 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 797 798 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 799 PRI_VIEWPORT_WIDTH, viewport->width, 800 PRI_VIEWPORT_HEIGHT, viewport->height); 801 802 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 803 PRI_VIEWPORT_X_START, viewport->x, 804 PRI_VIEWPORT_Y_START, viewport->y); 805 806 /*for stereo*/ 807 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 808 SEC_VIEWPORT_WIDTH, viewport->width, 809 SEC_VIEWPORT_HEIGHT, viewport->height); 810 811 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 812 SEC_VIEWPORT_X_START, viewport->x, 813 SEC_VIEWPORT_Y_START, viewport->y); 814 815 /* DC supports NV12 only at the moment */ 816 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 817 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 818 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 819 820 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 821 PRI_VIEWPORT_X_START_C, viewport_c->x, 822 PRI_VIEWPORT_Y_START_C, viewport_c->y); 823 } 824 825 void hubp1_read_state(struct hubp *hubp) 826 { 827 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 828 struct dcn_hubp_state *s = &hubp1->state; 829 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 830 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 831 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 832 833 /* Requester */ 834 REG_GET(HUBPRET_CONTROL, 835 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 836 REG_GET_4(DCN_EXPANSION_MODE, 837 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 838 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 839 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 840 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 841 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 842 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 843 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 844 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 845 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 846 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 847 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 848 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 849 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 850 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 851 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 852 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 853 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 854 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 855 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 856 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 857 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 858 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 859 860 /* DLG - Per hubp */ 861 REG_GET_2(BLANK_OFFSET_0, 862 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 863 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 864 865 REG_GET(BLANK_OFFSET_1, 866 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 867 868 REG_GET(DST_DIMENSIONS, 869 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 870 871 REG_GET_2(DST_AFTER_SCALER, 872 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 873 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 874 875 if (REG(PREFETCH_SETTINS)) 876 REG_GET_2(PREFETCH_SETTINS, 877 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 878 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 879 else 880 REG_GET_2(PREFETCH_SETTINGS, 881 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 882 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 883 884 REG_GET_2(VBLANK_PARAMETERS_0, 885 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 886 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 887 888 REG_GET(REF_FREQ_TO_PIX_FREQ, 889 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 890 891 /* DLG - Per luma/chroma */ 892 REG_GET(VBLANK_PARAMETERS_1, 893 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 894 895 REG_GET(VBLANK_PARAMETERS_3, 896 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 897 898 if (REG(NOM_PARAMETERS_0)) 899 REG_GET(NOM_PARAMETERS_0, 900 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 901 902 if (REG(NOM_PARAMETERS_1)) 903 REG_GET(NOM_PARAMETERS_1, 904 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 905 906 REG_GET(NOM_PARAMETERS_4, 907 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 908 909 REG_GET(NOM_PARAMETERS_5, 910 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 911 912 REG_GET_2(PER_LINE_DELIVERY_PRE, 913 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 914 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 915 916 REG_GET_2(PER_LINE_DELIVERY, 917 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 918 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 919 920 if (REG(PREFETCH_SETTINS_C)) 921 REG_GET(PREFETCH_SETTINS_C, 922 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 923 else 924 REG_GET(PREFETCH_SETTINGS_C, 925 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 926 927 REG_GET(VBLANK_PARAMETERS_2, 928 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 929 930 REG_GET(VBLANK_PARAMETERS_4, 931 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 932 933 if (REG(NOM_PARAMETERS_2)) 934 REG_GET(NOM_PARAMETERS_2, 935 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 936 937 if (REG(NOM_PARAMETERS_3)) 938 REG_GET(NOM_PARAMETERS_3, 939 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 940 941 REG_GET(NOM_PARAMETERS_6, 942 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 943 944 REG_GET(NOM_PARAMETERS_7, 945 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 946 947 /* TTU - per hubp */ 948 REG_GET_2(DCN_TTU_QOS_WM, 949 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 950 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 951 952 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 953 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 954 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 955 956 /* TTU - per luma/chroma */ 957 /* Assumed surf0 is luma and 1 is chroma */ 958 959 REG_GET_3(DCN_SURF0_TTU_CNTL0, 960 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 961 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 962 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 963 964 REG_GET(DCN_SURF0_TTU_CNTL1, 965 REFCYC_PER_REQ_DELIVERY_PRE, 966 &ttu_attr->refcyc_per_req_delivery_pre_l); 967 968 REG_GET_3(DCN_SURF1_TTU_CNTL0, 969 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 970 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 971 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 972 973 REG_GET(DCN_SURF1_TTU_CNTL1, 974 REFCYC_PER_REQ_DELIVERY_PRE, 975 &ttu_attr->refcyc_per_req_delivery_pre_c); 976 977 /* Rest of hubp */ 978 REG_GET(DCSURF_SURFACE_CONFIG, 979 SURFACE_PIXEL_FORMAT, &s->pixel_format); 980 981 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 982 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 983 984 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 985 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 986 987 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 988 PRI_VIEWPORT_WIDTH, &s->viewport_width, 989 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 990 991 REG_GET_2(DCSURF_SURFACE_CONFIG, 992 ROTATION_ANGLE, &s->rotation_angle, 993 H_MIRROR_EN, &s->h_mirror_en); 994 995 REG_GET(DCSURF_TILING_CONFIG, 996 SW_MODE, &s->sw_mode); 997 998 REG_GET(DCSURF_SURFACE_CONTROL, 999 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1000 1001 REG_GET_3(DCHUBP_CNTL, 1002 HUBP_BLANK_EN, &s->blank_en, 1003 HUBP_TTU_DISABLE, &s->ttu_disable, 1004 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1005 1006 REG_GET(DCN_GLOBAL_TTU_CNTL, 1007 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1008 1009 REG_GET_2(DCN_TTU_QOS_WM, 1010 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1011 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1012 } 1013 1014 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1015 { 1016 enum cursor_pitch hw_pitch; 1017 1018 switch (pitch) { 1019 case 64: 1020 hw_pitch = CURSOR_PITCH_64_PIXELS; 1021 break; 1022 case 128: 1023 hw_pitch = CURSOR_PITCH_128_PIXELS; 1024 break; 1025 case 256: 1026 hw_pitch = CURSOR_PITCH_256_PIXELS; 1027 break; 1028 default: 1029 DC_ERR("Invalid cursor pitch of %d. " 1030 "Only 64/128/256 is supported on DCN.\n", pitch); 1031 hw_pitch = CURSOR_PITCH_64_PIXELS; 1032 break; 1033 } 1034 return hw_pitch; 1035 } 1036 1037 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1038 unsigned int cur_width, 1039 enum dc_cursor_color_format format) 1040 { 1041 enum cursor_lines_per_chunk line_per_chunk; 1042 1043 if (format == CURSOR_MODE_MONO) 1044 /* impl B. expansion in CUR Buffer reader */ 1045 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1046 else if (cur_width <= 32) 1047 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1048 else if (cur_width <= 64) 1049 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1050 else if (cur_width <= 128) 1051 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1052 else 1053 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1054 1055 return line_per_chunk; 1056 } 1057 1058 void hubp1_cursor_set_attributes( 1059 struct hubp *hubp, 1060 const struct dc_cursor_attributes *attr) 1061 { 1062 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1063 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1064 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1065 attr->width, attr->color_format); 1066 1067 hubp->curs_attr = *attr; 1068 1069 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1070 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1071 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1072 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1073 1074 REG_UPDATE_2(CURSOR_SIZE, 1075 CURSOR_WIDTH, attr->width, 1076 CURSOR_HEIGHT, attr->height); 1077 1078 REG_UPDATE_3(CURSOR_CONTROL, 1079 CURSOR_MODE, attr->color_format, 1080 CURSOR_PITCH, hw_pitch, 1081 CURSOR_LINES_PER_CHUNK, lpc); 1082 1083 REG_SET_2(CURSOR_SETTINS, 0, 1084 /* no shift of the cursor HDL schedule */ 1085 CURSOR0_DST_Y_OFFSET, 0, 1086 /* used to shift the cursor chunk request deadline */ 1087 CURSOR0_CHUNK_HDL_ADJUST, 3); 1088 } 1089 1090 void hubp1_cursor_set_position( 1091 struct hubp *hubp, 1092 const struct dc_cursor_position *pos, 1093 const struct dc_cursor_mi_param *param) 1094 { 1095 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1096 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 1097 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 1098 int x_hotspot = pos->x_hotspot; 1099 int y_hotspot = pos->y_hotspot; 1100 uint32_t dst_x_offset; 1101 uint32_t cur_en = pos->enable ? 1 : 0; 1102 1103 /* 1104 * Guard aganst cursor_set_position() from being called with invalid 1105 * attributes 1106 * 1107 * TODO: Look at combining cursor_set_position() and 1108 * cursor_set_attributes() into cursor_update() 1109 */ 1110 if (hubp->curs_attr.address.quad_part == 0) 1111 return; 1112 1113 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1114 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 1115 y_hotspot = pos->x_hotspot; 1116 x_hotspot = pos->y_hotspot; 1117 } 1118 1119 if (param->mirror) { 1120 x_hotspot = param->viewport.width - x_hotspot; 1121 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1122 } 1123 1124 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1125 dst_x_offset *= param->ref_clk_khz; 1126 dst_x_offset /= param->pixel_clk_khz; 1127 1128 ASSERT(param->h_scale_ratio.value); 1129 1130 if (param->h_scale_ratio.value) 1131 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1132 dc_fixpt_from_int(dst_x_offset), 1133 param->h_scale_ratio)); 1134 1135 if (src_x_offset >= (int)param->viewport.width) 1136 cur_en = 0; /* not visible beyond right edge*/ 1137 1138 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1139 cur_en = 0; /* not visible beyond left edge*/ 1140 1141 if (src_y_offset >= (int)param->viewport.height) 1142 cur_en = 0; /* not visible beyond bottom edge*/ 1143 1144 if (src_y_offset + (int)hubp->curs_attr.height <= 0) 1145 cur_en = 0; /* not visible beyond top edge*/ 1146 1147 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1148 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1149 1150 REG_UPDATE(CURSOR_CONTROL, 1151 CURSOR_ENABLE, cur_en); 1152 1153 REG_SET_2(CURSOR_POSITION, 0, 1154 CURSOR_X_POSITION, pos->x, 1155 CURSOR_Y_POSITION, pos->y); 1156 1157 REG_SET_2(CURSOR_HOT_SPOT, 0, 1158 CURSOR_HOT_SPOT_X, x_hotspot, 1159 CURSOR_HOT_SPOT_Y, y_hotspot); 1160 1161 REG_SET(CURSOR_DST_OFFSET, 0, 1162 CURSOR_DST_X_OFFSET, dst_x_offset); 1163 /* TODO Handle surface pixel formats other than 4:4:4 */ 1164 } 1165 1166 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1167 { 1168 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1169 uint32_t clk_enable = enable ? 1 : 0; 1170 1171 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1172 } 1173 1174 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1175 { 1176 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1177 1178 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1179 } 1180 1181 void hubp1_init(struct hubp *hubp) 1182 { 1183 //do nothing 1184 } 1185 static const struct hubp_funcs dcn10_hubp_funcs = { 1186 .hubp_program_surface_flip_and_addr = 1187 hubp1_program_surface_flip_and_addr, 1188 .hubp_program_surface_config = 1189 hubp1_program_surface_config, 1190 .hubp_is_flip_pending = hubp1_is_flip_pending, 1191 .hubp_setup = hubp1_setup, 1192 .hubp_setup_interdependent = hubp1_setup_interdependent, 1193 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1194 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1195 .set_blank = hubp1_set_blank, 1196 .dcc_control = hubp1_dcc_control, 1197 .mem_program_viewport = min_set_viewport, 1198 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1199 .set_cursor_attributes = hubp1_cursor_set_attributes, 1200 .set_cursor_position = hubp1_cursor_set_position, 1201 .hubp_disconnect = hubp1_disconnect, 1202 .hubp_clk_cntl = hubp1_clk_cntl, 1203 .hubp_vtg_sel = hubp1_vtg_sel, 1204 .hubp_read_state = hubp1_read_state, 1205 .hubp_clear_underflow = hubp1_clear_underflow, 1206 .hubp_disable_control = hubp1_disable_control, 1207 .hubp_get_underflow_status = hubp1_get_underflow_status, 1208 .hubp_init = hubp1_init, 1209 }; 1210 1211 /*****************************************/ 1212 /* Constructor, Destructor */ 1213 /*****************************************/ 1214 1215 void dcn10_hubp_construct( 1216 struct dcn10_hubp *hubp1, 1217 struct dc_context *ctx, 1218 uint32_t inst, 1219 const struct dcn_mi_registers *hubp_regs, 1220 const struct dcn_mi_shift *hubp_shift, 1221 const struct dcn_mi_mask *hubp_mask) 1222 { 1223 hubp1->base.funcs = &dcn10_hubp_funcs; 1224 hubp1->base.ctx = ctx; 1225 hubp1->hubp_regs = hubp_regs; 1226 hubp1->hubp_shift = hubp_shift; 1227 hubp1->hubp_mask = hubp_mask; 1228 hubp1->base.inst = inst; 1229 hubp1->base.opp_id = 0xf; 1230 hubp1->base.mpcc_id = 0xf; 1231 } 1232 1233 1234